*SUBCIRCUITE

.subckt NOT 1 2 3
MP 3 1 2 2 CMOSP L=0.5u W=1.5u
MN 3 1 0 0 CMOSN L=0.5u W=0.75u
.ends
.subckt INV3S 1 2 3 6 7
MP1 4 6 2 2 CMOSP L=0.5u W=1.5u
MP2 3 1 4 2 CMOSP L=0.5u W=1.5u
MN1 3 1 5 0 CMOSN L=0.5u W=0.75u
MN2 5 7 0 0 CMOSN L=0.5u W=0.75u
.ends
.subckt NOR 1 2 3 4
MP1 5 1 3 3 CMOSP L=0.5u W=3u
MP2 4 2 5 3 CMOSP L=0.5u W=3u
MN1 4 1 0 0 CMOSN L=0.5u W=0.75u
MN2 4 2 0 0 CMOSN L=0.5u W=0.75u
.ends
.subckt NAND 1 2 3 4
MP1 4 1 3 3 CMOSP L=0.5u W=0.75u
MP2 4 2 3 3 CMOSP L=0.5u W=0.75u
MN1 5 1 0 0 CMOSN L=0.5u W=0.75u
MN2 4 2 5 0 CMOSN L=0.5u W=0.75u
.ends
.subckt AND 1 2 4 5
X1 1 2 4 3 NAND
X2 3 4 5 NOT
.ends
.subckt OR 1 2 4 5
X1 1 2 4 3 NOR
X2 3 4 5 NOT
.ends
.subckt SDFFS 1 2 3 4 5 19 15 16

XAND1 1 2 19 6 AND
XAND2 7 3 19 8 AND
XNAND1 10 4 19 11 NAND
XNAND2 12 4 19 13 NAND
XOR1 6 8 19 9 OR
XINV1 2 19 7 NOT
XINV2 13 19 14 NOT
XINV3 14 19 15 NOT
XINV4 13 19 16 NOT
XINV5 5 19 17 NOT
XINV6 17 19 18 NOT
XINV3S1 9 19 10 17 18 INV3S
XINV3S2 11 19 18 17 10 INV3S
XINV3S3 11 19 12 17 18 INV3S
XINV3S4 13 19 12 17 18 INV3S
.ends