Address Indexed 'AI' Interface Architecture Specification: Revision 1.0

AI Architecture Specification Revision 1.
Address Indexed 'AI' Interface

Architecture Specification
Revision 1.0
Issue Date: September 10, 2013
LSI Confidential
All information provided herein is the copyright of LSI and is presented “AS IS”. All information is subject
to change.
AI Architecture Specification Revision 1.0
PREFACE
This document describes the functionality and signaling of the Address Indexed
interface.
Intended Audience
The intended audience includes ASIC Designers, ASIC Verification Engineers, Validation
Engineers, and Firmware Engineers.
Conventions used in this document

 AI – Address Indexed
 Byte – 8-bits
 Request – One address and data pair on AI
 Transaction – One or more AI requests ended by AI_RdDone and AI_RdRdy or
AI_WrDone and AI_WrRdy.
 RD – Read
 WR – Write
LSI Confidential Page 2 of 14 9/10/2013

to change.
Revision History
Table 1-1 Revision History

Date Version Author Revision
08/01/13 0.1 Omar Guerra  Initial. Taken from PLB Slave EDS.
08/05/13 0.2 Omar Guerra  Made updates based on feedback.
 Changed “Incrementing” to “Indexed”.
 Got rid of “Clk/Reset Signals” section. Designers may choose to
have async AI Interfaces.
 Added that AI implements an odd parity scheme.
 Changed revision number from 1.0 to 0.2.
 Fixed some formatting.
08/06/13 0.3 Omar Guerra  Updated this table to indicate initial revision was 0.1 and not 1.0
 Got rid of concept of “slave device” and “master device”. Now
just referred to as “slave” and “master” respectively.
 Fixed typos.
 Made note of the
o Concurrency of RD and WR channels.
o Read data returned by slave in same order as
addresses presented by master.
 Added “Implementation” Section.
08/07/13 0.4 Omar Guerra  Added “Err” signals will be normally low.
 Added that parity will always be valid, regardless of byte
enables.
 Added new RD diagram showing how Ai_RdSel can go inactive
and how Rdy and Ack can go active simultaneously.
 Some cosmetic changes to timing diagrams.
8/20/2013 0.5 Omar Guerra  Changed file name from AI_ArchSpec1.0 to AI_ArchSpec0.5.
 Updated definition for transaction
 Updated some text in figures
 In implementation guide, have to account for possibility of
AI_RdRdy and AI_WrRdy always driven to 1’b1.
8/27/2013 0.6 Omar Guerra  Changes prompted by review.
9/10/2013 1.0 Omar Guerra  Changed to version 1.0

to change.
TABLE OF CONTENTS
PREFACE .................................................................................................................. 2
Intended Audience ............................................................................................... 2
Conventions used in this document ....................................................................... 2
Revision History ................................................................................................... 3
1 AI INTERFACE ..................................................................................................... 7
1.1 Data Alignment ............................................................................................. 7
1.2 RD Signals .................................................................................................... 8
1.2.1 Timing Diagram .................................................................................. 9
1.3 WR Signals ................................................................................................. 11
1.3.1 Timing Diagram ................................................................................ 12
2 IMPLEMENTATION GUIDE .................................................................................. 14

2.1 Multiple Slave Support Guide ....................................................................... 14

to change.
LIST OF FIGURES
Figure 1-1 AI Data Alignment..................................................................................... 7
Figure 1-2 AI RD Connection Diagram ........................................................................ 8
Figure 1-3 AI RD Timing Diagram ............................................................................ 10
Figure 1-4 AI RD Timing Diagram ............................................................................ 10
Figure 1-5 AI WR Connection Diagram ..................................................................... 11
Figure 1-6 AI WR Timing Diagram ............................................................................ 13
Figure 2-1 AI Multi-Slave AI_RdData Connection Diagram ......................................... 14

to change.
LIST OF TABLES
Table 1-1 Revision History ......................................................................................... 3
Table 1-2 AI RD Signals............................................................................................. 8
Table 1-3 AI WR Signals .......................................................................................... 11

to change.
1 AI INTERFACE
AI is a 128-bit data and 32-bit address interface and has independent RD and WR
channels. Because of the channel independence, the RD and WR channels may be
active concurrently on the AI inteferface. The AI protocol allows throttling from the
slave to the master with the ability to stream data with no wait states. The AI protocol
involves presenting an address to the slave and the slave providing RD data or
accepting WR data. Once that request is accepted, the master will move to the next
request, that is, transition to the next address. Note, that a master’s transaction may
take one or more AI requests.
The master is allowed to present the address as is required to fulfill its current
transaction (i.e., master does not have to present addresses in any order). It is up to
the slave to process each AI request individually and not make any assumptions on the
current request based on past requests (i.e., the slave can’t assume the addresses are
coming in any specific order); it must provide data or accept data for the current
request (i.e., address).
1.1 Data Alignment

AI RD and WR data requests will be address aligned on the data bus. The byte address
will be provided as well as byte enables.
Addr BE Data Bus

32'hBEEF_BAD0 16'hFFFF V V V V V V V V V V V V V V V V
32'hBEEF_BAD1 16'hFFFE V V V V V V V V V V V V V V V X
32'hBEEF_BADF 16'h8000 V X X X X X X X X X X X X X X X
32'hBEEF_BAD0 16'h000F X X X X X X X X X X X X V V V V
V = Valid Data Byte
X = Don't Care Byte (Can be any data,
including valid data)
Figure 1-1 AI Data Alignment

to change.
1.2 RD Signals
The following signals will be used to perform RD requests on the AI interface.
Table 1-2 AI RD Signals

Name Width Description
AI_RdSel [N - 1:0] Slave Read Select – Where, N is equal to number of
slaves.
AI_RdAddr [31:0] Slave Read Address
AI_RdDone Slave Read Done
AI_RdBe [15:0] Slave Read Byte Enables
AI_RdRdy Slave Read Ready
AI_RdData [143:0] Slave Read Data – {16-bit parity, 128-bit data}
AI implements an odd parity scheme.
AI_RdDataAck Slave Read Data Acknowledge
AI_RdErr Slave Read Error
AI_RdSel[N - 1:0]
AI_RdAddr[31:0]
AI_RdDone
AI_RdBe[15:0]
AI Master AI Slave
AI_RdRdy
AI_RdData[143:0]
AI_RdDataAck
AI_RdErr
Figure 1-2 AI RD Connection Diagram
AI_RdSel informs a slave that the AI_RdAddr presented is valid. AI_RdSel will be as
wide as needed to communicate with all slaves on the AI interface.
AI_RdAddr is the 32-bit byte address passed to the slave for the location of the data
requested. The value of AI_RdAddr is valid when the slave samples a high on
AI_RdSel. Refer to figure “AI Data Alignment”.
AI_RdDone informs the slave that the address presented is the last address needed to
fulfill the master’s RD transaction. This signal will be asserted concurrently with last

to change.
address phase. Regardless of whether the RD transaction requires many requests or

just one request to be fulfilled, the assertion of this signal will indicate the currently
presented address is the last address for a RD transaction.
AI_RdBe informs the slave of the RD byte enables. The byte enables will indicate
which bytes will be read from the 16 byte location.
AI_RdRdy informs the master that the slave is ready to accept a valid address or it
has accepted the valid address presented. This signal allows the slave to throttle
masters on the RD channel. If there was a valid address presented to the slave then the
master will transition to the next valid address, if one exists, upon sampling AI_RdRdy
high. If the AI_RdRdy is sampled low then the master will have to hold the valid
address until the slave indicates that the valid address presented was accepted, by
sampling AI_RdRdy high. This signal should be normally high from the slave to reduce
latency, but is not prohibited from being normally low.
AI_RdData is the data from the slave to the master at a width of 144-bits. The data
on AI_RdData will be valid when the AI_RdDataAck is sampled high by the master. The
upper 16-bits are odd byte parity bits and the lower 128-bits are the actual data bits.
Anytime the slave drives AI_RdData, the target will also drive valid parity for all data
byte lanes, regardless of the byte enables. The slave will return data in the same order
as the addresses were presented by the master.
AI_RdDataAck is the data acknowledge signal from the slave to the master. When
this signal is sampled high, the contents on the AI_RdData are valid. Also, when this
signal is sampled high, the AI_RdErr is valid and is associated with the current data
phase being acknowledged. For zero-latency requests, the slave is permitted to assert
AI_RdDataAck and AI_RdRdy concurrently with AI_RdSel.
AI_RdErr is the error signal that is associated with the current acknowledged data
phase. This signal is only valid when AI_RdDataAck is sampled high and informs the
master the slave has encountered an error for current (i.e., the one currently being data
ack’d) request.
1.2.1 Timing Diagram

The following are timing diagrams for RD transactions.

to change.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
AI_RdSel
AI_RdAddr A B C D E F G0 H I J K0 L M N0
AI_RdBe A B C D E F G0 H I J K0 L M N0
AI_RdDone
AI_RdRdy
Latency – The initial latency is the amount of time it takes from when a master device asserts AI_RdSel for an address to when the master
device detects AI_RdRdy asserted. The slave device can insert wait states (hence, increase overall latency) in the data transfer by not
asserting AI_RdDataAck. For instance, the latency for data ‘A’ is 5 clocks and for ‘F’, 7 clocks.
AI_RdData O1 A B C D O1 E F H I J O1 L M O1
AI_RdDataAck
AI_RdErr
Data Read = A, B, C, D, E, F, H, I, J, L, M
Data Error = A, B, C, D, E, F, J, M
Note, that AI requests A-F, H-J, L, and M each constitute one transaction.
Note, AI_RdData is returned in the same order as addresses presented by master.
0
– Ignored, AI_RdSel not active
1
– O = {16'hFFFF,128'h0}
Figure 1-3 AI RD Timing Diagram
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
AI_RdSel
AI_RdAddr A B0 C D0 E F0 G H0 I J0 K L0
AI_RdBe A B0 C D0 E F0 G H0 I J0 K L0
AI_RdDone
AI_RdRdy
AI_RdData O1 A C E O1 G O1 I O1 K O1
AI_RdDataAck
AI_RdErr
Data Read = A, C, E, G, I, and K

Note, that AI requests A-C-E and G-I-K each constitute one transaction.
Note, AI_RdData is returned in the same order as addresses presented by master.
0
– Ignored, AI_RdSel not active
1
– O = {16'hFFFF,128'h0}
Figure 1-4 AI RD Timing Diagram

to change.
1.3 WR Signals
The following signals will be used to perform WR requests to the slave.
Table 1-3 AI WR Signals

Name Width Description
AI_WrSel [N - 1:0] Slave Write Select – N is equal to number of slaves.
AI_WrAddr [31:0] Slave Write Address – Only valid when AI_WrSel is
active.
AI_WrDone Slave Write Done – Asserted in last data phase per
transaction
AI_WrBe [15:0] Slave Write Enables – Byte Enables. Indicates which
bytes in AI_WrData are valid. Only valid when
AI_WrSel is active.
AI_WrData [143:0] Slave Write Data – {16-bit parity, 128-bit data}
AI implements an odd parity scheme.
AI_WrRdy Slave Write Ready – Valid Address/Byte Enable/Data
Accepted
AI_WrErr Slave Write Error – must be valid during transaction
AI_WrSel[N - 1:0]
AI_WrAddr[31:0]
AI_WrDone
AI_WrBe[15:0]
AI Master AI Slave
Ai_WrData[143:0]
AI_WrRdy
AI_WrErr
Figure 1-5 AI WR Connection Diagram
AI_WrSel informs a slave that the WR context information (AI_WrAddr, AI_WrBE, and
AI_WrData) presented is valid. The AI_WrSel port will be as wide as needed to
communicate with all slaves on the AI interface
AI_WrAddr is the 32-bit byte address that is presented to the slave and is only valid
when AI_WrSel is sampled high by the slave. Refer to figure “AI Data Alignment”.

to change.
AI_WrDone informs the slave that the current WR data phase is the last data phase
for the transaction. Regardless of whether the WR transaction requires many requests
or just one request to be fulfilled, the assertion of this signal will indicate the currently
presented address is the last address for a WR transaction.
AI_WrBe is the byte-enables for the 16 byte data being presented to the slave and is
only valid when the AI_WrSel is sampled high by the slave.
AI_WrData is the 144-bit data port that is presented to the slave and is only valid
when the AI_WrSel is sampled high by the slave. The upper 16-bits are byte odd parity
bits and the lower 128-bits are the actual data bits. Anytime the master drives
AI_WrData, the master will also drive valid parity for all data byte lanes, regardless of
the byte enables.
AI_WrRdy informs the master that the slave is ready to accept valid WR context
information (AI_WrAddr, AI_WrBe, and AI_WrData) or it has accepted the valid WR
context information presented. This signal allows the slave to throttle masters on the
WR channel. If there was valid WR context information presented to the slave then the
master will transition to the next valid WR context information, if one exists, upon
sampling AI_WrRdy high. If the AI_WrRdy is sampled low then the master will have to
hold the valid WR context information until the slave indicates that the valid WR context
information presented was accepted, by sampling AI_WrRdy high. This signal should
be normally high from the slave to reduce latency, but is not prohibited from being
normally low.
AI_WrErr informs the master that the slave encountered an error with the particular
request. Normally, the signal will be driven low and should only be driven high to
indicate an error. This signal must be asserted during the request that caused the error.
Therefore, the signal must NOT be asserted before or after WR request has completed.
The signal may assert during all requests for a transaction or for any one particular
request anywhere in between, and including, the beginning and end of a transaction.
This signal is ONLY valid when a request is presented and AI_WrRdy is asserted.
1.3.1 Timing Diagram

The following is a timing diagram for WR transactions.

to change.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
AI_WrSel
AI_WrAddr A B C D E F G0 H I J K0 L M N0
AI_WrData A B C D E F G0 H I J K0 L M N0
AI_WrBe A B C D E F G0 H I J K0 L M N0
AI_WrRdy
AI_WrDone
AI_WrErr
Data Written = A, B, C, D, E, F, H, I, J, L, M
Data Error = A, F, L
Note, that AI requests A-C, D-F, and H-L, and M each constitute one transaction.
0
– Ignored, AI_WrSel not active
Figure 1-6 AI WR Timing Diagram

to change.
2 IMPLEMENTATION GUIDE
2.1 Multiple Slave Support Guide

The AI interface may be used to support multiple slaves. The master will provide the
proper width of AI_RdSel/AI_WrSel to support the number of targets on the AI interface
and will route AI_RdSel/AI_WrSel to the proper slave (i.e., AI_RdSel [0] to slave 0,
etc.).
Slaves that are not currently selected and not participating in the transfer will drive 0’s
for all outputs (except for parity and maybe AI_WrRdy and AI_RdRdy, which are driven
to 1’s). The master will receive all the “OR’d” and “AND’d” signals from all targets.
For instance, a target that is not providing read data will drive 128’h0 on AI_RdData
[127:0] and 16’hFFFF on AI_RdData [143:128] (i.e., parity). The master will receive
the “OR’d” AI_RdData [127:0] from all slaves and the “AND’d” AI_RdData [143:128]
from all slaves. See Figure 2-1. Note, Figure 2-1 only specifies how AI_RdData should
be “OR’d” and “AND’d” and sent back to the master. Other signals like AI_RdDataAck,
AI_RdErr, etc. will have to be “OR’d” in a similar fashion.
AI_RdSel[1:0] AI_RdSel[0]
AI_RdData[143:128]
AI Slave 0
AI_RdData[127:0]
AI_RdData[143:128]
AI Master
AI_RdData[127:0] AI_RdSel[1]
AI_RdData[143:128]
AI Slave 1
AI_RdData[127:0]
Figure 2-1 AI Multi-Slave AI_RdData Connection Diagram

to change.

Address Indexed 'AI' Interface Architecture Specification: Revision 1.0

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AI Architecture Specification Revision 1.

Address Indexed 'AI' Interface

Issue Date: September 10, 2013

Conventions used in this document

LSI Confidential Page 2 of 14 9/10/2013

Table 1-1 Revision History

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2 IMPLEMENTATION GUIDE .................................................................................. 14

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1.1 Data Alignment

Addr BE Data Bus

Figure 1-1 AI Data Alignment

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Table 1-2 AI RD Signals

Figure 1-2 AI RD Connection Diagram

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address phase. Regardless of whether the RD transaction requires many requests or

1.2.1 Timing Diagram

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Figure 1-3 AI RD Timing Diagram

Data Read = A, C, E, G, I, and K

Figure 1-4 AI RD Timing Diagram

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Table 1-3 AI WR Signals

Figure 1-5 AI WR Connection Diagram

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1.3.1 Timing Diagram

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Figure 1-6 AI WR Timing Diagram

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2.1 Multiple Slave Support Guide

Figure 2-1 AI Multi-Slave AI_RdData Connection Diagram

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