coatings

Article
Double-Gate Two-Step Source/Drain Poly-Si
Thin-Film Transistor
Feng-Tso Chien 1, * , Chih-Ping Hung 1 , Hsien-Chin Chiu 2 , Tsung-Kuei Kang 1 ,
Ching-Hwa Cheng 1 and Yao-Tsung Tsai 3
1 Department of Electronic Engineering, Feng Chia University, Taichung 407, Taiwan;
ttps30233@gmail.com (C.-P.H.); kangtk@fcu.edu.tw (T.-K.K.); chengch@fcu.edu.tw (C.-H.C.)
2 Department of Electronic Engineering, Chang Gung University, Taoyuan 33302, Taiwan;
hcchiu@mail.cgu.edu.tw
3 Department of Electrical Engineering, National Central University, Jhongli 320, Taiwan; tsai@ee.ncu.edu.tw
* Correspondence: ftchien@fcu.edu.tw; Tel.: +886-424517250 (ext. 4957)




Received: 13 March 2019; Accepted: 1 April 2019; Published: 3 April 2019


Abstract: A current improved and electric field reduced double-gate (DG) polycrystalline silicon
thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated
in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD)
area together with a partial gate overlapped lightly doped drain (P-GOLDD) structure, can lower the
device drain electric field (DEF) to reveal a better device performance. Comparisons have been made
with respect to a traditional single top gate (STG) device. The operation current of the proposed
DGTSD-TFT is almost twice as large as that of the STG structure. The OFF-state leakage current
and kink effect, as well as the ON/OFF current ratio for this double-gate and two-step source/drain
structure, are also improved simultaneously because of a reduced DEF. A hot carrier stress test reveals
that that two-step source/drain structure can achieve more stable device characteristics than the
traditional device.

Keywords: thin-film transistor (TFT); polycrystalline silicon (poly-Si); kink effect; two-step
source/drain (TSD); double gate (DG)

1. Introduction
The low temperature polycrystalline silicon thin film transistor (poly-Si TFT) fabricated on glass
substrates has been widely studied and used for active-matrix organic liquid crystal display (AMOLCD)
and active matrix organic light emitting (AMOLED) display applications, peripheral driver and pixel
switches circuits [1], because it has a high electron mobility and On-state current when compared to
the amorphous silicon (a-Si) TFT [2]. The most critical issue for the conventional poly-Si TFT is its high
drain electric field (DEF) that causes a great deal of impact ionization, which leads to an intense kink
effect and degrades the device performance [3,4]. This drawback also limits this device’s use in digital
and analog circuits on glass for high resolution displays. Moreover, the conventional poly-Si device
encounters a large leakage current problem that degrades its switching performance [5].
Many structures have been reported to be able to reduce the high DEF and thus to improve
the device characteristics [3,6–10]. The offset-gate device was shown to lower the DEF effectively,
but its On-current was also significantly decreased because of an additional series resistance [6].
Lightly doped drain (LDD) [7], RSD [8,9], and GOLDD [10] were proposed to reduce the series
resistance problem. Even though the above mentioned structures could effectively lower the high DEF,
the ON-current of those structures still need to be improved when considering the current driving
capability and high-resolution display applications. In addition, most RSD structures need to adopt

Coatings 2019, 9, 233; doi:10.3390/coatings9040233 www.mdpi.com/journal/coatings

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and high-resolution display applications. In addition, most RSD structures need to adopt chemical
chemical
mechanical mechanical
polishingpolishing (CMP) processes
(CMP) processes [9]. Therefore,
[9]. Therefore, to implement to implement
a low DEFadevice low DEF with device
a reducedwith
aleakage
reduced leakage current and an improved operation current structure
current and an improved operation current structure at the same time is a very important at the same time is a very
important issue for adesigning
issue for designing a high performance
high performance poly-Si TFT. poly-Si TFT.
A DG structure was used to improve
A DG structure was used to improve the device current the device current drive
drive capability
capability effectively
effectively [11,12].
[11,12].
However,
However, the double gate structure has an electric field superposition problem around the
the double gate structure has an electric field superposition problem around the
channel/drain
channel/drain junctionjunctionand andworsens
worsensthe the DEF
DEF [13].
[13]. Moreover,
Moreover, the the fabrication
fabrication of of this
this structure
structure has has aa
misalignment
misalignment issue issue between
betweenthe theup upandandbottom
bottom gates
gates [14].
[14]. In addition,
In addition, the the leakage
leakage currentcurrent
at theatOFFthe
OFF
state state
mode mode for the
for the double-gate
double-gate structure
structure becomes
becomes unacceptably
unacceptably large[13].
large [13].AADG DGTFT TFT with
with aa
conventional
conventional RSD structure was designed to improve the device performance [13–15]. But these
RSD structure was designed to improve the device performance [13–15]. But these
designs
designs required
required two twoCMP CMPprocess
processsteps,
steps,and
andthe theprecise
precisewet wetetching
etchingonon the
the nitride
nitride sacrificial
sacrificiallayer
layeris
difficult
is difficultto to
control.
control. OurOurpreviously
previouslystudystudyproposed
proposedaaZ-gate Z-gatestructure
structureto toovercome
overcome the the electric
electric field
field
superposition
superposition problem [16], but it still encountered a misalignment problem between the top and
problem [16], but it still encountered a misalignment problem between the top and
bottom
bottom gates.
gates.
In
In this
this work,
work,we weproposed
proposeda aDG DGTFT TFTtogether
together with
with a TSD
a TSD structure
structure (DGTSD-TFT)
(DGTSD-TFT) to improve
to improve the
device characteristics. This TSD design can be an extended RSD (E-RSD)
the device characteristics. This TSD design can be an extended RSD (E-RSD) and form a partial thicker and form a partial thicker
channel
channel near
near thethe drain
drain to to lower
lower the
the impact
impact of of the
the electric
electric field
field superposition
superposition problem problem [16]. [16]. There
There is is aa
report that two-dimensional drain TFTs can reduce the device leakage
report that two-dimensional drain TFTs can reduce the device leakage current because of a lower current because of a lower lateral
electric field byfield
lateral electric changing its highest
by changing its location [17]. But [17].
highest location the LDD
But theareaLDD
shown areain shown
[17] is difficult
in [17] istodifficult
control
after adopting
to control aftertwo different
adopting twokinds of dopants.
different kinds ofThe TSD design
dopants. The TSD can form
design a partial
can form gatea overlapped
partial gate
lightly
overlapped lightly doped drain (P-GOLDD) that is similar to the structure shown in [17], lower
doped drain (P-GOLDD) that is similar to the structure shown in [17], to further to furtherthe
lateral electric
lower the field.
lateral The design
electric information
field. The of DGTSD-TFT
design information is shown in Figure
of DGTSD-TFT is shown 1. The DG is adopted
in Figure 1. The DG to
improve
is adopted thetodevice
improveON-state current.
the device The E-RSD
ON-state and P-GOLDD
current. The E-RSD used
andinP-GOLDD
TSD can overcome used in the TSDextra can
high electric
overcome thefield
extra inhigh
conventional DGin
electric field devices. Because
conventional DG wedevices.
combine the RSD
Because weand DG designs
combine the RSD in and
our
device,
DG designswe need in ouronedevice,
more mask, as compared
we need one moretomask, the conventional
as compared RSD or DG
to the devices, to RSD
conventional accomplish
or DG
our structure. This DGTSD-TFT can effectively lower the high DEF,
devices, to accomplish our structure. This DGTSD-TFT can effectively lower the high DEF, and and alleviate the impact ionization
phenomenon
alleviate the impactto repress the device
ionization kink effect. Moreover,
phenomenon to repress this the P-GOLDD
device kinkdesign effect.ensures
Moreover, that the
thistop P-
and
GOLDDbottom channels
design ensuresare that
not athe
symmetric
top and frame;
bottomthe channelare
channels length
not ais symmetric
defined by frame; the topthe one,channel
which
makes
length DGTSD-TFTs
is defined by the freetop
of the
one,misalignment
which makesproblem. DGTSD-TFTs free of the misalignment problem.

Figure 1.
Figure 1. Detailed design information for
for the
the double-gate
double-gate two-step
two-step source/drain
source/drain Poly-Si TFT.

2. Device Fabrication
2. Device Fabrication
To + poly-Si layer (200 nm) was first formed on oxidized silicon wafers,
To fabricate
fabricate the
the device,
device, an
an nn+ poly-Si layer (200 nm) was first formed on oxidized silicon wafers,
and
and this layer was then patterned to be the bottom
this layer was then patterned to be the bottom gate.
gate. After
After that,
that, an
an oxide
oxide (50
(50 nm)
nm) and
and an undoped
an undoped
α-Si (200 nm) were deposited. A phosphorous ion implantation (dose = 1 × 10 13 cm−2 at 40 keV) was
α-Si (200 nm) were deposited. A phosphorous ion implantation (dose = 1 × 1013 cm−2 at 40 keV) was
used,
used, and
and aa GOLDD
GOLDD area area was
was defined. Figure 22 illustrates
defined. Figure illustrates the
the main
main process
process steps
steps of
of aa DGTSD-TFT.
DGTSD-TFT.
An undoped α-Si with 100 nm thickness was formed, after which the active
An undoped α-Si with 100 nm thickness was formed, after which the active area was patterned. area was patterned.
Thereafter, this α-Si channel layer was recrystallized in a furnace for 24 h at 600 ◦ C to become the
Thereafter, this α-Si channel layer was recrystallized in a furnace for 24 h at 600 °C to become the
poly-Si
poly-Si film.
film. Then,
Then, aa top
top gate
gate oxide
oxide (50
(50 nm)
nm) and
and an
an n n++ poly-Si
poly-Sitop
topgate
gate(200
(200nm)
nm)were
wereininturn
turndeposited.
deposited.
After
After patterning the top gate region, a phosphorous implantation was performed to make the
patterning the top gate region, a phosphorous implantation was performed to make the drain
drain
and source regions. Subsequently, a 0.2 µm oxide was formed to serve as the passivation
and source regions. Subsequently, a 0.2 μm oxide was formed to serve as the passivation layer. Finally, layer. Finally,
contact areas were opened and an Al-Si-Cu metal layer was accomplished and defined to be the metal
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contact areas were opened and an Al-Si-Cu metal layer was accomplished and defined to be the metal
pads afterward. Further improved device characteristics can be achieved by applying an H2 or NH3
pads
pads afterward.
afterward. Further
Further improved
improved device
device characteristics
characteristics can
can be
be achieved
achieved by
by applying
applying an
an H
H22aor
or NH
NH33
treatment. The scanning electron microscopy (SEM) photography for our DGTSD-TFT with 0.5-μm
treatment. The
treatment. The scanning
scanning electron
electron microscopy
microscopy (SEM)
(SEM) photography
photography for for our
our DGTSD-TFT
DGTSD-TFT with
with aa 0.5-μm
0.5-µm
P-GOLDD region and a 300 nm RSD structure is shown in Figure 3.
P-GOLDD region
P-GOLDD region and
and aa 300
300 nm
nm RSD
RSD structure
structure is
is shown
shown inin Figure
Figure 3.
3.

(a) (b)
(a) (b)

(c) (d)
(c) (d)

(e)
(e)
Figure 2. Main fabrication processes of the double-gate two-step source/drain Poly-Si TFT: (a) Making
Figure
a bottom Mainand
2. Main
gate fabrication
fabrication processes
implanting of the double-gate
the GOLDD two-step
layer, (b) forming the source/drain
two-step partial GOLDD Poly-Si
Poly-Si TFT:
region, (c)(a) Making
depositing
aa bottom gate and implanting the GOLDD layer, (b) forming the partial GOLDD region, (c) depositing
channel, (d) defining the top gate and forming the drain/source areas, and (e) contact opening and
channel,
ametal pads(d) defining the top gate
forming. gate and
and forming
forming the
the drain/source
drain/source areas, and (e) contact opening and
metal pads forming.

Figure 3. SEM image of double-gate two-step source/drain Poly-Si TFT.

Figure 3. SEM image of double-gate two-step source/drain Poly-Si TFT.
3. Structure Simulation,3.Device
Figure SEM image of double-gate
Measurement andtwo-step source/drain Poly-Si TFT.
Discussion
In order to investigate the reduction of the DEF and impact ionization rate (IPR) in DGTSD-TFT
compared to a single top gate traditional device, two dimensional device numerical simulations were
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3. Structure Simulation, Device Measurement and Discussion

Coatings 2019, 9, 233 4 of 7
In order to investigate the reduction of the DEF and impact ionization rate (IPR) in DGTSD-TFT
compared to a single top gate traditional device, two dimensional device numerical simulations were
adopted by using the ISE-TCAD simulator [3,18]. Analyzing Analyzing the
the location
location and
and magnitude
magnitude of ofhigh
highDEF,
DEF,
which can be simulated using the simulation methodology in our previous work [16], can validate
the improvement of DEF with the proposed structure. Since the kink effect is caused by a great deal
of impact ionization, we can also achieve a suppressed kink effect device by designing a low IPR
structure [3]. Furthermore, the device leakage current can be predicted by simulating the device DEF
with a negative
negative gate
gate bias
bias[9].
[9].From
Fromthethesimulation
simulationresults
results(simulated
(simulated VdsV=ds10
atat =V 10and
V andVgs V
= gs = 5the
5 V), V),
the maximum DEF and IPR are 2.51 × 10 5 V/cm and 3.72 × 1027 27 cm−3−3 /s for our DGTSD structure,
maximum DEF and IPR are 2.51 × 10 V/cm and 3.72 × 10 cm /s for our DGTSD structure,
5

respectively, andand those

thosenumbers
numbersare are3.59 5 5V/cm and 2.73 × 1028
3.59××1010 V/cm and 2.73 × 1028 cm cm−−33/s
/sforforan
an STG
STG traditional
traditional DG TFT is modeled,
device. If a traditional modeled, these values are much higher than those in an STG device
because of the DG superposition effect [16]. The The detailed
detailed simulation
simulation comparisons for convention STG
and DG devices can be found in our previous publication [16]. A negative gate bias was simulated to
predict the
thedevices’
devices’leakage
leakagecharacteristics.
characteristics.The
Thesimulated maximum
simulated maximum DEF DEF(V gs(V=gs−=5−5
V and
V andV dsVds
= 5= V) is
5 V)
4.48 × 10 5 5V/cm for our DGTSD design and 7.07 × 1055 V/cm for a conventional structure. The reduced
is 4.48 × 10 V/cm for our DGTSD design and 7.07 × V/cm for a conventional structure. The reduced
DEF and IPR in DGTSD-TFT will be beneficial for lowering the device leakage current and mitigating
the kink phenomenon even when a DG structure is used. Moreover, Moreover, the operation
operation current
current of our
proposed device is increased.
increased. Figure
Figure 44 depicts
depicts the
themeasured outputVVds
measuredoutput ds-I ds curves for
ds curves for a DGTSD-TFT
and for an STG traditional device. The On-state current of DGTSD-TFT is about twice as large as that
of the STG traditional structure. It is obvious that the kink effect of our DGTSD-TFT
DGTSD-TFT can be overcome
and repressed effectively by virtue of the design of the P-GOLDD and E-RSD structure (two-step
source/draindesign).
source/drain design).These
Thesedesigned
designedstructures
structuresarearevery
very helpful
helpful inin decreasing
decreasing the the TFT
TFT high DEF
problem and in improving the device device performance.
performance.

Measured
Figure 4.4.Measured output Vds-IVdsdscurves
output -Ids curves
of ourof our double-gate
double-gate two-steptwo-step source/drain
source/drain structure
structure (DGTSD-
(DGTSD-TFT) and conventional traditional single top
TFT) and conventional traditional single top gate device. gate device.

The measured
The measured transfer
transfer performance
performance of of DGTSD-TFT
DGTSD-TFT and and aa conventional
conventional top top single
single gate
gate structure
structure
are shown in Figure 5. It can be seen that the leakage current, which is measured at Vgs = −5gsV =
are shown in Figure 5. It can be seen that the leakage current, which is measured at V and −5VVds
and V = 5 V, of the DGTSD-TFT (5.12 × 10 − 11 A) is lower than that of the traditional STG TFT
= 5 V, of the DGTSD-TFT (5.12 × 10 A) is lower than that of the traditional STG TFT (3.47 × 10 A).
ds −11 −10

(3.47 −10 A). This low leakage current is contributed by a low negative gate bias DEF that comes
× 10leakage
This low current is contributed by a low negative gate bias DEF that comes from a two-step
from a two-step
source/drain source/drain
design. Our P-GOLDD design.designOur P-GOLDD design is adrain
is a two-dimensional two-dimensional
doping profiles drain doping
structure,
profiles structure, which can provide a way to manipulate the location and physical
which can provide a way to manipulate the location and physical extent of the high electric field near extent of the high
electric field near the drain [17]. In addition, our extended RSD design can form
the drain [17]. In addition, our extended RSD design can form a partial thicker channel near the drain a partial thicker
channel
to lowernear the drain
the impact of to
thelower thefield
electric impact of the electric
superposition field superposition
problem [16]. Therefore, problem [16].DEF
the high Therefore,
can be
the high DEF can be reduced and moved away from the gate electrode to lower
reduced and moved away from the gate electrode to lower the leakage current [17]. The threshold the leakage current [17].
The threshold voltage of the proposed TFT and conventional TFT is 5.5 and
voltage of the proposed TFT and conventional TFT is 5.5 and 6 V (extracted at Vds = 0.1 V as 6 V (extracted at V = 0.1
ds Ids = 10V
as Idsrespectively.
nA), = 10 nA), respectively.
The measured The measured
subthreshold subthreshold
swing (S.S.)swing
and (S.S.) and mobility
effective effective (μ
mobility (µeff ) of
eff) of DGTSD-
DGTSD-TFT (conventional STG device) is 0.65 (1.34) V/dec and 20.07 (9.33) cm2 /V·s, at V ds = 0.1 V.
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TFT
TFT (conventional
(conventional STG
STG device)
device) is is 0.65
0.65 (1.34)
(1.34) V/dec
V/dec and
and 20.07
20.07 (9.33)
(9.33) cm
cm22/V·s,
/V·s, at
at VVdsds == 0.1
0.1 V.
V. These
These
improvements
improvements are
are attributed
attributed to
to the
the double
double gate
gate design.
design. The
The calculated
calculated ON/OFF
ON/OFF
These improvements are attributed to the double gate design. The calculated ON/OFF current ratios current
current ratios
ratios of
of our
our
of
proposal
proposal
our DGTSD
DGTSD
proposal DGTSDstructure
structure and
structure of
andandof theof conventional
the conventional
the conventionalone are
oneone 2.84
are are ×× 10
2.842.8410×and
6
6
10 3.34
and6 ×× 10
3.34 3.34
and
5
10 ×
5 ,, respectively.
respectively.
5 The
The
10 , respectively.
device
device
The breakdown
breakdown
device breakdownvoltages
voltages (V BR),
(VBR
voltages ),(Vdefined
defined as
as the
the drain
drain voltage
voltage when
when IIdsds == 22 nA
nA atat V
Vgsgs == 00 V
BR ), defined as the drain voltage when Ids = 2 nA at V gs = 0 V [3],
V [3],
[3], of
of the
the
proposed
proposed
of TFT
the proposed and
TFT and conventional
TFTconventional
and conventional STG
STGSTG TFT, are
TFT,TFT, 12.93
are are
12.93 and
and
12.93 8.97
8.97
and V, respectively.
V,V,respectively.
8.97 These
respectively.These improvements
These improvements
improvements
are
are attributed
are attributed to
attributed to the
to the reduced
the reduced DEF
reduced DEF structures.
DEF structures.
structures.

Figure 5.
Figure 5. Device
5.Device
Device transfer
transfer
transfer characteristics
characteristics
characteristics for for
for the
the the double-gate
double-gate
double-gate two-steptwo-step
two-step source/drain
source/drain
source/drain structure structure
structure (DGTSD-
(DGTSD-
(DGTSD-TFT)
TFT)
TFT) and
and for and
for the for the conventional
the conventional
conventional single
single top single
top gate top
gate TFT.
TFT. gate TFT.

A
A 3000
3000 sss hot-carrier
A 3000 hot-carrier stress test
hot-carrier stress
stress test for
test forboth
for bothstructures
both structureswas
structures wasperformed
was performedat
performed atV
at VVdsdsds== =
2020
20 VV
V and
and
and V V=gs
Vgsgs = 15
= 15
15 VV toV
to
to investigate
investigate
investigate thethe
the devices’
devices’
devices’ electrical
electrical
electrical reliability.
reliability.
reliability. Figure
Figure
Figure 6a 6a depicts
6a depicts
depicts thethe
the shift
shift
shift of of threshold
of threshold
threshold voltage
voltage
voltage (Vthth(V
(V th )
)) for
for
for
bothboth
both devices devices
devices after after stress.
after stress.
stress. The The
The V V
Vthth of of
th the
of the
the STG STG traditional
STG traditional
traditional devicedevice
device after after
after the the reliability
the reliability test
reliability test changes
test changes
changes
significantly,
significantly,
significantly, but but it
but it remains
it remains almost
remains almost
almost the the same
the same value
same value
value inin our
in our DGTSD-TFT.
our DGTSD-TFT.
DGTSD-TFT. Figure Figure
Figure 6b 6b
6b demonstrates
demonstrates
demonstrates that that
the
the current
the current variations
current variations
variations of of the
of the maximum
maximum ON-current
the maximum ON-currentdrop
ON-current drop(∆I
drop (ΔI ) and
andminimum
max)) and
(ΔImax
max minimumdrain
minimum draincurrent
drain current increase
current increase
increase
(∆I
(ΔI
(ΔImin
min ) after
min)) after
after thethe reliability
the reliability stress.
reliability stress.
stress. It It can
It can be
can be observed
be observed
observed that that the
that the ∆I
the ΔI and
max and
ΔImax
max and ΔI∆I
ΔIminmin for
min for the
for the STG
the STG traditional
STG traditional
traditional
device
device exhibit
device exhibit bigger
bigger changes
exhibit bigger changesthan
changes thanthose
than thoseof
those ofour
of ourDGTSD-TFT
our DGTSD-TFTafter
DGTSD-TFT afterthe
after the3000
the 3000ssshot
3000 hotcarrier
hot carriertest.
carrier test.The
test. The∆I
The ΔI
ΔImax
max
max
and
and ∆I
and ΔI
ΔImin are
min are
min 14.2%
are 14.2%
14.2% andand 34.1%
and 34.1%
34.1% for for
for our our DGTSD-TFT,
our DGTSD-TFT, respectively,
DGTSD-TFT, respectively,
respectively, whilewhile those
while those
those numbersnumbers
numbers are are 51.4%
are 51.4%
51.4% and and
and
69.4%
69.4%
69.4% for for the
for theconventional
the conventionalSTG
conventional STGdevice.
STG device.The
device. Thereliability
The reliability
reliability test
test
test indicates
indicates
indicates that
that
that our
our our designed
designed
designed E-RSD
E-RSD
E-RSD and
and andP-
P-
P-GOLDD
GOLDD
GOLDD structures structures
structures are
are
are beneficial
beneficial
beneficial forforfor achieving
achieving
achieving a reliable
aa reliable
reliable device.
device.
device.

(a)(a) (b)
(b)
Figure
Figure 6.
6. (a)
(a)The
(a) Theshift
The shiftof
shift ofofV thss and
Vth
V thand (b) the
(b)(b)
s and changes
thethe
changes of
of maximum
changes maximum
of maximum(minimum)
(minimum)
(minimum)IIdsds for
Idsthe
for fordouble-gate
the double-gate two-
two-
the double-gate
step
step source/drain
source/drain
two-step (DGTSD)
(DGTSD)
source/drain (DGTSD) TFT
TFT and
TFTconventional
and conventional one
one versus
and conventional versus the
the hot
one versus thecarrier
hot carrier
hot carrierstress time.
stressstress
time.time.
Coatings 2019, 9, 233 6 of 7

These experimental results show that the proposed double-gate accompanied with the two-step
source/drain design can increase the device’s operation current and lower its drain electric field as
compared with a traditional STG structure. Additionally, the proposed device’s OFF-state leakage
current can be reduced, and no profound kink effect is observed. In addition, the proposed structure
has no misalignment problem that is commonly encountered in traditional DG devices [13].

4. Conclusions
In this paper, a DG poly-Si TFT with a two-step source/drain structure for a high current and low
DEF design is proposed and investigated. The P-GOLDD and E-RSD design can effectively reduce the
DEF to decrease the drain side IPR and quell the device kink effect. Our DG design demonstrates a
higher ON-state current than the traditional STG structure. The proposal DGTSD structure can achieve
a lower leakage current and a better subthreshold swing performance as compared with the traditional
STG device. Therefore, the ON/OFF current ratio of our DGTSD structure is obtained. All these
characteristics make the proposed DGTSD structure an attractive device design in fully integrated
AM-LCDs for system-on-panel high-performance analog or digital circuits.

Author Contributions: Conceptualization, F.-T.C.; Methodology, F.-T.C. and C.-P.H.; Resources, H.-C.C., T.-K.K.
and C.-H.C.; Software, C.-P.H. and Y.-T.T.; Formal Analysis, C.-P.H., F.-T.C. and H.-C.C.; Writing-Original Draft
Preparation, C.-P.H.; Writing-Review and Editing, F.-T.C., H.-C.C. and Y.-T.T.
Funding: This research was funded by the Ministry of Science and Technology of Taiwan, Grant MOST
No. 107-2221-E-035-060.
Conflicts of Interest: The authors declare no conflict of interest.

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