PD - 94338A

IRF3808S
AUTOMOTIVE MOSFET
Typical Applications
IRF3808L
● Integrated Starter Alternator HEXFET® Power MOSFET
● 42 Volts Automotive Electrical Systems D
Benefits VDSS = 75V
● Advanced Process Technology
● Ultra Low On-Resistance
● Dynamic dv/dt Rating
RDS(on) = 0.007Ω
G
● 175°C Operating Temperature
● Fast Switching ID = 106AV
S
● Repetitive Avalanche Allowed up to Tjmax
Description
Designed specifically for Automotive applications, this Advanced
Planar Stripe HEXFET ® Power MOSFET utilizes the latest pro-
cessing techniques to achieve extremely low on-resistance per
silicon area. Additional features of this HEXFET power MOSFET
are a 175°C junction operating temperature, low RθJC, fast switch-
ing speed and improved repetitive avalanche rating. This combina-
tion makes the design an extremely efficient and reliable choice for
use in higher power Automotive electronic systems and a wide D2Pak TO-262
variety of other applications. IRF3808S IRF3808L

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 106V
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 75V A
IDM Pulsed Drain Current Q 550
PD @TC = 25°C Power Dissipation 200 W
Linear Derating Factor 1.3 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche EnergyR 430 mJ
IAR Avalanche CurrentQ 82 A
EAR Repetitive Avalanche EnergyW See Fig.12a, 12b, 15, 16 mJ
dv/dt Peak Diode Recovery dv/dt S 5.5 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.75 °C/W
RθJA Junction-to-Ambient (PCB Mounted, Steady State)** ––– 40

HEXFET(R) is a registered trademark of International Rectifier.

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IRF3808S/IRF3808L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 75 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.086 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 5.9 7.0 mΩ VGS = 10V, ID = 82A T
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 100 ––– ––– S VDS = 25V, ID = 82A
––– ––– 20 VDS = 75V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 60V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 150 220 ID = 82A
Qgs Gate-to-Source Charge ––– 31 47 nC VDS = 60V
Qgd Gate-to-Drain ("Miller") Charge ––– 50 76 VGS = 10VT
td(on) Turn-On Delay Time ––– 16 ––– VDD = 38V
tr Rise Time ––– 140 ––– ID = 82A
ns
td(off) Turn-Off Delay Time ––– 68 ––– RG = 2.5Ω
tf Fall Time ––– 120 ––– VGS = 10V T
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH G
from package
LS Internal Source Inductance ––– 7.5 –––
and center of die contact S

Ciss Input Capacitance ––– 5310 ––– VGS = 0V

Coss Output Capacitance ––– 890 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 130 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 6010 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 570 ––– VGS = 0V, VDS = 60V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance U ––– 1140 ––– VGS = 0V, VDS = 0V to 60V

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
D
IS Continuous Source Current MOSFET symbol
––– ––– 106V
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 550

(Body Diode) Q p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 82A, VGS = 0VT
trr Reverse Recovery Time ––– 93 140 ns TJ = 25°C, IF = 82A
Qrr Reverse RecoveryCharge ––– 340 510 nC di/dt = 100A/µs T
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: U Coss eff. is a fixed capacitance that gives the same charging time
Q Repetitive rating; pulse width limited by as Coss while VDS is rising from 0 to 80% VDSS .
max. junction temperature. (See fig. 11). V Calculated continuous current based on maximum allowable
R Starting TJ = 25°C, L = 0.130mH junction temperature. Package limitation current is 75A.
RG = 25Ω, IAS = 82A. (See Figure 12). W Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
S ISD ≤ 82A, di/dt ≤ 310A/µs, VDD ≤ V(BR)DSS, avalanche performance.
TJ ≤ 175°C ** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
T Pulse width ≤ 400µs; duty cycle ≤ 2%. For recommended footprint and soldering techniques refer to
application note #AN-994.
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 IRF3808S/IRF3808L

 
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V
I D, Drain-to-Source Current (A)

I D, Drain-to-Source Current (A)

100 100
4.5V

4.5V

10 10

1
 20µs PULSE WIDTH
T J= 25 ° C
1
 20µs PULSE WIDTH
T J= 175 ° C

0.1 1 10 100 0.1 1 10 100

V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000.00

3.0
I D = 137A
ID, Drain-to-Source Current (Α )

2.5
TJ = 175°C
RDS(on) , Drain-to-Source On Resistance

2.0
(Normalized)

100.00 1.5

T J = 25°C 1.0

0.5

VDS = 15V
20µs PULSE WIDTH 
V GS = 10V
10.00 0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
1.0 3.0 5.0 7.0 9.0 11.0 13.0 15.0 TJ , Junction Temperature ( °C)
VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature
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IRF3808S/IRF3808L

100000


12
VGS = 0V, f = 1 MHZ 
ID = 82A
V DS = 60V
Ciss = Cgs + Cgd, Cds SHORTED V DS = 37V
Crss = Cgd 10 V DS = 15V

Coss = Cds + Cgd

C, Capacitance(pF)

VGS, Gate-to-Source Voltage (V)

10000 8

Ciss
6

1000 Coss 4

Crss
100 0
0 40 80 120 160
1 10 100
QG , Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.00 10000

OPERATION IN THIS AREA

LIMITED BY R DS (on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100.00 T J = 175°C 1000

10.00 100
100µsec
T J = 25°C

1.00 10 1msec
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse 10msec
0.10 1
0.0 0.5 1.0 1.5 2.0 1 10 100 1000
VSD , Source-toDrain Voltage (V) VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRF3808S/IRF3808L

120
RD

LIMITED BY PACKAGE VDS

100 VGS
D.U.T.
RG
+
80 -VDD
I D , Drain Current (A)

10V
60
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

40
Fig 10a. Switching Time Test Circuit

20 VDS
90%
0
25 50 75 100 125 150 175

TC , Case Temperature ( ° C)

10%
VGS
Fig 9. Maximum Drain Current Vs.
td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

1
(Z thJC )

D = 0.50

0.20
Thermal Response


0.1
0.10

P DM
0.05
t1

0.02 t2



SINGLE PULSE
0.01 (THERMAL RESPONSE)
Notes:
1. Duty factor D = t1/ t 2
2. Peak T J = P DM x Z thJC +T C
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10

t 1, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF3808S/IRF3808L


800
1 5V
ID
TOP 34A
58A
L D R IV E R 640 BOTTOM 82A
VDS

E AS , Single Pulse Avalanche Energy (mJ)

RG D .U .T + 480
V
- DD
IA S A
20V
tp 0 .0 1 Ω
320

Fig 12a. Unclamped Inductive Test Circuit

V (B R )D SS
160
tp

0
25 50 75 100 125 150

Starting Tj, Junction Temperature ( ° C)

IAS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
QG

10 V
QGS QGD 3.5
VGS(th) Gate threshold Voltage (V)

VG 3.0

ID = 250µA
Charge 2.5

Fig 13a. Basic Gate Charge Waveform

Current Regulator
Same Type as D.U.T.
2.0

50KΩ

12V .2µF 1.5

.3µF

+
V
D.U.T. - DS
1.0
VGS -75 -50 -25 0 25 50 75 100 125 150 175 200

3mA T J , Temperature ( °C )

IG ID
Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature
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 IRF3808S/IRF3808L

10000

1000
Duty Cycle = Single Pulse Allowed avalanche Current vs
Avalanche Current (A)

avalanche pulsewidth, tav

100 assuming ∆ Tj = 25°C due to
0.01 avalanche losses. Note: In no
case should Tj be allowed to
0.05 exceed Tjmax
10
0.10

0.1
1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

500 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 10% Duty Cycle 1. Avalanche failures assumption:
ID = 140A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

400
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
300 not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
200 4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
100
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
0 t av = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = t av ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = ∆T/ ZthJC

Fig 16. Maximum Avalanche Energy ∆T/ [1.3·BV·Zth]
Iav = 2∆
Vs. Temperature EAS (AR) = PD (ave)·tav
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IRF3808S/IRF3808L

Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T* • Low Stray Inductance
• Ground Plane
S
• Low Leakage Inductance
Current Transformer
-

+
R
T
- +
-

Q
RG • dv/dt controlled by RG +
• ISD controlled by Duty Factor "D" VDD
-
• D.U.T. - Device Under Test
VGS

* Reverse Polarity of D.U.T for P-Channel

Driver Gate Drive

P.W.
Period D=
P.W. Period

[VGS=10V ] ***

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
[VDD]
Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% [ ISD ]

*** VGS = 5.0V for Logic Level and 3V Drive Devices

Fig 17. For N-channel HEXFET® power MOSFETs

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 IRF3808S/IRF3808L

D2Pak Package Outline

1 0.54 (.4 15) -B - 1 0.16 (.4 00 )

1 0.29 (.4 05) 4.69 (.1 85) RE F.
1.4 0 (.055 ) 4.20 (.1 65)
-A- 1.3 2 (.05 2)
M AX. 1.2 2 (.04 8)
2
6.47 (.2 55 )
6.18 (.2 43 )

1.7 8 (.07 0) 15 .4 9 (.6 10) 2.7 9 (.110 )

1.2 7 (.05 0) 1 3 14 .7 3 (.5 80) 2.2 9 (.090 )

5 .28 (.20 8) 2.61 (.1 03 )

4 .78 (.18 8) 2.32 (.0 91 )

8.8 9 (.3 50 )
1.40 (.0 55) 1.3 9 (.0 5 5) R E F.
3X
1.14 (.0 45) 0 .93 (.03 7 ) 0.5 5 (.022 ) 1.1 4 (.0 4 5)
3X 0.4 6 (.018 )
0 .69 (.02 7 )
5 .08 (.20 0) 0 .25 (.01 0 ) M B A M M IN IM U M R E CO M M E ND E D F O O TP R IN T

1 1.43 (.4 50 )

NO TE S: LE A D A SS IG N M E N TS 8.89 (.3 50 )
1 D IM EN S IO N S A FTER SO L D ER D IP. 1 - G A TE
2 D IM EN S IO N IN G & TO LE RA N C IN G PE R A N S I Y1 4.5M , 198 2. 2 - D R AIN 17 .78 (.70 0)
3 - S O U RC E
3 C O N TRO L LIN G D IM EN SIO N : IN C H .
4 H E ATSINK & L EA D D IM EN S IO N S D O N O T IN C LU D E B UR R S.
3 .8 1 (.15 0)

2.5 4 (.100 )
2 .08 (.08 2) 2X
2X

D2Pak Part Marking Information

THIS IS AN IRF530S WITH PART NUMBER

LOT CODE 8024 INTERNATIONAL
ASSEMBLED ON WW 02, 2000 RECTIFIER F530S
IN THE ASSEMBLY LINE "L" LOGO
DATE CODE
YEAR 0 = 2000
ASSEMBLY
LOT CODE WEEK 02
LINE L

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IRF3808S/IRF3808L

TO-262 Package Outline

TO-262 Part Marking Information

EXAMPLE: THIS IS AN IRL3103L

LOT CODE 1789 PART NUMBER
INTERNATIONAL
ASSEMBLED ON WW 19, 1997
RECTIFIER
IN THE ASSEMBLY LINE "C" LOGO
DATE CODE
YEAR 7 = 1997
ASSEMBLY
LOT CODE WEEK 19
LINE C

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 IRF3808S/IRF3808L

D2Pak Tape & Reel Information

TRR

1 .6 0 (.0 6 3 )
1 .5 0 (.0 5 9 )
1 .6 0 (.0 6 3 )
4 .10 (.1 6 1 ) 1 .5 0 (.0 5 9 )
3 .90 (.1 5 3 ) 0 .3 6 8 (.0 1 4 5 )
0 .3 4 2 (.0 1 3 5 )

F E E D D I R E C T IO N 1 .8 5 (.0 73 ) 1 1 .6 0 (.4 5 7 )
1 .6 5 (.0 65 ) 1 1 .4 0 (.4 4 9 ) 2 4 .3 0 (.9 5 7 )
1 5 .4 2 (.6 0 9 )
2 3 .9 0 (.9 4 1 )
1 5 .2 2 (.6 0 1 )
TRL
1 .7 5 (.0 6 9 )
1 0 .9 0 (.4 2 9 ) 1 .2 5 (.0 4 9 )
1 0 .7 0 (.4 2 1 ) 4 .7 2 (.1 3 6 )
1 6 .1 0 ( .6 3 4 ) 4 .5 2 (.1 7 8 )
1 5 .9 0 ( .6 2 6 )

F E E D D IR E C T IO N

1 3 .5 0 (.5 3 2 ) 2 7 .4 0 (1 .0 7 9 )
1 2 .8 0 (.5 0 4 ) 2 3 .9 0 (.9 4 1 )

330.00 6 0 .0 0 (2 .3 6 2)
(14.1 73) M IN .
MA X .

3 0 .4 0 (1 .1 9 7 )
N O TE S : M A X.
1 . C O M F O R M S T O EIA-4 1 8 . 26 .40 (1.039) 4
2 . C O N TR O L L IN G D IM EN SIO N : M IL L IM ET ER . 24 .40 (.961)
3 . D IM E NS IO N M E A SU R ED @ HU B .
3
4 . IN C L U D E S FL A N G E D IST O R T IO N @ O U TE R E D G E .

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.03/02
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/