Virtual Memory

LECTURE 3
Address
Translation
Page fault Step 1: Initiate Page Read

 When a referenced page is uncached Processor

 It is to be brought from secondary storage Step 3:

Interrupt indicating
Cache Page Transfer
Completion

Memory-I/O Bus

Memory Disk Controller

Step 2: Page Transfer via DMA

Disk Disk
Virtual Memory Problems
 Table Fragmentation
Wastage of main memory space due to occupancy by page tables
 Internal Fragmentation
The last page of a process usually remains partially empty
This results in space wastage when assigned to a page frame
This space cannot be used by any other page
 Every Instruction/data access from main memory effectively means two
main memory accesses
 Translation Lookaside Buffer (TLB)
A small fully-associative cache that holds address translation information for
most recently referenced pages
Integrated
operation
of a TLB and
Cache
These are some typical values of a TLB:
 size: 12 bits – 4,096 entries.
 hit time: 0.5 – 1 clock cycle.
 miss penalty: 10 – 100 clock cycles.
 miss rate: 0.01 – 1%
  Virtual address space is divided into variable-
sized segments
 A segment is a logically related group of
instructions (e.g. a function, or procedure) or
data (e. g. an array or a structure)
 They are defined by programmers
A segment must be contiguous in physical
Another 
memory

scheme of  It does not suffer from internal fragmentation

It does suffer from external fragmentation
managing VM -


 Spaces wasted between segments which

Segmentation are not big enough to accommodate a
single segment (holes)
 Frequent storage compaction or garbage
collection (combining small holes into one
big space) is required to evade the space
wastage
 Placing a segment in physical memory also
requires some placement algorithm