US010593812B2

(12) United States Patent ( 10 ) Patent No.: US 10,593,812 B2

Ramkumar et al. (45 ) Date of Patent: *Mar. 17 , 2020

( 54 ) RADICAL OXIDATION PROCESS FOR (58 ) Field of Classification Search

FABRICATING A NONVOLATILE CHARGE ??? ............... B82Y 10/00 ; HO1L 21/0214 ; HOLL
TRAP MEMORY DEVICE 21/02164; HO1L 21/0217 ; HO1L 21/022 ;
(Continued )
(71) Applicant: LONGITUDE FLASH MEMORY References Cited
SOLUTIONS LTD ., Dublin ( IE ) (56 )
U.S. PATENT DOCUMENTS
(72) Inventors: Krishnaswamy Ramkumar, San Jose ,
CA (US ); Sagy Charel Levy , Zichron 4,257,832 A 3/1981 Schwabe et al .
Yaakov (IL ); Jeong Soo Byun , 4,395,438 A 7/1983 Chiang
Cupertino , CA (US) (Continued )
(73) Assignee : LONGITUDE FLASH MEMORY FOREIGN PATENT DOCUMENTS
SOLUTIONS LTD ., Dublin ( IE ) CN 1107254 A 8/1995
CN 1801478 A 7/2006
( * ) Notice : Subject to any disclaimer , the term of this
patent is extended or adjusted under 35 ( Continued )
U.S.C. 154 (b ) by 0 days . OTHER PUBLICATIONS
This patent is subject to a terminal dis
claimer. European Search Report for European Application No. 13767422.2
dated Mar. 30 , 2017 ; 6 pages .
(21) Appl. No .: 16 /000,015 (Continued )
(22 ) Filed : Jun . 5 , 2018 Primary Examiner — Thanh T Nguyen
(74 ) Attorney, Agent, or Firm — Kunzler Bean &
(65) Prior Publication Data Adamson
US 2018/0351004 A1 Dec. 6 , 2018
(57) ABSTRACT
A method for fabricating a nonvolatile charge trap memory
Related U.S. Application Data device is described . The method includes subjecting a sub
(63 ) Continuation of application No. 14 /605,231, filed on strate to a first oxidation process to form a tunneloxide layer
Jan. 26 , 2015 , now Pat. No. 10,304,968, which is a overlying a polysilicon channel, and forming over the tunnel
oxide layer a multi-layer charge storing layer comprising an
(Continued ) oxygen -rich , first layer comprising a nitride, and an oxygen
(51) Int. Cl. lean , second layer comprising a nitride on the first layer. The
HOIL 29/792 (2006.01) substrate is then subjected to a second oxidation process to
HOIL 21/28 (2006.01)
consume a portion of the second layer and form a high
temperature -oxide (HTO ) layer overlying the multi-layer
(Continued ) charge storing layer. The stoichiometric composition of the
( 52 ) U.S. CI. first layer results in it being substantially trap free, and the
CPC HOIL 29/7926 ( 2013.01 ); B82 Y 10/00 stoichiometric composition of the second layer results in it
(2013.01); HOIL 21/022 (2013.01); being trap dense . The second oxidation process can com
(Continued ) (Continued )
1400

1414

1420

1402
1418
1404
1421

1419
1406
1416
1410 1412 1410
1408
 US 10,593,812 B2
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1500

FORM A TUNNELING OXIDE LAYER OVER A SILICON CONTAINING

LAYER ON A SURFACE OF A SUBSTRATE
1502

FORM A BOTTOM NITRIDE LAYER OF A MULTI-LAYER CHARGE STORING

LAYER ON A SURFACE OF THE TUNNELING OXIDE LAYER
1504

FORM AN ANTI- TUNNELING LAYER ON A SURFACE OF THE BOTTOM

NITRIDE LAYER
1506

FORM A TOP NITRIDE LAYER OF THE MULTI-LAYER CHARGE STORING

LAYER ON A SURFACE OF THE ANTI - TUNNELING LAYER

1508

FORM A HTO LAYER ON A SURFACE OF THE SECOND LAYER OF THE

MULTI-LAYER CHARGE STORING LAYER

FINISH

FIG . 15
U.S. Patent Mar. 17 , 2020 Sheet 19 of 24 US 10,593,812 B2

1600

1610

1612

-1602

1604 1608

1606

FIG . 16A
U.S. Patent Mar. 17 , 2020 Sheet 20 of 24 US 10,593,812 B2

1612

1602
1620
1626 1618
1628 -1614
1624 1616
1622

1606

FIG . 16B
U.S. Patent Mar. 17 , 2020
2 Sheet 21 of 24 US 10,593,812 B2

1700

1712

T 1702

1708 1710

1706

FIG . 17A
1726

1700

-1714 1702
-1720
1702 -1724
-1722 1712
1716
1718

1706

FIG . 17B FIG . 17C

U.S. Patent Mar. 17 , 2020 Sheet 22 of 24 US 10,593,812 B2

1800

1804
1808
M810

11812

1802 10B

1814

FIG . 18A 1806

1810
OOOO

1802 1816 1818 1812

151808 151820

FIG . 18B
U.S. Patent Mar. 17 , 2020 Sheet 23 of 24 US 10,593,812 B2

1910 19107
With 1908 1908
1902 1902
1912
1904 1904
21906 1906

FIG . 19A FIG . 19B

1918 1916 1914 1918 1916 1914
111910 19107
1912 11908 1908 1920
11902 1902
1904 11906 1906 1904

FIG . 19C FIG . 19D

1924 1922
1918 1916 1914 1928 1930
1910 19104
1926 1908 1908 1924
1902 1902 /
1904 1906 1906 1904

FIG . 19E FIG . 19F

U.S. Patent Mar. 17 , 2020 Sheet 24 of 24 US 10,593,812 B2

2008 2008

2002 2002
2002 ,
2012
20044 2004
2010 2006 2010 2006

FIG . 20A FIG . 20B

2020
2008 2016 2016b 2016a

2002 2010
2012

2010 2006 2018 2014

FIG . 20C FIG . 20D

2008 2026 2026

2002 2002
2022 2022
2010 2006 2010 2006

FIG . 20E FIG . 20F

 US 10,593,812 B2
1 2
RADICAL OXIDATION PROCESS FOR One problem with conventional SONOS transistors is the
FABRICATING A NONVOLATILE CHARGE poor data retention in the nitride or oxy -nitride layer 106B
TRAP MEMORY DEVICE that limits semiconductor device 100 lifetime and its use in
several applications due to leakage current through the layer.
CROSS -REFERENCE TO RELATED 5
APPLICATIONS BRIEF DESCRIPTION OF THE DRAWINGS

This application is a continuation of U.S. patent applica Embodiments of the present invention are illustrated by
tion Ser. No. 14 /605,231, filed Jan. 26 , 2015 , which is a 10
way of example , and not limitation , in the figures of the
continuation of U.S.patent application Ser.No. 13 /539,458 , accompanying drawings in which :
filed Jul. 1 , 2012 , now U.S. Pat. No. 8,940,645 , issued Jan. FIG . 1 illustrates a cross -sectional view of a conventional
27, 2015 , which is a continuation -in -part of U.S. patent nonvolatile charge trap memory device .
application Ser. No. 12 / 197,466 , filed Aug. 25 , 2008 , now FIG . 2 illustrates a cross -sectional view of an oxidation
U.S. Pat. No. 8,318,608 , issued Nov. 27 , 2012 , which is a 15 chamber of a batch -processing tool, in accordance with an
continuation ofU.S. patent application Ser. No. 12/ 124,855 , embodiment of the present invention .
filed May 21, 2008 , now U.S. Pat. No. 8,283,261, issued FIG . 3 depicts a Flowchart representing a series of opera
Oct. 9 , 2012 , which claims the benefit of priority under 35 tions in a method for fabricating a nonvolatile charge trap
U.S.C. 119(e ) to U.S. Provisional Patent Application Ser . memory device , in accordance with an embodiment of the
No. 60 /940,139 , filed May 25 , 2007, and U.S. Provisional 20 present invention .
Application No. 60/986,637 , filed Nov. 9 , 2007 , all of which FIG . 4A illustrates a cross - sectional view of a substrate
are incorporated by reference herein in their entirety . having a charge trapping layer formed thereon , correspond
ing to operation 302 from the Flowchart of FIG . 3 , in
TECHNICAL FIELD accordance with an embodiment of the present invention .
25 FIG . 4B illustrates a cross -sectional view of a substrate
Embodiments of the present invention are in the field of having a charge trapping layer with a blocking dielectric
Semiconductor Fabrication and, in particular, Semiconduc layer formed thereon , corresponding to operation 304 from
tor Device Fabrication . the Flowchart of FIG . 3 , in accordance with an embodiment
of the present invention .
BACKGROUND 30 FIG . 5 depicts a Flowchart representing a series of opera
tions in a method for fabricating a nonvolatile charge trap
For the past several decades, the scaling of features in memory device , in accordance with an embodiment of the
integrated circuits has been a driving force behind an present invention .
ever-growing semiconductor industry . Scaling to smaller FIG . 6A illustrates a cross -sectional view of a substrate ,
and smaller features enables increased densities of func- 35 corresponding to operation 502 from the Flowchart of FIG .
tional units on the limited real estate of semiconductor chips . 5 , in accordance with an embodiment of the present inven
For example, shrinking transistor size allows for the incor tion .
poration of an increased number of memory devices on a FIG . 6B illustrates a cross -sectional view of a substrate
chip , lending to the fabrication of products with increased having a first dielectric layer formed thereon , corresponding
capacity. The drive for ever-more capacity , however , is not 40 to operation 504 from the Flowchart of FIG.5 , in accordance
without issue. The necessity to optimize the performance of with an embodiment of the present invention .
each device becomes increasingly significant. FIG . 6C illustrates a cross -sectional view of a substrate
Non -volatile semiconductor memories typically use having a charge trapping layer formed thereon , correspond
stacked floating gate type field -effect- transistors. In such ing to operation 508 from the Flowchart of FIG . 5 , in
transistors, electrons are injected into a floating gate of a 45 accordance with an embodiment of the present invention .
memory cell to be programmed by biasing a control gate and FIG . 6D illustrates a cross -sectional view of a substrate
grounding a body region of a substrate on which thememory having a charge trapping layer with a blocking dielectric
cell is formed . An oxide-nitride -oxide (ONO ) stack is used layer formed thereon , corresponding to operation 510 from
as either a charge storing layer, as in a semiconductor-oxide the Flowchart of FIG . 5 , in accordance with an embodiment
nitride -oxide-semiconductor (SONOS) transistor , or as an 50 of the present invention .
isolation layer between the floating gate and control gate, as FIG . 6E illustrates a cross - sectional view of a nonvolatile
in a split gate flash transistor. FIG . 1 illustrates a cross charge trap memory device, in accordance with an embodi
sectional view of a conventional nonvolatile charge trap ment of the present invention .
memory device. FIG . 7A illustrates a cross -sectional view of a substrate
Referring to FIG . 1, semiconductor device 100 includes a 55 including first and second exposed crystal planes, in accor
SONOS gate stack 104 including a conventional ONO dance with an embodiment of the present invention .
portion 106 formed over a silicon substrate 102. Semicon FIG . 7B illustrates a cross -sectional view of the substrate
ductor device 100 further includes source and drain regions including first and second crystal planes and having a
110 on either side of SONOS gate stack 104 to define a dielectric layer formed thereon , in accordance with an
channel region 112. SONOS gate stack 104 includes a 60 embodiment of the present invention .
poly -silicon gate layer 108 formed above and in contact with FIG . 8 illustrates an arrangement of process chambers in
ONO portion 106. Polysilicon gate layer 108 is electrically a cluster tool, in accordance with an embodiment of the
isolated from silicon substrate 102 by ONO portion 106 . present invention.
ONO portion 106 typically includes a tunnel oxide layer FIG . 9 depicts a Flowchart representing a series of opera
106A , a nitride or oxynitride charge -trapping layer 106B , 65 tions in a method for fabricating a nonvolatile charge trap
and a top oxide layer 106C overlying nitride or oxynitride memory device , in accordance with an embodiment of the
layer 106B . present invention .
 US 10,593,812 B2
3 4
FIG . 10A illustrates a cross -sectional view of a substrate , FIG . 19A through 19F illustrate a gate first scheme for
in accordance with an embodiment of the present invention . fabricating the non- planar multigate device of FIG . 18A .
FIG . 10B illustrates a cross - sectional view of a substrate FIG . 20A through 20F illustrate a gate last scheme for
having a tunnel dielectric layer formed thereon , correspond fabricating the non -planar multigate device of FIG . 18A .
ing to operation 402 from the Flowchart of FIG . 4 , in 5
accordance with an embodiment of the present invention . DETAILED DESCRIPTION
FIG . 10C illustrates a cross -sectional view of a substrate
having a charge -trapping layer formed thereon , correspond Embodiments of a non - volatile charge trap memory
ing to operation 406 from the Flowchart of FIG . 4 , in device integrated with logic devices are described herein
accordance with an embodiment of the present invention . 10 with reference to figures . However, particular embodiments
FIG . 10D illustrates a cross - sectional view of a substrate may be practiced without one or more of these specific
having a top dielectric layer formed thereon, corresponding details, or in combination with other known methods, mate
to operation 408 from the Flowchart of FIG . 4 , in accordance rials , and apparatuses . In the following description , numer
with an embodiment of the present invention . ous specific details are set forth , such as specific materials,
FIG . 10E illustrates a cross-sectional view of a nonvola- 15 dimensions and processes parameters etc. to provide a
tile charge trap memory device , in accordance with an thorough understanding of the present invention . In other
embodiment of the present invention . instances,well -known semiconductor design and fabrication
FIG . 11 depicts a Flowchart representing a series of techniques have not been described in particular detail to
operations in a method for fabricating a nonvolatile charge avoid unnecessarily obscuring the present invention . Refer
trap memory device, in accordance with an embodiment of 20 ence throughout this specification to “ an embodiment”
the present invention . means that a particular feature, structure , material, or char
FIG . 12A illustrates a cross -sectional view of a substrate acteristic described in connection with the embodiment is
having a tunnel dielectric layer formed thereon , correspond included in at least one embodiment of the invention. Thus,
ing to operation 602 from the Flowchart of FIG . 6 , in the appearances of the phrase “ in an embodiment” in various
accordance with an embodiment of the present invention . 25 places throughout this specification are not necessarily refer
FIG . 12B illustrates a cross -sectional view of a substrate ring to the same embodiment of the invention . Furthermore,
having an oxygen - rich silicon oxy -nitride portion of a the particular features, structures , materials, or characteris
charge-trapping layer formed thereon , corresponding to tics may be combined in any suitable manner in one ormore
operation 606 from the Flowchart of FIG . 6 , in accordance embodiments .
with an embodiment of the present invention . 30 Methods to fabricate a nonvolatile charge trap memory
FIG . 12C illustrates a cross - sectional view of a substrate device are described herein . In the following description ,
having a silicon -rich silicon oxy -nitride portion of a charge numerous specific details are set forth , such as specific
trapping layer formed thereon , corresponding to operation dimensions, in order to provide a thorough understanding of
610 from the Flowchart of FIG . 6 , in accordance with an the present invention . It will be apparent to one skilled in the
embodiment of the present invention . 35 art that the present invention may be practiced without these
FIG . 12D illustrates a cross -sectional view of a substrate specific details . In other instances, well -known processing
having a top dielectric layer formed thereon , corresponding steps, such as patterning steps or wet chemical cleans, are
to operation 612 from the Flowchart of FIG . 6 , in accordance not described in detail in order to not unnecessarily obscure
with an embodiment of the present invention . the present invention. Furthermore, it is to be understood
FIG . 12E illustrates a cross -sectional view of a nonvola- 40 that the various embodiments shown in the Figures are
tile charge trap memory device , in accordance with an illustrative representations and are not necessarily drawn to
embodiment of the present invention . scale .
FIG . 13A illustrates a cross - sectional view of a substrate Disclosed herein is a method to fabricate a nonvolatile
including first and second exposed crystal planes, in accor charge trap memory device. A substrate may first be pro
dance with an embodiment of the present invention . 45 vided having a charge-trapping layer disposed thereon. In
FIG . 13B illustrates a cross - sectional view of the substrate one embodiment, a portion of the charge -trapping layer is
including first and second crystal planes and having a then oxidized to form a blocking dielectric layer above the
dielectric layer formed thereon , in accordance with an charge- trapping layer by exposing the charge -trapping layer
embodiment of the present invention . to a radical oxidation process.
FIG . 14 illustrates a cross -sectional view of a nonvolatile 50 Formation of a dielectric layer by a radical oxidation
charge trap memory device including an ONONO stack . process may provide higher quality films than processes
FIG . 15 depicts a Flowchart representing a series of involving steam growth , i.e. wet growth processes. Further
operations in a method for fabricating a nonvolatile charge more , a radical oxidation process carried out in a batch
trap memory device including an ONONO stack , in accor processing chamber may provide high quality films without
dance with an embodiment of the present invention . 55 impacting the throughput (wafers /Hr) requirements that a
FIG . 16A illustrates a non -planar multigate device includ fabrication facility may require. By carrying out the radical
ing a split charge - trapping region . oxidation process at temperatures compatible with such a
FIG . 16B illustrates a cross -sectional view of the non chamber , such as temperatures approximately in the range of
planar multigate device of FIG . 16A . 600-900 degrees Celsius , the thermalbudget tolerated by the
FIGS. 17A and 17B illustrate a non -planar multigate 60 substrate and any other features on the substrate may not be
device including a split charge -trapping region and a hori impacted to the extent typical of processes over 1000
zontal nanowire channel. degrees Celsius. In accordance with an embodiment of the
FIG . 17C illustrates a cross - sectional view of a vertical present invention , a radical oxidation process involving
string of non-planar multigate devices of FIG . 17A . flowing hydrogen (H2) and oxygen (O2) gas into a batch
FIGS. 18A and 18B illustrate a non -planar multigate 65 processing chamber is carried out to effect growth of a
device including a split charge - trapping region and a vertical dielectric layer by oxidation consumption of an exposed
nanowire channel. substrate or film . In one embodiment, multiple radical
 US 10,593,812 B2
5 6
oxidation processes are carried out to provide a tunnel of the present invention . Referring to operation 304 of
dielectric layer and a blocking dielectric layer for a non Flowchart 300 and corresponding FIG . 4B , a blocking
volatile charge trap memory device . These dielectric layers dielectric layer 406 is formed on charge - trapping layer 404 .
may be of very high quality , even at a reduced thickness. In In accordance with an embodiment of the present invention,
one embodiment, the tunnel dielectric layer and theblocking 5 blocking dielectric layer 406 is formed by oxidizing region
dielectric layer are both denser and are composed of sub 404B of the charge- trapping layer by exposing the charge
stantially fewer hydrogen atoms/cm3 than a tunnel dielectric trapping layer to a radical oxidation process . In that embodi
layer or a blocking dielectric layer formed by wet oxidation ment , region 404A of the original charge trapping layer is
techniques. In accordance with another embodiment of the now labeled as charge -trapping layer 404 .
present invention , a dielectric layer formed by carrying out 10 Blocking dielectric layer 406 may be composed of a
a radical oxidation process is less susceptible to crystal plane material and have a thickness suitable to maintain a barrier
orientation differences in the substrate from which it is
grown. In one embodiment, the cornering effect caused by tocapacitance
charge leakage without significantly decreasing the
of a subsequently formed gate stack in a non
differential crystal plane oxidation rates is significantly
reduced by forming a dielectric layer via a radicaloxidation 15 ment
volatile, region
charge404Btrapis memory device . In a specific embodi
a silicon -rich silicon oxy - nitride region
process.
A portion of a nonvolatile charge trap memory device may having a thickness approximately in the range of 2-3 nano
be fabricated by carrying out a radical oxidation process in meters and is oxidized to form blocking dielectric layer 406
a process chamber . In accordance with an embodimentof the having a thickness approximately in the range of 3.5-4.5
present invention , the process chamber is a batch -processing 20 nanometers. In that embodiment, blocking dielectric layer
chamber. FIG . 2 illustrates a cross - sectional view of an 406 is composed of silicon dioxide.
oxidation chamber of a batch - processing tool, in accordance Blocking dielectric layer 406 may be formed by a radical
with that embodiment. Referring to FIG . 2 , a batch -process oxidation process. In accordance with an embodiment of the
ing chamber 200 includes a carrier apparatus 204 to hold a present invention , the radical oxidation process involves
plurality of semiconductor wafers 202. In one embodiment, 25 flowing hydrogen (Hz) and oxygen (Oz) gas into a furnace ,
the batch -processing chamber is an oxidation chamber. In a such as the batch processing chamber 200 described in
specific embodiment, the process chamber is a low - pressure association with FIG . 2. In one embodiment, the partial
chemical vapor deposition chamber . The plurality of semi pressures of Hz and Oz have a ratio to one another of
conductor wafers 202 may be arranged in such a way as to approximately 1: 1. However, in an embodiment, an ignition
maximize exposure of each wafer to a radical oxidation 30 event is not carried out which would otherwise typically be
process, while enabling the inclusion of a reasonable num used to pyrolyze the H , and O2 to form steam . Instead , H2
ber of wafers (e.g. 25 wafers), to be processed in a single and O2 are permitted to react to form radicals at the surface
pass . It should be understood , however, that the present of region 404B . In one embodi the radicals are used to
invention is not limited to a batch -processing chamber. consume region 404B to provide blocking dielectric layer
In an aspect of the present invention , a portion of a 35 406. In a specific embodiment, the radical oxidation process
nonvolatile charge trap memory device is fabricated by a includes oxidizing with a radical such as , but not limited to ,
radical oxidation process. FIG . 3 depicts a Flowchart rep an OH radical , an HO2 radical or an O diradical at a
resenting a series of operations in a method for fabricating temperature approximately in the range of600-900 degrees
a nonvolatile charge trap memory device, in accordance with Celsius. In a particular embodiment, the radical oxidation
an embodiment of the present invention . FIGS. 4A -4B 40 process is carried out at a temperature approximately in the
illustrate cross -sectional views representing operations in range of 700-800 degrees Celsius at a pressure approxi
the fabrication of a nonvolatile charge trap memory device , mately in the range of 0.5-5 Torr. In one embodiment, the
in accordance with an embodiment of the present invention . second radical oxidation process is carried out for a duration
FIG . 4A illustrates a cross -sectional view of a substrate approximately in the range of 100-150 minutes.
having a charge trapping layer formed thereon , correspond- 45 Referring to operation 306 of Flowchart 300 , blocking
ing to operation 302 from the Flowchart of FIG . 3 , in dielectric layer 406 may be further subjected to a nitridation
accordance with an embodiment of the present invention . process in the first process chamber. In accordance with an
Referring to operation 302 of Flowchart 300 and corre embodimentof the present invention , the nitridation process
sponding FIG . 4A , a substrate 400 is provided having a includes annealing blocking dielectric layer 406 in an atmo
charge- trapping layer disposed thereon . In an embodiment, 50 sphere including nitrogen at a temperature approximately in
the charge -trapping layer has a first region 404A and a the range of700-800 degrees Celsius for a duration approxi
second region 404B disposed above substrate 400. In one mately in the range of 5 minutes -60 minutes. In one embodi
embodiment, a dielectric layer 402 is disposed between ment, the atmosphere including nitrogen is composed of a
substrate 400 and the charge trapping layer, as depicted in gas such as , but not limited to , nitrogen (N2), nitrous oxide
FIG . 4A . The charge - trapping layer may be composed of a 55 (N2O ), nitrogen dioxide (NO2), nitric oxide (NO ) or ammo
material and have a thickness suitable to store charge and , nia (NH3). Alternatively , this nitridation step , i.e. operation
hence , change the threshold voltage of a subsequently 306 from Flowchart 300 , may be skipped .
formed gate stack . In an embodiment, region 404A of the In an aspect of the present invention , both a tunnel
charge-trapping layer will remain as an intact charge - trap dielectric layer and a blocking dielectric layer may be
ping layer following subsequent process operations. How- 60 formed by radical oxidation processes. FIG . 5 depicts a
ever, in that embodiment, region 404B of the as -formed Flowchart 500 representing a series of operations in a
charge trapping layer will be consumed to form a second method for fabricating a nonvolatile charge trap memory
dielectric layer, above region 404A . device , in accordance with an embodiment of the present
FIG . 4B illustrates a cross -sectional view of substrate invention . FIGS. 6A -6E illustrates cross - sectional views
having a charge trapping layer with a blocking dielectric 65 representing operations in the fabrication of a nonvolatile
layer formed thereon , corresponding to operation 304 from charge trap memory device , in accordance with an embodi
the Flowchart of FIG . 3 , in accordance with an embodiment ment of the present invention .
 US 10,593,812 B2
7 8
FIG . 6A illustrates a cross - sectional view of a substrate , event is not carried out which would otherwise typically be
corresponding to operation 502 from the Flowchart of FIG . used to pyrolyze the Hz and Oz to form steam . Instead , Hz
5 , in accordance with an embodiment of the present inven and Oz are permitted to react to form radicals at the surface
tion . Referring to operation 502 of Flowchart 500 and of substrate 600. In one embodiment, the radicals are used
corresponding FIG . 6A , a substrate 600 is provided in a ui to consume the top portion of substrate 600 to provide first
process chamber. dielectric layer 602. In a specific embodiment, the radical
Substrate 600 may be composed of a material suitable for oxidation process includes oxidizing with a radical such as,
semiconductor device fabrication . In one embodiment, sub but not limited to, an OH radical, an HO , radical or an O
strate 600 is a bulk substrate composed of a single crystal of diradical at a temperature approximately in the range of
a material which may include, but is not limited to , silicon , 10 600-900 degrees Celsius. In a particular embodiment, the
germanium , silicon - germanium or a III- V compound semi radical oxidation process is carried out at a temperature
conductor material. In another embodiment, substrate 600 approximately in the range of 700-800 degrees Celsius at a
includes a bulk layer with a top epitaxial layer. In a specific pressure approximately in the range of 0.5-5 Torr. In one
embodiment, the bulk layer is composed of a single crystal embodiment, the radical oxidation process is carried out for
of a material which may include, but is not limited to , 15 a duration approximately in the range of 100-150 minutes.
silicon , germanium , silicon - germanium , a III- V compound In accordance with an embodiment of the present invention ,
semiconductor material or quartz , while the top epitaxial first dielectric layer 602 is formed as a high -density, low
layer is composed of a single crystal layer which may hydrogen - content film .
include , but is not limited to , silicon , germanium , silicon Referring to operation 506 of Flowchart 500 , subsequent
germanium or a III - V compound semiconductor material. In 20 to forming first dielectric layer 602, but prior to any further
another embodiment, substrate 600 includes a top epitaxial processing, first dielectric layer 602 may be subjected to a
layer on a middle insulator layer which is above a lower bulk nitridation process . In an embodiment, the nitridation pro
layer. The top epitaxial layer is composed of a single crystal cess is carried out in the same process chamber used to form
layer which may include , but is not limited to , silicon ( i.e. to first dielectric layer 502 , without removing substrate 600
form a silicon -on - insulator (SOI) semiconductor substrate ), 25 from the process chamber between process steps. In one
germanium , silicon- germanium or a III - V compound semi embodiment, the annealing includes heating substrate 600 in
conductor material. The insulator layer is composed of a an atmosphere including nitrogen at a temperature approxi
material which may include, but is not limited to , silicon mately in the range of 700-800 degrees Celsius for a
dioxide , silicon nitride or silicon oxy -nitride. The lower bulk duration approximately in the range of 5 minutes -60 min
layer is composed of a single crystal which may include, but 30 utes. In one embodiment, the atmosphere including nitrogen
is not limited to , silicon , germanium , silicon - germanium , a is composed of a gas such as, but not limited to , nitrogen
III- V compound semiconductormaterialor quartz. Substrate (N2), nitrous oxide (N2O ), nitrogen dioxide (NO2), nitric
600 may further include dopant impurity atoms. oxide (NO ) or ammonia (NH3). In one embodiment, the
FIG . 6B illustrates a cross -sectional view of a substrate nitridation occurs following a nitrogen or argon purge of the
having a dielectric layer formed thereon, corresponding to 35 process chamber following the first radical oxidation pro
operation 504 from the Flowchart of FIG . 5 , in accordance cess . Alternatively , the above nitridation step may be
with an embodiment of the present invention . Referring to skipped.
operation 504 of Flowchart 500 and corresponding FIG . 6B , FIG . 6C illustrates a cross - sectional view of a substrate
substrate 600 is subjected to a first radical oxidation process having a charge trapping layer formed thereon , correspond
to form a first dielectric layer 602 . 40 ing to operation 508 from the Flowchart of FIG . 5 , in
First dielectric layer 602 may be composed of a material accordance with an embodiment of the present invention .
and have a thickness suitable to allow charge carriers to Referring to operation 508 of Flowchart 500 and corre
tunnel into a subsequently formed charge trapping layer sponding FIG . 6C , a charge - trapping layer having a first
under an applied gate bias, while maintaining a suitable region 604A and a second region 604B is formed on first
barrier to leakage when a subsequently formed nonvolatile 45 dielectric layer 602. In an embodiment, the formation of the
charge trap memory device is unbiased . First dielectric layer charge-trapping layer is carried out in the same process
602 may be referred to in the art as a tunnel dielectric layer. chamber used to form first dielectric layer 602 , without
In accordance with an embodiment of the present invention , removing substrate 600 from the process chamber between
first dielectric layer 602 is formed by an oxidation process process steps.
where the top surface of substrate 600 is consumed . Thus, in 50 The charge- trapping layer may be composed of a material
an embodiment, first dielectric layer 602 is composed of an and have a thickness suitable to store charge and , hence ,
oxide of the material of substrate 600. For example , in one change the threshold voltage of a subsequently formed gate
embodiment, substrate 600 is composed of silicon and first stack . In accordance with an embodiment of the present
dielectric layer 602 is composed of silicon dioxide . In a invention , the charge- trapping layer is composed of two
specific embodiment, first dielectric layer 602 is formed to 55 regions 604A and 604B , as depicted in FIG . 6C . In an
a thickness approximately in the range of 1-10 nanometers. embodiment, region 604A of the charge-trapping layer will
In a particular embodiment, first dielectric layer 602 is remain as an intact charge -trapping layer following subse
formed to a thickness approximately in the range of 1.5-2.5 quent process operations. However, in that embodiment,
nanometers. region 604B of the as - formed charge -trapping layer will be
First dielectric layer 602 may be formed by a radical 60 consumed to form a second dielectric layer , above region
oxidation process. In accordance with an embodiment of the 604A .
present invention , the radical oxidation process involves The charge - trapping layer having regions 604A and 604B
flowing hydrogen (H2 ) and oxygen (O2) gas into a furnace , may be formed by a chemical vapor deposition process. In
such as the batch processing chamber 200 described in accordance with an embodiment of the present invention ,
association with FIG . 2. In one embodiment, the partial 65 the charge-trapping layer is composed of a material such as ,
pressures of Hz and Oz have a ratio to one another of but not limited to , silicon nitride , silicon oxy-nitride, oxy
approximately 1 :1 . However, in an embodiment, an ignition gen -rich silicon oxy -nitride or silicon -rich silicon oxy -ni
 US 10,593,812 B2
9 10
tride. In one embodiment, regions 604A and 604B of the ing to operation 510 from the Flowchart of FIG . 5 , in
charge- trapping layer are formed at a temperature approxi accordance with an embodiment of the present invention .
mately in the range of 600-900 degrees Celsius. In a specific Referring to operation 510 of Flowchart 500 and corre
embodiment, the charge -trapping layer is formed by using sponding FIG . 6D , a second dielectric layer 606 is formed on
gases such as, but not limited to , dichlorosilane (H2SiCl2 ), 5 charge -trapping layer 604. In an embodiment, the formation
bis- tert -butylamino )silane (BTBAS ), ammonia (NH3) or of second dielectric layer 606 is carried out in the same
nitrous oxide (N2O ). In one embodiment, the charge trap process chamber used to form first dielectric layer 602 and
ping layer is formed to a total thickness approximately in the the charge- trapping layer, without removing substrate 600
range of 5-15 nanometers and region 604B accounts for a from the process chamber between process steps . In one
thickness approximately in the range of 2-3 nanometers of 10 embodiment, the second radical oxidation process is carried
the total thickness of the charge-trapping layer. In that out following a nitrogen or argon purge of the process
embodiment, region 604A accounts for the remaining total chamber following the deposition of the charge -trapping
thickness of the charge - trapping layer, i.e. region 604A layer
accounts for the portion of the charge - trapping layer that is Second dielectric layer 606 may be composed of a mate
not subsequently consumed to form a top or blocking 15 rial and have a thickness suitable to maintain a barrier to
dielectric layer. charge leakage without significantly decreasing the capaci
In another aspect of the present invention , the charge tance of a subsequently formed gate stack in a nonvolatile
trapping layer may include multiple composition regions . charge trapmemory device . Second dielectric layer 606 may
For example, in accordance with an embodiment of the be referred to in the art as a blocking dielectric layer or a top
present invention , the charge- trapping layer includes an 20 dielectric layer. In accordance with an embodiment of the
oxygen -rich portion and a silicon - rich portion and is formed present invention , second dielectric layer 606 is formed by
by depositing an oxygen -rich oxy -nitride film by a first consuming region 604B of the charge -trapping layer formed
composition of gases and , subsequently, depositing a sili in operation 508 , described in association with FIG . 6C .
con - rich oxy -nitride film by a second composition of gases . Thus, in one embodiment, region 604B is consumed to
In one embodiment, the charge - trapping layer is formed by 25 provide second dielectric layer 606 , while region 604A
modifying the flow rate of ammonia (NH3) gas, and intro remains a charge-trapping layer 604. In a specific embodi
ducing nitrous oxide (N2O ) and dichlorosilane (SiH2Cb ) to ment , region 604B is a silicon -rich silicon oxy-nitride region
provide the desired gas ratios to yield first an oxygen -rich having a thickness approximately in the range of 2-3 nano
oxy-nitride film and then a silicon - rich oxy -nitride film . In meters and is oxidized to form second dielectric layer 606
a specific embodiment, the oxygen - rich oxy -nitride film is 30 having a thickness approximately in the range of 3.5-4.5
formed by introducing a process gasmixture including N20 , nanometers. In that embodiment, second dielectric layer 606
NH3 and SiH2Cb , whilemaintaining the process chamber at is composed of silicon dioxide . In accordance with an
a pressure approximately in the range of 5-500 m Torr, and embodiment of the present invention , second dielectric layer
maintaining substrate 600 at a temperature approximately in 606 is formed by a second radical oxidation process, similar
the range of 700-850 degrees Celsius, for a period approxi- 35 to the radical oxidation process carried out to form blocking
mately in the range of 2.5-20 minutes. In a further embodi dielectric layer 406 , described in association with FIG . 4B .
ment,the process gas mixture includes N20 and NH , having In one embodiment, referring to operation 512 of Flowchart
a ratio of from about 8 :1 to about 1:8 and SiH , C1 and NH ; 500 , subsequent to forming second dielectric layer 606 ,
having a ratio of from about 1: 7 to about 7 : 1, and can be second dielectric layer 606 is further subjected to a nitrida
introduced at a flow rate approximately in the range of 5-200 40 tion process similar to the nitridation process described in
standard cubic centimeters per minute ( sccm ). In another association with operation 506 from Flowchart 500. In a
specific embodiment, the silicon-rich oxy-nitride film is specific embodiment, the nitridation occurs following a
formed by introducing a process gas mixture including N20 , nitrogen or argon purge of the process chamber following
NH3 and SiH2Cb , while maintaining the chamber at a the second radical oxidation process. Alternatively , this
pressure approximately in the range of 5-500 mTorr, and 45 nitridation step may be skipped. In accordance with an
maintaining substrate 600 at a temperature approximately in embodiment of the present invention , no additional deposi
the range of 700-850 degrees Celsius, for a period approxi tion processes are used in the formation of second dielectric
mately in the range of 2.5-20 minutes. In a further embodi layer 606 .
ment, the process gas mixture includes N20 and NH3 Thus, in accordance with an embodiment of the present
having a ratio of from about 8 :1 to about 1:8 and SiH2Cb 50 invention , an ONO stack including first dielectric layer 602 ,
and NH3mixed in a ratio of from about 1:7 to about 7 : 1 , charge-trapping layer 604 and second dielectric layer 606 is
introduced at a flow rate of from about 5 to about 20 seem . formed in a single pass in a process chamber. By fabricating
In accordance with an embodiment of the present invention , these layers in a single pass ofmultiple wafers in the process
the charge - trapping layer comprises a bottom oxygen - rich chamber, high throughput requirements may be met while
silicon oxy -nitride portion having a thickness approximately 55 still ensuring the formation of very high quality films. Upon
in the range of 2.5-3.5 nanometers and a top silicon -rich fabrication of an ONO stack including first dielectric layer
silicon oxy -nitride portion having a thickness approximately 602, charge -trapping layer 604 and second dielectric layer
in the range of 9-10 nanometers. In one embodiment, a 606 , a nonvolatile charge trap memory device may be
region 504B of charge- trapping layer accounts for a thick fabricated to include a patterned portion of the ONO stack .
ness approximately in the range of 2-3 nanometers of the 60 FIG . 6E illustrates a cross-sectional view of a nonvolatile
total thickness of the top silicon -rich silicon oxy -nitride charge trap memory device , in accordance with an embodi
portion of the charge -trapping layer . Thus, region 604B , ment of the present invention .
which is targeted for subsequent consumption to form a Referring to FIG . 6E , a nonvolatile charge trap memory
second dielectric layer, may be composed entirely of silicon device includes a patterned portion of the ONO stack formed
rich silicon oxy -nitride . 65 over substrate 600. The ONO stack includes first dielectric
FIG . 6D illustrates a cross -sectional view of a substrate layer 602 , charge -trapping layer 604 and second dielectric
having a second dielectric layer formed thereon , correspond layer 606. A gate layer 608 is disposed on second dielectric
 US 10,593,812 B2
11 12
layer 606. The nonvolatile charge trap memory device of an insulating material suitable for adhesion to substrate
further includes source and drain regions 612 in substrate 700. An exposed portion of substrate 700 extends above the
600 on either side of the ONO stack , defining a channel top surface of isolation regions 702. In accordance with an
region 614 in substrate 600 underneath the ONO stack . A embodiment of the present invention , the exposed portion of
pair of dielectric spacers 610 isolates the sidewalls of first 5 substrate 700 has a first exposed crystal plane 704 and a
dielectric layer 602 , charge -trapping layer 604, second second exposed crystal plane 706. In one embodiment, the
dielectric layer 606 and gate layer 608. In a specific embodi crystal orientation of first exposed crystal plane 704 is
ment, channel region 614 is doped P -type and , in an alter different from the crystal orientation of second exposed
native embodiment, channel region 614 is doped N -type . crystal plane 706. In a specific embodiment, substrate 700 is
In accordance with an embodiment of the present inven- 10 composed of silicon , first exposed crystal plane 704 has
tion , the nonvolatile charge trap memory device described in < 100 > orientation , and second exposed crystal plane 706 has
association with FIG . 6E is a SONOS -type device . By < 110 > orientation .
convention , SONOS stands for “ Semiconductor -Oxide -Ni Substrate 700 may be subjected to a radical oxidation
tride -Oxide - Semiconductor," where the first “ Semiconduc process to form a dielectric layer by consuming (oxidizing )
tor” refers to the channel region material, the first “ Oxide ” 15 the top surface of substrate 700. In one embodiment, the
refers to the tunnel dielectric layer, “ Nitride” refers to the oxidizing of substrate 700 by a radical oxidation process
charge -trapping dielectric layer, the second “ Oxide” refers includes oxidizing with a radical selected from the group
to the top dielectric layer (also known as a blocking dielec consisting of an OH radical, an HO2 radical or an O
tric layer) and the second “ Semiconductor” refers to the gate diradical. FIG . 7B illustrates a cross - sectional view of
layer. Thus, in accordance with an embodiment of the 20 substrate 700 including first and second crystal planes 704
present invention , first dielectric layer 602 is a tunnel and 706 , respectively , and having a dielectric layer 708
dielectric layer and second dielectric layer 606 is a blocking formed thereon , in accordance with an embodiment of the
dielectric layer. present invention . In an embodiment, first portion 708A of
Gate layer 608 may be composed of any conductor or dielectric layer 708 is formed on first exposed crystal plane
semiconductor material suitable for accommodating a bias 25 704 and a second portion 708B of dielectric layer 708 is
during operation of a SON OS- type transistor. In accordance formed on second exposed crystal plane 706 , as depicted in
with an embodiment of the present invention , gate layer 608 FIG . 7B . In one embodiment, the thickness T10f firstportion
is formed by a chemical vapor deposition process and is 708A of dielectric layer 708 is approximately equal to the
composed of doped poly -crystalline silicon. In another thickness T2 of second portion 708B of dielectric layer 708 ,
embodiment, gate layer 608 is formed by physical vapor 30 even though the crystal plane orientation of first exposed
deposition and is composed of a metal-containing material crystal plane 704 and second exposed crystal plane 706
which may include , but is not limited to , metal nitrides, differ. In a specific embodiment, the radical oxidation of
metal carbides, metal silicides, hafnium , zirconium , tita substrate 700 is carried out a temperature approximately
nium , tantalum , aluminum , ruthenium , palladium , platinum , in the range of 600-900 degrees Celsius . In a specific
cobalt or nickel. 35 embodiment, the radical oxidation of substrate 700 is carried
Source and drain regions 612 in substrate 600 may be any out at a temperature approximately in the range of 700-800
regions having opposite conductivity to channel region 614 . degrees Celsius at a pressure approximately in the range of
For example, in accordance with an embodiment of the 0.5-5 Torr.
present invention, source and drain regions 612 are N -type Thus , a method for fabricating a nonvolatile charge trap
doped regions while channel region 614 is a P -type doped 40 memory device has been disclosed . In accordance with an
region . In one embodiment, substrate 600 and , hence, chan embodiment of the present invention , a substrate is provided
nel region 614, is composed of boron -doped single -crystal having a charge -trapping layer disposed thereon . A portion
silicon having a boron concentration in the range of 1x1015 of the charge - trapping layer is then oxidized to form a
1x1019 atoms/cm3. In that embodiment, source and drain blocking dielectric layer above the charge -trapping layer by
regions 612 are composed of phosphorous- or arsenic doped 45 exposing the charge- trapping layer to a radical oxidation
regions having a concentration of N - type dopants in the process .
range of 5x1016-5x1019 atoms/cm °. In a specific embodi In another aspect of the present invention , it may be
ment, source and drain regions 612 have a depth in substrate desirable to use a cluster tool to carry out a radical oxidation
600 in the range of 80-200 nanometers . In accordance with process. Accordingly, disclosed herein is a method to fab
an alternative embodiment of the present invention , source 50 ricate a nonvolatile charge trap memory device . A substrate
and drain regions 612 are P - type doped regions while may first be subjected to a first radical oxidation process to
channel region 614 is an N -type doped region . form a first dielectric layer in a first process chamber of a
In another aspect of the present invention , a dielectric cluster tool. In one embodiment, a charge - trapping layer is
layer formed by radical oxidation of the top surface of a then deposited above the first dielectric layer in a second
substrate in an oxidation chamber may be less susceptible to 55 process chamber of the cluster tool. The charge-trapping
crystal plane orientation differences in the substrate upon layer may then be subjected to a second radical oxidation
which it is grown. For example , in one embodiment, the process to form a second dielectric layer above the charge
cornering effect caused by differential crystal plane oxida trapping layer . In one embodiment, the second dielectric
tion rates is significantly reduced by forming a dielectric layer is formed by oxidizing a portion of the charge -trapping
layer by a radical oxidation process . FIG . 7 A illustrates a 60 layer in the first process chamber of the cluster tool. In a
cross - sectional view of a substrate including first and second specific embodiment, the cluster tool is a single -wafer
exposed crystal planes, in accordance with an embodiment cluster tool.
of the present invention. Formation of a dielectric layer in a chamber of a cluster
Referring to FIG . 7 A , a substrate 700 has isolation tool may permit the growth of the dielectric layer at tem
regions 702 formed thereon . Substrate 700 may be com- 65 peratures higher than normally achievable in batch process
posed of a material described in association with substrate ing chambers . Furthermore, a radical oxidation process may
600 from FIG . 6A . Isolation regions 702 may be composed be carried out in the chamber of the cluster tool as the
 US 10,593,812 B2
13 14
primary pathway for growing the dielectric layer. In accor surface, of a wafer rests on the chuck for processing and
dance with an embodimentof the present invention , a radical transfer events . In one embodiment, by having the flat
oxidation process involving flowing hydrogen (H2) and surface of a wafer rest on the chuck , more rapid ramp rates
oxygen (O2) gas into an oxidation chamber of a cluster tool for heating the wafer are achievable by heating the wafer via
is carried out to effect growth of a dielectric layer by 5 the chuck . In a specific embodiment, cluster tool 800 is a
oxidation consumption of an exposed substrate or film . In single -wafer cluster tool.
one embodiment, multiple radical oxidation processes are Process chambers 802 , 804 and 806 may include, but are
carried out in an oxidation chamber of a cluster tool to not limited to , oxidation chambers, low -pressure chemical
provide a tunnel dielectric layer and a blocking dielectric vapor deposition chambers , or a combination thereof. For
layer for a non -volatile charge trap memory device . These 10 example, in accordance with an embodiment of the present
dielectric layers may be of very high quality , even at a invention , first process chamber 804 is a first oxidation
reduced thickness . In one embodiment, the tunnel dielectric chamber , second process chamber 806 is a low -pressure
layer and the blocking dielectric layer are both denser and chemical vapor deposition chamber, and third process cham
are composed of substantially fewer hydrogen atoms/cm3 ber 808 is a second oxidation chamber. An example of an
than a tunnel dielectric layer or a blocking dielectric layer 15 oxidation chamber is the In - Situ Steam Generation (ISSG )
formed in a batch process chamber. Furthermore , the sub chamber from Applied Materials, Inc. Examples of low
strate upon which a tunnel dielectric layer and a blocking pressure chemical vapor deposition chambers include a
dielectric layer are formed may be exposed to a shorter SiNgenTM chamber and an OXYgenTM chamber from
temperature ramp rate and stabilization time in an oxidation Applied Materials, Inc. Instead of heating entire process
chamber of a cluster tool as compared with a batch process 20 chambers to heat a wafer, which is the case for typical batch
chamber. Thus, in accordance with an embodiment of the process chambers, a chuck used for carrying a single wafer
present invention embodiment, the impact on the thermal may be heated to heat the wafer. In accordance with an
budget of the substrate is reduced by employing a radical embodiment of the present invention , a chuck is used to heat
oxidation process in an oxidation chamber of a cluster tool. a wafer to the desired process temperature . Thus, relatively
In accordance with another embodiment of the present 25 short temperature ramp times and stabilization times may be
invention , a dielectric layer formed by carrying out a radical achieved .
oxidation process in an oxidation chamber of a cluster tool A portion ofa nonvolatile charge trap memory device may
is less susceptible to crystal plane orientation differences in be fabricated in a cluster tool. FIG . 9 depicts a Flowchart
the substrate from which it is grown . In one embodiment,the 900 representing a series of operations in a method for
cornering effect caused by differential crystal plane oxida- 30 fabricating a nonvolatile charge trap memory device, in
tion rates is significantly reduced by forming a dielectric accordance with an embodiment of the present invention.
layer via a radical oxidation process carried out in an FIGS. 10A - 10E illustrates cross -sectional views represent
oxidation chamber of a cluster tool. ing operations in the fabrication of a nonvolatile charge trap
A portion of a nonvolatile charge trap memory device may memory device , in accordance with an embodiment of the
be fabricated in a cluster tool. FIG . 8 illustrates an arrange- 35 present invention .
ment of process chambers in a cluster tool, in accordance Referring to FIG . 10A , a substrate 1000 is provided in a
with an embodiment of the present invention . Referring to cluster tool. In one embodiment, substrate 1000 is provided
FIG . 8, an arrangement of process chambers in a cluster tool in a transfer chamber, such as transfer chamber 802
800 includes a transfer chamber 802 , a first process chamber described in association with FIG . 8 .
804 , a second process chamber 806 and a third process 40 Substrate 1000 may be composed of any material suitable
chamber 808. In an embodiment, transfer chamber 802 is for for semiconductor device fabrication . In one embodiment,
receiving a wafer from an external environment for intro substrate 1000 is a bulk substrate composed of a single
duction into cluster tool 800. In one embodiment, each of the crystal of a materialwhich may include ,but is not limited to ,
process chambers 802 , 804 and 806 are arranged in a way silicon , germanium , silicon-germanium or a III - V com
such that a wafer may be passed back - and forth between 45 pound semiconductormaterial. In another embodiment, sub
these chambers and transfer chamber 802 , as depicted by the strate 1000 includes a bulk layer with a top epitaxial layer.
double -headed arrows in FIG . 8. In accordance with an In a specific embodiment, the bulk layer is composed of a
additional embodiment of the present invention , although single crystal of a material which may include , but is not
not shown, cluster tool 800 may be configured such that a limited to , silicon , germanium , silicon - germanium , a III- V
wafer can be transferred directly between any pairing of 50 compound semiconductor material or quartz, while the top
process chambers 802, 804 or 806 . epitaxial layer is composed of a single crystal layer which
Cluster tool 800 may be any cluster tool for which an may include, but is not limited to , silicon , germanium ,
outside environment is excluded in and between process silicon - germanium or a III - V compound semiconductor
chambers 804, 806 and 808 and transfer chamber 802. Thus, material. In another embodiment, substrate 1000 includes a
in accordance with an embodiment of the present invention , 55 top epitaxial layer on a middle insulator layer which is above
once a wafer has entered process chamber 802 , it is pro a lower bulk layer. The top epitaxial layer is composed of a
tected from an external environment as it is moved into and single crystal layer which may include, but is not limited to ,
between process chambers 804, 806 and 808 and transfer silicon (i.e. to form a silicon - on -insulator (SOI) semicon
chamber 802. An example of such a cluster tool is the ductor substrate ), germanium , silicon - germanium or a III - V
Centura® platform commercially available from Applied 60 compound semiconductor material. The insulator layer is
Materials, Inc., located in Santa Clara , Calif. In one embodi composed of a material which may include, but is not
ment, once a wafer has been received by transfer chamber limited to , silicon dioxide , silicon nitride or silicon oxy
802, a vacuum of less than approximately 100 mTorr is nitride . The lower bulk layer is composed of a single crystal
maintained in cluster tool 800. In accordance with an which may include , but is not limited to , silicon , germanium ,
embodiment of the present invention , cluster tool 800 incor- 65 silicon -germanium , a III- V compound semiconductor mate
porates a chuck (or multiple chucks, e.g., one chuck for each rial or quartz . Substrate 1000 may further include dopant
chamber ) upon which the flat surface, as opposed to the edge impurity atoms.
 US 10,593,812 B2
15 16
FIG . 10B illustrates a cross -sectional view of a substrate nitridation occurs in a separate process chamber. Alterna
having a tunnel dielectric layer formed thereon , correspond tively , this nitridation step may be skipped .
ing to operation 902 from the Flowchart of FIG . 9 , in FIG . 10C illustrates a cross - sectional view of a substrate
accordance with an embodiment of the present invention . having a charge - trapping layer formed thereon , correspond
Referring to operation 902 of Flowchart 900 and corre 5 ing to operation 906 from the Flowchart of FIG . 9 , in
accordance with an embodiment of the present invention .
sponding FIG . 10B , substrate 1000 is subjected to a first Referring
radical oxidation process in a first process chamber of the sponding FIG to operation 906 of Flowchart 900 and corre
cluster tool to form a first dielectric layer 1002 . . 10C , a charge -trapping layer having a first
First dielectric layer 1002 may be composed of a material region 1004A and a second region 1004B is formed on first
and have a thickness suitable to allow charge carriers to 10 dielectric tool. 1002 in the second process chamber of a
layer
tunnel into a subsequently formed charge trapping layer cluster
under an applied gate bias, while maintaining a suitable andThehavecharge a
- trapping layer may be composed of a material
thickness suitable to store charge and, hence ,
barrier to leakage when a subsequently formed nonvolatile change the threshold voltage of a subsequently formed gate
charge trap memory device is unbiased . In accordance with 15 stack . In accordance with an embodiment of the present
an embodimentof the present invention , first dielectric layer invention , the charge -trapping layer is composed of two
1002 is formed by an oxidation process where the top regions 1004A and 1004B , as depicted in FIG . 10C . In an
surface of substrate 1000 is consumed . Thus, in an embodi embodiment, region 1004A of the charge -trapping layer will
ment, first dielectric layer 1002 is composed of an oxide of remain as an intact charge- trapping layer following subse
the materialof substrate 1000. For example , in one embodi- 20 quent process operations. However, in that embodiment,
ment, substrate 1000 is composed of silicon and first dielec region 1004B of the as- formed charge-trapping layer will be
tric layer 1002 is composed of silicon dioxide. In a specific consumed to form a second dielectric layer, above region
embodiment, first dielectric layer 1002 is formed to a 1004A . In one embodiment, regions 1004A and 1004B of
thickness approximately in the range of 1-10 nanometers . In the charge- trapping layer are formed in the same process
a particular embodiment, first dielectric layer 1002 is formed 25 step and are composed of the same material.
to a thickness approximately in the range of 1.5-2.5 nano The charge -trapping layer having regions 1004A and
meters . 1004B may be formed by a chemical vapor deposition
First dielectric layer 1002 may be formed by a radical process. In accordance with an embodiment of the present
oxidation process. In accordance with an embodiment of the invention , the charge-trapping layer is composed of a mate
present invention , the radical oxidation process involves 30 rial such as, but not limited to , silicon nitride, silicon
flowing hydrogen (Hz) and oxygen (Oz) gas into an oxida oxy -nitride, oxygen - rich silicon oxy -nitride or silicon -rich
tion chamber, such as the oxidation chambers 804 or 808 silicon oxynitride. In an embodiment, the charge- trapping
described in association with FIG . 8. In one embodiment, the layer is formed on first dielectric layer 1002 in a low
partial pressures of Hz and Oz have a ratio to one another pressure chemical vapor deposition chamber, such as the
approximately in the range of 1:50-1:5 . However , in an 35 SiNgenTM low -pressure chemical vapor deposition chamber
embodiment, an ignition event is not carried out which described in association with process chamber 806 from
would otherwise typically be used to pyrolyze the Hz and Oz FIG . 8. In one embodiment, the second process chamber is
to form steam . Instead , Hz and Oz are permitted to react to a low -pressure chemical vapor deposition chamber and
form radicals at the surface of substrate 1000. In one regions 1004A and 1004B of the charge -trapping layer are
embodiment, the radicals are used to consume the top 40 formed at a temperature less than the temperature used to
portion of substrate 1000 to provide first dielectric layer form first dielectric layer 1002. In a specific embodiment,
1002. In a specific embodiment, the radical oxidation pro regions 1004A and 1004B of the charge -trapping layer are
cess includes oxidizing with a radical such as, but not formed at a temperature approximately in the range of
limited to , an OH radical, an HO , radical or an O diradical. 700-850 degrees Celsius. In an embodiment, the second
In a particular embodiment, the radical oxidation process is 45 process chamber is a low -pressure chemical vapor deposi
carried out at a temperature approximately in the range of tion chamber and the charge - trapping layer is formed by
950-1100 degrees Celsius at a pressure approximately in the using gases such as, but not limited to , dichlorosilane
range of 5-15 Torr. In one embodiment, the radical oxidation (H2SiC12), bis-( tert-butylamino ) silane (BTBAS), ammonia
process is carried out for a duration of approximately in the (NH3 ) or nitrous oxide (N2O ). In accordance with an
range of 1-3 minutes. In accordance with an embodiment of 50 embodiment of the present invention, the charge- trapping
the present invention , first dielectric layer 1002 is formed as layer is formed to a total thickness approximately in the
a high -density, low -hydrogen - content film . range of 5-15 nanometers and region 1004B accounts for a
Referring to operation 904 of Flowchart 900 , subsequent thickness approximately in the range of 2-3 nanometers of
to forming first dielectric layer 1002 ,but prior to any further the total thickness of the charge -trapping layer. In that
processing, first dielectric layer 1002 may be subjected to a 55 embodiment, region 1004A accounts for the remaining total
nitridation process . In an embodiment, the nitridation pro thickness of the charge -trapping layer, i.e. the portion of the
cess is carried out in the same process chamber used to form charge -trapping layer that is not subsequently consumed to
first dielectric layer 1002. In one embodiment, first dielectric form a top or blocking dielectric layer .
layer 1002 is annealed in the first process chamber, wherein In another aspect of the present invention , the charge
the annealing includes heating substrate 1000 in an atmo- 60 trapping layer may include multiple composition regions.
sphere including nitrogen at a temperature approximately in For example , in accordance with an embodiment of the
the range of 900-1100 degrees Celsius for a duration present invention , the charge - trapping layer includes an
approximately in the range of 30 seconds-60 seconds. In one oxygen - rich portion and a silicon - rich portion and is formed
embodiment, the atmosphere including nitrogen is com by depositing an oxygen -rich oxy -nitride film by a first
posed of a gas such as, but not limited to , nitrogen (N2), 65 composition of gases in the second process chamber and,
nitrous oxide (N2O ), nitrogen dioxide (NO2), nitric oxide subsequently, depositing a silicon - rich oxy -nitride film by a
(NO ) or ammonia (NH3). In another embodiment, the second composition of gases in the second process chamber.
 US 10,593,812 B2
17 18
In one embodiment, the charge- trapping layer is formed by Second dielectric layer 1006 may be formed by a second
modifying the flow rate of ammonia (NH3) gas, and intro radical oxidation process. In accordance with an embodi
ducing nitrous oxide (N2O ) and dichlorosilane (SiH2Cb ) to ment of the present invention , the second radical oxidation
provide the desired gas ratios to yield first an oxygen -rich process involves flowing hydrogen (Hz) and oxygen ( OZ )
oxy -nitride film and then a silicon - rich oxy -nitride film . In 5 gas into an oxidation chamber, such as the oxidation cham
a specific embodiment, the oxygen -rich oxynitride film is bers 804 or 808 described in association with FIG . 8. In one
formed by introducing a process gas mixture including N20 , embodiment, the partial pressures ofHz and Oz have a ratio
NH3 and SiH2Cb , while maintaining the chamber at a to one another approximately in the range of 1:50-1:5 .
pressure approximately in the range of 0.5-500 Torr, and However, in an embodiment, an ignition event is not carried
maintaining substrate 1000 at a temperature approximately 10 out which would otherwise typically be used to pyrolyze the
in the range of 700-850 degrees Celsius, for a period Hz and Oz to form steam . Instead , Hz and Oz are permitted
approximately in the range of 2.5-20 minutes . In a further to react to form radicals at the surface of region 1004B . In
embodiment, the process gas mixture includes N20 and one embodiment, the radicals are used to consume region
NH3 having a ratio of from about 8 : 1 to about 1:8 and 1004B to provide second dielectric layer 1006. In a specific
SiH2Cb and NH3 having a ratio of from about 1: 7 to about 15 embodiment, the second radical oxidation process includes
7 :1 , and can be introduced at a flow rate approximately in the oxidizing with a radical such as , but not limited to , an OH
range of 5-200 standard cubic centimeters per minute radical, an HO2 radical or an O diradical. In a particular
( seem ). In another specific embodiment, the silicon - rich embodiment, the second radical oxidation process is carried
oxy -nitride film is formed by introducing a process gas out at a temperature approximately in the range of 950-1100
mixture including N20 , NH3 and SiH2Cb , while maintain- 20 degrees Celsius at a pressure approximately in the range of
ing the chamber at a pressure approximately in the range of 5-15 Torr. In one embodiment, the second radical oxidation
0.5-500 Torr, and maintaining substrate 1000 at a tempera process is carried out for a duration approximately in the
ture approximately in the range of 700-850 degrees Celsius, range of 1-3 minutes . In accordance with an embodiment of
for a period approximately in the range of2.5-20 minutes . In the present invention , first dielectric layer 1002 is formed as
a further embodiment, the process gasmixture includes N20 25 a high -density , low -hydrogen content film . In one embodi
and NH3 having a ratio of from about 8 : 1 to about 1:8 and ment, no additional deposition step is required to form a
SiH2Cb and NH3mixed in a ratio of from about 1 :7 to about complete second dielectric layer 1006 , as depicted in FIG .
7 : 1 , introduced at a flow rate of from about 5 to about 20 10D and shown in Flowchart 900. Depending on wafer
seem . In accordance with an embodiment of the present pass -through logistics in the cluster tool, the second radical
invention , the charge- trapping layer comprises a bottom 30 oxidation process may be carried out in the same, i.e. first,
oxygen -rich silicon oxy-nitride portion having a thickness chamber as the first radical oxidation process used to form
approximately in the range of 2.5-3.5 nanometers and a top first dielectric layer 1002 or in a different, e.g. third, process
silicon -rich silicon oxynitride portion having a thickness chamber of the cluster tool. Thus, in accordance with an
approximately in the range of 9-10 nanometers . In one embodiment of the present invention , reference to a first
embodiment, a region 1004B of charge -trapping layer 35 process chamber can be used to mean reintroduction into the
accounts for a thickness approximately in the range of 2-3 first process chamber or to mean introduction into a process
nanometers of the total thickness of the top silicon -rich chamber different from the first process chamber.
silicon oxy-nitride portion of the charge -trapping layer. Referring to operation 910 of Flowchart 900 , subsequent
Thus, region 1004B , which is targeted for subsequent con to forming second dielectric layer 1006 , but prior to remov
sumption to form a second dielectric layer , may be com- 40 ing substrate 1000 from the cluster tool, second dielectric
posed entirely of silicon -rich silicon oxy -nitride. layer 1006 may be further subjected to a nitridation process
FIG . 10D illustrates a cross -sectional view of a substrate in the first process chamber. In accordance with an embodi
having a top dielectric layer formed thereon , corresponding ment of the present invention , the nitridation process
to operation 908 from the Flowchart of FIG.9, in accordance includes annealing second dielectric layer 1006 in an atmo
with an embodiment of the present invention . Referring to 45 sphere including nitrogen at a temperature approximately in
operation 908 of Flowchart 900 and corresponding FIG . the range of 900-1100 degrees Celsius for a duration
10D , a second dielectric layer 1006 is formed on charge approximately in the range of 30 seconds-60 seconds. In one
trapping layer 1004 in the first process chamber of the embodiment, the atmosphere including nitrogen is com
cluster tool. posed of a gas such as, but not limited to , nitrogen (N2),
Second dielectric layer 1006 may be composed of a 50 nitrous oxide (N2O ), nitrogen dioxide (NO2), nitric oxide
material and have a thickness suitable to maintain a barrier (NO ) or ammonia (NH3). Alternatively , this nitridation step ,
to charge leakage without significantly decreasing the i.e. operation 910 from Flowchart 900 , may be skipped and
capacitance of a subsequently formed gate stack in a non the wafer unloaded from the cluster tool.
volatile charge trap memory device. In accordance with an Thus , in accordance with an embodiment of the present
embodiment of the present invention , second dielectric layer 55 invention , an ONO stack including first dielectric layer
1006 is formed by consuming region 1004B of the charge 1002, charge- trapping layer 1004 and second dielectric layer
trapping layer formed in operation 906 , described in asso 1006 is formed in a single pass in a cluster tool. By
ciation with FIG . 10C . Thus , in one embodiment region fabricating these layers in a single pass in the cluster tool,
1004B is consumed to provide second dielectric layer 1006 , pristine interfaces between first dielectric layer 1002 and
while region 1004A remains a charge - trapping layer 1004. 60 charge-trapping layer 1004 and between charge-trapping
In a specific embodiment, region 1004B is a silicon -rich layer 1004 and second dielectric layer 1006 may be pre
silicon oxy -nitride region having a thickness approximately served . In one embodiment, first dielectric layer 1002,
in the range of 2-3 nanometers and is oxidized to form charge-trapping layer 1004 and second dielectric layer 1006
second dielectric layer 1006 having a thickness approxi are formed without breaking vacuum in the cluster tool. In
mately in the range of 3.5-4.5 nanometers. In that embodi- 65 one embodiment, each layer is formed at a different tem
ment, second dielectric layer 1006 is composed of silicon perature to tailor film properties without incurring signifi
dioxide. cant ramp time penalties . Furthermore, by fabricating these
 US 10,593,812 B2
19 20
layers in a cluster tool, as opposed to fabricating in batch range of 1x1015-1x1019 atoms/cm . In that embodiment,
processing tools , the overall uniformity of the stack of layers source and drain regions 1012 are composed of phospho
may be optimized . For example , in accordance with an rous- or arsenic -doped regions having a concentration of
embodiment of the present invention , by fabricating layers N -type dopants in the range of 5x1016-5x1019 atoms/cm3. In
1002, 1004 and 1006 in a cluster tool, the variability in 5 a specific embodiment, source and drain regions 1012 have
thickness of the stack of layers 1002 , 1004 and 1006 across a depth in substrate 1000 in the range of 80-200 nanometers .
a single wafermay be reduced by as much as approximately In accordance with an alternative embodiment of the present
30 % . In an exemplary embodiment, 1 cr is approximately in invention , source and drain regions 1012 are P -type doped
the range of 1-2 % of the thickness of first dielectric layer regions while channel region 1014 is an -N - type doped
1002. In a specific embodiment, the cluster tool is a single- 10 region .
wafer cluster tool. In another aspect of the present invention, a charge
Upon fabrication of an ONO stack including first dielec trapping layer may include multiple composition regions,
tric layer 1002, charge- trapping layer 1004 and second where the composition region closest to a tunnel dielectric
dielectric layer 1006 , a nonvolatile charge trap memory layer is subjected to a radical oxidation process . FIG . 11
device may be fabricated to include a patterned portion of 15 depicts a Flowchart 1100 representing a series of operations
the ONO stack . FIG . 10E illustrates a cross - sectional view in a method for fabricating a nonvolatile charge trap memory
of a nonvolatile charge trap memory device , in accordance device , in accordance with an embodiment of the present
with an embodiment of the present invention . invention . FIGS. 12A - 12E illustrate cross -sectional views
Referring to FIG . 10E , a nonvolatile charge trap memory representing operations in the fabrication of a nonvolatile
device includes a patterned portion of the ONO stack formed 20 charge trap memory device , in accordance with an embodi
over substrate 1000. The ONO stack includes first dielectric ment of the present invention .
layer 1002 , charge-trapping layer 1004 and second dielectric FIG . 12A illustrates a cross -sectional view of a substrate
layer 1006. A gate layer 1008 is disposed on second dielec having a first dielectric layer formed thereon , corresponding
tric layer 1006. The nonvolatile charge trap memory device to operation 1102 from the Flowchart of FIG . 11 , in accor
further includes source and drain regions 1012 in substrate 25 dance with an embodiment of the present invention . Refer
1000 on either side of the ONO stack , defining a channel ring to operation 1102 of Flowchart 1100 and corresponding
region 1014 in substrate 1000 underneath the ONO stack . A FIG . 12A , substrate 1200 is subjected to a first radical
pair of dielectric spacers 1010 isolates the sidewalls of first oxidation process in a first process chamber of a cluster tool
dielectric layer 1002, charge -trapping layer 1004 , second to form a first dielectric layer 1202. Substrate 1200 and first
dielectric layer 1006 and gate layer 1008. In a specific 30 dielectric layer 1202 may be composed of materials
embodiment, channelregion 1014 is doped P -type and , in an described in association with substrate 1000 and first dielec
alternative embodiment, channel region 1014 is doped tric layer 1002 from FIGS. 10A and 10B , respectively . The
N - type . radical oxidation process used to form first dielectric layer
In accordance with an embodiment of the present inven 1202 may be similar to the radical oxidation process used to
tion , the nonvolatile charge trap memory device described in 35 form first dielectric layer 1002, described in association with
association with FIG . 10E is a SONOS -type device. By FIG . 10B .
convention , SONOS stands for “ Semiconductor -Oxide -Ni Referring to operation 1104 of Flowchart 1100 , subse
tride -Oxide- Semiconductor," where the first “ Semiconduc quent to forming first dielectric layer 1202 , but prior to any
tor ” refers to the channel region material, the first “ Oxide” further processing, first dielectric layer 1202 may be sub
refers to the tunnel dielectric layer, “ Nitride ” refers to the 40 jected to a nitridation process. The nitridation process may
charge-trapping dielectric layer, the second “ Oxide ” refers be similar to the nitridation process described in association
to the top dielectric layer (also known as a blocking dielec with operation 904 of Flowchart 900. In one embodiment,
tric layer) and the second “ Semiconductor” refers to the gate the nitridation process is carried out in the same process
layer. Thus, in accordance with an embodiment of the chamber used to form first dielectric layer 1202. In another
present invention , first dielectric layer 1002 is a tunnel 45 embodiment, the nitridation occurs in a separate process
dielectric layer and second dielectric layer 1006 is a block chamber . Alternatively , this nitridation step may be skipped .
ing dielectric layer. FIG . 12B illustrates a cross -sectional view of a substrate
Gate layer 1008 may be composed of any conductor or having an oxygen - rich silicon oxy -nitride portion of a
semiconductor material suitable for accommodating a bias charge- trapping layer formed thereon , corresponding to
during operation of a SON OS- type transistor. In accordance 50 operation 1106 from the Flowchart of FIG . 11 , in accordance
with an embodiment of the present invention , gate layer with an embodiment of the present invention . Referring to
1008 is formed by a chemical vapor deposition process and operation 1106 of Flowchart 1100 and corresponding FIG .
is composed of doped poly -crystalline silicon . In another 12B , an oxygen - rich silicon oxy -nitride portion 1204A is
embodiment, gate layer 1008 is formed by physical vapor formed on first dielectric layer 1202 in a second process
deposition and is composed of a metal-containing material 55 chamber of the cluster tool. Oxygen - rich silicon oxy -nitride
which may include , but is not limited to , metal nitrides, portion 1204A may be composed of an oxygen -rich silicon
metal carbides, metal silicides, hafnium , zirconium , tita oxynitride material and formed by a technique described in
nium , tantalum , aluminum , ruthenium , palladium , platinum , association with first region 1004A from FIG . 10C .
cobalt or nickel. Referring to operation 1108 from Flowchart 1100, in
Source and drain regions 1012 in substrate 1000 may be 60 accordance with an embodiment of the present invention,
any regions having opposite conductivity to channel region oxygen -rich silicon oxy-nitride portion 1204A is subjected
1014. For example, in accordance with an embodiment of to a second radical oxidation process in the first process
the present invention, source and drain regions 1012 are chamber of the cluster tool. The second radical oxidation
N - type doped regions while channel region 1014 is a P -type process may be similar to one of the radical oxidation
doped region . In one embodiment, substrate 1000 and , 65 processes used to form first dielectric layer 1002 or second
hence, channel region 1014 , is composed of boron -doped dielectric layer 1006 , described in association with FIGS.
single crystal silicon having a boron concentration in the 10B and 10D , respectively . In an embodiment, carrying out
 US 10,593,812 B2
21 22
the second radical oxidation process is made possible reintroduction into the first process chamber or to mean
because oxygen -rich silicon oxy -nitride portion 1204A is introduction into a process chamber different from the first
maintained in the environment within the tool and thus process chamber.
retains a pristine surface. In one embodiment, the second Referring to operation 1114 of Flowchart 1100 , subse
radical oxidation process densifies oxygen -rich silicon oxy 5 quent to forming second dielectric layer 1206 , but prior to
nitride portion 1204A . Depending on wafer pass -through removing substrate 1200 from the cluster tool, second
logistics in the cluster tool, the second radical oxidation dielectric layer 1206 may be further subjected to a nitrida
process may be carried out in the same, i.e. first , chamber as tion process in the first process chamber. The nitridation
the radical oxidation process used to form first dielectric process may be similar to the nitridation process described
layer 1202 or in a different, e.g. third, process chamber. 10 one in association with
, theoperation
nitridation910process
from isFlowchart
carried out900.
in theIn
Thus, in accordance with an embodiment of the present sameembodiment
invention , reference to a first process chamber can be used 1206. process
In
chamber used to form second dielectric layer
another embodiment, the nitridation occurs in a
to mean reintroduction into the first process chamber or to separate process chamber . Alternatively, this nitridation step
mean introduction into a process chamber different from the 15 may be skipped .
first process chamber. Upon fabrication of an ONO stack including first dielec
FIG . 12C illustrates a cross -sectional view of a substrate tric layer 1202 , charge- trapping layer 1204 and second
having a silicon - rich silicon oxy -nitride portion of a charge dielectric layer 1206 , a nonvolatile charge trap memory
trapping layer formed thereon , corresponding to operation device may be fabricated to include a patterned portion of
1110 from the Flowchart of FIG . 11, in accordance with an 20 the ONO stack . FIG . 12E illustrates a cross-sectional view
embodiment of the present invention .Referring to operation of a nonvolatile charge trap memory device , in accordance
1110 of Flowchart 1100 and corresponding FIG . 12C , a with an embodiment of the present invention .
silicon -rich silicon oxy -nitride portion having a first region Referring to FIG . 12E , a nonvolatile charge trap memory
1204B and a second region 1204C is formed on oxygen -rich device includes a patterned portion of the ONO stack formed
silicon oxy -nitride portion 1204A in the second process 25 over substrate 1200. The ONO stack includes first dielectric
chamber of the cluster tool. The silicon -rich silicon oxyni layer 1202, charge -trapping layer 1204 and second dielectric
tride portion may be composed of a silicon -rich silicon layer 1206. A gate layer 1208 is disposed on second dielec
oxy -nitride material and formed by a technique described in tric layer 1206. The nonvolatile charge trap memory device
association with second region 1004B from FIG . 10C . further includes source and drain regions 1212 in substrate
Depending on wafer pass- through logistics in the cluster 30 1200 on either side of the ONO stack , defining a channel
tool, the deposition of silicon -rich silicon oxy -nitride portion region 1214 in substrate 1200 underneath the ONO stack . A
of the charge- trapping layer may be carried out in the same, pair of dielectric spacers 1210 isolates the sidewalls of first
i.e. second , chamber as the deposition of oxygen -rich silicon dielectric layer 1202, charge -trapping layer 204 , second
oxy -nitride portion 1204A of the charge- trapping layer or in dielectric layer 1206 and gate layer 1208. In accordance with
a different process chamber. Thus, in accordance with an 35 an embodiment of the present invention , charge- trapping
embodiment of the present invention , reference to a second layer 1204 is composed of an oxygen -rich silicon oxy
process chamber can be used to mean reintroduction into the nitride portion 1204A and a silicon -rich silicon oxy -nitride
second process chamber or to mean introduction into a portion 1204B , as depicted in FIG . 12E . In one embodiment,
process chamber different from the second process chamber. the nonvolatile charge trap memory device is a SONOS -type
FIG . 12D illustrates a cross -sectional view of a substrate 40 device .Gate layer 1208 , source and drain regions 1212 and
having a top dielectric layer formed thereon , corresponding channel region 1214 may be composed of materials
to operation 1112 from the Flowchart of FIG . 11 , in accor described in association with gate layer 1008 , source and
dance with an embodiment of the present invention . Refer drain regions 1012 and channel region 1014 from FIG . 10E .
ring to operation 1112 of Flowchart 1100 and corresponding In another aspect of the present invention , a dielectric
FIG . 12D , a second dielectric layer 1206 is formed on 45 layer formed by radical oxidation of the top surface of a
charge-trapping layer 1204 in the first process chamber of substrate in an oxidation chamber may be less susceptible to
the cluster tool. In accordance with an embodiment of the crystal plane orientation differences in the substrate upon
present invention , second dielectric layer 1206 is formed by which it is grown. For example , in one embodiment, the
consuming second region 1204C of the silicon -rich silicon cornering effect caused by differential crystal plane oxida
oxy -nitride portion by a third radical oxidation process . 50 tion rates is significantly reduced by forming a dielectric
Thus, in one embodiment, the remaining charge - trapping layer in an oxidation chamber of a cluster tool. FIG . 13A
layer 1204 between first dielectric layer 1202 and second illustrates a cross-sectional view of a substrate including first
dielectric layer 1204 is composed of oxygen -rich silicon and second exposed crystal planes, in accordance with an
oxy -nitride portion 1204A and first region 1204B of the embodiment of the present invention .
silicon -rich silicon oxy -nitride portion 1204 , as depicted in 55 Referring to FIG . 13A , a substrate 1300 has isolation
FIG . 12D . The third radical oxidation process used to regions 1302 formed thereon . Substrate 1300 may be com
consume second region 1204C of the silicon-rich silicon posed of a material described in association with substrate
oxy -nitride portion to provide second dielectric layer 1206 1000 from FIG . 10A . Isolation regions 1302 may be com
may be similar to the radical oxidation process used to form posed of an insulating material suitable for adhesion to
second dielectric layer 1006 , described in association with 60 substrate 1300. An exposed portion of substrate 1300
FIG . 10D . Depending on wafer pass -through logistics in the extends above the top surface of isolation regions 1302. In
cluster tool, the third radical oxidation process may be accordance with an embodiment of the present invention ,
carried out in the same, i.e. first, chamber as the radical the exposed portion of substrate 1300 has a first exposed
oxidation process used to form first dielectric layer 1202 or crystal plane 1304 and a second exposed crystal plane 1306 .
in a different, e.g. third , process chamber. Thus, in accor- 65 In one embodiment, the crystal orientation of first exposed
dance with an embodiment of the present invention , refer crystal plane 1304 is different from the crystal orientation of
ence to a first process chamber can be used to mean second exposed crystal plane 1306. In a specific embodi
 US 10,593,812 B2
23 24
ment, substrate 1300 is composed of silicon , first exposed ment of the silicon -oxide -oxynitride-oxide -silicon structure,
crystal plane 1304 has < 100 > orientation , and second thereby extending the operating life of the device.
exposed crystal plane 1306 has < 110 > orientation . It has further been found the anti-tunneling layer 1421
Substrate 1300 may be subjected to a radical oxidation substantially reduces the probability of electron charge that
process in a cluster tool to form a dielectric layer by 5 accumulates at the boundaries of the upper nitride layer
consuming (oxidizing ) the top surface of substrate 1300. In 1418 during programming from tunneling into the bottom
one embodiment, the oxidizing of substrate 1300 by a nitride layer 1419, resulting in lower leakage current than for
radical oxidation process includes oxidizing with a radical the structure illustrated in FIG . 1 .
selected from the group consisting of an OH radical, an HO2 10 The multi-layer charge storing layer can have an overall
radical or an O diradical. FIG . 13B illustrates a cross thickness of from about 50 Å to about 150 Å , and in certain
sectional view of substrate 1300 including first and second embodiments less than about 100 Å , with the with the
crystal planes 1304 and 1306 , respectively, and having a thickness of the anti-tunneling layer 1421 being from about
dielectric layer 1308 formed thereon , in accordance with an 5 Å to about 20 Å , and the thicknesses of the nitride layers
1418 , 1419 , being substantially equal.
embodiment of the present invention . In an embodiment, 15 A method or forming or fabricating a split multi- layer
first portion 1308A of dielectric layer 1308 is formed on first charge storing structure according to one embodiment will
exposed crystal plane 1304 and a second portion 1308B of now be described with reference to the flowchart of FIG . 15 .
dielectric layer 1308 is formed on second exposed crystal Referring to FIG . 15 , the method begins with forming a
plane 1306 , as depicted in FIG . 13B . In one embodiment, the first oxide layer, such as a tunneling oxide layer, over a
thickness T10f first portion 1308A of dielectric layer 1308 is 20 silicon containing layer on a surface of a substrate (1500 ).
approximately equal to the thickness T2 of second portion As noted above, the tunneling oxide layer can be formed or
1308B of dielectric layer 1308, even though the crystalplane deposited by any suitable means, including a plasma oxida
orientation of first exposed crystal plane 1304 and second tion process, In - Situ Steam Generation (ISSG ) or a radical
exposed crystal plane 1306 differ . In a specific embodiment, oxidation process . In one embodiment, the radical oxidation
the radical oxidation of substrate 1300 is carried out at a 25 process involves flowing hydrogen (H ) and oxygen (02)
temperature approximately in the range of 950-1100 degrees gas into a processing chamber or furnace to effect growth of
Celsius at a pressure approximately in the range of 5-15 Torr. a the tunneling oxide layer by oxidation consumption of a
In one embodiment, subsequent to forming dielectric layer portion of the substrate .
1308 , substrate 1300 is annealed in the oxidation chamber in Next, the first or bottom nitride or nitride containing layer
an atmosphere including nitrogen at a temperature approxi- 30 of the multi- layer charge storing layer is formed on a surface
mately in the range of 900-1100 degrees Celsius for a of the tunneling oxide layer ( 1502 ). In one embodiment, the
duration approximately in the range of 30 seconds -60 sec nitride layers are formed or deposited in a low pressure CVD
onds. process using a silicon source , such as silane (SiH_), chlo
Implementations and Alternatives rosilane (SiHzCl), dichlorosilane or DCS (SiH ,C12 ), tetra
In one aspect the present disclosure is directed to memory 35 chlorosilane ( SiC14 ) or Bis - TertiaryButylAmino Silane (BT
devices including an oxide split multi -layer charge storing BAS), a nitrogen source , such as nitrogen (N2), ammonia
structure . FIG . 14 is a block diagram illustrating a cross (NH3), nitrogen trioxide (NO3) or nitrous oxide (N2O ), and
sectional side view of an embodiment of one such semicon an oxygen -containing gas, such as oxygen (02) or N2O .
ductor memory device 1400. The memory device 1400 Alternatively , gases in which hydrogen has been replaced by
includes a SONONOS stack 1402 including an ONONO 40 deuterium can be used , including, for example , the substi
structure 1404 formed over a surface 1406 of a substrate tution of deuterated -ammonia (ND3) for NH3. The substi
1408. Substrate 1408 includes one or more diffusion regions tution of deuterium for hydrogen advantageously passivates
1410 , such as source and drain regions, aligned to the gate Si dangling bonds at the silicon -oxide interface , thereby
stack 1402 and separated by a channel region 1412. Gen increasing an NBTI (Negative Bias Temperature Instability )
erally, the SONONOS structure 1402 includes a polysilicon 45 lifetime of the devices.
or metal gate layer 1414 formed upon and in contact with the For example , the lower or bottom nitride layer can be
ONONO structure 1404. The gate 1414 is separated or deposited over the tunneling oxide layer by placing the
electrically isolated from the substrate 1408 by the ONONO substrate in a deposition chamber and introducing a process
structure 1404. The ONONO structure 1404 includes a thin , gas including N , O , NH , and DCS, while maintaining the
lower oxide layer or tunneling oxide layer 1416 that sepa- 50 chamber at a pressure of from about 5 milliTorr (mT) to
rates or electrically isolates the stack 1402 from the channel about 500 mT, and maintaining the substrate at a tempera
region 1412, a top or blocking oxide layer 1420, and a ture of from about 700 degrees Celsius to about 850 degrees
multi - layer charge storing layer 1404. The multi-layer Celsius and in certain embodiments at least about 760
charge storing layer generally includes at least two nitride degrees Celsius, for a period of from about 2.5 minutes to
layers having differing compositions of silicon , oxygen and 55 about 20 minutes. In particular, the process gas can include
nitrogen , including a silicon - rich , nitrogen - rich , and oxygen a first gas mixture of N20 and NHzmixed in a ratio of from
lean top nitride layer 1418 , a silicon - rich , oxygen -rich , the about 8 : 1 to about 1 :8 and a second gas mixture of DCS and
bottom nitride layer 1419 , and an oxide, anti- tunneling layer NH3mixed in a ratio of from about 1:7 to about 7: 1 , and can
1421. be introduced at a flow rate of from about 5 to about 200
It has been found that a silicon - rich , oxygen -rich , bottom 60 standard cubic centimeters per minute ( sccm ). It has been
nitride layer 1419 decreases the charge loss rate after pro found that an oxynitride layer produced or deposited under
gramming and after erase , which is manifested in a small these condition yields a silicon -rich , oxygen -rich , bottom
voltage shift in the retention mode, while a silicon -rich , nitride layer.
nitrogen -rich , and oxygen - lean top nitride layer 1418 Next , the anti- tunneling layer is formed or deposited on a
improves the speed and increases of the initial difference 65 surface of the bottom nitride layer (1504 ). As with the
between program and erase voltage without compromising a tunneling oxide layer, the anti - tunneling layer can be formed
charge loss rate ofmemory devices made using an embodi or deposited by any suitable means , including a plasma
 US 10,593,812 B2
25 26
oxidation process , In -Situ Steam Generation (ISSG ) or a or device (1508 ). The gate layer can be, for example , a
radical oxidation process. In one embodiment, the radical polysilicon layer deposited by a CVD process to form a
oxidation process involves flowing hydrogen (H2) and oxy silicon -oxide - nitride- oxide- nitride-oxide-silicon (SONOS)
gen (O2) gas into a batch -processing chamber or furnace to structure .
effect growth of the anti-tunneling layer by oxidation con 5 In another aspect the present disclosure is also directed to
sumption of a portion of the bottom nitride layer. multigate or multigate -surface memory devices including
The second or top nitride layer of the multi -layer charge charge -trapping regions overlying two or more sides of a
storing layer is then formed on a surface of the anti channel formed on or above a surface of a substrate, and
tunneling layer (1506 ). The top nitride layer can be depos methods of fabricating the same. Multigate devices include
ited over the anti-tunneling layer 1421 in a CVD process 10 both planar and non -planar devices. A planar multigate
using a process gas including N2O , NHz and DCS, at a device (not shown) generally includes a double -gate planar
chamber pressure of from about 5 mT to about 500 mT, and device in which a number of first layers are deposited to
at a substrate temperature of from about 700 degrees Celsius form a first gate below a subsequently formed channel, and
to about 850 degrees Celsius and in certain embodiments at a number of second layers are deposited thereover to form
least about 760 degrees Celsius, for a period of from about 15 a second gate. A non -planar multigate device generally
2.5 minutes to about 20 minutes. In particular, the process includes a horizontal or vertical channel formed on or above
gas can include a first gasmixture of N20 and NH3 mixed a surface of a substrate and surrounded on three or more
in a ratio of from about 8 : 1 to about 1:8 and a second gas sides by a gate .
mixture ofDCS and NHzmixed in a ratio of from about 1: 7 FIG . 16A illustrates one embodiment of a non -planar
to about 7 :1, and can be introduced at a flow rate of from 20 multigate memory device including a charge -trapping
about 5 to about 20 sccm . It has been found that an region . Referring to FIG . 16A , the memory device 1600 ,
oxynitride layer produced or deposited under these condition commonly referred to as a finFET, includes a channel 1602
yields a silicon - rich , nitrogen -rich , and oxygen -lean top formed from a thin film or layer of semiconducting material
nitride layer 1418 , which improves the speed and increases overlying a surface 1604 on a substrate 1606 connecting a
of the initial difference between program and erase voltage 25 source 1608 and a drain 1610 of the memory device . The
without compromising a charge loss rate ofmemory devices channel 1602 is enclosed on three sides by a fin which forms
made using an embodiment of the silicon -oxide -oxynitride a gate 1612 of the device. The thickness of the gate 1612
oxide-silicon structure , thereby extending the operating life (measured in the direction from source to drain ) determines
of the device . the effective channel length of the device.
In some embodiments, the silicon - rich , nitrogen - rich , and 30 In accordance with the present disclosure, the non -planar
oxygen - lean top nitride layer can be deposited over the multigate memory device 1600 of FIG . 16A can include a
anti-tunneling layer in a CVD process using a process gas split charge- trapping region . FIG . 16B is a cross -sectional
including BTBAS and ammonia (NH3) mixed at a ratio of view of a portion of the non -planar memory device of FIG .
from about 7 : 1 to about 1 : 7 to further include a concentra 16A including a portion of the substrate 1606 , channel 1602
tion of carbon selected to increase the number of traps 35 and the gate 1612 illustrating a multi-layer charge storing
therein . The selected concentration of carbon in the second layer 1614. The gate 1612 further includes a tunnel oxide
oxynitride layer can include a carbon concentration of from layer 1616 overlying a raised channel 1602, a blocking
about 5 % to about 15 % . dielectric 1618 and a metal gate layer 1620 overlying the
Finally, a top, blocking oxide layer or HTO layer is blocking layer to form a control gate of the memory device
formed on a surface of the second layer of the multi- layer 40 1600. In some embodiments a doped polysilicon may be
charge storing layer (1508 ). As with the tunneling oxide deposited instead of metal to provide a polysilicon gate
layer and the anti- tunneling layer the HTO layer can be layer. The channel 1602 and gate 1612 can be formed
formed or deposited by any suitable means, including a directly on substrate 1606 or on an insulating or dielectric
plasma oxidation process, In -Situ Steam Generation (ISSG ) layer 1622, such as a buried oxide layer, formed on or over
or a radical oxidation process . In one embodiment, the HTO 45 the substrate .
layer is formed using a plasma oxidation performed in a Referring to FIG . 16B , the multi -layer charge storing
plasma process chamber. Typical deposition conditions used layer 1614 includes at least one lower or bottom charge
for this process are R.F power in the range 1500 W to trapping layer 1624 including nitride closer to the tunnel
10000 W , H2 and O2with H2 volume percent between 0 % oxide layer 1616 , and an upper or top charge -trapping layer
and 90 % , substrate temperature between 300 C to 400 C , 50 1626 overlying the bottom charge -trapping layer . Generally,
deposition time being 20 to 60 sec the top charge -trapping layer 1626 includes a silicon -rich ,
Alternatively, the HTO layer is formed using an ISSG oxygen - lean nitride layer and includes a majority of a charge
oxidation process. In one embodiment, the ISSG is per traps distributed in multiple charge -trapping layers, while
formed in an RTP chamber, such as the ISSG chamber from the bottom charge -trapping layer 1624 includes an oxygen
Applied Materials described above, at pressures of from 55 rich nitride or silicon oxynitride, and is oxygen -rich relative
about 8 to 12 Torr and a temperature of about 1050 ° C. with to the top charge -trapping layer to reduce the number of
an oxygen rich gas mixture hydrogen to which from about charge traps therein . By oxygen -rich it is meant wherein a
0.5 % to 33 % hydrogen has been added . The deposition time concentration of oxygen in the bottom charge- trapping layer
is in the range 20 to 60 sec . 1624 is from about 15 to about 40 % , whereas a concentra
It will be appreciated that in either embodiment the 60 tion of oxygen in top charge-trapping layer 1626 is less than
thickness of the top nitride layer may be adjusted or about 5 % .
increased as some of the top nitride layer will be effectively In one embodiment, the blocking dielectric 1618 also
consumed or oxidized during the process of forming the includes an oxide, such as an HTO , to provide an ONNO
HTO layer. structure. The channel 1602 and the overlying ONNO struc
Optionally, the method may further include forming or 65 ture can be formed directly on a silicon substrate 1606 and
depositing a metal or polysilicon containing layer on a overlaid with a doped polysilicon gate layer 1620 to provide
surface of the HTO layer to form a gate layer of the transistor a SONNOS structure .
 US 10,593,812 B2
27 28
In some embodiments , such as that shown in FIG . 16B , HfO , Zirconium based material such as ZrSiON , ZrSiO or
the multi -layer charge storing layer 1614 further includes at Zro , and Yttrium based material such as Y203 .
least one thin , intermediate or anti-tunneling layer 1628 In another embodiment, shown in FIGS. 17A and 17B , the
including a dielectric, such as an oxide , separating the top memory device can include a nanowire channel formed from
charge-trapping layer 1626 from the bottom charge - trapping 5 a thin film of semiconducting material overlying a surface

layer 1624. As noted above, the anti- tunneling layer 1628 on a substrate connecting a source and a drain of the memory
substantially reduces the probability of electron charge that device . By nanowire channel it is meant a conducting
accumulates at the boundaries of the upper nitride layer channel formed in a thin strip of crystalline silicon material,
1626 during programming from tunneling into the bottom having a maximum cross -sectional dimension of about 10
nitride layer 1624 . 10 nanometers (nm ) or less , and more preferably less than about
As with the embodiments described above , either or both 6 nm . Optionally , the channel can be formed to have < 100 >
of the bottom charge- trapping layer 1624 and the top charge surface crystalline orientation relative to a long axis of the
channel.
trapping layer 1626 can include silicon nitride or silicon Referring to FIG . 17A , the memory device 1700 includes
oxynitride, and can be formed , for example, by a CVD 15 a horizontal nanowire channel 1702 formed from a thin film
process including N2O /NH3 and DCS /NH3 gas mixtures in or layer of semiconducting material on or overlying a
ratios and at flow rates tailored to provide a silicon -rich and surface on a substrate 1706 , and connecting a source 1708
oxygen-rich oxynitride layer. The second nitride layer of the and a drain 1710 of thememory device . In the embodiment
multi-layer charge storing structure is then formed on the shown, the device has a gate -all -around (GAA ) structure in
middle oxide layer. The top charge- trapping layer 1626 has 20 which the nanowire channel 1702 is enclosed on all sides by
a stoichiometric composition of oxygen , nitrogen and /or a gate 1712 of the device . The thickness of the gate 1712
silicon different from that of the bottom charge -trapping (measured in the direction from source to drain ) determines
layer 1624 , and may also be formed or deposited by a CVD the effective channel length of the device .
process using a process gas including DCS/NH , and N , O / In accordance with the present disclosure , the non - planar
NHz gas mixtures in ratios and at flow rates tailored to 25 multigate memory device 1700 of FIG . 17A can include a
provide a silicon -rich , oxygen - lean top nitride layer. split charge-trapping region . FIG . 17B is a cross -sectional
In those embodiments including an intermediate or anti view of a portion of the non -planar memory device of FIG .
tunneling layer 1628 including oxide, the anti- tunneling 17A including a portion of the substrate 1706 , nanowire
layer can be formed by oxidation of the bottom oxynitride channel 1702 and the gate 1712 illustrating a split charge
layer, to a chosen depth using radical oxidation . Radical 30 trapping region . Referring to FIG . 17B , the gate 1712
oxidation may be performed , for example, at a temperature includes a tunneloxide 1714 overlying the nanowire channel
of 1000-1100 degrees Celsius using a single wafer tool, or 1702, a split charge -trapping region , a blocking dielectric
800-900 degrees Celsius using a batch reactor tool. A 1716 and a gate layer 1718 overlying the blocking layer to
mixture ofH2 and O2 gassesmay be employed at a pressure form a control gate of the memory device 1700. The gate
of 300-500 Tor for a batch process , or 10-15 Tor using a 35 layer 1718 can comprise a metal or a doped polysilicon . The
single vapor tool, for a time of 1-2 minutes using a single split charge - trapping region includes at least one inner
wafer tool, or 30 min - 1 hour using a batch process . charge-trapping layer 1720 comprising nitride closer to the
Finally, in those embodiments including a blocking tunnel oxide 1714 , and an outer charge -trapping layer 1722
dielectric 1618 including oxide the oxide may be formed or overlying the inner charge-trapping layer. Generally, the
deposited by any suitable means. In one embodiment the 40 outer charge - trapping layer 1722 comprises a silicon - rich ,
oxide of the blocking dielectric 1618 is a high temperature oxygen -lean nitride layer and comprises a majority of a
oxide deposited in a HTO CVD process. Alternatively , the charge traps distributed in multiple charge - trapping layers ,
blocking dielectric 1618 or blocking oxide layer may be while the inner charge -trapping layer 1720 comprises an
thermally grown, however it will be appreciated that in this oxygen -rich nitride or silicon oxynitride, and is oxygen -rich
embodiment the top nitride thickness may be adjusted or 45 relative to the outer charge-trapping layer to reduce the
increased as some of the top nitride will be effectively number of charge traps therein .
consumed or oxidized during the process of thermally In some embodiments, such as that shown , the split
growing the blocking oxide layer . A third option is to oxidize charge-trapping region further includes at least one thin ,
the top nitride layer to a chosen depth using radical oxida intermediate or anti - tunneling layer 1724 comprising a
tion . 50 dielectric, such as an oxide, separating outer charge -trapping
A suitable thickness for the bottom charge-trapping layer layer 1722 from the inner charge -trapping layer 1720. The
1624 may be from about 30 Å to about 160 Å (with some anti- tunneling layer 1724 substantially reduces the probabil
variance permitted , for example +10 Å ), ofwhich about 5-20 ity of electron charge that accumulates at the boundaries of
Å may be consumed by radical oxidation to form the outer charge - trapping layer 1722 during programming from
anti-tunneling layer 1628. A suitable thickness for the top 55 tunneling into the inner charge -trapping layer 1720, result
charge - trapping layer 1626 may be at least 30 Å . In certain ing in lower leakage current.
embodiments, the top charge-trapping layer 1626 may be As with the embodiment described above , either or both
formed up to 130 Å thick, of which 30-70 Å may be of the inner charge- trapping layer 1720 and the outer charge
consumed by radical oxidation to form the blocking dielec trapping layer 1722 can comprise silicon nitride or silicon
tric 1618. A ratio of thicknesses between the bottom charge- 60 oxynitride, and can be formed , for example , by a CVD
trapping layer 1624 and top charge - trapping layer 1626 is process including N2O /NHz and DCS /NH3 gas mixtures in
approximately 1: 1 in some embodiments, although other ratios and at flow rates tailored to provide a silicon -rich and
ratios are also possible . oxygen -rich oxynitride layer. The second nitride layer of the
In other embodiments, either or both of the top charge multi -layer charge storing structure is then formed on the
trapping layer 1626 and the blocking dielectric 1618 may 65 middle oxide layer. The outer charge-trapping layer 1722
include a high K dielectric . Suitable high K dielectrics has a stoichiometric composition of oxygen , nitrogen and /or
include hafnium based materials such as HfSION , HfSiO or silicon different from that of the inner charge -trapping layer
 US 10,593,812 B2
29 30
1720 , and may also be formed or deposited by a CVD surrounded by a tunnel oxide 1808, a charge -trapping region
process using a process gas including DCS/NH , and N , O / 1810 , a blocking layer 1812 and a gate layer 1814 overlying
NH3 gas mixtures in ratios and at flow rates tailored to the blocking layer to form a control gate of the memory
provide a silicon -rich , oxygen -lean top nitride layer . device 1800. The channel 1802 can include an annular
In those embodiments including an intermediate or anti- 5 region in an outer layer of a substantially solid cylinder of
tunneling layer 1724 comprising oxide , the anti -tunneling semiconducting material, or can include an annular layer
layer can be formed by oxidation of the inner charge formed over a cylinder of dielectric filler material. As with
trapping layer 1720 , to a chosen depth using radical oxida the
tion . Radical oxidation may be performed , for example , at a can horizontal nanowires described above, the channel 1802
comprise polysilicon or recrystallized polysilicon to
temperature
wafer tool, orof800-900
1000-1100 degrees
degrees CelsiusCelsius
using using
a batcha reactor
single 10 form amonocrystalline channel.Optionally, where the chan
tool. A mixture of H , and O2 gasses may be employed at a nel 1802 includes a crystalline silicon , the channel can be
pressure of 300-500 Tor for a batch process, or 10-15 Tor toformed to have < 100 > surface crystalline orientation relative
a long axis of the channel.
using a single vapor tool, for a time of 1-2 minutes using a
single wafer tool, or 30 min - 1 hour using a batch process. 15 theIn charge
some embodiments , such as that shown in FIG . 18B ,
- trapping region 1810 can be a split charge
Finally , in those embodiments in which the blocking trapping region including at least a first or inner charge
dielectric 1716 comprises oxide, the oxidemay be formed or
deposited by any suitable means . In one embodiment the trapping layer 1816 closest to the tunnel oxide 1808 , and a
oxide of blocking dielectric 1716 is a high temperature oxide second or outer charge trapping layer 1818. Optionally , the
deposited in a HTO CVD process. Alternatively , the block- 20 first and second charge trapping layers can be separated by
ing dielectric 1716 or blocking oxide layer may be thermally an intermediate oxide or anti -tunneling layer 1820 .
grown , however it will be appreciated that in this embodi As with the embodiments described above , either or both
ment the thickness of the outer charge-trapping layer 1722 of the first charge trapping layer 1816 and the second charge
may need to be adjusted or increased as some of the top trapping layer 1818 can comprise silicon nitride or silicon
nitride will be effectively consumed or oxidized during the 25 oxynitride, and can be formed , for example, by a CVD
process of thermally growing the blocking oxide layer. process including N2O /NHz and DCS/NH3 gas mixtures in
A suitable thickness for the inner charge-trapping layer ratios and at flow rates tailored to provide a silicon -rich and
1720 may be from about 30 Å to about 80 Å (with some oxygen -rich oxynitride layer.
variance permitted, for example +10 Å ), of which about 5-20 Finally, either or both of the second charge trapping layer
Å may be consumed by radical oxidation to form the 30 1818 and the blocking layer 1812 may comprise a high K
anti-tunneling layer 1724. A suitable thickness for the outer dielectric , such as HfSiON , HfSiO , HfO , ZrSiON , ZrSiO ,
charge - trapping layer 1722 may be at least 30 Å . In certain Zro , or Y203.
embodiments, the outer charge -trapping layer 1722 may be A suitable thickness for the first charge trapping layer
formed up to 170 Å thick , of which 30-70 Å may be 1816 may be from about 30 Å to about 80 Å (with some
consumed by radical oxidation to form the blocking dielec- 35 variance permitted , for example # 10 Å ), ofwhich about 5-20
tric 1716. A ratio of thicknesses between the inner charge Å may be consumed by radical oxidation to form the
trapping layer 1720 and the outer charge -trapping layer 1722 anti-tunneling layer 1820. A suitable thickness for the sec
is approximately 1: 1 in some embodiments, although other ond charge trapping layer 1818 may be at least 30 Å , and a
ratios are also possible . suitable thickness for the blocking dielectric 1812 may be
In other embodiments, either or both of the outer charge- 40 from about 30-70 Å .
trapping layer 1722 and the blocking dielectric 1716 may The memory device 1800 of FIG . 18A can be made using
comprise a high K dielectric. Suitable high K dielectrics either a gate first or a gate last scheme. FIGS. 19A - F
include hafnium based materials such as HfSION , HfSiO or illustrate a gate first scheme for fabricating the non -planar
HfO , Zirconium based material such as ZrSiON , ZrSiO or multigate device of FIG . 18A . FIGS. 20A - F illustrate a gate
Zro , and Yttrium based material such as Y203. 45 last scheme for fabricating the non -planar multigate device
FIG . 17C illustrates a cross - sectional view of a vertical of FIG . 18A .
string of non - planar multigate devices 1700 of FIG . 17A Referring to FIG . 19A , in a gate first scheme a first or
arranged in a Bit - Cost Scalable or BiCS architecture 1726 . lower dielectric layer 1902 , such as a blocking oxide , is
The architecture 1726 consists of a vertical string or stack of formed over a first, doped diffusion region 1904 , such as a
non -planar multigate devices 1700 , where each device or 50 source or a drain , in a substrate 1906. A gate layer 1908 is
cell includes a channel 1702 overlying the substrate 1706 , deposited over the first dielectric layer 1902 to form a
and connecting a source and a drain (not shown in this control gate of the device , and a second or upper dielectric
figure) of the memory device , and having a gate -all -around layer 1910 formed thereover. As with embodiments
(GAA ) structure in which the nanowire channel 1702 is described above, the first and second dielectric layers 1902,
enclosed on all sides by a gate 1712. The BiCS architecture 55 1910 , can be deposited by CVD , radical oxidation or be
reduces number of critical lithography steps compared to a formed by oxidation of a portion of the underlying layer or
simple stacking of layers , leading to a reduced cost per substrate. The gate layer 1908 can comprise a metal depos
memory bit. ited or a doped polysilicon deposited by CVD . Generally the
In another embodiment, the memory device is or includes thickness of the gate layer 1908 is from about 40-50 Å , and
a non -planar device comprising a verticalnanowire channel 60 the first and second dielectric layers 1902 , 1910 , from about
formed or from a semiconducting material projecting 20-80 Å .
above or from a number of conducting, semiconducting Referring to FIG . 19B , a first opening 1912 is etched
layers on a substrate. In one version of this embodiment, through the overlying gate layer 1908, and the first and
shown in cut-away in FIG . 18A , the memory device 1800 second dielectric layers 1902, 1910 , to the diffusion region
comprises a vertical nanowire channel 1802 formed in a 65 1904 in the substrate 1906.Next, layers of a tunneling oxide
cylinder of semiconducting material connecting a source 1914 , charge- trapping region 1916 , and blocking dielectric
1804 and drain 1806 of the device . The channel 1802 is 1918 are sequentially deposited in the opening and the
 US 10,593,812 B2
31 32
surface of the upper dielectric layer 1910 planarize to yield intermediate structure shown in FIG . 20C . In some embodi
the intermediate structure shown in FIG . 19C . ments , such as that shown in FIG . 20D , the charge-trapping
Although not shown, it will be understood that as in the region 2016 can be a split charge -trapping region including
embodiments described above the charge-trapping region at least a first or inner charge trapping layer 2016 a closest to
1916 can include a split charge- trapping region comprising 5 the tunnel oxide 2014 , and a second or outer charge trapping
at least one lower or bottom charge -trapping layer closer to layer 2016b . Optionally, the first and second charge trapping
the tunnel oxide 1914 , and an upper or top charge-trapping layers can be separated by an intermediate oxide or anti
layer overlying the bottom charge -trapping layer.Generally,
the top charge - trapping layer comprises a silicon -rich , oxy tunneling layer 2020 .
gen -lean nitride layer and comprises a majority of a charge 10 opening 2012gateandlayer
Next , a 2022 is deposited into the second
traps distributed in multiple charge-trapping layers, while 2002 planarized to yield the of
the surface the upper dielectric layer
intermediate structure illus
the bottom charge -trapping layer comprises an oxygen -rich trated in FIG . 20E . As with embodiments described
nitride or silicon oxynitride, and is oxygen -rich relative to the gate layer 2022 can comprise a metal depositedabove or
,
a
the top charge -trapping layer to reduce the number of charge
traps therein . In some embodiments, the split charge-trap- 15 doped polysilicon . Finally , an opening 2024 is etched
ping region 1916 further includes at least one thin , interme through the gate layer 2022 to form control gate of separate
diate or anti-tunneling layer comprising a dielectric , such as memory devices 2026 .
an oxide, separating the top charge -trapping layer from the Thus, a method for fabricating a nonvolatile charge trap
bottom charge -trapping layer. memory device has been disclosed . In accordance with an
Next, a second or channel opening 1920 is anisotropically 20 embodiment of the present invention , a substrate is sub
etched through tunneling oxide 1914 , charge -trapping jected to a first radical oxidation process to form first
region 1916 , and blocking dielectric 1918 , FIG . 19D .Refer dielectric layer in a first process chamber of a cluster tool.
ring to FIG . 19E , a semiconducting material 1922 is depos A charge - trapping layer may then be deposited above the
ited in the channel opening to form a vertical channel 1924 first dielectric layer in a second process chamber of the
therein . The vertical channel 1924 can include an annular 25 cluster tool. In one embodiment, the charge -trapping layer is
region in an outer layer of a substantially solid cylinder of then subjected to a second radical oxidation process to form
semiconducting material, or, as shown in FIG . 19E , can a second dielectric layer above the charge-trapping layer by
include a separate , layer semiconducting material 1922 oxidizing a portion of the charge -trapping layer in the first
surrounding a cylinder of dielectric filler material 1926 .
Referring to FIG . 19F, the surface of the upper dielectric 30 process
an oxide
chamber of the cluster tool. By forming all layers of
-nitride-oxide (ONO ) stack in a cluster tool, inter
layer 1910 is planarized and a layer of semiconducting face damage may be reduced between the respective layers.
material 1928 including a second , doped diffusion region Thus, in accordance with an embodiment of the present
1930 , such as a source or a dra formed therein deposited invention , an ONO stack is fabricated in a single pass in a
over the upper dielectric layer to form the device shown.
Referring to FIG . 20A , in a gate last scheme a dielectric 35 cluster tool in order to preserve a pristine interface between
layer 2002 , such as an oxide, is formed over a sacrificial the layers in the ONO stack . In a specific embodiment, the
cluster tool is a single-wafer cluster tool.
layer 2004 on a surface on a substrate 2006 , an opening
etched through the dielectric and sacrificial layers and a
vertical channel 2008 formed therein . As with embodiments What is claimed is:
described above, the vertical channel 2008 can include an 40 1. A memory device , comprising :
annular region in an outer layer of a substantially solid a channel formed over a semiconductormaterial structure
cylinder of semiconducting material 2010 , such as polycrys connecting a first and second diffusion regions , the
talline or monocrystalline silicon, or can include a separate , channel being formed from a layer of semiconductor
layer semiconducting material surro rrounding a cylinder of material;
dielectric filler material (not shown ). The dielectric layer 45 a tunnel oxide disposed abutting the channel;
2002 can comprise any suitable dielectric material , such as a multi -layer charge storing layer including a first nitride
a silicon oxide , capable of electrically isolating the subse layer disposed adjacent to the tunnel oxide and a
quently formed gate layer of the memory device 1800 from second nitride layer overlying the first nitride layer, the
an overlying electrically active layer or another memory first nitride layer being substantially trap free and the
device. The sacrificial layer 2004 can comprise any suitable 50 second nitride layer being trap dense, wherein the first
material that can be etched or removed with high selectivity and second nitride layers have differing compositions
relative to the material of the dielectric layer 2002 , substrate of silicon , oxygen , and nitrogen ; and
2006 and vertical channel 2008 . a blocking dielectric layer including high -temperature
Referring to FIG . 20B , a second opening 2012 is etched oxide (HTO ) disposed adjacent to the second nitride
through the etched through the dielectric and sacrificial 55 layer,
layers 2002 , 2004 , to the substrate 1906 , and the sacrificial wherein at least one of the blocking dielectric layer and
layer 2004 etched or removed . The sacrificial layer 2004 can the second nitride layer includes a high K dielectric
comprise any suitable material that can be etched or material, and wherein the tunnel oxide, the multi-layer
removed with high selectivity relative to the material of the charge storing layer, and the blocking dielectric layer
dielectric layer 2002, substrate 2006 and vertical channel 60 are disposed overlying at least a top surface and two
2008. In one embodiment the sacrificial layer 2004 com side surfaces of the channel.
prises that can be removed by Buffered Oxide Etch (BOE 2. The memory device of claim 1, wherein the high K
etch ). dielectric material in at least one of the blocking dielectric
Referring to FIGS . 20C and 20D , layers of a tunneling layer and the second nitride layer is a zirconium based
oxide 2014 , charge - trapping region 2016 , and blocking 65 high -K dielectric material.
dielectric 2018 are sequentially deposited in the opening and 3. The memory device of claim 2 , wherein the channel
the surface of the dielectric layer 2002 planarize to yield the comprises recrystallized polysilicon .
 US 10,593,812 B2
33 34
4. The memory device of claim 1, wherein the high K dense, wherein the first and second nitride layers
dielectric material in at least one of the blocking dielectric have differing compositions of silicon , oxygen , and
layer and the second nitride layer is an yttrium based high -K nitrogen ; and
dielectric material. the multi -layer charge storing layer is enclosed on all
5. The memory device of claim 1, wherein the high K 5 sides by a blocking dielectric layer including high
dielectric material in at least one of the blocking dielectric temperature -oxide (HTO ) disposed adjacent to the
layer and the second nitride layer is a hafnium based high -K second nitride layer, wherein at least one of the
dielectric material. blocking dielectric layer and the second nitride layer
includes a high K dielectric material.
6. The memory device of claim 1, wherein the channel 10 13. The memory device of claim 12 , wherein the high K
comprises polysilicon . dielectric material in at least one of the blocking dielectric
7. The memory device of claim 1 , wherein the channel layer and the second nitride layer is a zirconium based
comprises a silicon nanowire . high - K dielectric material.
8. The memory device of claim 7 , wherein the channel, 14. The memory device of claim 12 , wherein the high K
dielectric material in at least one of the blocking dielectric
first and second diffusion regions are suspended above the 15 dielectric
semiconductor material structure . layer and thematerial
second. nitride layer is an yttrium based high-K
9. Thememory device of claim 1, wherein the channel is 15. The memory device of claim 12 , wherein the high K
disposed over an insulating layer , the insulating layer being dielectric material in at least one of the blocking dielectric
disposed overlying the semiconductor material structure. layer and the second nitride layer is a hafnium based high -K
10. The memory device of claim 1, wherein the first 20 dielectric material.
nitride layer of the multi - layer charge storing layer includes 16. The memory device of claim 12 , wherein an anti
an oxygen -rich nitride having a concentration of oxygen in tunneling layer including oxide is disposed between the first
range of 15 % to 40 % , and wherein the second nitride layer and second nitride layers of the multi -layer charge storing
includes an oxygen -lean nitride layer having a concentration layer .
17. The memory device of claim 12 , wherein the first
of oxygen in a range of less than 5 % . 25
11. The memory device of claim 1, wherein the channel nitride layer of the multi -layer charge storing layer includes
is vertical and oriented substantially perpendicular to a top a range of -15rich% tonitride
an oxygen having a concentration of oxygen in
40 % , and wherein the second nitride layer
surface of the semiconductor material structure .
12. A memory device, comprising : includes an oxygen -lean nitride layer having a concentration
30 of oxygen in a range of less than 5 % .
a gate structure ; and 18. The memory device of claim 12 , wherein each of the
multiple nanowire channels enclosed on all sides by the nanowire channel is formed from a thin strip of crystalline
gate structure , the multiple nanowire channels being silicon material having a maximum cross -sectional dimen
stacked vertically and each being suspended horizon sion of less than 10 nm .
tally above a semiconductor material structure , 35 19. The memory device of claim 12 , wherein each of the
wherein :
each of the multiple nanowire channels is enclosed on multiple nanowire channels is formed from a thin strip of
crystalline silicon material having < 100 > surface crystalline
all sides by a tunnel oxide layer ;
the tunnel oxide layer is enclosed on all sides by a orientation relative to a long axis of the multiple nanowire
multi-layer charge storing layer including a first channels .
20. The memory device of claim 12, wherein the multiple
nitride layer disposed adjacent to the tunnel oxide 40 nanowire channels are arranged in a Bit -Cost Scalable
layer and a second nitride layer overlying the first (BiCS ) architecture
nitride layer, the firstnitride layer being substantially .
trap free and the second nitride layer being trap