Final Project: Colorequence A Didactic Game: Digital Systems With Reconfigurable Logic

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Final Project: Colorequence A

Didactic Game
Digital Systems with Reconfigurable Logic
Members:
Alejandro Mellado Morales

Jorge Guerrero Montes
José Carlos Esquivel García
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TABLE OF CONTENT
TABLE OF CONTENT ............................................................................................................................................................................... 2

TABLE OF ILUSTRATIONS .................................................................................................................................................................... 2
INTRODUCTION ........................................................................................................................................................................................ 3
PRIMARY OUTCOME ........................................................................................................................................................................... 3
GENERAL DESCRIPTION ................................................................................................................................................................... 3
THEORETICAL FRAMEWORK ............................................................................................................................................................. 3
DEVELOPMENTAL COORDINATION DISORDER ..................................................................................................................... 4
ATTENTION DEFICIT/HYPERACTIVITY DISORDER .............................................................................................................. 4
ATTENTION DEFICIT DISORDER WITHOUT HYPERACTIVITY ......................................................................................... 5
FPGA AND ACTIVE VHDL .................................................................................................................................................................. 5
GENERAL CARACTERISTICS OF Cyclone® IV EP4CE115 .................................................................................................. 6
VISUAL STUDIO .................................................................................................................................................................................... 7
RS-232 ...................................................................................................................................................................................................... 7
ADC ............................................................................................................................................................................................................ 8
METHODOLOGY ........................................................................................................................................................................................ 8
RESULTS .................................................................................................................................................................................................... 19
CONCLUSION ........................................................................................................................................................................................... 26
REFERENCES ........................................................................................................................................................................................... 27
TABLE OF ILUSTRATIONS
FIGURE 1. THE DE2-115 BOARD .................................................................................................................................................................... 7
FIGURE 2: EXAMPLE OF THE RS-232 COMMUNICATION. ............................................................................................................................. 8
FIGURE 3: CONCEPT DESIGN OF THE PROJECT AND THE CONTROLLER. ................................................................................................... 19
FIGURE 4: RESULT OF THE CONTROLLER BUILT. ......................................................................................................................................... 20
FIGURE 5: 3D PRINTED PART TO HOST THE LEDS AND THE BUTTON. .................................................................................................... 21
FIGURE 6: 3D PRINTED PART TO HOST THE LEDS AND THE BUTTON. .................................................................................................... 22
FIGURE 7: 3D PRINTED PARTS HOSTING THE PUSH BUTTONS................................................................................................................... 22
FIGURE 8: LED IGNITED WITHIN THE PUSH BUTTON COCOON. ................................................................................................................ 23
FIGURE 9: LOOK AT THE HOLLOW SPACE OF THE CONTROLLER TO HOST THE CIRCUITRY OF THE PROJECT . ..................................... 24
FIGURE 10: GRAPHIC USER INTERFACE DEVELOPED IN THE IDE VISUAL STUDIO. .............................................................................. 25
FIGURE 11: CONNECTIONS TO THE FPGA. .................................................................................................................................................. 26
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INTRODUCTION
PRIMARY OUTCOME
Design an educational Joystick able to detect different common problems related to kid-
learning and motor coordination. This device will be programmed with a basic game
(scalable to more games): the classic game to remember the order and press the button
as fast as you can in a specific given order.
GENERAL DESCRIPTION
In order to enhance the understanding and detection of motor coordination issues and
attention deficit in children, this project will design an educational device which will consist
of four colored buttons with LEDs inside. The device will run a sequence that the children
will have to reproduce by pushing the buttons according to the previously indicated order.
Thus, via UART communication (RS-232), the device will send the score to a computer
user interface. This UI is meant to be user friendly, easy-to-use, and colorful. Hence, it
may attract the kids’ attention. The device will also have two pots to regulate the time
base, which regulates the time given to the user to reproduce the sequence, and the
luminous intensity of the LEDs -which is helpful in cases where photophobia is present-.
The heart of the project will be an FPGA programmed with the sequence, the
communication via RS-232, and the Analog-to-Digital conversion interpreter.
THEORETICAL FRAMEWORK
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DEVELOPMENTAL COORDINATION DISORDER
DCD is a motor skills disorder that affects five to six percent of all school-aged children.
DCD occurs when a delay in the development of motor skills, or difficulty coordinating
movements, results in a child being unable to perform common, everyday tasks. By
definition, children with DCD do not have an identifiable medical or neurological condition
that explains their coordination problems.
Children with DCD have difficulty mastering simple motor activities, such as tying shoes
or going downstairs, and are unable to perform age-appropriate academic and self-care
tasks. Some children may experience difficulties in a variety of areas while others may
have problems only with specific activities.
Children with DCD usually have normal or above average intellectual abilities. However,
their motor coordination difficulties may impact their academic progress, social
integration and emotional development.
Also, DCD is commonly associated with other developmental conditions, including
attention deficit/hyperactivity disorder (ADHD), learning disabilities (LD), speech-
language delays and emotional and behavioral problems [1].
In order to give a diagnosis of DCD, the following criteria are necessary [1]:
A. Learning an execution of coordinated motor skills is below expected level for age.
B. Motor skill difficulties significantly interfere with the activities of daily living and
impact academic/school productivity, prevocational and vocational activities,
leisure and play.
C. Onset is in the early developmental period.
D. Motor skill difficulties are not better explained by intellectual delay, visual
impairment or other neurological conditions that affect movement.
ATTENTION DEFICIT/HYPERACTIVITY DISORDER
ADHD is a neurological disorder that causes a range of behaviour problems such as

difficulties with attending to instructions, focusing on schoolwork, keeping up with
assignments, completing tasks, and social interaction [2]. There are three types [3]:
1. ADHD, combined: The most common type. A child is impulsive and hyperactive.
Also has trouble paying attention and is easily distracted.
2. ADHD, impulsive/hyperactive: The least common type. A child is impulsive and
hyperactive, but does not have trouble paying attention.
3. ADHD, inattentive and distractible: A child with this type is mostly inattentive and
easily distracted.
It is a brain-based problem. Children with ADHD have low levels of a brain chemical
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(dopamine). Studies show that brain metabolism in children with ADHD is lower in the
parts of the brain that control attention, social judgement, and movement [3].
The most common symptoms are [3]:
• Inattention: short attention span for age, hard time listening to others, hard time
attending to details, easily distracted, forgetful, poor organizational skills, and poor
study skills for age.
• Impulsivity: often interrupts, has a hard time waiting, tends to blurt out answers
instead of waiting to be called on, takes risks often, and often without thinking
before acting.
• Hyperactivity: seems to always be in motion, has a hard time staying in a seat,
fidgets with hands or squirms when in a seat, talks a lot, hard time doing quiet
activities, loses or forgets things repeatedly, is not able to stay on a task and shifts
from one to another without completing any.
ATTENTION DEFICIT DISORDER WITHOUT HYPERACTIVITY
In the Diagnostic and Statistical Manual of Mental Disorders, Fifth Edition (DSM-5), this
condition is officially known as “attentional deficit/hyperactivity disorder, predominantly
inattentive presentation” [2]. People with the inattentive type of ADHD struggle to pay
attention or stay focused for long periods of time. Some of the symptoms of this type of
ADHD include [2]:
• Being easily distracted.

• Difficulty following directions.
• Difficulty staying on task.
• Forgetfulness.
• Losing personal items.
• Not paying attention.
• Problems staying organized.
• Short attention span.
Children may appear to be bored or disinterested in classroom activities. They may also
be prone to daydreaming and forgetfulness, work at slow pace, and turn in incomplete
work [2].
FPGA AND ACTIVE VHDL
An FPGA (field-programmable gate array) is a field-programmable logic gate matrix, that

is, it is a programmable device that contains blocks of logic whose interconnection and
functionality can be configured at the moment. FPGAs are similar to ASICs however they
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are slower, have higher power consumption and cannot cover such complex systems [4].
Active is a private electronic project automation company, which provides computer
applications and instruments, involving FPGAs. Among the software they offer is Active-
HDL, which is an integrated FPGA design creation and simulation solution for computer-
based environments.
GENERAL CARACTERISTICS OF Cyclone® IV EP4CE115
The DE2 series has consistently been at the forefront of educational development boards
by distinguishing itself with an abundance of interfaces to accommodate various
application needs. The Terasic DE2-115 offers an optimal balance of low cost, low power
and a rich supply of logic, memory and DSP capabilities (Terasic Inc., 2021)
Cyclone® IV EP4CE115
• 114,480 logic elements (LEs)
• 3,888 Embedded memory (Kbits)
• 266 Embedded 18 x 18 multipliers
• 4 General-purpose PLLs
• 528 User I/Os
Memory Devices
• 128MB (32Mx32bit) SDRAM
• 2MB (1Mx16) SRAM
• 8MB (4Mx16) Flash with 8-bit mode
• 32Kbit EEPROM
Switches and Indicators

• 18 switches and 4 push-buttons
• 18 red and 9 green LEDs
• Eight 7-segment displays
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Figure 1. The DE2-115 Board
VISUAL STUDIO
Microsoft Visual Studio is an integrated development environment (IDE) from Microsoft.

It is used to develop computer programs, as well as websites, web apps, web services
and mobile apps. Visual Studio uses Microsoft software development platforms such as
Windows API, Windows Forms, Windows Presentation Foundation, Windows Store and
Microsoft Silverlight. It can produce both native code and managed code [5].
RS-232
RS-232 (Recommended Standard 232) - standard describes an interface for serial bi-
directional data transfer between the terminal (DTE, Data Terminal Equipment) and end-
device (DCE, Data Circuit-Terminating Equipment) [6].
The data transmission format is asynchronous, since a separate signal is not required
for synchronization, but each character includes both the 8 data bits and the start and
stop bits to establish it. The start bit, or start bit, has the function of providing the
synchronization signal so that the receiving device can sample the rest of the eight data
bits - this through a rising edge -. The transmission speed defines the period of each of
the bits. At the end of the frame, the stop bits are generated, whose function is to return
the signal to the low state to prepare the next rising edge (start bit) [6].
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Figure 2: Example of the RS-232 communication.
ADC
Analog to digital conversion is the process of transforming the signal from the analog
domain to the digital domain. This process could take place at baseband, as is the case
of direct conversion receivers, or at intermediate frequency (IF) or low IF depending on
the requirements and consequently on the receiver architecture pursued by the designers
[7].
The converted digital output for a given converter is in standard binary format. Actual
converter circuits, however, may use any one of a variety of codes, including binary, Gray
Code, excess 3, and others [7].
METHODOLOGY
I. Build the controller for the game, this one will have the following characteristics:
a. Made of wood.
b. 4 holes to host the push buttons.
c. Hollow space to host the circuitry.
d. 2 holes to host the two pots.
II. Assemble the controller.
III. Develop the game, the UART communication, and the ADC interpreter as
following:
a. Code of the game, programmed in Active VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH. all;
entity GAME1 is
generic( -- Porque
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no son variables fisicas, son seniales

K: integer:= 11; -- Constante del
comparador
N: integer:= 4 -- Cuantos
bits necesito para representar a K -- RECORDAR QUE COMO ES
EL ULTIMO, NO LLEVA ;
);
port(
RST : in STD_LOGIC;
-- Reset maestro
H : in STD_LOGIC;
-- Senial de habilitacion de la base de tiempo
(Hace que el contador funcione)
BTN1: in STD_LOGIC;
BTN2: in STD_LOGIC;
BTN3: in STD_LOGIC;
BTN4: in STD_LOGIC;
LOSE: in STD_LOGIC;
LED : out STD_LOGIC_VECTOR(3 downto 0);
puntos : out STD_LOGIC_VECTOR(7 downto 0)
);
end GAME1;
architecture Behavioral of GAME1 is

signal Qp, Qn : STD_LOGIC_VECTOR(N-1 downto 0):=(others => '0');
-- Qn es lo que valdra en el futuro y Qp es el
valor actual
signal flag : STD_LOGIC:='0';
signal flagconH: STD_LOGIC_VECTOR(1 downto 0):=(others => '0');
signal CTA : STD_LOGIC_VECTOR(N-1 downto 0):=(others => '0');
signal BTN : STD_LOGIC:='0';
begin
CTA <= Qp;

flagconH <= flag & H;
-- Define si se incrementa el contador aumenta o se

reinicia
Mux: process(flagconH, Qp) is
-- Se pone en proceso las
variables a utilizar para comparar
begin
case flagconH is
when "01" => Qn <= Qp + 1;
when "11" => Qn <= (Others=>'0');
when others => Qn <= Qp;
end case;
end process Mux;
Comparador: process (Qp, H) is

begin
if Qp = K then
flag <= '1';
else
flag <= '0';
end if;
end process Comparador;
combinacional: process (BTN, RST) is -- Registro

begin
if RST = '0' then
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Qp <= (others=>'0');
elsif BTN'event and BTN= '1' then
Qp <= Qn;
end if;
end process combinacional;
secuencia: process (CTA, BTN1, BTN2, BTN3, BTN4, LOSE) is

begin
case CTA is
when "0000" => LED <="0010";
--2|
when "0001" => LED <="0001"; -
-1|
when "0010" => LED <="1000";
--4|
when "0011" => LED <="0100";
--3|
when "0100" => LED <="0001";
--1|
when "0101" => LED <="1000";
--4|
when "0110" => LED <="0010";
--2|
when "0111" => LED <="0100";
--3|
when "1000" => LED <="0001";
--1|
when "1001" => LED <="1000";
--4|
when "1010" => LED <="1111";
when others => LED <= (others => '0');
end case;
case CTA is
when "0000" => puntos <="00000000";
when "0001" => puntos <="00000001";
when "0010" => puntos <="00000010";
when "0011" => puntos <="00000011";
when "0100" => puntos <="00000100";
when "0101" => puntos <="00000101";
when "0110" => puntos <="00000110";
when "0111" => puntos <="00000111";
when "1000" => puntos <="00001000";
when "1001" => puntos <="00001001";
when "1010" => puntos <="00001011";
when others => puntos <= (others => '0');
end case;
if LOSE ='1' then

LED <="1111";
end if;
if (BTN2 = '1' and CTA = "0000" and LOSE='0')

then --2
BTN <= '1';
elsif (BTN1 = '1' and CTA = "0001" and LOSE='0')
then --1
BTN <= '1';
then --4
BTN <= '1';
then --3
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BTN <= '1';

then --1
BTN <= '1';
then --4
BTN <= '1';
then --2
BTN <= '1';
then --3
BTN <= '1';
then --1
BTN <= '1';
then --4
BTN <= '1';
else
BTN <= '0';
end if;
end process secuencia;
end Behavioral;
b. Code of the time base, programmed in Active VHDL:
library IEEE;
entity PULSO_SEGUNDO is -- BASE DE TIEMPO

GENï¿½RICA
generic( -- Porque
no son variables fï¿½sicas, son seï¿½ales
K: integer:= 1*49999999; -- Constante del
comparador
N: integer:= 30 -- Cuï¿½ntos bits
necesito para representar a K -- RECORDAR QUE COMO ES EL
ï¿½LTIMO, NO LLEVA ;
);
port(
CLK : in STD_LOGIC; -- Reloj maestro
NORMAL DE 50MHz
RST : in STD_LOGIC; -- Reset maestro
H : in STD_LOGIC; -- Seï¿½al de
habilitaciï¿½n de la base de tiempo (Hace que el contador
funcione)
BT : out STD_LOGIC; -- Base de tiempo
-- RECORDAR QUE COMO ES EL ï¿½LTIMO, NO LLEVA ;
LED : out STD_LOGIC -- Salida a LED
);
end PULSO_SEGUNDO;
architecture Behavioral of PULSO_SEGUNDO is

-- Qn es lo que valdrï¿½ en el futuro y Qp es el
valor actual
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signal BdT : STD_LOGIC:='0';

signal BAN : STD_LOGIC:='0';
signal BAN_2 : STD_LOGIC:='0';
signal ONOFF : STD_LOGIC_VECTOR(1 downto 0):=(others => '0');
signal BdTconH : STD_LOGIC_VECTOR(1 downto 0):=(others => '0');
begin
BT <= BdT;
BdTconH <= BdT & H;
ONOFF <= BAN & BAN_2;
LED <= BAN;
-- Define si se incrementa el contador aumenta o se

reinicia
Mux: process(BdTconH, Qp) is
begin
case BdTconH is
when "01" => Qn <= Qp + 1;
when "11" => Qn <= (Others=>'0');
end case;
end process Mux;
Comparador: process (Qp, RST) is

begin
if Qp = K then
BdT <= '1';
BAN <= not BAN_2;
else
BdT <= '0';
end if;
if RST = '0' then
BdT <= '0';
end if;
combinacional: process (CLK, RST) is -- Registro

begin
if RST = '0' then
elsif CLK'event and CLK= '1' then
Qp <= Qn;
BAN_2 <= BAN;
end if;
end Behavioral;
c. Codes for the RS-232 communication, programmed in Active VHDL:
Transmitter:
library IEEE;
use IEEE.STD_LOGIC_ARITH.all;
entity TX is
port(
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BAUD : in STD_LOGIC; -- Baudios

SND : in STD_LOGIC;
DATO : in std_logic_vector(7 downto 0);
Tx : out std_logic
); -- Salida de secuencia
end TX;
architecture simple of TX is
signal Qp, Qn : std_logic_vector(4 downto 0) := (others => '0');
signal Tx_s : std_logic:='1';
signal start : std_logic:='0';

signal data : std_logic_vector(7 downto 0):=(others=>'0');
signal stop : std_logic:='1';

signal parity : std_logic:='0';
begin
Tx <= Tx_s;
data <= DATO;
secuencial: process (Qp,BAUD) is

begin
case Qp is
when "00000" =>
if BAUD ='1' and SND = '1' then
Tx_s <= start;
Qn <= "00001";
end if;
when "00001" =>
Tx_s <= data(0);
Qn <= "00010";
when "00010" =>

Tx_s <= data(1);
Qn <= "00011";
when "00011" =>

Tx_s <= data(2);
Qn <= "00100";
when "00100" =>

Tx_s <= data(3);
Qn <= "00101";
when "00101" =>

Tx_s <= data(4);
Qn <= "00110";
when "00110" =>

Tx_s <= data(5);
Qn <= "00111";
when "00111" =>

Tx_s <= data(6);
Qn <= "01000";
when "01000" =>

Tx_s <= data(7);
Qn <= "01001";
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--when "01001" =>

--Tx_s <= parity;
--Qn <= "01010";
when "01001" =>

Tx_s <= stop;
Qn <= "01011";
when others =>

Tx_s <= '1';
Qn <= (others => '0');
end case;
end process secuencial;
FF: process(BAUD) is
begin
if BAUD'event and BAUD = '1' then
Qp <= Qn;
end if;
end process FF;
end architecture simple;
Receiver:
library IEEE;
use IEEE.STD_LOGIC_ARITH.all;
entity RX is
port(
BAUD : in std_logic;
RST : in std_logic;
Rx : in std_logic;
start: out std_logic
);
end entity RX;
architecture simple of RX is
signal Qp, Qn : std_logic_vector (4 downto 0):=(others => '0');
signal data : std_logic_vector(7 downto 0) :=(others => '0');
signal Rx_s : std_logic:='1';
signal leds: std_logic_vector(7 downto 0):=(others=>'0');
--signal start : std_logic:='0';
signal parity : std_logic :='0';
signal stop : std_logic :='1';
begin
Rx_s <= Rx;
secuencial:process (Qp, Rx_s) is

begin
case Qp is
when "00000" =>
if Rx_s = '0' then
Qn <= "00001";
else
Qn <="00000";
end if;
when "00001" =>
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data(0) <= Rx_s;

Qn <= "00010";
when "00010" =>

data(1) <= Rx_s;
Qn <= "00011";
when "00011" =>

data(2) <= Rx_s;
Qn <= "00100";
when "00100" =>

data(3) <= Rx_s;
Qn <= "00101";
when "00101" =>

data(4) <= Rx_s;
Qn <= "00110";
when "00110" =>

data(5) <= Rx_s;
Qn <= "00111";
when "00111" =>

data(6) <= Rx_s;
Qn <= "01000";
when "01000" =>

data(7) <= Rx_s;
Qn <= "01001";
when "01001" =>

parity <= Rx_s;
Qn <= "01010";
when "01010" =>

stop <= Rx_s;
Qn <= "01011";
when others =>
Qn <= (others => '0');
end case;
end process secuencial;
mostrar:process(data) is
begin
case data is
when "00000001"=>
start<='1';
when "00000000"=>
start<='0';
when others =>
start<='0';
end case;
end process mostrar;
FF:process (RST, BAUD) is

begin
if RST = '0' then
Qp <= (others => '0');
elsif BAUD'event and Baud ='1' then
Qp <= Qn;
end if;
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end process FF;
end architecture simple;
d. Code for the score, programmed in Active VHDL:
library IEEE;
entity CUENTA is
generic( -- Porque
no son variables fisicas, son seniales
K: integer:= 10; -- Constante del
comparador
N: integer:= 6 -- Cuantos
bits necesito para representar a K
);
port(
PULS: in STD_LOGIC; -- Reloj maestro
NORMAL DE 50MHz
RST : in STD_LOGIC; -- Reset maestro
H : in STD_LOGIC; -- Senial de
habilitacion de la base de tiempo (Hace que el contador funcione)
CUEN: out STD_LOGIC_VECTOR(N-1 downto 0)
);
end CUENTA;
architecture Behavioral of CUENTA is

signal flag : STD_LOGIC:='0';
signal flagconH: STD_LOGIC_VECTOR(1 downto 0):=(others => '0');
signal CTA : STD_LOGIC_VECTOR(5 downto 0):=(others => '0');
begin
CUEN <= Qp;

flagconH <= flag & H;
Mux: process(flagconH, Qp) is

begin
case flagconH is
when "01" => Qn <= Qp + 1;
when "11" => Qn <= (Others=>'0');
end case;
end process Mux;
Comparador: process (Qp, H) is

begin
if Qp = K then
flag <= '1';
else
flag <= '0';
end if;
combinacional: process (PULS, RST) is -- Registro

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begin
if RST = '0' then
elsif PULS = '1' then
Qp <= Qn;
end if;
end Behavioral;
e. Assembly of the previous codes, programmed in Active VHDL:
library IEEE;
entity PROYECTO is
generic(
count : integer:= 1*49999999;
bits : integer:= 27*3;
KA : integer:= 10;
NUM : integer:= 6
);
port(
CLK : in STD_LOGIC;
--RST : in STD_LOGIC;
push1: in STD_LOGIC;
ADC1 : in STD_LOGIC;
ADC2 : in STD_LOGIC;
SWTH : in STD_LOGIC;
MUESTRA : OUT STD_LOGIC;
MUESTRA2: OUT STD_LOGIC;
pin_tx : OUT STD_LOGIC;
pin_rx : IN STD_LOGIC;
FOCO1 : OUT STD_LOGIC;
LED : OUT std_logic_vector(3 downto 0)
);
end PROYECTO;
architecture completa of PROYECTO is
signal CTA : std_logic_vector(NUM-1 downto 0);

signal RST : std_logic:='1';
signal temp1 : std_logic;
signal jugando: std_logic;
signal pulso : std_logic;
signal pulso0 : std_logic;
signal puntos : std_logic_vector(7 downto 0);
signal send : std_logic:='0';
signal H : std_logic;
signal baudios: std_logic;
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signal start : std_logic;

signal loser : std_logic:='0';
begin
H <= jugando;
RST <= jugando;
FOCO1<= H;
FOCO2<= RST;
FOCO3<= loser;
FOCO4<= pulso;
MUESTRA <= ADC1;
MUESTRA2<= ADC2;
U : entity work.PULSO_SEGUNDO generic map
(15*49999999, 40) port map (CLK, RST, H, temp1, pulso0);
U0 : entity work.PULSO_SEGUNDO generic map
U3 : entity work.CUENTA port map (pulso, RST, H,
CTA);
U4 : entity work.GAME1 port map (RST, H, push1,
push2, push3, push4, loser, LED, puntos);
U5 : entity work.TX port map (baudios, send,
puntos, pin_tx);
U6 : entity work.RX port map (baudios, RST,
pin_rx, start);
U7 : entity work.PULSO_SEGUNDO generic map (488, 13)
port map (CLK, RST, H, baudios);--5209
timeover: process (pulso, RST, jugando) is

begin
if pulso = '1' and RST = '0' then
loser <= '0';
elsif pulso='0' then
loser <='1';
end if;
end process timeover;
hard: process (ADC1, ADC2, loser) is

begin
if (ADC1='1' and ADC2='1' and loser='0') then
pulso <= pulso3;
elsif (ADC1='1' and ADC2='0' and loser='0') then
pulso <= pulso2;
pulso <= pulso1;
pulso <= pulso0;
else
pulso <= '1';
end if;
end process hard;
envio: process (loser, pin_rx) is

begin
if loser='1' then --MODIFICAR PARA QUE NO ENVÃ•E
POR TODO EL SEGUNDO.
send <='1';
jugando <='0';
--RST <= '0';
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else
send <= '1';
end if;
if pin_rx='0' then
jugando <= '1';
--RST <= '1';
end if;
end process envio;
end architecture completa;
IV. Develop the GUI using the IDE Visual Studio.

V. Verify that the programs execute well.
VI. Make the circuitry in protoboard to check the performance of the project.
VII. Once the project is running well, weld the components to a PCB.
VIII. Run the game.
RESULTS
We started by building the controller. We used wood for the structure, which was based
on the concept design shown in Figure 3:
Figure 3: Concept design of the project and the controller.
The result is appreciable in the next image (Look at Figure 4):

|
Figure 4: Result of the controller built.
The engineering behind the arrangement of the buttons and the pots is in the 3D printed
parts that were especially designed to fit with the dimensions of our controller. These
parts were designed in SolidWorks and the result are in Figure 5 and Figure 6.
|
Figure 5: 3D printed part to host the LEDs and the button.

|
Figure 6: 3D printed part to host the LEDs and the button.
We disassembled two plastic balls to make the push buttons (Look at Figure 7). As it
shown on the Figure 5 and Figure 6, the printed parts have space to host four LEDs.
Figure 7: 3D printed parts hosting the push buttons.

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Thus, when the LEDs ignite to show the sequence, the colored plastic will be illuminated
with an attractive glow (Look at Figure 8).
Figure 8: LED ignited within the push button cocoon.
Here on the Figure 9, we can appreciate a look to the hollow space that the controller
has for the circuitry.
|
Figure 9: Look at the hollow space of the controller to host the circuitry of the project.
Once the controller was finished, we started coding the game using Active VHDL. The
programs developed for the project are in the methodology section.
Meanwhile, we also started the programming for the UI, which result is shown in Figure
10.
|
Figure 10: Graphic User Interface developed in the IDE Visual Studio.
Finally, we linked the FPGA to the controller and to the PC (Look at Figure 11).
|
Figure 11: Connections to the FPGA.
CONCLUSION
This project was a real challenge, not just because it required from us to apply most of
the knowledge acquired in theoretical classes, it also put us to test. We had to do some
research so that we could achieve the goal.
We struggled a lot with the ADC interpreter and the RS-232 communication, principally
with the communication. Most of these problems were because, even though we were
programming well the code, the FPGA did not send or receive any data. In fact, for all
the codes we made more than three versions while we were seeking for the problem.
We also had to do some adjustments in the User Interface, because it was having some
trouble interpreting the data sent by the FPGA.
Fortunately, we found a way to make everything work. Yes, it is true that we had better
expectations for the final prototype, although we are proud of what we did and how it
ended working fine. One key element that helped us was the improvement in teamwork,
we started working separately and ended working organized and together.
|
REFERENCES
[1] Developmental Coordination Disorder. CanChild.
https://canchild.ca/en/diagnoses/developmental-coordination-disorder accesed on June
21st, 2021.
[2] Attention Deficit Disorder Without Hyperactivity. Very Well Mind. Logsdon, Ann.
https://www.verywellmind.com/add-and-attention-deficit-disorders-2161810 accesed on
June 21st, 2021.
[3] Attention-Deficit/Hyperactivity Disorder (ADHD) in Children. Stanford Children’s

Health. https://www.stanfordchildrens.org/en/topic/default?id=attention-
deficithyperactivitydisorderadhdinchildren-90-P02552 accesed on June 21st, 2021.
[4] Field Programmable Gate Array (FPGA). XILINX.

https://www.xilinx.com/products/silicon-devices/fpga/what-is-an-fpga.html accesed on
June 21st, 2021.
[5] Microsoft Visual Studio. Wikipedia.

https://en.wikipedia.org/wiki/Microsoft_Visual_Studio accesed on June 21st, 2021.
[6] RS-232 Recommended Standard. SoftElectro.

http://www.softelectro.ru/rs232_en.html accesed on June 21st, 2021.
[7] Analog to Digital Conversion. Science Direct. Rouphael, Tony & Terrell, David.
https://www.sciencedirect.com/topics/engineering/analog-to-digital-conversion accesed
on June 21st, 2021.

Final Project: Colorequence A Didactic Game: Digital Systems With Reconfigurable Logic

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Final Project: Colorequence A Didactic Game: Digital Systems With Reconfigurable Logic

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Final Project: Colorequence A

Alejandro Mellado Morales

TABLE OF CONTENT ............................................................................................................................................................................... 2

DEVELOPMENTAL COORDINATION DISORDER

ATTENTION DEFICIT/HYPERACTIVITY DISORDER

ADHD is a neurological disorder that causes a range of behaviour problems such as

ATTENTION DEFICIT DISORDER WITHOUT HYPERACTIVITY

• Being easily distracted.

FPGA AND ACTIVE VHDL

An FPGA (field-programmable gate array) is a field-programmable logic gate matrix, that

GENERAL CARACTERISTICS OF Cyclone® IV EP4CE115

Switches and Indicators

Figure 1. The DE2-115 Board

Microsoft Visual Studio is an integrated development environment (IDE) from Microsoft.

Figure 2: Example of the RS-232 communication.

no son variables fisicas, son seniales

architecture Behavioral of GAME1 is

signal BTN : STD_LOGIC:='0';

CTA <= Qp;

-- Define si se incrementa el contador aumenta o se

Comparador: process (Qp, H) is

combinacional: process (BTN, RST) is -- Registro

secuencia: process (CTA, BTN1, BTN2, BTN3, BTN4, LOSE) is

if LOSE ='1' then

if (BTN2 = '1' and CTA = "0000" and LOSE='0')

BTN <= '1';

end process secuencia;

b. Code of the time base, programmed in Active VHDL:

entity PULSO_SEGUNDO is -- BASE DE TIEMPO

architecture Behavioral of PULSO_SEGUNDO is

signal BdT : STD_LOGIC:='0';

-- Define si se incrementa el contador aumenta o se

Comparador: process (Qp, RST) is

combinacional: process (CLK, RST) is -- Registro

c. Codes for the RS-232 communication, programmed in Active VHDL:

BAUD : in STD_LOGIC; -- Baudios

signal start : std_logic:='0';

signal stop : std_logic:='1';

secuencial: process (Qp,BAUD) is

when "00010" =>

when "00011" =>

when "00100" =>

when "00101" =>

when "00110" =>

when "00111" =>

when "01000" =>

--when "01001" =>

when "01001" =>

when others =>

end architecture simple;

Rx_s <= Rx;

secuencial:process (Qp, Rx_s) is

data(0) <= Rx_s;

when "00010" =>

when "00011" =>

when "00100" =>

when "00101" =>

when "00110" =>

when "00111" =>

when "01000" =>

when "01001" =>

when "01010" =>