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FEATURES
• 8 Darlington Arrays per Package
• Minus 500 mA (Source) Output Current (Single Output)
• Output voltage 50V
• Output Clamp Diodes
• Input Compatible with Various Types of Logic
• Relay-Driver Applications SOP-18
• Input pins placed opposite to output pins to simplify
layout
APPLICATION
• Relay Drivers
• Stepper and DC Brushed Motor Drivers DIP-18
• Lamp Drivers
• Display Drivers
• Line Drivers
• Logic Buffers
ORDERING INFORMATION
Device Package
DESCRIPTION
TD62783AD SOP-18
The TD62783A is monolithic high-voltage, high-current
TD62783AN DIP-18
Darlington transistor arrays. Each consists of eight
NPN Darlington pairs that feature high-voltage outputs
with common-anode clamp diodes for switching
inductive loads. The collector-current rating of a single
Darlington pair is minus 500 mA. The Darlington pairs
may be paralleled for higher current capability.
Applications include relay drivers, hammer drivers,
lamp drivers, display drivers (LED and gas discharge),
line drivers, and logic buffers.
ORDERING INFORMATION
I1 1 18 O1
I2 2 17 O2
I3 3 16 O3
I4 4 15 O4
I5 5 14 O5
I6 6 13 O6
I7 7 12 O7
I8 8 11 O8
VCC 9 10 GND
SOP-18 / DIP-18
PIN DESCRIPTION
Pin No.
Pin Name Pin Function
SOP-18 DIP-18
1 1 I1
2 2 I2
3 3 I3
4 4 I4
Channel 1 through 8 Darlington Base Input
5 5 I5
6 6 I6
7 7 I7
8 8 I8
10 10 GND Ground
11 11 O8
12 12 O7
13 13 O6
14 14 O5
Channel 1 through 8 Darlington Emitter Output
15 15 O4
16 16 O3
17 17 O2
18 18 O1
1 18
IN1 OUT1
2 17
IN2 OUT2
3 16
IN3 OUT3
4 15
IN4 OUT4
5 14
IN5 OUT5
6 13
IN6 OUT6
7 12
IN7 OUT7
8 11
IN8 OUT8
9 10
VCC GND
BLOCK DIAGRAM
VCC
(C)
R3
Input R1: 10 kΩ
(B) R1 R2: 2.6 kΩ
R3: 20 kΩ
R2 R4: 10 kΩ
Output
(E) R5: 5.0 kΩ
R4 R5
GND
(COM)
Output Leakage Current ICEX Fig. 1 VCC = 50V, VIN = 0.4V - - 100 µA
VIN = 2.4V - - 52
Input Current IIN(ON) Fig. 3 µA
VIN = 3.85V - - 260
Input Voltage at ON state VIN(ON) Fig. 4 VCE = 2.0V, IOUT = −350mA - - 2.0 V
VCC VCC
VCE(SAT)
IOUT
VIN ICEX VIN
VCC VCC
ICC
IIN(ON) VCE
Fig. 3. IIN(ON), ICC Test Circuit Fig. 4. VIN(ON), VIN(OFF) Test Circuit
VCC Open
Open Open
IR VR IF VF
tr tf
VCC 90%
VIH
VIN 50%
10%
0
Pulse Width
VOUT 50%
VOL
* CL includes probe and jig capacitance. * Pulse Width 50µs, Duty Cycle 10%, tr ≤ 5ns, tf ≤ 10ns
Fig. 7. tON, tOFF Test Circuit Fig. 8. Propagation Delay Time Waveform
T.B.D.
The description in this data sheet is subject to change without any notice to describe its electrical characteristics
properly.