Adrv9008 1

Integrated Dual RF Receivers
Data Sheet ADRV9008-1

FEATURES In addition to automatic gain control (AGC), the ADRV9008-1 also
Dual receivers features flexible external gain control modes, allowing dynamic
Maximum receiver bandwidth: 200 MHz gain control.
Fully integrated, fractional-N, RF synthesizers The received signals are digitized with a set of four, high dynamic
Fully integrated clock synthesizer range, continuous time, sigma-delta (Σ-Δ) ADCs that provide
Multichip phase synchronization for RF LO and baseband clocks inherent antialiasing. The combination of the direct conversion
JESD204B datapath interface architecture (which does not suffer from out of band image
Tuning range (center frequency): 75 MHz to 6000 MHz mixing) and the lack of aliasing reduces the requirements of the RF
filters compared to the requirements of traditional intermediate
APPLICATIONS
frequency (IF) receivers.
3G/4G/5G FDD, macrocell base stations
The fully integrated phase-locked loop (PLL) provides high
Wideband active antenna systems
performance, low power, fractional-N, RF synthesis for the
Massive multiple input, multiple output (MIMO)
Phased array radar
receiver signal paths. An additional synthesizer generates the
Electronic warfare
clocks needed for the converters, digital circuits, and serial
Military communications interface. A multichip synchronization mechanism synchronizes
Portable test equipment the phase of the RF local oscillator (LO) and baseband clocks
between multiple ADRV9008-1 chips. The ADRV9008-1 features
GENERAL DESCRIPTION the isolation that high performance base station applications
The ADRV9008-1 is a highly integrated, dual radio frequency (RF), require. All voltage controlled oscillators (VCOs) and loop
agile receiver offering integrated synthesizers and digital signal filter components are integrated.
processing functions. The IC delivers a versatile combination of The high speed JESD204B interface supports up to 12.288 Gbps
high performance and low power consumption required by lane rates, resulting in a single lane per receiver in the widest
3G/4G/5G macrocell, frequency division duplex (FDD), base bandwidth mode. The interface also supports interleaved mode
station applications. for lower bandwidths, reducing the total number of high speed
The receive path consists of two independent, wide bandwidth, data interface lanes to one. Both fixed and floating point data
direct conversion receivers with state-of-the-art dynamic range. formats are supported. The floating point format allows internal
The complete receive subsystem includes automatic and manual AGC to be invisible to the demodulator device.
attenuation control, dc offset correction, quadrature error The core of the ADRV9008-1 can be powered directly from
correction (QEC), and digital filtering, eliminating the need for 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire
these functions in the digital baseband. RF front-end control and serial port. Comprehensive power-down modes are included to
several auxiliary functions, such as analog-to-digital converters minimize power consumption during normal use. The
(ADCs), digital-to-analog converters (DACs), and general-purpose ADRV9008-1 is packaged in a 12 mm × 12 mm, 196-ball chip
input/outputs (GPIOs) for the power amplifier (PA), are also scale ball grid array (CSP_BGA).
integrated.
Rev. 0 Document Feedback

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ADRV9008-1 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Theory of Operation ...................................................................... 47
Applications ....................................................................................... 1 Receivers ...................................................................................... 47
General Description ......................................................................... 1 Clock Input.................................................................................. 47
Revision History ............................................................................... 2 Synthesizers ................................................................................. 47
Functional Block Diagram .............................................................. 3 SPI................................................................................................. 47
Specifications..................................................................................... 4 JTAG Boundary Scan ................................................................. 47
Current and Power Consumption Specifications..................... 8 Power Supply Sequence ............................................................. 47
Timing Diagrams.......................................................................... 9 GPIO_x Pins ............................................................................... 48
Absolute Maximum Ratings.......................................................... 10 Auxiliary Converters .................................................................. 48
Reflow Profile .............................................................................. 10 JESD204B Data Interface .......................................................... 48
Thermal Management ............................................................... 10 Applications Information .............................................................. 49
Thermal Resistance .................................................................... 10 PCB Layout and Power Supply Recommendations ............... 49
ESD Caution ................................................................................ 10 PCB Material and Stackup Selection ....................................... 49
Pin Configuration and Function Descriptions ........................... 11 Fanout and Trace Space Guidelines ......................................... 51
Typical Performance Characteristics ........................................... 17 Component Placement and Routing Guidelines ................... 52
75 MHz to 525 MHz Band ........................................................ 17 RF and JESD204B Transmission Line Layout ........................ 58
650 MHz to 3000 MHz Band .................................................... 25 Isolation Techniques Used on the ADRV9008-1W/PCBZ ... 60
3400 MHz to 4800 MHz Band .................................................. 33 RF Port Interface Information .................................................. 61
5100 MHz to 5900 MHz Band .................................................. 40 Outline Dimensions ....................................................................... 68
Receiver Input Impedance......................................................... 45 Ordering Guide .......................................................................... 68
Terminology .................................................................................... 46
REVISION HISTORY
9/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 68
FUNCTIONAL BLOCK DIAGRAM

Rx2 ADRV9008-1
RX1_IN+
Rx1 SYNCIN0±
SYNCIN1±
RX1_IN–
ADC SERDOUT0±
RX2_IN+
SERDOUT1±
LPF SERDOUT2±
RX2_IN– DIGITAL
PROCESSING SERDOUT3±
SYSREF_IN±
ADC DECIMATION
pFIR GP_INTERRUPT
AGC RX1_ENABLE
LPF DC OFFSET RX2_ENABLE
QEC
JESD204B RESET
RF_EXT_LO_I/O+ RF LO Arm CIF/RIF TEST
RF_EXT_LO_I/O– SYNTHESIZER Cortex-M3 SCLK
CS
SDO
SDIO
GPIOs, AUXILIARY ADCs, REF_CLK_IN +

AND AUXILIARY DACs CLOCK
GENERATION REF_CLK_IN –
16830-001
GPIO_3p3_x GPIO_x AUXADC_x
Figure 1.
SPECIFICATIONS
Electrical characteristics at VDDA1P31 = 1.3 V, VDDD1P3_DIG = 1.3 V, TJ = full operating temperature range, and LO frequency (fLO) =
1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer to the Typical Performance Characteristics
section for input/output circuit path loss. The device configuration profile for the 75 MHz to 525 MHz frequency range is as follows:
receiver = 50 MHz bandwidth (inphase quadrature (I/Q) rate = 61.44 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.
Unless otherwise specified, the device configuration for all other frequency ranges is as follows: receiver = 200 MHz bandwidth (I/Q rate =
245.76 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
RECEIVERS
Center Frequency 75 6000 MHz
Gain Range 30 dB
Analog Gain Step 0.5 dB Attenuator steps from 0 dB to 6 dB
1 dB Attenuator steps from 6 dB to 30 dB
Bandwidth Ripple ±0.5 dB 200 MHz bandwidth, compensated by
programmable finite impulse response (FIR)
filter
±0.2 dB Any 20 MHz bandwidth span, compensated
by programmable FIR filter
Receiver (Rx) Bandwidth 200 MHz
Receiver Alias Band 80 dB Due to digital filters
Rejection
Maximum Useable Input PHIGH 0 dB attenuation, increases decibel
Level for decibel with attenuation, continuous
wave (CW) = 1800 MHz, corresponds to
−1 dBFS at ADC
−11 dBm 75 MHz < f ≤ 3000 MHz
−10.2 dBm 3000 MHz < f ≤ 4800 MHz
−9.5 dBm 4800 MHz < f ≤ 6000 MHz
Noise Figure NF 0 dB attenuation, at receiver port
11.5 dB 75 MHz < f ≤ 600 MHz
12 dB 600 MHz < f ≤ 3000 MHz
13 dB 3000 MHz < f ≤ 4800 MHz
15.2 dB 4800 MHz < f ≤ 6000 MHz
Ripple 1.8 dB At band edge maximum bandwidth mode
Input Third-Order Intercept IIP3
Point
Difference Product 12 dBm 75 MHz < f ≤ 600 MHz, (PHIGH − 12) dB per
tone; 600 MHz < f ≤ 6000 MHz, (PHIGH − 10) dB
per tone; two tones near band edge
Sum Product 12 dBm 75 MHz < f ≤ 600 MHz, (PHIGH − 12) dB per
tone; 600 MHz < f ≤ 6000 MHz, (PHIGH − 10) dB
per tone; two tones at bandwidth/6 offset
from the LO
Third-Order Harmonic HD3 75 MHz < f ≤ 600 MHz, (PHIGH − 6) dB; 600
Distortion MHz < f ≤ 6000 MHz, (PHIGH − 4) dB; CW tone
at bandwidth/6 offset from the LO
−65 dBc 75 MHz < f ≤ 600 MHz
−66 dBc 600 MHz < f ≤ 4800 MHz
−62 dBc 4800 MHz < f ≤ 6000 MHz
Second-Order Input IIP2 62 dBm 75 MHz < f ≤ 600 MHz, (PHIGH − 12) dB per
Intermodulation tone; 600 MHz < f ≤ 6000 MHz, (PHIGH − 10) dB
Intercept Point per tone; 0 dB attenuation, complex
Image Rejection 75 dB QEC active, within 200 MHz receiver
bandwidth
Input Impedance 100 Ω Differential (see Figure 168)
Receiver to Receiver 77 dB 75 MHz < f ≤ 600 MHz
Isolation
65 dB 600 MHz < f ≤ 4800 MHz
61 dB 4800 MHz < f ≤ 6000 MHz
Receiver Band Spurs −95 dBm No more than one spur at this level per
Referenced to RF Input at 10 MHz of receiver bandwidth
Maximum Gain
Receiver LO Leakage at Leakage decreases decibel for decibel with
Receiver Input at attenuation for first 12 dB
Maximum Gain
−70 dBm 75 MHz < f ≤ 600 MHz
−70 dBm 600 MHz < f ≤ 3000 MHz
−65 dBm 3000 MHz < f ≤ 6000 MHz
LO SYNTHESIZER
LO Frequency Step 2.3 Hz 1.5 GHz to 2.8 GHz, 76.8 MHz phase
frequency detector (PFD) frequency
LO Spur −85 dBc Excludes integer boundary spurs
Integrated Phase Noise 2 kHz to 18 MHz
75 MHz LO 0.014 °rms Narrow PLL loop bandwidth (50 kHz)
1900 MHz LO 0.2 °rms Narrow PLL loop bandwidth (50 kHz)
3800 MHz LO 0.36 °rms Wide PLL loop bandwidth (300 kHz)
5900 MHz LO 0.54 °rms Wide PLL loop bandwidth (300 kHz)
Spot Phase Noise
75 MHz LO Narrow PLL loop bandwidth
10 kHz Offset −126.5 dBc/Hz
100 kHz Offset −132.8 dBc/Hz
1 MHz Offset −150.1 dBc/Hz
1900 MHz LO Narrow PLL loop bandwidth
100 kHz Offset −100 dBc/Hz
1.2 MHz Offset −135 dBc/Hz
6 MHz Offset −150 dBc/Hz
3800 MHz LO Wide PLL loop bandwidth
5900 MHz LO Wide PLL loop bandwidth
1.2 MHz Offset −119.7 dBc/Hz
LO PHASE SYNCHRONIZATION Change in LO delay per temperature
change
Phase Deviation 1.6 ps/°C
EXTERNAL LO INPUT
Input Frequency fEXTLO 300 8000 MHz Input frequency must be 2× the desired LO
frequency
Input Signal Power 0 12 dBm 50 Ω matching at the source
3 dBm fEXTLO ≤ 2 GHz, add 0.5 dBm/GHz above
2 GHz
6 dBm fEXTLO = 8 GHz
External LO Input Signal To ensure adequate QEC
Differential
Phase Error 3.6 ps
Amplitude Error 1 dB
Duty Cycle Error 2 %
Even Order Harmonics −50 dBc
CLOCK SYNTHESIZER
Integrated Phase Noise 1 kHz to 100 MHz
1966.08 MHz LO 0.4 °rms PLL optimized for close in phase noise
Spot Phase Noise
1966.08 MHz
REFERENCE CLOCK
(REF_CLK_IN±)
Frequency Range 10 1000 MHz
Signal Level 0.3 2.0 V p-p AC-coupled, common-mode voltage (VCM) =
618 mV, use <1 V p-p input clock for best
spurious performance
AUXILIARY CONVERTERS
ADC
Resolution 12 Bits
Input Voltage
Minimum 0.05 V
Maximum VDDA_ V
3P3 −
0.05
DAC
Resolution 10 Bits Includes four offset levels
Output Voltage
Minimum 0.7 V 1 V VREF
Maximum VDDA_ V 2.5 V VREF
3P3 −
0.3
Output Drive Capability 10 mA
DIGITAL SPECIFICATIONS
(CMOS): SERIAL PERIPHERAL
INTERFACE (SPI), GPIO_x
Logic Inputs
Input Voltage
High Level VDD_ VDD_ V
INTERFACE INTERFACE
× 0.8
Low Level 0 VDD_ V
INTERFACE
× 0.2
Input Current
High Level −10 +10 μA
Low Level −10 +10 μA
Logic Outputs
Output Voltage
High Level VDD_ V
INTERFACE
× 0.8
Low Level VDD_ V
INTERFACE
× 0.2
Drive Capability 3 mA
DIGITAL SPECIFICATIONS
(CMOS): GPIO_3p3_x
Logic Inputs
Input Voltage
High Level VDDA_ VDDA_3P3 V
3P3 × 0.8
Low Level 0 VDDA_ V
3P3 × 0.2
Input Current
High Level −10 +10 μA
Low Level −10 +10 μA
Logic Outputs
Output Voltage
High Level VDDA_ V
3P3 × 0.8
Low Level VDDA_ V
3P3 × 0.2
Drive Capability 4 mA
DIGITAL SPECIFICATIONS, LOW
VOLTAGE DIFFERENTIAL
SIGNALING (LVDS)
Logic Inputs (SYSREF_IN±,
SYNCINx±)
Input Voltage Range 825 1675 mV Each differential input in the pair
Input Differential Voltage −100 +100 mV
Threshold
Receiver Differential 100 Ω Internal termination enabled
Input Impedance
SPI TIMING See the UG-1295 for more information
SCLK Period tCP 20 ns
SCLK Pulse Width tMP 10 ns
CS Setup to First SCLK tSC 3 ns
Rising Edge
Last SCLK Falling Edge to CS tHC 0 ns
Hold
SDIO Data Input Setup to tS 2 ns
SCLK
SDIO Data Input Hold to tH 0 ns
SCLK
SCLK Rising Edge to Output tCO 3 8 ns
Data Delay (3-Wire Mode
or 4-Wire Mode)
Bus Turnaround Time, Read tHZM tH tCO ns
After Baseband Processor
(BBP) Drives Last Address
Bit
Bus Turnaround Time, Read tHZS 0 tCO ns
After ADRV9008-1 Drives
Last Data Bit
JESD204B DATA OUTPUT AC-coupled
TIMING
Unit Interval UI 81.38 320 ps
Data Rate Per Channel (NRZ) 3125 12288 Mbps
Rise Time tR 24 39.5 ps 20% to 80% in 100 Ω load
Fall Time tF 24 39.4 ps 20% to 80% in 100 Ω load
Output Common-Mode VCM 0 1.8 V AC-coupled
Voltage
Differential Output Voltage VDIFF 360 600 770 mV
Short-Circuit Current IDSHORT −100 +100 mA
Differential Termination 80 94.2 120 Ω
Impedance
Total Jitter 15.13 ps Bit error rate (BER) = 10−15
Uncorrelated Bounded UBHPJ 0.56 ps
High Probability Jitter
Duty Cycle Distortion DCD 0.369 ps
SYSREF_IN± Setup Time to 2.5 ns See Figure 2
REF_CLK_IN±
SYSREF_IN± Hold Time to −1.5 ns See Figure 2
REF_CLK_IN±
Latency tLAT_FRM REF_CLK_IN± = 245.76 MHz
89.4 Clock Receiver bandwidth = 200 MHz, IQ rate =
cycles 245.76 MHz, lane rate = 9830.4 MHz,
M = 2, L = 2, N = 16, S = 1
364.18 ns
1
VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RF_VCO_LDO, VDDA1P3_RF_LO,
VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.
CURRENT AND POWER CONSUMPTION SPECIFICATIONS

Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY CHARACTERISTICS
VDDA1P31 Analog Supply 1.267 1.3 1.33 V
VDDD1P3_DIG Supply 1.267 1.3 1.33 V
VDDA1P8_AN Supply 1.71 1.8 1.89 V
VDDA1P8_BB Supply 1.71 1.8 1.89 V
VDD_INTERFACE Supply 1.71 1.8 2.625 V CMOS and LVDS supply, 1.8 V to 2.5 V nominal range
VDDA_3P3 Supply 3.135 3.3 3.465 V
POSITIVE SUPPLY CURRENT LO at 2600 MHz
200 MHz Receiver Bandwidth Two receivers enabled
VDDA1P31 Analog Supply 1645 mA
VDDD1P3_DIG Supply 984 mA Receiver QEC active
VDDA1P8_AN Supply 0.4 mA
VDDA1P8_BB Supply 68 mA
VDD_INTERFACE Supply 8 mA
VDDA_3P3 Supply 3 mA No Auxiliary DAC x or AUXADC_x enabled (if enabled,
AUXADC_x adds 2.7 mA, and each Auxiliary DAC x
adds 1.5 mA)
Total Power Dissipation 3.57 W Typical supply voltages, receiver QEC active
1
VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX, VDDA1P3_RF_VCO_LDO,
VDDA1P3_RF_LO, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.
TIMING DIAGRAMS
AT DEVICE PINS REF_CLK_IN± DELAY AT DEVICE CORE
IN REFERENCE TO SYSREF_IN±
tH tH t’H t’H
tS tS t’S t’S
REF_CLK_IN±
tH = –1.5ns CLK DELAY = 2ns t’H = +0.5ns

tS = +2.5ns t’S = +0.5ns
NOTES
1. tH AND tS ARE THE HOLD AND SETUP TIMES FOR THE REF_CLK_IN± PINS. t’H AND t’S REFER TO THE
16830-005
DELAYED HOLD AND SETUP TIMES AT THE DEVICE CORE IN REFERENCE TO THE SYSREF_N± SIGNALS
DUE TO AN INTERNAL BUFFER THAT THE SIGNAL PASSES THROUGH.
Figure 2. SYSREF_IN± Setup and Hold Timing
tH tH tH tH
tS tS tS tS
REF_CLK_IN±
SYSREF_IN±
16830-006
tH = –1.5ns
VALID SYSREF INVALID SYSREF tS = +2.5ns
Figure 3. SYSREF_IN± Setup and Hold Timing Examples, Relative to Device Clock
ABSOLUTE MAXIMUM RATINGS
Table 3. exposed die package to provide the customer with the most
Parameter Rating
effective method of controlling the die temperature. The exposed
die allows cooling of the die directly. Figure 4 shows the profile
VDDA1P31 to VSSA −0.3 V to +1.4 V
view of the device mounted to a user printed circuit board (PCB)
VDDD1P3_DIG to VSSD −0.3 V to +1.4 V
and a heat sink (typically the aluminum case) to keep the junction
VDD_INTERFACE to VSSA −0.3 V to +3.0 V
(exposed die) below the maximum junction temperature shown
VDDA_3P3 to VSSA −0.3 V to +3.9 V
in Table 3. The device is designed for a lifetime of 10 years when
VDD_INTERFACE Logic Inputs and −0.3 V to VDD_
Outputs to VSSD INTERFACE + 0.3 V operating at the maximum junction temperature.
JESD204B Logic Outputs to VSSA −0.3 V to VDDA1P3_SER THERMAL RESISTANCE
Input Current to Any Pin Except ±10 mA
θJA is specified for the worst-case conditions, that is, a device
Supplies
soldered in a circuit board for surface-mount packages. Thermal
Maximum Input Power into RF Port 23 dBm (peak)
resistance data for the ADRV9008-1 mounted on both a JEDEC
Maximum Junction Temperature 110°C
2S2P test board and a 10-layer Analog Devices, Inc., evaluation
Storage Temperature Range −65°C to +150°C
board is listed in Table 4. Do not exceed the absolute maximum
1
VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, junction temperature rating in Table 3. Ten-layer PCB entries
VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX, VDDA1P3_RF_VCO_LDO, refer to the 10-layer Analog Devices evaluation board, which
VDDA1P3_RF_LO, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_SYNTH, and
VDDA1P3_CLOCK_VCO_LDO. more accurately reflects the PCB used in customer applications.
Stresses at or above those listed under Absolute Maximum Table 4. Thermal Resistance1, 2
Ratings may cause permanent damage to the product. This is a
Package Type θJA θJC_TOP θJB ΨJT ΨJB Unit
stress rating only; functional operation of the product at these
BC-196-13 21.1 0.04 4.9 0.3 4.9 °C/W
or any other conditions above those indicated in the operational
1
For the θJC test, 100 µm thermal interface material (TIM) is used. TIM is
section of this specification is not implied. Operation beyond assumed to have 3.6 thermal conductivity watts/(meter × Kelvin).
the maximum operating conditions for extended periods may 2
Using enhanced heat removal techniques such as PCB, heat sink, and airflow
affect product reliability. improves the thermal resistance values.
REFLOW PROFILE
The ADRV9008-1 reflow profile is in accordance with the ESD CAUTION
JEDEC JESD204B criteria for Pb-free devices. The maximum
reflow temperature is 260°C.
THERMAL MANAGEMENT
The ADRV9008-1 is a high power device that can dissipate over
3 W depending on the user application and configuration.
Because of the power dissipation, the ADRV9008-1 uses an
CUSTOMER CASE (HEAT SINK)
CUSTOMER THERMAL FILLER
SILICON (DIE)
IC PROFILE
PACKAGE SUBSTRATE
16830-008
CUSTOMER PCB
Figure 4. Typical Thermal Management Solution
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1 2 3 4 5 6 7 8 9 10 11 12 13 14
A VSSA VSSA VSSA VSSA RX2_IN+ RX2_IN– VSSA VSSA RX1_IN+ RX1_IN– VSSA VSSA VSSA VSSA
VDDA1P3_ RF_EXT_ RF_EXT_

B RX_RF VSSA VSSA VSSA VSSA VSSA LO_I/O– LO_I/O+ VSSA VSSA VSSA VSSA VSSA VSSA
VDDA1P3_
VDDA1P3_ VDDA1P3_RF_ VDDA1P1_ VDDA1P3_ AUX_VCO_
C GPIO_3p3_0 GPIO_3p3_3 VDDA1P3_RX VSSA RF_VCO_LDO VCO_LDO RF_VCO RF_LO VSSA LDO VSSA VDDA_3P3 GPIO_3p3_9 RBIAS
VDDA1P1_
D GPIO_3p3_1 GPIO_3p3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSA AUX_VCO VSSA VSSA GPIO_3p3_8 GPIO_3p3_10
AUX_SYNTH_
E GPIO_3p3_2 GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSA OUT AUXADC_3 VDDA1P8_AN GPIO_3p3_7 GPIO_3p3_11
F VSSA VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA
VDDA1P3_ VDDA1P3_ RF_SYNTH_

CLOCK_ VDDA1P3_
G VSSA VSSA VSSA VSSA VSSA RF_SYNTH AUX_SYNTH VTUNE VSSA VSSA VSSA VSSA VSSA
SYNTH
H DNC VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA DNC
GP_
J DNC VSSA GPIO_18 RESET INTERRUPT TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA DNC
K VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CS GPIO_14 GPIO_9 VSSA VSSA
VDDD1P3_ VDDD1P3_ VDDA1P3_ VDDA1P3_

L VSSA VSSA SYNCIN1– SYNCIN1+ GPIO_6 GPIO_7 VSSD DIG DIG VSSD GPIO_15 GPIO_8 SER SER
VDDA1P1_ VDD_ VDDA1P3_ VDDA1P3_

M CLOCK_VCO VSSA SYNCIN0– SYNCIN0+ RX1_ENABLE VSSD RX2_ENABLE VSSD VSSA GPIO_17 GPIO_16 INTERFACE SER SER
VDDA1P3_
CLOCK_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_
N VCO_LDO VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA SER SER SER SER SER SER VSSA
AUX_SYNTH_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_

P VTUNE VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+ SER SER VSSA SER SER SER SER
ADRV9008-1 16830-999
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions

Pin No. Type Mnemonic Description
A1 to A4, A7, A8, A11 to A14, B2 Input VSSA Analog Supply Voltage (VSS).
to B6, B9 to B14, C4, C9, C11,
D3 to D9, D11, D12, E6, E9, F1,
F2, F5 to F10, F12 to F14, G1
to G4, G6, G10 to G14, H2 to
H10, H13, J2, J13, K1, K2, K13,
K14, L1, L2, M2, M9, N2, N7,
N14, P2, P3, P10
A5, A6 Input RX2_IN+, RX2_IN− Differential Input for Receiver 1. When unused, connect these
pins to ground.
A9, A10 Input RX1_IN+, RX1_IN− Differential Input for Receiver 2. When unused, connect these
pins to ground.
B1 Input VDDA1P3_RX_RF Receiver Mixer Supply.
B7, B8 Input RF_EXT_LO_I/O−, Differential External LO Input/Output. If these pins are used
RF_EXT_LO_I/O+ for external LO, the input frequency must be 2× the desired
carrier frequency. When unused, do not connect these pins.
C1 Input/ GPIO_3p3_0 GPIO Pin Referenced to 3.3 V Supply. The alternate function is
output Auxiliary DAC 4. Because this pin contains an input stage, the
voltage on the pin must be controlled. When unused, this pin
can be tied to ground through a resistor to safeguard against
misconfiguration, or this pin can be left floating, programmed as
an output, and driven low.
C2 Input/ GPIO_3p3_3 GPIO Pin Referenced to 3.3 V Supply. Because this pin contains
output an input stage, the voltage on the pin must be controlled. When
unused, this pin can be tied to ground through a resistor to
safeguard against misconfiguration, or this pin can be left
floating, programmed as an output, and driven low.
C3 Input VDDA1P3_RX 1.3 V Supply for Receiver Baseband Circuits, Transimpedance
Amplifier (TIA), Baseband Filters, and Auxiliary DACs.
C5, C6 Input VDDA1P3_RF_VCO_LDO RF VCO Low Dropout (LDO) Supply Inputs. Connect Pin C5 to
Pin C6. Use a separate trace to a common supply point.
C7 Input VDDA1P1_RF_VCO 1.1 V VCO Supply. Decouple this pin with 1 µF.
C8 Input VDDA1P3_RF_LO 1.3 V LO Generator for RF Synthesizer. This pin is sensitive to
aggressors.
C10 Input VDDA1P3_AUX_VCO_LDO 1.3 V Supply.
C12 Input VDDA_3P3 General-Purpose Output Pull-Up Voltage and Auxiliary DAC
Supply Voltage.
C13 Input/ GPIO_3p3_9 GPIO Pin Referenced to 3.3 V Supply. The alternative function
output is Auxiliary DAC 9. Because this pin contains an input stage,
the voltage on the pin must be controlled. When unused, this
pin can be tied to ground through a resistor to safeguard
against misconfiguration, or this pin can be left floating,
programmed as an output, and driven low.
C14 Input/ RBIAS Bias Resistor. Tie this pin to ground using a 14.3 kΩ resistor.
output This pin generates an internal current based on an external
1% resistor.
D1 Input/ GPIO_3p3_1 GPIO Pin Referenced to 3.3 V Supply. The alternative function
D10 Input VDDA1P1_AUX_VCO 1.1 V VCO Supply. Decouple with 1 µF.
E1 Input/ GPIO_3p3_2 GPIO Pin Referenced to 3.3 V Supply. Because this pin contains
output an input stage, the voltage on the pin must be controlled.
When unused, this pin can be tied to ground through a resistor
to safeguard against misconfiguration, or this pin can be left
floating, programmed as an output, and driven low.
E2 Input/ GPIO_3p3_5 GPIO Pin Referenced to 3.3 V Supply. The alternative function
E4 Input VDDA1P8_BB 1.8 V Supply for the ADC and DAC.
E5 Input VDDA1P3_BB 1.3 V Supply for the ADC, DAC, and Auxiliary ADCs.
E7, E8 Input REF_CLK_IN+, REF_CLK_IN− Device Clock Differential Input.
E10 Output AUX_SYNTH_OUT Auxiliary PLL Output. When unused, do not connect this pin.
E11, F3, F4, F11 Input AUXADC_0 to AUXADC_3 Auxiliary ADC Input. When unused, connect these pins to ground
with a pull-down resistor, or connect directly to ground.
E12 Input VDDA1P8_AN 1.8 V Bias Supply for Analog Circuitry.
programmed as outputs, and driven low.
G5 Input VDDA1P3_CLOCK_SYNTH 1.3 V Supply Input for Clock Synthesizer. Use a separate trace
on the PCB back to a common supply point.
G7 Input VDDA1P3_RF_SYNTH 1.3 V RF Synthesizer Supply Input. This pin is sensitive to
aggressors.
G8 Input VDDA1P3_AUX_SYNTH 1.3 V Auxiliary Synthesizer Supply Input.
G9 Output RF_SYNTH_VTUNE RF Synthesizer VTUNE Output.
H1, J1, H14, J14 DNC1 DNC Do Not Connect. Do not connect these pins.
H11 Input/ GPIO_12 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
output stage, the voltage on the pin must be controlled. When
safeguard against misconfiguration, or it can be left floating,
H12 Input/ GPIO_11 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
J3 Input/ GPIO_18 Digital GPIO, 1.8 V to 2.5 V. The joint test action group (JTAG)
output function is test clock (TCLK). Because this pin contains an input
stage, the voltage on the pin must be controlled. When
J4 Input RESET Active Low Chip Reset.
J5 Output GP_INTERRUPT General-Purpose Digital Interrupt Output Signal. When
unused, do not connect this pin.
J6 Input TEST Pin Used for JTAG Boundary Scan. When unused, connect this
pin to ground.
J7 Input/ GPIO_2 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to
output 0. Because this pin contains an input stage, the voltage on the
pin must be controlled. When unused, this pin can be tied to
ground through a resistor to safeguard against misconfiguration,
or it can be left floating, programmed as an output, and
driven low.
J8 Input/ GPIO_1 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0.
output Because this pin contains an input stage, the voltage on the pin
must be controlled. When unused, this pin can be tied to ground
through a resistor to safeguard against misconfiguration, or it can
be left floating, programmed as an output, and driven low.
J9 Input/ SDIO Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire
output Mode.
J10 Output SDO Serial Data Output. In SPI 3-Wire mode, do not connect this pin.
J11 Input/ GPIO_13 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
J12 Input/ GPIO_10 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
K3, K4 Input SYSREF_IN+, SYSREF_IN− LVDS Input.
K5 Input/ GPIO_5 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test data
output output (TDO). Because this pin contains an input stage, the
voltage on the pin must be controlled. When unused, this pin
can be tied to ground through a resistor to safeguard against
misconfiguration, or it can be left floating, programmed as an
output, and driven low.
K6 Input/ GPIO_4 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test rest (TRST).
output Because this pin contains an input stage, the voltage on the
pin must be controlled. When unused, this pin can be tied to
ground through a resistor to safeguard against
K7 Input/ GPIO_3 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1.
K8 Input/ GPIO_0 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1.
K9 Input SCLK Serial Data Bus Clock.
K10 Input CS Serial Data Bus Chip Select, Active Low.
K11 Input/ GPIO_14 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
K12 Input/ GPIO_9 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
L3, L4 Input SYNCIN1−, SYNCIN1+ LVDS Input. When unused, connect these pins to ground with a
pull-down resistor, or connect directly to ground.
L5 Input/ GPIO_6 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test data input
output (TDI). Because this pin contains an input stage, the voltage on
the pin must be controlled. When unused, this pin can be tied
to ground through a resistor to safeguard against
L6 Input/ GPIO_7 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test mode
output select input (TMS). Because this pin contains an input stage,
against misconfiguration, or it can be left floating, programmed
as an output, and driven low.
L7, L10, M6, M8 Input VSSD Digital VSS.
L8, L9 Input VDDD1P3_DIG 1.3 V Digital Core. Connect Pin L8 to Pin L9. Use a separate
trace to a common supply point.
L11 Input/ GPIO_15 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
L12 Input/ GPIO_8 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
L13, L14, M13, M14, N8 to N13, Input VDDA1P3_SER 1.3 V Supply for JESD204B Serializer.
P8, P9, P11 to P14
M1 Input VDDA1P1_CLOCK_VCO 1.1 V VCO Supply. Decouple this pin with 1 µF.
M3, M4 Input SYNCIN0−, SYNCIN0+ JESD204B Receiver Channel 0. These pins form the synchro-
nization signal associated with receiver channel data on the
JESD204B interface. When unused, connect these pins to ground
M5 Input RX1_ENABLE Receiver 1 Enable Pin. When unused, connect this pin to ground
M7 Input RX2_ENABLE Receiver 2 Enable Pin. When unused, connect this pin to ground
M10 Input/ GPIO_17 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
M11 Input/ GPIO_16 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input
M12 Input VDD_INTERFACE Input/Output Interface Supply, 1.8 V to 2.5 V.
N1 Input VDDA1P3_CLOCK_VCO_LDO 1.3 V Supply. Use a separate trace to a common supply point.
N3, N4 Output SERDOUT3−, SERDOUT3+ RF Current Mode Logic (CML) Differential Output 3. When
unused, do not connect these pins.
N5, N6 Output SERDOUT2−, SERDOUT2+ RF CML Differential Output 2. When unused, do not connect
these pins.
P1 Output AUX_SYNTH_VTUNE Auxiliary Synthesizer VTUNE Output.
P4, P5 Output SERDOUT1−, SERDOUT1+ RF CML Differential Output 1. When unused, do not connect
these pins.
P6, P7 Output SERDOUT0−, SERDOUT0+ RF CML Differential Output 0. When unused, do not connect
these pins.
1
DNC means do not connect.
TYPICAL PERFORMANCE CHARACTERISTICS

The temperature settings refer to the die temperature.
75 MHz TO 525 MHz BAND
0 45
–10 40
+110°C
+110°C
+25°C
RECEIVER LO LEAKAGE (dBm)
–20
RECEIVER NOISE FIGURE (dB)

35 +25°C
–40°C
–40°C
–30
30
–40
25
–50
20
–60
15
–70
10
–80
–90 5
–100 16830-581 0
16830-584
75 125 175 225 275 325 375 425 475 525 0 2 4 6 8 10 12 14 16 18 20
RECEIVER LO FREQUENCY (MHz) RECEIVER ATTENUATION (dB)
Figure 6. Receiver LO Leakage vs. Receiver LO Frequency, 75 MHz, 300 MHz, Figure 9. Receiver Noise Figure vs. Receiver Attenuation, LO = 525 MHz,
525 MHz; Receiver Attenuation = 0 dB, RF Bandwidth = 50 MHz, RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS,
Sample Rate = 61.44 MSPS Integration Bandwidth = 1 MHz to 25 MHz
45 20
40 18
+110°C
+110°C
+25°C 16
35 +25°C
–40°C
–40°C
14
30
12
25
10
20
8
15
6
10
4
5 2
0 0
16830-582
16830-585
0 2 4 6 8 10 12 14 16 18 20 75 175 275 375 475
RECEIVER ATTENUATION (dB) RECEIVER LO FREQUENCY (MHz)
Figure 7. Receiver Noise Figure vs. Receiver Attenuation, LO = 75 MHz, Figure 10. Receiver Noise Figure vs. Receiver LO Frequency, Receiver
RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, Attenuation = 0 dB, RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS,
Integration Bandwidth = 1 MHz to 25 MHz Integration Bandwidth = ±25 MHz
45 20
40 +110°C
+110°C
18 +25°C
+25°C
35 –40°C
–40°C
30 16
25
14
20
15 12
10
10
5
0 8
16830-583
16830-589
0 2 4 6 8 10 12 14 16 18 20 –25 –15 –5 5 15 25
RECEIVER ATTENUATION (dB) RECEIVER OFFSET FREQUENCY FROM LO (75MHz)
Figure 8. Receiver Noise Figure vs. Receiver Attenuation, LO = 300 MHz, Figure 11. Receiver Noise Figure vs. Receiver Offset Frequency from LO,
RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, Integration Bandwidth = 200 kHz, LO = 75 MHz
Integration Bandwidth = 1 MHz to 25 MHz
20 110
+110°C
18 +25°C 100
–40°C
RECEIVER IIP2 (dBm)

16 90
14 80
12 70 +110°C (SUM)
+25°C (SUM)
–40°C (SUM)
60 +110°C (DIFF)
10 +25°C (DIFF)
–40°C (DIFF)
50
16830-593
8
16830-590
–25 –15 –5 5 15 25 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
RECEIVER OFFSET FREQUENCY FROM LO (300MHz) RECEIVER ATTENUATION (dB)
Figure 12. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Figure 15. Receiver IIP2 vs. Receiver Attenuation, LO = 300 MHz, Tones Placed
Integration Bandwidth = 200 kHz, LO = 300 MHz at 310 MHz and 311 MHz, −23.5 dBm Plus Attenuation
20 80
RECEIVER IIP2 SUM AND DIFFERENCE

+110°C 75
18 +25°C
–40°C
ACROSS BANDWIDTH (dBm)

70
16
65
14 60
+110°C (SUM)
55 +25°C (SUM)
12 –40°C (SUM)
+110°C (DIFF)
50 +25°C (DIFF)
10 –40°C (DIFF)
45
8 40
16830-591
–25 –15 –5 5 15 25 80.0 82.5 87.5 90.0 92.5 95.0 97.5 100.0 102.5
81.0 83.5 88.5 91.0 93.5 96.0 98.5 101.0 103.5
16830-594
RECEIVER OFFSET FREQUENCY FROM LO (525MHz)
75
SWEPT PASS BAND FREQUENCY (MHz)
Figure 13. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Figure 16. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass
Integration Bandwidth = 200 kHz, LO = 525 MHz Band Frequency, Receiver Attenuation = 0 dB, LO = 75 MHz, 10 Tone Pairs,
−23.5 dBm Each
100 80
95
75
90
70
RECEIVER IIP2 (dBm)
85
80 65
75
60
70 +110°C (SUM)
+110°C (SUM) 55 +25°C (SUM)
65 +25°C (SUM) –40°C (SUM)
–40°C (SUM) +110°C (DIFF)
60 50 +25°C (DIFF)
+110°C (DIFF)
+25°C (DIFF) –40°C (DIFF)
55 –40°C (DIFF) 45
50
16830-592
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 40
305.0 307.5 310.0 312.5 315.0 317.5 320.0 322.5 325.0 327.5
RECEIVER ATTENUATION (dB) 306.0 308.5 311.0 313.5 316.0 318.5 321.0 323.5 326.0 328.5
16830-595
300
Figure 14. Receiver IIP2 vs. Receiver Attenuation, LO = 75 MHz,
Figure 17. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass
Tones Placed at 82.5 MHz and 83.5 MHz, −23.5 dBm Plus Attenuation
Band Frequency, Receiver Attenuation = 0 dB, LO = 300 MHz, 10 Tone pairs,
−23.5 dBm Each
110 25
Rx1 (SUM) = +110°C
Rx1 (DIFF) = +110°C
100 Rx1 (SUM) = +25°C
Rx1 (DIFF) = +25°C 20
Rx1 (SUM) = –40°C
RECEIVER IIP2 (dBm)
RECEIVER IIP3 (dBm)

Rx1 (DIFF) = –40°C
90
15
80
10 Rx1 = +110°C
70 Rx2 (SUM) = +110°C Rx1 = +25°C
Rx2 (DIFF) = +110°C Rx1 = –40°C
Rx2 (SUM) = +25°C Rx2 = +110°C
Rx2 (DIFF) = +25°C 5 Rx2 = +25°C
60 Rx2 (SUM) = –40°C Rx2 = –40°C
Rx2 (DIFF) = –40°C
50 0
16830-596
0 5 10 15 20 25 30 305.0 307.5 310.0 312.5 315.0 317.5 320.0 322.5 325.0 327.5
16830-599
RECEIVER ATTENUATION (dB) 306.0 308.5 311.0 313.5 316.0 318.5 321.0 323.5 326.0 328.5
Figure 18. Receiver IIP2 vs. Receiver Attenuation, LO = 75 MHz, Tones Placed at Figure 21. Receiver IIP3, Receiver Attenuation = 0 dB, LO = 300 MHz, Tone 2 =
77 MHz and 97 MHz, −23.5 dBm Plus Attenuation Tone 1 + 1 MHz, −21 dBm Each, Swept Across Pass Band
80 50
Rx1 (SUM) = +110°C
Rx1 (DIFF) = +110°C 45
75 Rx1 (SUM) = +25°C

Rx1 (DIFF) = +25°C 40
70 Rx1 (SUM) = –40°C

Rx1 (DIFF) = –40°C
RECEIVER IIP3 (dBm)

35
65
30
60 25
20 Rx1 = +110°C
55
Rx1 = +25°C
Rx2 (SUM) = +110°C 15 Rx1 = –40°C
50 Rx2 (DIFF) = +110°C Rx2 = +110°C
Rx2 (SUM) = +25°C 10 Rx2 = +25°C
Rx2 (DIFF) = +25°C Rx2 = –40°C
45 Rx2 (SUM) = –40°C 5
Rx2 (DIFF) = –40°C
40 0
16830-600
79.5 82.0 84.5 87.0 89.5 92.0 94.5 97.0 99.5 0 5 10 20 25 30 35
16830-597
77.0 77.0 77.0 77.0 77.0 77.0 77.0 77.0 77.0 ATTENUATION (dB)
Figure 19. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass Figure 22. Receiver IIP3 vs. Attenuation, LO = 300 MHz, Tone 1 = 302 MHz,
Band Frequency, Receiver Attenuation = 0 dB, LO = 75 MHz, Tone 1 = Tone 2 = 322 MHz, −19 dBm Plus Attenuation
77 MHz, Tone 2 Swept, −23.5 dBm Each
50 25
45
40 20
RECEIVER INPUT IP3 (dBm)
RECEIVER IIP3 (dBm)
35
30 15
25
20 Rx1 = +110°C 10 Rx1 = +110°C

Rx1 = +25°C Rx1 = +25°C
15 Rx1 = –40°C Rx1 = –40°C
Rx2 = +110°C Rx2 = +110°C
10 Rx2 = +25°C 5 Rx2 = +25°C
Rx2 = –40°C Rx2 = –40°C
5
0 0
16830-598
0 5 10 15 20 25 30 302.0 302.0 302.0 302.0 302.0 302.0 302.0 302.0 302.0 302.0
16830-601
ATTENUATION (dB) 304.5 307.0 309.5 312.0 314.5 317.0 319.5 322.0 324.5 327.0
Figure 20. Receiver IIP3 vs. Attenuation, LO = 300 MHz, Tone 1 = 325 MHz, Figure 23. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =
Tone 2 = 326 MHz, −21 dBm Plus Attenuation 0 dB, LO = 300 MHz, Tone 1 = 302 MHz, Tone 2 Swept Across Pass Band, −19 dBm
Each
–10 0
–20
+110°C +110°C
–20
–30 +25°C +25°C
–40°C –40°C
RECEIVER IMAGE (dBc)

–40
–40
–50
–60 –60
–70
–80
–80
–90
–100
–100
–110 –120
16830-602
16830-605
–25 –20 –15 –10 –5 0 5 10 15 20 25 0 5 10 15 20 25 30
BASEBAND FREQUENCY OFFSET ATTENUATOR SETTING (dB)
Figure 24. Receiver Image vs. Baseband Frequency Offset, Figure 27. Receiver Image vs. Attenuator Setting, RF Bandwidth = 25 MHz,
Attenuation = 0 dB, RF Bandwidth = 50 MHz, Tracking Calibration Active, Tracking Calibration Active, Sample Rate = 61.44 MSPS, LO = 75 MHz,
Sample Rate = 61.44 MSPS, LO = 75 MHz Baseband Frequency = 25 MHz
–10 0
–20
+110°C +110°C
–20
–30 +25°C +25°C
–40°C –40°C
–40 RECEIVER IMAGE (dBc)

–40
–50
–60 –60
–70
–80
–80
–90
–100
–100
–110 –120
16830-603
16830-606
–25 –20 –15 –10 –5 0 5 10 15 20 25 0 5 10 15 20 25 30
BASEBAND FREQUENCY OFFSET ATTENUATOR SETTING (dB)
Figure 25. Receiver Image vs. Baseband Frequency Offset, Figure 28. Receiver Image vs. Attenuator Setting, RF Bandwidth = 25 MHz,
Attenuation = 0 dB, RF Bandwidth = 50 MHz, Tracking Calibration Active, Tracking Calibration Active, Sample Rate = 61.44 MSPS, LO = 325 MHz,
Sample Rate = 61.44 MSPS, LO = 300 MHz Baseband Frequency = 25 MHz
–10 25
–20
+110°C 20 +110°C
–30 +25°C +25°C
–40°C 15 –40°C
–40
RECEIVER GAIN (dB)
10
–50
–60 5
–70
0
–80
–5
–90
–10
–100
–110 –15
16830-604
16830-607
–25 –20 –15 –10 –5 0 5 10 15 20 25 0 5 10 15 20 25 30

BASEBAND FREQUENCY OFFSET RECEIVER ATTENUATOR SETTING (dB)
Figure 26. Receiver Image vs. Baseband Frequency Offset, Figure 29. Receiver Gain vs. Receiver Attenuator Setting,
Attenuation = 0 dB, RF Bandwidth = 50 MHz, Tracking Calibration Active, RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, LO = 75 MHz
Sample Rate = 61.44 MSPS, LO = 525 MHz
25 0.5
0.4
20 +110°C +110°C
RECEIVER GAIN STEP ERROR (dB)

+25°C 0.3 +25°C
15 –40°C –40°C
0.2
RECEIVER GAIN (dB)
10
0.1
5 0
–0.1
0
–0.2
–5
–0.3
–10
–0.4
–15 –0.5
16830-608
16830-611
0 5 10 15 20 25 30 0 3 6 9 12 15 18 21 24 27 30
RECEIVER ATTENUATOR SETTING (dB) RECEIVER ATTENUATOR SETTING (dB)
Figure 30. Receiver Gain vs. Receiver Attenuator Setting, Figure 33. Receiver Gain Step Error vs. Receiver Attenuator Setting,
RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, LO = 325 MHz LO = 75 MHz
25 0.5
0.4
20 +110°C +110°C

+25°C 0.3 +25°C
15 –40°C –40°C
0.2
RECEIVER GAIN (dB)
10
0.1
5 0
–0.1
0
–0.2
–5
–0.3
–10
–0.4
–15 –0.5
16830-612
16830-609
0 5 10 15 20 25 30 0 3 6 9 12 15 18 21 24 27 30
Figure 31. Receiver Gain vs. Receiver Attenuator Setting, Figure 34. Receiver Gain Step Error vs. Receiver Attenuator Setting,
RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, LO = 525 MHz LO = 325 MHz
0.5
24
0.4
+110°C +110°C
22 +25°C 0.3 +25°C

–40°C –40°C
0.2
RECEIVER GAIN (dB)
20
0.1
18
0
16 –0.1
–0.2
14
–0.3
12
–0.4
10 –0.5
16830-613
16830-610
75 125 175 225 275 320 375 425 475 525 0 3 6 9 12 15 18 21 24 27 30

LO FREQUENCY (MHz) RECEIVER ATTENUATOR SETTING (dB)
Figure 35. Receiver Gain Step Error vs. Receiver Attenuator Setting,
Figure 32. Receiver Gain vs. LO Frequency,
LO = 525 MHz
RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS
0.5 –70
0.4
0.3 –75 +110°C
0.2 +25°C
RECEIVER DC OFFSET (dBFS)

BASEBAND FLATNESS (dB)
–80 –40°C
NORMALIZED RECEIVER
0.1
0
–85
–0.1
–0.2
–90
–0.3
–0.4 I RIPPLE = +110°C –95
–0.5 I RIPPLE = +25°C
I RIPPLE = –40°C
–0.6 –100
Q RIPPLE = +110°C
–0.7 Q RIPPLE = +25°C
–0.8 Q RIPPLE = –40°C –105
–0.9
–110
16830-617
–1.0
0 5 10 15 20 25 30
0.998
3.998
6.998
9.998
12.982
15.986
18.994
22.006
25.006
27.998
RECEIVER ATTENUATOR SETTING (dB)
16830-614
BASEBAND OFFSET FREQUENCY (MHz)
Figure 36. Normalized Receiver Baseband Flatness vs. Baseband Offset Figure 39. Receiver DC Offset vs. Receiver Attenuator Setting, LO = 525 MHz
Frequency (Receiver Flatness), LO = 75 MHz
–50 –30
ATTN = 15 +110°C
–40
ATTN = 15 +25°C
+110°C ATTN = 15 –40°C
–60 –50
+25°C ATTN = 0 +110°C
–40°C
RECEIVER HD2 LEFT (dBc) –60 ATTN = 0 +25°C
ATTN = 0 –40°C
–70 –70
–80
–80 –90
–100
–90 –110
–120
–100 –130
–140
–110 –150
16830-618
16830-615
75 125 175 225 275 325 375 425 475 525 –30 –20 –10 0 10 20 30
RECEIVER LO FREQUENCY (MHz) BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)
Figure 37. Receiver DC Offset vs. Receiver LO Frequency Figure 40. Receiver Second-Order Harmonic Distortion (HD2) Left vs.
Baseband Frequency Offset and Attenuation, Tone Level = −21 dBm at
Attenuation = 0 dB, X-Axis Is Baseband Frequency Offset of Fundamental
Tone, Not Frequency of HD2 Product (HD2 Product is 2× Baseband
Frequency), HD2 Canceller Disabled, LO = 75MHz
–70 –30
ATTN = 15 +110°C
–40
ATTN = 15 +25°C
–75 +110°C –50 ATTN = 15 –40°C
+25°C ATTN = 0 +110°C
RECEIVER HD2 LEFT (dBc)
–80 –40°C –60 ATTN = 0 +25°C

ATTN = 0 –40°C
–70
–85
–80
–90 –90
–100
–95
–110
–100 –120
–130
–105
–140
–110 –150
16830-619
16830-616
0 5 10 15 20 25 30 –30 –20 –10 0 10 20 30

RECEIVER ATTENUATOR SETTING (dB) BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)
Figure 38. Receiver DC Offset vs. Receiver Attenuator Setting, Figure 41. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation,
LO = 75 MHz Tone Level −21 dBm at Attenuation = 0 dB, X-Axis Is Baseband Frequency
Offset of Fundamental Tone, Not Frequency of HD2 Product (HD2 Product Is
2× Baseband Frequency), HD2 Canceller Disabled, LO = 300 MHz
–30 –10
ATTN = 15 +110°C +110°C Rx2 (RIGHT) +110°C Rx2 (LEFT)
–40
RECEIVER HD3, LEFT AND RIGHT (dBc)

ATTN = 15 –40°C –30 +25°C Rx2 (RIGHT) +25°C Rx2 (LEFT)
–50
–60 ATTN = 0 +25°C –40°C Rx2 (RIGHT) –40°C Rx2 (LEFT)

ATTN = 0 –40°C –50 –40°C Rx1 (RIGHT) –40°C Rx1 (LEFT)
–70
–80 –70
–90
–100 –90
–110
–110
–120
–130
–130
–140
–150
16830-620
–150
–30 –20 –10 0 10 20 30
16830-623
–25 –20 –15 –10 –5 5 10 15 20 25
BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz) 525
FREQUENCY OFFSET FROM LO (MHz)
Figure 42. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation, Figure 45. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone
Tone Level −21 dBm at Attenuation = 0 dB, X-Axis Is Baseband Frequency Level −17 dBm at Attenuation = 0 dB, LO = 525 MHz
Offset of Fundamental Tone, Not Frequency of HD2 Product (HD2 Product Is
2× Baseband Frequency), HD2 Canceller Disabled, LO = 525 MHz
–10 0
+110°C Rx2 (RIGHT) +110°C Rx2 (LEFT)
+110°C Rx1 (RIGHT) +110°C Rx1 (LEFT) –5
–30 +25°C Rx2 (RIGHT) +25°C Rx2 (LEFT) +110°C

+25°C Rx1 (RIGHT) +25°C Rx1 (LEFT) –10 +25°C
–40°C Rx2 (RIGHT) –40°C Rx2 (LEFT) –40°C
–50 –40°C Rx1 (RIGHT) –40°C Rx1 (LEFT)
RECEIVER EVM (dB) –15
–20
–70
–25
–90 –30
–35
–110
–40
–130 –45
–50
16830-624
–150 –65 –55 –45 –35 –25 –15 –5 5
16830-621
–25 –20 –15 –10 –5 5 10 15 20 25

75 LTE 20MHz RF INPUT POWER (dBm)
FREQUENCY OFFSET FROM LO AND ATTENUATION (MHz)
Figure 43. Receiver HD3, Left and Right vs. Frequency Offset from LO and Figure 46. Receiver Error Vector Magnitude (EVM) vs. LTE 20 MHz RF Input
Attenuation, Tone Level = −16 dBm at Attenuation = 0 dB, LO = 75 MHz Power, LTE 20 MHz RF Signal, LO = 75 MHz, Default AGC Settings
–10 0
+110°C Rx2 (RIGHT) +110°C Rx2 (LEFT)
+110°C Rx1 (RIGHT) +110°C Rx1 (LEFT) –5
–30 +25°C Rx2 (RIGHT) +25°C Rx2 (LEFT) +110°C

+25°C Rx1 (RIGHT) +25°C Rx1 (LEFT) –10 +25°C
–40°C Rx2 (RIGHT) –40°C Rx2 (LEFT) –40°C
–50 –40°C Rx1 (RIGHT) –40°C Rx1 (LEFT) –15
RECEIVER EVM (dB)
–20
–70
–25
–90 –30
–35
–110
–40
–130
–45
–50
16830-625
–150
–65 –55 –45 –35 –25 –15 –5 5
16830-622
–25 –20 –15 –10 –5 5 10 15 20 25

Figure 44. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone Figure 47. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF
Level −17 dBm at Attenuation = 0 dB, LO = 300 MHz Signal, LO = 300 MHz, Default AGC Settings
0 –80
–85 100Hz = –99.81dBc/Hz
1kHz = –108.20dBc/Hz
–5 –90 10kHz = –114.24dBc/Hz
+110°C –95 100kHz = –120.82dBc/Hz
–10 +25°C 1MHz = –147.16dBc/Hz
–100
–40°C 10MHz = –152.38dBc/Hz
–105 100MHz = –152.51dBc/Hz
PHASE NOISE (dBc/Hz)

–15
RECEIVER EVM (dB)
–110
–20 –115
–120
–25 –125
–130
–30 –135
–140
–35
–145
–40 –150
–155
–45 –160
–165
–50 –170
16830-626
16830-051
–65 –55 –45 –35 –25 –15 –5 5 100 1k 10k 100k 1M 10M 100M
LTE 20MHz RF INPUT POWER (dBm) FREQUENCY (Hz)
Figure 48. Receiver EVM vs. LTE 20 MHz RF Input Power, Figure 51. LO Phase Noise vs. Frequency Offset, LO = 300 MHz, PLL Loop
LTE 20 MHz RF Signal, LO = 525 MHz, Default AGC Settings Bandwidth = 50 kHz
0 –80
–85 100Hz = –95.48dBc/Hz
1kHz = –103.55dBc/Hz
RECEIVER TO RECEIVER ISOLATION (dB)
10 –90 10kHz = –109.36dBc/Hz

Rx1 TO Rx2 –95 100kHz = –116.28dBc/Hz
20 Rx2 TO Rx1 1MHz = –144.62dBc/Hz
–100
10MHz = –152.33dBc/Hz
–105
30 100MHz = –152.85dBc/Hz
–110
40 –115
–120
50 –125
–130
60 –135
–140
70
–145
80 –150
–155
90 –160
–165
100 –170
16830-627
16830-052
0 100 200 300 400 500 600 100 1k 10k 100k 1M 10M 100M
LO FREQUENCY (MHz) FREQUENCY (Hz)
Figure 49. Receiver to Receiver Isolation vs. LO Frequency, Figure 52. LO Phase Noise vs. Frequency Offset, LO = 525 MHz, PLL Loop
Baseband Frequency = 10 MHz Bandwidth = 50 kHz
–80
100Hz = –110.00dBc/Hz
–85 1kHz = –120.75dBc/Hz
–90 10kHz = –126.54dBc/Hz
–95 100kHz = –132.76dBc/Hz
1MHz = –150.09dBc/Hz
–100 10MHz = –151.09dBc/Hz
–105 100MHz = –150.74dBc/Hz
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
–170
16830-050
100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)
Figure 50. LO Phase Noise vs. Frequency Offset, LO = 75 MHz, PLL Loop
Bandwidth = 50 kHz
0 45
–0.25 40 +110°C
–0.50 +25°C
RECEIVER NOISE FIGURE (dBc)

RECEIVER OFF CHIP MATCHING
35 –40°C
–0.75
CIRCUIT PATH LOSS (dB)
–1.00 30
–1.25 25
–1.50
20
–1.75
–2.00 15
–2.25 10
–2.50
5
–2.75
–3.00 0
16830-698
0 2 4 6 8 10 12 14 16 18 20
500
750
1000
1250
1500
1750
2000
2250
2500
2750
3000
16830-695
ATTENUATION (dB)
LO FREQUENCY (MHz)
Figure 53. Receiver Off Chip Matching Circuit Path Loss vs. LO Frequency, Figure 56. Receiver Noise Figure vs. Attenuation, LO = 1850 MHz,
Can Be Used for De-Embedding Performance Data 200 MHz Bandwidth, Sample Rate = 245.76 MSPS,
Integration Bandwidth = 500 kHz to 100 MHz
0 45
+110°C
–10 +110°C 40 +25°C
–40°C
+25°C

–20 –40°C 35
–30 30
–40
25
–50
20
–60
15
–70
10
–80
5
–90
0
16830-699
–100 0 2 4 6 8 10 12 14 16 18 20
650
850
1050
1250
1450
1650
1850
2050
2250
2450
2650
2850
RECEIVER ATTENUATION (dB)

16830-696
RECEIVER LO FREQUENCY (MHz)
Figure 54. Receiver LO Leakage vs. Receiver LO Frequency, Receiver Figure 57. Receiver Noise Figure vs. Receiver Attenuation, 2850 MHz LO,
Attenuation = 0 dB, RF Bandwidth = 200 MHz, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS,
Sample Rate = 245.76 MSPS Integration Bandwidth = 500 kHz to 100 MHz
45 20
40 +110°C 18
+25°C
16
35 –40°C
14
30
12
25
10
20
8
15 +110°C
6 +25°C
10 –40°C
4
5
2
0
16830-697
0 2 4 6 8 10 12 14 16 18 20 0
650
850
1050
1250
1450
1650
1850
2050
2250
2450
2650
2850
16830-700
ATTENUATION (dB)

Figure 55. Receiver Noise Figure vs. Attenuation, LO = 650 MHz, RF Figure 58. Receiver Noise Figure vs. Receiver LO Frequency,
Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS, Integration Bandwidth = Receiver Attenuation = 0 dB, RF Bandwidth = 200 MHz,
500 kHz to 100 MHz Sample Rate = 245.76 MSPS, Integration Bandwidth = ±100 MHz
20 40
–40°C –40°C
+25°C +25°C
+110°C 35 +110°C
18

30
16
25
14 20
15
12
10
10
5
8 0
16830-326
16830-323
–100 –80 –60 –40 –20 0 20 40 60 80 100 –20 –15 –10 –5 0 5 10
RECEIVER OFFSET FREQUENCY FROM LO (650MHz) CW OUT OF BAND BLOCKER LEVEL (dBm)
Figure 59. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Integration Figure 62. Receiver Noise Figure vs. CW Out of Band Blocker Level, LO =
Bandwidth = 200 kHz, LO = 650 MHz 1685 MHz, Blocker = 2085 MHz
20 110
–40°C –40°C (SUM)
+25°C –40°C (DIFF)
+110°C
+25°C (SUM)
18 100 +25°C (DIFF)
+110°C (SUM)
+110°C (DIFF)
16 RECEIVER IIP2 (dBm) 90
14 80
12 70
10 60
8
16830-324
50
16830-327
–100 –80 –60 –40 –20 0 20 40 60 80 100 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
RECEIVER OFFSET FREQUENCY FROM LO (1850MHz) RECEIVER ATTENUATION (dB)
Figure 60. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Integration Figure 63. Receiver IIP2 vs. Receiver Attenuation, LO = 1800 MHz, Tones
Bandwidth = 200 kHz, LO = 1850 MHz Placed at 1845 MHz and 1846 MHz, −21 dBm Each at Attenuation = 0 dB
20 80
–40°C
+25°C
+110°C
75
18
70
16
65
14 60
55
12
–40°C (SUM)
50 –40°C (DIFF)
+25°C (SUM)
10 +25°C (DIFF)
45 +110°C (SUM)
+110°C (DIFF)
8
16830-325
40
–100 –80 –60 –40 –20 0 20 40 60 80 100 806 826 846 866 886 906
RECEIVER OFFSET FREQUENCY FROM LO (2850MHz) 805 825 845 865 885 905
16830-328
800
Figure 61. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Integration Figure 64. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass
Bandwidth = 200 kHz, LO = 2850 MHz Band Frequency, Receiver Attenuation = 0 dB, LO = 800 MHz, Six Tone Pairs,
−21 dBm Each
80 100
RX1 +110°C MAX OF IIP2_SUM_CF
95 RX1 +110°C MAX OF IIP2_DIF_CF
75
70 RX1 +25°C MAX OF IIP2_SUM_CF

RX1 +25°C MAX OF IIP2_DIF_CF
RECEIVER IIP2 (dBm)

85
80
RX1 –40°C MAX OF IIP2_SUM_CF
60 75 RX1 –40°C MAX OF IIP2_DIF_CF
RX2 –40°C MAX OF IIP2_DIF_CF
70
55
–40°C (SUM) 65
50 –40°C (DIFF)
+25°C (SUM) 60
+25°C (DIFF)
45 +110°C (SUM) 55
+110°C (DIFF)
40 50
1806 1826 1846 1866 1886 1906
807
812
822
827
832
837
842
847
852
857
862
867
872
877
882
887
892
897
902
907
1805 1825 1845 1865 1885 1905
16830-329
16830-089
1800
TONE1 = 802MHz, TONE2 = SWEPT ACROSS PASSBAND
SWEPT PASS BAND FREQUENCY (MHz) ATTENUATOR = 0
Figure 65. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass Figure 68. Receiver IIP2 Sum and Difference Across Bandwidth, Receiver
Band Frequency, Receiver Attenuation = 0 dB, LO = 1800 MHz, Six Tone Pairs, Attenuation = 0 dB, LO = 800 MHz, Tone 1 = 802 MHz, Tone 2 Swept,
−21 dBm Each −21 dBm Each, IIP2_SUM_CF and IIP2_DIF_CF Indicate Sum and Difference
Products
SUM AND DIFFERENCE ACROSS BANDWIDTH (dBm)

SUM AND DIFFERENCE ACROSS BANDWIDTH (dBm)
80 100
Rx1 –40°C MAX OF IIP2_SUM_CF
95 Rx1 –40°C MAX OF IIP2_DIF_CF
75 Rx1 +25°C MAX OF IIP2_SUM_CF
Rx1 +25°C MAX OF IIP2_DIF_CF
90 Rx1 +110°C MAX OF IIP2_SUM_CF
70 Rx1 +110°C MAX OF IIP2_DIF_CF
85 Rx2 –40°C MAX OF IIP2_SUM_CF
Rx2 –40°C MAX OF IIP2_DIF_CF
RECEIVER IIP2
Rx2 +25°C MAX OF IIP2_SUM_CF

RECEIVER IIP2
65 80
Rx2 +25°C MAX OF IIP2_DIF_CF
Rx2 +110°C MAX OF IIP2_SUM_CF
75 Rx2 +110°C MAX OF IIP2_DIF_CF
60
70
55
65
–40°C (SUM)
50 –40°C (DIFF) 60
+25°C (SUM)
+25°C (DIFF) 55
45 +110°C (SUM)
+110°C (DIFF)
50
16830-332
40 1807 1817 1827 1837 1847 1857 1867 1877 1887 1897 1907
2906 2926 2946 2966 2986 3006 SWEPT PASS BAND FREQUENCY (MHz)
16830-330
2905 2925 2945 2965 2985 3005

Figure 66. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass Figure 69. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass
Band Frequency, Receiver Attenuation = 0 dB, LO = 2900 MHz, Six Tone Pairs, Band Frequency, Receiver Attenuation = 0 dB, LO = 1800 MHz, Tone 1 =
−21 dBm Each 1802 MHz, Tone 2 Swept, −21 dBm Each, IIP2_SUM_CF and IIP2_DIF_CF
Indicate Sum and Difference Products
100 100
RX1 +110°C MAX OF IIP2_SUM_CF Rx1 –40°C (SUM)
95 RX1 +110°C MAX OF IIP2_DIF_CF 95 Rx1 –40°C (DIF)
RX2 +110°C MAX OF IIP2_SUM_CF Rx1 +25°C (SUM)

RX2 +110°C MAX OF IIP2_DIF_CF Rx1 +25°C (DIF)
90 90 Rx1 +110°C (SUM)
Rx1 +110°C (DIF)

RECEIVER IIP2 (dBm)
85 85 Rx2 –40°C (SUM)

Rx2 –40°C (DIF)
80 80 Rx2 +110°C (SUM)
Rx2 +110°C (DIF)
75 75
70 RX1 +25°C MAX OF IIP2_SUM_CF 70

RX1 +25°C MAX OF IIP2_DIF_CF
65 RX2 +25°C MAX OF IIP2_DIF_CF 65
60 RX1 –40°C MAX OF IIP2_DIF_CF 60
55 RX2 –40°C MAX OF IIP2_DIF_CF 55
50 50
16830-333
0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 2907 2917 2927 2937 2947 2957 2967 2977 2987 2997 3007
16830-088
TONE1 = 1802MHz, TONE2 = 1892MHz SWEPT PASS BAND FREQUENCY (MHz)

ATTENUATOR = SWEPT
Figure 67. Receiver IIP2, LO = 1800 MHz, Tones Placed at 1802 MHz and Figure 70. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass
1892 MHz, −21 dBm Each at Attenuation = 0 dB, IIP2_SUM_CF and IIP2_DIF_CF Band Frequency, Receiver Attenuation = 0 dB, LO = 2900 MHz, Tone 1 =
Indicate Sum and Difference Products 2902 MHz, Tone 2 Swept, −21 dBm Each
45 25
Rx1 –40°C Rx1 –40°C
Rx1 +25°C Rx1 +25°C
40 Rx1 +110°C Rx1 +110°C
Rx2 –40°C Rx2 –40°C
35 Rx2 +25°C 20 Rx2 +25°C
Rx2 +110°C Rx2 +110°C
RECEIVER IIP3 (dBm)
RECEIVER IIP3 (dBm)

30
15
25
20
10
15
10
5
5
16830-334
0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 0
2905 2915 2925 2935 2945 2955 2965 2975 2985 2995 3005 3015 3025
16830-337
ATTENUATION (dB) 2906 2916 2926 2936 2946 2956 2966 2976 2986 2996 3006 3016 3026
Figure 71. Receiver IIP3 vs. Attenuation, LO = 1800 MHz, Tone 1 = 1890 MHz, Figure 74. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =
Tone 2 = 1891 MHz, −21 dBm Each at Attenuation = 0 dB 0 dB, LO = 2900 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each,
Swept Across Pass Band
30 60
Rx1 –40°C Rx1 –40°C
Rx1 +25°C Rx1 +25°C
Rx1 +110°C Rx1 +110°C
25 Rx2 –40°C 50 Rx2 –40°C
Rx2 +25°C Rx2 +25°C
Rx2 +110°C Rx2 +110°C
RECEIVER IIP3 (dBm)
RECEIVER IIP3 (dBm)
20 40
15 30
10 20
5 10
0 0
16830-338
805 815 825 835 845 855 865 875 885 895 905 915 925 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0
16830-335
806 816 826 836 846 856 866 876 886 896 906 916 926
ATTENUATION (dB)
Figure 72. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation = Figure 75. Receiver IIP3 vs. Attenuation, LO = 1800 MHz, Tone 1 = 1802 MHz,
0 dB, LO = 800 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each, Tone 2 = 1892 MHz, −21 dBm Each at Attenuation = 0 dB
30 30
Rx1 –40°C Rx1 –40°C
Rx1 +25°C Rx1 +25°C
Rx1 +110°C Rx1 +110°C
25 Rx2 –40°C 25 Rx2 –40°C
Rx2 +25°C Rx2 +25°C
RECEIVER IIP3 (dBm)
Rx2 +110°C Rx2 +110°C

20
RECEIVER IIP3 (dBm)
20
15
15
10
10
5
5
0
16830-339
807 817 827 837 847 857 867 877 887 897 907
0 SWEPT PASS BAND FREQUENCY (MHz)
1805 1815 1825 1835 1845 1855 1865 1875 1885 1895 1905 1915 1925
16830-336
1806 1816 1826 1836 1846 1856 1866 1876 1886 1896 1906 1916 1926
SWEPT PASS BAND FREQUENC Y (MHz)
Figure 73. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation = Figure 76. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =
0 dB, LO = 1800 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each, 0 dB, LO = 800 MHz, Tone 1 = 802 MHz, Tone 2 Swept Across Pass Band,
Swept Across Pass Band −21 dBm Each
30 0
Rx1 –40°C –40°C
Rx1 +25°C +25°C
Rx1 +110°C +110°C
25 Rx2 –40°C –20
Rx2 +25°C
RECEIVER IIP3 (dBm)
Rx2 +110°C

20
–40
15
–60
10
–80
5
–100
0
16830-340
1807 1817 1827 1837 1847 1857 1867 1877 1887 1897 1907
SWEPT PASS BAND FREQUENCY (MHz) –120
16830-343
–100 –75 –50 –25 0 25 50 75 100
BASEBAND FREQUENCY OFFSET (Hz)
Figure 77. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation = Figure 80. Receiver Image vs. Baseband Frequency Offset,
0 dB, LO = 1800 MHz, Tone 1 = 1802 MHz, Tone 2 Swept Across Pass Band, Attenuation = 0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,
−21 dBm Each Sample Rate = 245.76 MSPS, LO = 1850 MHz
30 0
–40°C
+25°C
+110°C
25 –20

RECEIVER IIP3 (dBm)
20 –40
15 –60
10 –80
Rx1 –40°C
5 Rx1 +25°C –100
Rx1 +110°C
Rx2 –40°C
Rx2 +110°C
0 –120
16830-344
16830-341
2907 2917 2927 2937 2947 2957 2967 2977 2987 2997 3007 –100 –75 –50 –25 0 25 50 75 100
SWEPT PASS BAND FREQUENCY (MHz) BASEBAND FREQUENCY OFFSET (Hz)
Figure 78. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation = Figure 81. Receiver Image vs. Baseband Frequency Offset,
0 dB, LO = 2900 MHz, Tone 1 = 2902 MHz, Tone 2 Swept Across Pass Band, Attenuation = 0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,
−21 dBm Each Sample Rate = 245.76 MSPS, LO = 2850 MHz
0 0
–40°C –40°C
+25°C +25°C
+110°C +110°C
–20 –20
–40 –40
–60 –60
–80 –80
–100 –100
–120 –120
16830-342
16830-345
–100 –75 –50 –25 0 25 50 75 100 0 2.5 5.0 7.5 10.0 12.5 15.0
BASEBAND FREQUENCY OFFSET (Hz) ATTENUATOR SETTING (dB)
Figure 79. Receiver Image vs. Baseband Frequency Offset, Figure 82. Receiver Image vs. Attenuator Setting,
Attenuation = 0 dB, 200 MHz RF Bandwidth, Tracking Calibration Active, RF Bandwidth = 200 MHz, Tracking Calibration Active,
Sample Rate = 245.76 MSPS, LO = 650 MHz Sample Rate = 245.76 MSPS, LO = 1850 MHz
25 0.10
–40°C 0.05
+25°C 0
20 +110°C –0.05
–0.10
–0.15

15
NORMALIZED RECEIVER
–0.20
RECEIVER GAIN (dB)
–0.25
10 –0.30
–0.35
–0.40
5 –0.45
–0.50
–0.55
0 –0.60
–0.65
–0.70 NORMALIZED I RIPPLE
–5 –0.75 NORMALIZED I RIPPLE
–0.80 NORMALIZED I RIPPLE
–10 –0.85 NORMALIZED Q RIPPLE
–0.90 NORMALIZED Q RIPPLE
–0.95 NORMALIZED Q RIPPLE
–15 –1.00
16830-346
0 5 10 15 20 25 30
1.004
4.492
7.996
11.516
15.044
18.484
22.004
25.492
29.012
32.492
36.004
39.484
43.012
46.484
50.012
53.524
57.004
60.484
64.004
67.516
70.996
74.468
78.004
81.476
84.988
88.492
92.012
95.492
98.996
112.916
102.484
106.004
109.468
16830-350
BASEBAND OFFSET FREQUENCY (MHz)
Figure 83. Receiver Gain vs. Receiver Attenuation, RF Bandwidth = 20 MHz, Figure 86. Normalized Receiver Baseband Flatness vs. Baseband Offset
Sample Rate = 245.76 MSPS, LO = 1850 MHz Frequency, LO = 2600 MHz
24 –70
–40°C –40°C
+25°C +25°C
22 +110°C +110°C
–75
20
RECEIVER GAIN (dB)
–80
18
–85
16
–90
14
–95
12
10 –100
16830-351
650
750
850
950
1150
1050
1250
1350
1450
1550
1650
1750
1850
1950
2050
2150
2250
2350
2450
2550
2650
2750
2850
650 850 1050 1250 1450 1650 1850 2050 2250 2450 2650 2850
16830-347

LO FREQUENCY (MHz)
Figure 84. Receiver Gain vs. LO Frequency, RF Bandwidth = 20 MHz, Sample Figure 87. Receiver DC Offset vs. Receiver LO Frequency
Rate = 245.76 MSPS
0.5 –70
–40°C –40°C
+25°C +25°C
0.4 +110°C +110°C
–75
0.3
0.2
–80
0.1
0 –85
–0.1
–90
–0.2
–0.3
–95
–0.4
–0.5 –100
16830-349
16830-352
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Figure 85. Receiver Gain Step Error vs. Receiver Attenuator Setting over Figure 88. Receiver DC Offset vs. Receiver Attenuator Setting, LO = 1850 MHz
Temperature
–30 10
ATTN = 15 –40°C Rx1 –40°C HD3 (LEFT)
ATTN = 0 –40°C Rx1 –40°C HD3 (RIGHT)

ATTN = 15 +25°C –10 Rx1 +25°C HD3 (LEFT)
–50 ATTN = 0 +25°C Rx1 +25°C HD3 (RIGHT)
ATTN = 15 +110°C Rx1 +110°C HD3 (LEFT)
ATTN = 0 +110°C –30 Rx1 +110°C HD3 (RIGHT)

Rx2 –40°C HD3 (LEFT)
–70 Rx2 –40°C HD3 (RIGHT)
–50
–90 –70
–90
–110
–110
–130 Rx2 +25°C HD3 (LEFT)
–130 Rx2 +25°C HD3 (RIGHT)
Rx2 +110°C HD3 (LEFT)
Rx2 +110°C HD3 (RIGHT)
–150
16830-353
–60 –40 –20 0 20 40 60 –150
–50 –40 –30 –20 10
–10 20 30 40 50
16830-356
Tone Level = −15 dBm at Attenuation = 0 dB, HD2 Correction Configured for Level = −15 dBm at Attenuation = 0 dB, LO = 650 MHz
Low-Side Optimization, X-Axis = Baseband Frequency Offset of Fundamental
Tone and Not the Frequency of the HD2 Product (HD2 Product = 2× Baseband
Frequency), LO = 650 MHz
–30 10
ATTN = 15 –40°C Rx1 –40°C HD3 (LEFT)
ATTN = 0 –40°C Rx1 –40°C HD3 (RIGHT)

ATTN = 15 +25°C –10 Rx1 +25°C HD3 (LEFT)
–50 ATTN = 0 +25°C Rx1 +25°C HD3 (RIGHT)
ATTN = 15 +110°C Rx1 +110°C HD3 (LEFT)
ATTN = 0 +110°C –30 Rx1 +110°C HD3 (RIGHT)

–50
–90 –70
–90
–110
–110
–130 Rx2 +25°C HD3 (LEFT)
–130 Rx2 +25°C HD3 (RIGHT)
–150
16830-354
–60 –40 –20 0 20 40 60 –150

–50 –40 –30 –20–10 10 20 30 40 50
16830-357
Low-Side Optimization, X-Axis = Baseband Frequency Offset of the Fundamental
Tone and Not the Frequency of the HD2 Product (HD2 Product = 2× the Baseband
–30 10
Rx1 –40°C HD3 (RIGHT)
–10 Rx1 +25°C HD3 (LEFT)

–50 Rx1 +25°C HD3 (RIGHT)
–30 Rx1 +110°C HD3 (RIGHT)

–50
–90 –70
–90
–110
ATTN = 15dB, +110°C
ATTN = 0dB, +110°C
–110
ATTN = 15dB, +25°C
–130 ATTN = 0dB, +25°C Rx2 +25°C HD3 (LEFT)
ATTN = 15dB, –40°C –130 Rx2 +25°C HD3 (RIGHT)
ATTN = 0dB, –40°C Rx2 +110°C HD3 (LEFT)
–150
16830-112
–150
–60 –40 –20 0 –20 –40 60
16830-358
–50 –40 –30 –20–10 10 20 30 40 50

Low-Side Optimization, X-Axis = Baseband Frequency Offset of the Fundamental
Tone and Not the Frequency of the HD2 Product (HD2 Product = 2× the Baseband
10 0
Rx1 –40°C HD3 (LEFT) –40°C
Rx1 –40°C HD3 (RIGHT) +25°C
–5
–10 Rx1 +25°C HD3 (LEFT) +110°C

–10
–30 Rx1 +110°C HD3 (RIGHT)
RECEIVER EVM (dB)

Rx2 –40°C HD3 (RIGHT) –15
–50
–20
–70
–25
–90
–30
–110
–35
–130 Rx2 +25°C HD3 (RIGHT)
Rx2 +110°C HD3 (LEFT) –40
–150
–45
16830-362
0 15 30 10 25 5 20 0 15 30 10 25 5 20 0 15 30 10 25 5 20 0 15 30
–50 –40 –30 –10–20 10 20 30 40 50 –65 –55 –45 –35 –25 –15 –5 5
16830-359
UPPER: RECEIVER ATTENUATION (dB)
LOWER: FREQUENCY OFFSET FROM LO (MHz)
Figure 95. Receiver HD3, Left and Right vs. Receiver Attenuation and Frequency Figure 98. Receiver EVM vs. LTE 20 MHz RF Input Power,
Offset from LO, Baseband Tone Held Constant, Tone Level Increased 1 for 1 as LTE 20 MHz RF Signal, LO = 2700 MHz
Attenuator is Swept from 0 dB to 30 dB, HD3 Right (High Side): Tone on Same Side
as HD3 Product; HD3 Left (Low Side): Tone on Opposite Side as HD3 Product,
CW Signal, LO = 1850 MHz, Tone Level = −15 dBm at Attenuation = 0 dB
0 0
–40°C –40°C
+25°C RECEIVER TO RECEIVER ISOLATION (dB) +25°C
–5 +110°C 10 +110°C
–10
20
–15
RECEIVER EVM (dB)
30
–20
40
–25
50
–30
60
–35
–40 70
–45 80
–50
16830-360
90
–65 –55 –45 –35 –25 –15 –5 5
650
750
850
950
1150
1050
1250
1350
1450
1550
1650
1750
1850
1950
2050
2150
2250
2350
2450
2550
2650
2750
2850
16830-363
LTE 20MHz RF INPUT POWER (dBm)
LO FREQUENCY (MHz)
Figure 96. Receiver EVM vs. LTE 20 MHz RF Input Power, Figure 99. Receiver to Receiver Isolation (dB) vs. LO Frequency (MHz)
LTE 20 MHz RF Signal, LO = 600 MHz
0 –70
–40°C
–5 +25°C
+110°C –80
–10 –90
LO PHASE NOISE (dB)
–15 –100
RECEIVER EVM (dB)
–20 –110
–25 –120
–30 –130
–35 –140
–40 –150
–45 –160
–50
16830-361
16830-364
–65 –55 –45 –35 –25 –15 –5 5 –170

100 1k 10k 100k 1M 10M 100M
LTE 20MHz RF INPUT POWER (dBm) FREQUENCY OFFSET (Hz)
Figure 97. Receiver EVM vs. LTE 20 MHz RF Input Power, Figure 100. LO Phase Noise vs. Frequency Offset, LO = 1900 MHz, Spectrum
LTE 20 MHz RF Signal, LO = 1800 MHz Analyzer Limits Far Out Noise
0 45
–0.2 40 +110°C
+25°C

–0.4 35 –40°C
–0.6
30
–0.8
25
–1.0
20
–1.2
15
–1.4
10
–1.6
5
–1.8
0
16830-806
–2.0
0 2 4 6 8 10 12 14 16 18 20
16830-803
3400 3600 3800 4000 4200 4400 4600 4800 5000
LO FREQUENCY (MHz)
Figure 101. Receiver Off Chip Matching Circuit Path Loss vs. LO Frequency Figure 104. Receiver Noise Figure vs. Receiver Attenuation,
(Simulation), Can Be Used for De-Embedding Performance Data LO = 4600 MHz, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS,
0 120
–10 +110°C
+25°C 110
–20 –40°C
–30 100
RECEIVER IIP2 (dBm)
–40
90
–50
80
–60
–70 70 IIP2 SUM +110°C

IIP2 SUM +25°C
–80 IIP2 SUM –40°C
60 IIP2 DIFF +110°C
–90 IIP2 DIFF +25°C
IIP2 DIFF –40°C
–100 50
16830-804
16830-807
3600 4600 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
RECEIVER LO FREQUENCY (MHz) RECEIVER ATTENUATION (dB)
Figure 102. Receiver LO Leakage from 3600 MHz to 4600 MHz, 0 dB Receiver Figure 105. Receiver IIP2 vs. Receiver Attenuation, LO = 3600 MHz, Tones
Attenuation, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate Placed at 3645 MHz and 3646 MHz, −21 dBm Plus Attenuation
45 110
40 +110°C
+25°C 100
35 –40°C
RECEIVER IIP2 (dBm)
30 90
25
80
20
15 70
IIP2 SUM +110°C
10 IIP2 SUM +25°C
60 IIP2 SUM –40°C
5 IIP2 DIFF +110°C
IIP2 DIFF +25°C
IIP2 DIFF –40°C
0 50
16830-805
16830-808
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
RECEIVER ATTENUATION (dB) RECEIVER ATTENUATION (dB)
Figure 103. Receiver Noise Figure vs. Receiver Attenuation, Figure 106. Receiver IIP2 vs. Receiver Attenuation, LO = 4600 MHz, Tones
LO = 3600 MHz, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS, Placed at 4645 MHz and 4646 MHz, −21 dBm Plus Attenuation
80 100
RECEIVER IIP2 SUM AND DIFFERENCE ACROSS
95
75
90
70
RECEIVER IIP2 (dBm)

85
BANDWIDTH (dBm)
65
80
60 75
55 70
IIP2 SUM +110°C 65 +110°C = Rx1 (DIFF) +110°C = Rx2 (DIFF)

50 IIP2 SUM +25°C +110°C = Rx1 (SUM) +110°C = Rx2 (SUM)
IIP2 SUM –40°C 60 +25°C = Rx1 (DIFF) +25°C = Rx2 (DIFF)
45 IIP2 DIFF +110°C +25°C = Rx1 (SUM) +25°C = Rx2 (SUM)
IIP2 DIFF +25°C 55 –40°C = Rx1 (DIFF) –40°C = Rx2 (DIFF)
IIP2 DIFF –40°C –40°C = Rx1 (SUM) –40°C = Rx2 (SUM)
40 50
16830-812
3606 3626 3646 3666 3686 3706 0 5 10 15 20 25 30
16830-809
3605 3625 3645 3665 3685 3705
RECEIVER ATTENUATION
Figure 107. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Figure 110. Receiver IIP2 vs. Receiver Attenuation, LO = 4600 MHz, Tones
Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 3600 MHz, Placed at 4602 MHz and 4692 MHz, −21 dBm Plus Attenuation
Six Tone Pairs, −21 dBm Plus Attenuation Each
80 100

+110°C = Rx1 (DIFF) +110°C = Rx2 (DIFF)

95
75 +110°C = Rx1 (SUM) +110°C = Rx2 (SUM)
+25°C = Rx1 (DIFF) +25°C = Rx2 (DIFF)
90
+25°C = Rx1 (SUM) +25°C = Rx2 (SUM)
70
–40°C = Rx1 (DIFF) –40°C = Rx2 (DIFF)
BANDWIDTH (dBm) 85
–40°C = Rx1 (SUM) –40°C = Rx2 (SUM)
BANDWIDTH (dBm)
65
80
60 75
70
55
IIP2 SUM +110°C 65

50 IIP2 SUM +25°C
IIP2 SUM –40°C 60
IIP2 DIFF +25°C 55
IIP2 DIFF –40°C
40 50
16830-813
4606 4626 4646 4666 4686 4706 3612 3622 3632 3642 3652 3662 3672 3682 3692 3702 3712
16830-810
4605 4625 4645 4665 4685 4705 SWEPT PASS BAND FREQUENCY (MHz)
Figure 108. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Figure 111. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept
Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 4600 MHz, Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 3600 MHz,
Six Tone Pairs, −21 dBm Each Tone 1 = 3602 MHz, Tone 2 Swept, −21 dBm Each
100 100
Rx1 +110°C IIP2_SUM_CF Rx2 +25°C IIP2_SUM_CF

95 95
Rx1 +110°C IIP2_DIF_CF Rx2 +25°C IIP2_DIF_CF
90 Rx2 +110°C IIP2_SUM_CF Rx1 –40°C IIP2_SUM_CF
90 Rx2 +110°C IIP2_DIF_CF Rx1 –40°C IIP2_DIF_CF
85 Rx1 +25°C IIP2_SUM_CF Rx2 –40°C IIP2_SUM_CF
RECEIVER IIP2 (dBm)
85 Rx1 +25°C IIP2_DIF_CF Rx2 –40°C IIP2_DIF_CF

BANDWIDTH (dBm)
80
80
75
75
70
70
65
65 +110°C = Rx1 (DIFF) +110°C = Rx2 (DIFF)
+110°C = Rx1 (SUM) +110°C = Rx2 (SUM) 60
Tone2
60 +25°C = Rx1 (DIFF) +25°C = Rx2 (DIFF)
+25°C = Rx1 (SUM) +25°C = Rx2 (SUM) 55
–40°C = Rx1 (DIFF) –40°C = Rx2 (DIFF)
55 50
–40°C = Rx1 (SUM) –40°C = Rx2 (SUM)
50 40
16830-811
16830-193
0 5 10 15 20 25 30 4612 4622 4632 4642 4652 4662 4672 4682 4692 4702 4712
RECEIVER ATTENUATION
Figure 109. Receiver IIP2 vs. Receiver Attenuation, LO = 3600 MHz, Figure 112. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept
Tone 1 = 4602 MHz and Tone 2 = 4692 MHz, −21 dBm Plus Attenuation Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 4600 MHz,
Tone 1 = 4602 MHz, Tone 2 Swept, −21 dBm Each, IIP2_SUM_CF and
IIP2_DIF_CF Indicate Sum and Difference Products
45 30
40
25
35
RECEIVER IIP3 (dBm)
RECEIVER IIP3 (dBm)

30 20
25
15
20
15 Rx1 = +110°C Rx1 = +110°C

Rx1 = +25°C 10
Rx1 = +25°C
Rx1 = –40°C Rx1 = –40°C
10
Rx2 = +110°C
Rx2 = +110°C
Rx2 = +25°C 5
5 Rx2 = +25°C
Rx2 = –40°C
Rx2 = –40°C
0
16830-814
0 5 10 15 20 25 30 0
4605 4625 4645 4665 4685 4705
ATTENUATION (dB)
16830-817
4606 4626 4646 4666 4686 4706
Figure 113. Receiver IIP3 vs. Attenuation, LO = 3600 MHz, Tone 1 = 3695 MHz, Figure 116. Receiver IIP3 vs. Receiver Attenuation, Receiver Attenuation = 0 dB,
Tone 2 = 3696 MHz, −21 dBm Plus Attenuation LO = 4600 MHz, Tone 2 = Tone 1 + 1 MHz,
−21 dBm Each, Swept Across Pass Band
45 50
45
40
40
35
RECEIVER IIP3 (dBm) 35
RECEIVER IIP3 (dBm)
30
30
25
25
20 20
Rx1 = +110°C
15 Rx1 = +110°C 15 Rx1 = +25°C
Rx1 = +25°C Rx1 = –40°C
Rx1 = –40°C 10 Rx2 = +110°C
10
Rx2 = +110°C Rx2 = +25°C
Rx2 = +25°C 5 Rx2 = –40°C
5 Rx2 = –40°C
0
16830-818
0 0 5 10 15 20 25 30
0 5 10 15 20 25 30
16830-815
TONE 1 = 4695MHz TONE 2 = 4696MHz RECEIVER ATTENUATION (dB)

RECEIVER ATTENUATION SWEPT (dB)
Figure 114. Receiver IIP3 vs. Receiver Attenuation Swept, LO = 4600 MHz, Figure 117. Receiver IIP3 vs. Receiver Attenuation, LO = 3600 MHz, Tone 1 =
Tone 1 = 4695 MHz, Tone 2 = 4696 MHz, −21 dBm Plus Attenuation 3602 MHz, Tone 2 = 3692 MHz, −21 dBm Plus Attenuation
30 50
RECEIVER IIP3 ACROSS BANDWITH (dBm)
25 50
RECEIVER IIP3 (dBm)
40
20
30
15
20 Rx1 = +110°C
10 Rx1 = +110°C Rx1 = +25°C
Rx1 = +25°C Rx1 = –40°C
Rx1 = –40°C Rx2 = +110°C
Rx2 = +110°C 10 Rx2 = +25°C
5 Rx2 = +25°C Rx2 = –40°C
Rx2 = –40°C
0
16830-819
0 0 5 10 15 20 25 30
3605 3625 3645 3665 3685 3705
16830-816
3606 3626 3646 3666 3686 3706 RECEIVER ATTENUATION (dB)

Figure 115. Receiver IIP3 Across Bandwidth, Receiver Attenuation = 0 dB, LO = Figure 118. Receiver IIP3 vs. Receiver Attenuation, LO = 4600 MHz,
3600 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each, Tone 1 = 4602 MHz, Tone 2 = 4692 MHz, −21 dBm Plus Attenuation
35 0
RECEIVER IIP3 ACROSS BANDWIDTH (dBm)
+110°C
30 +25°C
–20
–40°C

25
–40
20
–60
15
Rx1 = +110°C
Rx1 = +25°C –80
10
Rx1 = –40°C
Rx2 = +110°C
5 Rx2 = +25°C –100
Rx2 = –40°C
16830-820
3612 3632 3652 3672 3692 3712 –120
16830-823
–100 –75 –50 –25 0 25 50 75 100
BASEBAND FREQUENCY OFFSET (MHz)
Figure 119. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency, Figure 122. Receiver Image vs. Baseband Frequency Offset, Attenuation =
Receiver Attenuation = 0 dB, LO = 3600 MHz, Tone 1 = 3602 MHz, Tone 2 Swept 0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,
Across Pass Band, −21 dBm Each Sample Rate = 245.76 MSPS, LO = 4600 MHz
35 0
+110°C
30 +25°C
–20
–40°C
25
–40
20
–60
15
Rx1 = +110°C
Rx1 = +25°C –80
10
Rx1 = –40°C
Rx2 = +110°C
5 Rx2 = +25°C –100
Rx2 = –40°C
0
16830-821
4612 4632 4652 4672 4692 4712 –120
16830-824
0 5 10 15 20 25 30
ATTENUATOR SETTING (dB)
Figure 120. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency, Figure 123. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz,
Receiver Attenuation = 0 dB, LO = 4600 MHz, Tracking Calibration Active, Sample Rate = 245.76 MSPS,
Tone 1 = 4602 MHz, Tone 2 Swept Across Pass Band, −21 dBm Each LO = 3600 MHz, Baseband Frequency= 10 MHz
0 0
+110°C +110°C
–20 +25°C +25°C
–20
–40°C –40°C
–40 –40
–60 –60
–80 –80
–100 –100
–120 –120
16830-822
16830-825
–100 –75 –50 –25 0 25 50 75 100 0 5 10 15 20 25 30

BASEBAND FREQUENCY OFFSET (MHz) ATTENUATOR SETTING (dB)
Figure 121. Receiver Image vs. Baseband Frequency Offset, Attenuation = Figure 124. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz,
0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active, Tracking Calibration Active, Sample Rate = 245.76 MSPS,
Sample Rate = 245.76 MSPS, LO = 3600 MHz LO = 4600 MHz, Baseband Frequency = 10 MHz
25 0.5
+110°C 0.4 +110°C

20
+25°C +25°C

–40°C 0.3 –40°C
15
RECEIVER GAIN (dBc)
0.2
10
0.1
5 0
–0.1
0
–0.2
–5
–0.3
–10
–0.4
–15 –0.5
16830-826
16830-829
0 5 10 15 20 25 30 0 5 10 15 20 25 30
RECEIVER ATTENUATION (dB) RECEIVER ATTENUATOR SETTING (dB)
Figure 125. Receiver Gain vs. Receiver Attenuation, RF Bandwidth = 20 MHz, Figure 128. Receiver Gain Step Error vs. Receiver Attenuator Setting,
Sample Rate = 245.76 MSPS, LO = 3600 MHz LO = 3600 MHz
25 0.5
+110°C 0.4 +110°C

20
+25°C +25°C

–40°C 0.3 –40°C
15
RECEIVER GAIN (dBc)
0.2
10
0.1
5 0
–0.1
0
–0.2
–5
–0.3
–10
–0.4
–15 –0.5
16830-827
16830-830
0 5 10 15 20 25 30 0 5 10 15 20 25 30
RECEIVER ATTENUATION (dB) RECEIVER ATTENUATOR SETTING (dB)
Figure 126. Receiver Gain vs. Receiver Attenuation, RF Bandwidth = 20 MHz, Figure 129. Receiver Gain Step Error vs. Receiver Attenuator Setting,
Sample Rate = 245.76 MSPS, LO = 4600 MHz LO = 4600 MHz
24 –50
+110°C +110°C
22 +25°C +25°C
–60
–40°C –40°C
20
RECEIVER GAIN (dBc)
–70
18
–80
16
–90
14
–100
12
10 –110
16830-831
3400 3600 3800 4000 4200 4400 4600 4800

3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
16830-828

LO FREQUENCY (MHz)
Figure 127. Receiver Gain vs. LO Frequency, RF Bandwidth = 200 MHz, Figure 130. Receiver DC Offset vs. Receiver LO Frequency
Sample Rate = 245.76 MSPS
–70 –30
–40
–75 +110°C
+25°C –50
–40°C
RECEIVER HD2, LEFT (dBc)

–80 –60
–70
–85
–80
–90 –90
–100
–95
–110 ATTN = 0 +110°C
ATTN = 0 +25°C
–100 –120 ATTN = 0 –40°C
–130 ATTN = 15 +110°C
–105 ATTN = 15 +25°C
–140 ATTN = 15 –40°C
–110 –150
16830-832
16830-835
0 5 10 15 20 25 30 –60 –40 –20 0 20 40 60
RECEIVER ATTENUATOR SETTING (dB) BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)
Figure 131. Receiver DC Offset vs. Receiver Attenuator Setting, LO = 3600 MHz Figure 134. Receiver HD2, Left vs. Baseband Frequency Offset and
Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, X-Axis =
Baseband Frequency Offset of the Fundamental Tone, Not the Frequency of
the HD2 Product (HD2 Product = 2× the Baseband Frequency), HD2
Canceller Disabled, LO = 4600 MHz
–70 10
Rx1 = +110°C (RIGHT) Rx2 = +110°C (RIGHT)
+110°C Rx1 = +110°C (LEFT) Rx2 = +110°C (LEFT)
–75
+25°C RECEIVER HD3, LEFT AND RIGHT (dBc) –10
–40°C Rx1 = +25°C (LEFT) Rx2 = +25°C (LEFT)
–80 –30 Rx1 = –40°C (RIGHT) Rx2 = –40°C (RIGHT)

Rx1 = –40°C (LEFT) Rx2 = –40°C (LEFT)
–85 –50
–90 –70
–95 –90
–100 –110
–105
–130
–110
16830-833
0 5 10 15 20 25 30 –150
16830-836
–50 –40 –30 –20 –10 10 20 30 40 50
RECEIVER ATTENUATOR SETTING (dB) 3600
Figure 132. Receiver DC Offset vs. Receiver Attenuator Setting, Figure 135. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone
LO = 4600 MHz Level = −15 dBm at Attenuation = 0 dB, LO = 3600 MHz
–30 10
–40 Rx1 = +110°C (LEFT) Rx2 = +110°C (LEFT)
–10
–50 Rx1 = +25°C (RIGHT) Rx2 = +25°C (RIGHT)
Rx1 = +25°C (LEFT) Rx2 = +25°C (LEFT)
RECEIVER HD2, LEFT (dBc)
–60 –30 Rx1 = –40°C (RIGHT) Rx2 = –40°C (RIGHT)

Rx1 = –40°C (LEFT) Rx2 = –40°C (LEFT)
–70
–50
–80
–90 –70
–100
–90
–110 ATTN = 0 +110°C
ATTN = 0 +25°C
–120 ATTN = 0 –40°C –110
–130 ATTN = 15 +110°C
ATTN = 15 +25°C
–140 ATTN = 15 –40°C –130
–150
16830-834
–60 –40 –20 0 20 40 60 –150

16830-837
–50 –40 –30 –20

–10 10 20 30 40 50
FREQUENCY OFFSET FROM LO AND ATTENUATION (MHz)
Figure 133. Receiver HD2, Left vs. Baseband Frequency Offset and Figure 136. Receiver HD3, Left and Right vs. Frequency Offset from LO and
Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, X-Axis = Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB,
Baseband Frequency Offset of the Fundamental Tone Not the Frequency of LO = 4600 MHz
the HD2 Product (HD2 Product = 2× the Baseband Frequency), HD2
Canceller Disabled, LO = 3600 MHz
0 0
Rx1 TO Rx2 ISOLATION

–5 +110°C 10 Rx2 TO Rx1 ISOLATION
+25°C
–10 –40°C 20
–15
RECEIVER EVM (dB)
30
–20
40
–25
50
–30
60
–35
–40 70
–45 80
–50 90
16830-838
–65 –55 –45 –35 –25 –15 –5 5
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
16830-840
LTE 20MHz RF INPUT POWER (dBm)
LO FREQUENCY (MHz)
Figure 137. Receiver EVM vs. LTE 20 MHz RF Input Power, RF Signal = Figure 139. Receiver to Receiver Isolation vs. LO Frequency
LTE 20 MHz, LO = 3600 MHz, Default AGC Settings
0 –70
–5 +110°C –80
+25°C
–10 –40°C –90
LO PHASE NOISE (dB)

–100
RECEIVER EVM (dB)
–15
–110
–20
–120
–25
–130
–30
–140
–35
–150
–40 –160
–45 –170
16830-839
16830-841
–65 –55 –45 –35 –25 –15 –5 5 100 1k 10k 100k 1M 10M 100M
Figure 138. Receiver EVM vs. LTE 20 MHz RF Input Power, Figure 140. LO Phase Noise vs. Frequency Offset, LO = 3800 MHz, PLL Loop
RF Signal = LTE 20 MHz, LO = 4600 MHz, Default AGC Settings Bandwidth = 300 kHz, Spectrum Analyzer Limits Far Out Noise
0 80

–0.20
75
–0.40
70
–0.60
BANDWIDTH (dBm)
65
–0.80
–1.00 60
–1.20 55
–1.40 IIP2 SUM +110°C

50 IIP2 SUM +25°C
–1.60 IIP2 SUM –40°C
–1.80 IIP2 DIFF +25°C
IIP2 DIFF –40°C
–2.00 40
5805 5825 5845 5865 5885 5905
16830-902
16830-899
5000 5200 5400 5600 5800 6000 5806 5826 5846 5866 5886 5906
LO FREQUENCY (MHz) SWEPT PASS BAND FREQUENCY (MHz)
Figure 141. Receiver Off Chip Matching Circuit Path Loss vs. LO Frequency Figure 144. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept
(Simulation), Can Be Used for De-Embedding Performance Data Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 5800 MHz,
Six Tone Pairs, −21 dBm Plus Attenuation Each
0 110
Rx1 IIP2 DIFF +110°C
–10 +110°C Rx1 IIP2 SUM +110°C
+25°C 100 Rx1 IIP2 DIFF +25°C
–40°C
–20 Rx1 IIP2 SUM +25°C

Rx1 IIP2 DIFF –40°C
RECEIVER IIP2 (dBm)
–30 Rx1 IIP2 SUM –40°C

90
–40
–50 80
–60
70
–70 Rx2 IIP2 DIFF +110°C
Rx2 IIP2 SUM +110°C
–80 Rx2 IIP2 DIFF +25°C
60
Rx2 IIP2 SUM +25°C
–90 Rx2 IIP2 DIFF –40°C
Rx2 IIP2 SUM –40°C
–100 50
16830-903
16830-900
5200 5300 5400 5500 5600 5700 5800 0 5 10 15 20 25 30

RECEIVER LO FREQUENCY (MHz) RECEIVER ATTENUATION
Figure 142. Receiver LO Leakage vs. Receiver LO Frequency, 5200 MHz, Figure 145. Receiver IIP2 vs. Receiver Attenuation, LO = 5800 MHz, Tones
5500 MHz, and 5800 MHz, Receiver Attenuation = 0 dB, RF Bandwidth = Placed at 5802 MHz and 5892 MHz, −21 dBm Plus Attenuation
200 MHz, Sample Rate = 245.76 MSPS
110 80
IIP2 SUM +110°C Rx1 IIP2 DIFF +110°C

IIP2 SUM +25°C Rx1 IIP2 SUM +110°C
IIP2 SUM –40°C 75 Rx1 IIP2 DIFF +25°C
100
IIP2 DIFF +110°C Rx1 IIP2 SUM +25°C
IIP2 DIFF +25°C 70 Rx1 IIP2 DIFF –40°C
IIP2 DIFF –40°C Rx1 IIP2 SUM –40°C
RECEIVER IIP2 (dBm)
BANDWIDTH (dBm)
90
65
80 60
55
70 Rx2 IIP2 DIFF +110°C
50 Rx2 IIP2 SUM +110°C
Rx2 IIP2 DIFF +25°C
60 Rx2 IIP2 SUM +25°C
45 Rx2 IIP2 DIFF –40°C
Rx2 IIP2 SUM –40°C
50 40
5802 5812 5822 5832 5842 5852 5862 5872 5882 5892 5902
16830-901
16830-904
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 5802 5802 5802 5802 5802 5802 5802 5802 5802 5802 5802
ATTENUATION (dB) SWEPT PASS BAND FREQUENCY (MHz)
Figure 143. Receiver IIP2 vs. Attenuation, LO = 5800 MHz, Tones Placed at Figure 146. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept
5845 MHz and 5846 MHz, −21 dBm Plus Attenuation Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 5800 MHz,
Tone 1 = 5802 MHz, Tone 2 Swept, −21 dBm Each
45 30

Rx1 = +110°C Rx1 = +110°C
40 Rx1 = +25°C Rx1 = +25°C
Rx1 = –40°C 25 Rx1 = –40°C
35 Rx2 = +110°C Rx2 = +110°C
Rx2 = +25°C Rx2 = +25°C
RECEIVER IIP3 (dBm)
30 Rx2 = –40°C 20 Rx2 = –40°C
25
15
20
15 10
10
5
5
0 0
16830-905
0 5 10 15 20 25 30 5802 5802 5802 5802 5802 5802 5802 5802 5802 5802 5802 5802
16830-908
RECEIVER ATTENUATION (dB) 5812 5822 5832 5842 5852 5862 5872 5882 5892 5902 5912 5922
Figure 147. Receiver IIP3 vs. Receiver Attenuation, LO = 5800 MHz, Tone 1 = Figure 150. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency,
5895 MHz, Tone 2 = 5896 MHz, −21 dBm Plus Attenuation Receiver Attenuation = 0 dB, LO = 5800 MHz, Tone 1 = 5802 MHz, Tone 2
Swept Across Pass Band, −21 dBm Each
30 –10
Rx1 = +110°C
–20 +110°C
Rx1 = +25°C
25 Rx1 = –40°C +25°C
Rx2 = +110°C –30 –40°C
Rx2 = +25°C
RECEIVER IIP3 (dBm)
Rx2 = –40°C –40

20
–50
15 –60
–70
10
–80
5 –90
–100
0
5805 5815 5825 5835 5845 5855 5865 5875 5888 5895 5905 5915 –110
16830-906
16830-909
5806 5816 5826 5836 5846 5856 5866 5876 5886 5896 5906 5916 –100 –75 –50 –25 0 25 50 75 100
SWEPT PASS BAND FREQUENCY (MHz) BASEBAND FREQUENCY OFFSET (MHz)
Figure 148. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Figure 151. Receiver Image vs. Baseband Frequency Offset, Attenuation =
Attenuation = 0 dB, LO = 5800 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm 0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,
Each, Swept Across Pass Band Sample Rate = 245.76 MSPS, LO = 5200 MHz
60 –10
Rx1 = +110°C
–20 +110°C
Rx1 = +25°C
50 +25°C
Rx1 = –40°C
Rx2 = +110°C –30 –40°C
Rx2 = +25°C
RECEIVER IIP3 (dBm)
Rx2 = –40°C –40

40
–50
30 –60
–70
20
–80
10 –90
–100
0
16830-907
0 5 10 15 20 25 30 –110
16830-910
–100 –75 –50 –25 0 25 50 75 100

BASEBAND FREQUENCY OFFSET (MHz)
Figure 149. Receiver IIP3 vs. Receiver Attenuation, LO = 5800 MHz, Figure 152. Receiver Image vs. Baseband Frequency Offset, Attenuation =
Tone 1 = 5802 MHz, Tone 2 = 5892 MHz, −21 dBm Plus Attenuation 0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,
Sample Rate = 245.76 MSPS, LO = 5900 MHz
0 0.5
+110°C 0.4 +110°C

+25°C +25°C
RECEIVER GAIN STEP ERROR (dBc)

–20
–40°C 0.3 –40°C
0.2
–40
0.1
–60 0
–0.1
–80
–0.2
–0.3
–100
–0.4
–120 –0.5
16830-914
16830-911
0 2 10 15 20 25 30 0 2 10 15 20 25 30
ATTENUATOR SETTING (dB) RECEIVER ATTENUATOR SETTING AND TEMPERATURE (dB)
Figure 153. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz, Figure 156. Receiver Gain Step Error vs. Receiver Attenuator Setting and
Tracking Calibration Active, Sample Rate = 245.76 MSPS, Temperature, LO = 5600 MHz
LO = 5200 MHz, Baseband Frequency = 10 MHz
0 0.5
+110°C 0.4 +110°C

+25°C +25°C

–20
–40°C 0.3 –40°C
0.2
–40
0.1
–60 0
–0.1
–80
–0.2
–0.3
–100
–0.4
–120 –0.5
16830-912
16830-915
0 2 10 15 20 25 30 0 2 10 15 20 25 30
ATTENUATOR SETTING (dB) RECEIVER ATTENUATOR SETTING AND TEMPERATURE (dB)
Figure 154. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz, Figure 157. Receiver Gain Step Error vs. Receiver Attenuator Setting and
Tracking Calibration Active, Sample Rate = 245.76 MSPS, Temperature, LO = 6000 MHz
LO = 5900MHz, Baseband Frequency = 10 MHz
0.5 0.5
0.4
0.4 +110°C
+25°C 0.3
0.3 –40°C 0.2

0.2 0.1
NORMALIZED RECEIVER
0
0.1 –0.1
0 –0.2
–0.3
–0.1 –0.4
–0.2 –0.5
MAX OF NORMALIZED I RIPPLE –40°C
–0.6
–0.3 MAX OF NORMALIZED I RIPPLE +25°C
–0.7 MAX OF NORMALIZED I RIPPLE +110°C
–0.4 –0.8 MAX OF NORMALIZED Q RIPPLE –40°C
MAX OF NORMALIZED Q RIPPLE +25°C
–0.9
–0.5 MAX OF NORMALIZED Q RIPPLE +110°C
16830-913
–1.0
0 2 10 15 20 25 30
0.99
4.502
8.002
11.498
14.998
18.514
22.006
25.514
29.006
32.498
35.978
39.502
42.998
46.502
49.978
53.518
56.998
60.506
64.006
67.502
71.014
74.506
77.986
81.502
84.998
88.498
91.978
95.486
98.998
102.514
105.998
109.502
113.002
RECEIVER ATTENUATOR SETTING AND TEMPERATURE (dB)

16830-299
BASEBAND FREQUENCY (MHz)
Figure 155. Receiver Gain Step Error vs. Receiver Attenuator Setting and Figure 158. Normalized Receiver Baseband Flatness vs. Baseband Frequency
Temperature, LO = 5200 MHz (Receiver Flatness)
–30 –10
Rx2 = +110°C (LEFT) Rx2 = +110°C (RIGHT)
–40 Rx1 = +110°C (LEFT) Rx1 = +110°C (RIGHT)

–50 –30 Rx2 = +25°C (LEFT) Rx2 = +25°C (RIGHT)
–60 Rx2 = –40°C (LEFT) Rx2 = –40°C (RIGHT)

–70
–80 –70
–90
–100 –90
–110 ATTN = 15 +110°C
ATTN = 15 +25°C –110
–120 ATTN = 15 –40°C
–130 ATTN = 0 +110°C
ATTN = 0 +25°C –130
–140 ATTN = 0 –40°C
–150
16830-916
–150
–60 –40 –20 0 20 40 60
16830-919
–50 –40 –30 –20 –10 10 20 30 40 50
BASEBAND FREQUENCY OFFSET (MHz) 5900
Figure 159. Receiver HD2 Left vs. Baseband Frequency Offset, Tone Level = Figure 162. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone
−15 dBm at Attenuation = 0 dB, X-Axis = Baseband Frequency Offset of the Level = −15 dBm at Attenuation = 0 dB, LO = 5900 MHz
Fundamental Tone Not the Frequency of the HD2 Product (HD2 Product = 2×
the Baseband Frequency), HD2 Canceller Disabled,
LO = 5200 MHz
–30 0
–40 +110°C
–5
+25°C
–50
–40°C
–10
–60
RECEIVER EVM (dB)
–70 –15
–80
–20
–90
–25
–100
–110 ATTN = 15 +110°C –30
ATTN = 15 +25°C
–120 ATTN = 15 –40°C –35
–130 ATTN = 0 +110°C
ATTN = 0 +25°C
–40
–140 ATTN = 0 –40°C
–150 –45
16830-920
16830-917
–60 –40 –20 0 20 40 60 –65 –55 –45 –35 –25 –15 –5 5

BASEBAND FREQUENCY OFFSET (MHz) LTE 20MHz RF INPUT POWER (dBm)
Figure 160. Receiver HD2 Left vs. Baseband Frequency Offset, Tone Level = Figure 163. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF
−15 dBm at Attenuation = 0 dB, X-Axis = Baseband Frequency Offset of the Signal, LO = 5200 MHz, Default AGC Settings
Fundamental Tone Not the Frequency of the HD2 Product (HD2 Product = 2×
the Baseband Frequency), HD2 Canceller Disabled,
LO = 5900 MHz
–10 0
Rx1 = +110°C (LEFT) Rx1 = +110°C (RIGHT) –5 +110°C
–30 Rx2 = +25°C (LEFT) Rx2 = +25°C (RIGHT) +25°C

Rx1 = +25°C (LEFT) Rx1 = +25°C (RIGHT) –40°C
–10
Rx2 = –40°C (LEFT) Rx2 = –40°C (RIGHT)
RECEIVER EVM (dB)
–15
–70 –20
–25
–90
–30
–110
–35
–130 –40
–45
16830-921
–150 –65 –55 –45 –35 –25 –15 –5 5

16830-918
–50 –40 –30 –20 –10 10 20 30 40 50

Figure 161. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone Figure 164. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF
Level = −15 dBm at Attenuation = 0 dB, LO = 5200 MHz Signal, LO = 5500 MHz, Default AGC Settings
0 –20
–5 +110°C
–40
+25°C
–40°C
–10
–60
LO PHASE NOISE (dB)

RECEIVER EVM (dB)
–15
–80
–20
–100
–25
–120
–30
–140
–35
–40 –160
–45 –180
16830-922
16830-924
–65 –55 –45 –35 –25 –15 –5 5 100 1k 10k 100k 1M 10M 100M
Figure 165. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF Figure 167. LO Phase Noise vs. Frequency Offset, LO = 5900 MHz, PLL Loop
Signal, LO = 5800 MHz, Default AGC Settings Bandwidth > 300 kHz, Spectrum Analyzer Limits Far Out Noise
0
Rx1 TO Rx2
10
Rx2 TO Rx1
20
30
40
50
60
70
80
90
100
16830-923
5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000
LO FREQUENCY (MHz)
Figure 166. Receiver to Receiver Isolation vs. LO Frequency
RECEIVER INPUT IMPEDANCE
RX PORT SIMULATED IMPEDANCE: SEDZ
M15 M20
FREQUENCY = 100.0MHz FREQUENCY = 3.000GHz
S (1,1) = 0.390 / –1.819 S (1,1) = 0.267 / –64.650
IMPEDANCE = 113.933 – j3.331 IMPEDANCE = 55.102 – j28.685
M16 M21
FREQUENCY = 300.0MHz FREQUENCY = 4.000GHz
S (1,1) = 0.390 / –5.495 S (1,1) = 0.186 / –104.336
IMPEDANCE = 112.803 – j9.931 M23 IMPEDANCE = 42.821 – j16.026
M17 M22
FREQUENCY = 500.0MHz M15 FREQUENCY = 5.000GHz
M22 M16
S (1,1)
S (1,1) = 0.388 / –9.198 M17 S (1,1) = 0.164 / –173.106
M18
IMPEDANCE = 110.398 – j16.107 IMPEDANCE = 35.977 – j1.455
M21 M19
M20 M23
M18
FREQUENCY = 1.000GHz FREQUENCY = 6.000GHz
S (1,1) = 0.377 / –18.643 S (1,1) = 0.266 / 130.063
IMPEDANCE = 100.377 – j28.250 IMPEDANCE = 32.890 + j14.399
M19
FREQUENCY = 2.000GHz
S (1,1) = 0.336 / –39.123
IMPEDANCE = 74.966 – j35.800
16830-004
FREQUENCY (0Hz TO 6.000GHz)
Figure 168. Receiver Input Impedance, Series Equivalent Differential Impedance (SEDZ)
TERMINOLOGY
Large Signal Bandwidth Backoff
Large signal bandwidth, otherwise known as instantaneous Backoff is the difference (in dB) between full-scale signal power
bandwidth or signal bandwidth, is the bandwidth over which and the rms signal power.
there are large signals. For example, for Band 42 LTE, the large PHIGH
signal bandwidth is 200 MHz. PHIGH is the largest signal that can be applied without overloading
Occupied Bandwidth the ADC for the receiver input. This input level results in slightly
Occupied bandwidth is the total bandwidth of the active signals. less than full scale at the digital output because of the nature of the
For example, three 20 MHz carriers have a 60 MHz occupied continuous-time, Σ-Δ ADCs, which, for example, exhibit a soft
bandwidth, regardless of the placement of the carriers within overload in contrast to the hard clipping of pipeline ADCs.
the large signal bandwidth.
THEORY OF OPERATION
The ADRV9008-1 is a highly integrated, RF, agile receiver Clock PLL
subsystem capable of configuration for a wide range of The ADRV9008-1 contains a PLL synthesizer that generates
applications. The device integrates all RF, mixed-signal, and all the baseband related clock signals and serialization/
digital blocks necessary to provide all receiver functions in a deserialization (SERDES) clocks. This PLL is programmed
single device. Programmability allows the receiver to be adapted based on the data rate and sample rate requirements of the
for use in many TDD and 3G/4G/5G cellular standards. The system.
ADRV9008-1 contains two high speed links each for the receiver
chain. These links are JESD204B, Subclass 1 compliant. SPI
The ADRV9008-1 also provides tracking correction of dc offset The ADRV9008-1 uses an SPI interface to communicate with
QEC errors to maintain high performance under varying temp- the BBP. This interface can be configured as a 4-wire interface
eratures and input signal conditions. The device also includes test with a dedicated receiver port and transmitter port. The interface
modes that allow system designers to debug designs during can also be configured as a 3-wire interface with a bidirectional
prototyping and optimize radio configurations. data communications port. This bus allows the BBP to set all
device control parameters using a simple address data serial bus
RECEIVERS protocol.
The ADRV9008-1 receivers contain all the blocks necessary to Write commands follow a 24-bit format. The first five bits set
receive RF signals and convert them to digital data used by a BBP. the bus direction and the number of bytes to transfer. The next
Each receiver can be configured as a direct conversion system 11 bits set the address where the data is written. The final eight
that supports up to a 200 MHz bandwidth. Each receiver contains bits are the data transferred to the specific register address.
a programmable attenuator stage and matched I and Q mixers
Read commands follow a similar format with the exception that
that downconvert received signals to baseband for digitization.
the first 16 bits are transferred on the SDIO pin and the final eight
Achieve gain control by using the on-chip AGC or by allowing bits are read from the ADRV9008-1, either on the SDO pin in
the BBP to make gain adjustments in a manual gain control 4-wire mode or on the SDIO pin in 3-wire mode.
mode. Optimize performance by mapping each gain control
setting to specific attenuation levels at each adjustable gain block JTAG BOUNDARY SCAN
in the receiver signal path. Additionally, each channel contains The ADRV9008-1 provides support for the JTAG boundary
independent receive signal strength indicator (RSSI) measurement scan. There are five dual-function pins associated with the
capability, dc offset tracking, and all circuitry necessary for self JTAG interface. These pins, listed in Figure 5, are used to access
calibration. the on-chip test access port. To enable the JTAG functionality,
The receivers include ADCs and adjustable sample rates that set the GPIO_3 pin through the GPIO_0 pin to 1001 and pull
produce data streams from the received signals. The signals can the TEST pin high.
be conditioned further by a series of decimation filters and a POWER SUPPLY SEQUENCE
programmable FIR filter with additional decimation settings. The The ADRV9008-1 requires a specific power-up sequence to
sample rate of each digital filter block is adjustable by changing avoid undesired power-up currents. In the optimal power-up
decimation factors to produce the desired output data rate. sequence, the VDDD1P3_DIG supply and the VDDA1P3_x supply
CLOCK INPUT (VDDA1P3_x includes all 1.3 V domains) power up together
The ADRV9008-1 requires a differential clock connected to the first. If these supplies cannot be powered up simultaneously, then
REF_CLK_IN_x pins. The frequency of the clock input must be the VDDD1P3_DIG supply must power up first. Power up the
between 10 MHz and 1000 MHz, and the frequency must have VDDA_3P3 supply, the VDDA1P8_x supply, and the
low phase noise because this signal generates the RF LO and VDDA1P3_SER supply after powering up the 1.3 V supplies. The
internal sampling clocks. VDD_INTERFACE supply can be powered up at any time. No
device damage occurs if this sequence is not followed, but failing to
SYNTHESIZERS follow this sequence may result in higher than expected power-up
RF PLL currents. Toggle the RESET signal after the power stabilizes, prior
The ADRV9008-1 contains a fractional-N PLL to generate the to configuration. The power-down sequence is not critical. If a
RF LO for the signal paths. The PLL incorporates an internal power-down sequence is followed, remove the VDDD1P3_DIG
VCO and loop filter, requiring no external components. The supply last to avoid any back biasing of the digital control lines.
LOs on multiple chips can be phase synchronized to support
active antenna systems and beam forming applications.
GPIO_x PINS enabled, the auxiliary ADC is free running. The SPI reads provide
The ADRV9008-1 provides nineteen 1.8 V to 2.5 V GPIO signals the last value latched at the ADC output. The auxiliary ADC can
that can be configured for numerous functions. When configured also be multiplexed to a built in, diode-based temperature sensor.
as outputs, certain pins can provide real-time signal information to Auxiliary DAC x
the BBP, allowing the BBP to determine receiver performance. A The ADRV9008-1 contains 10 identical auxiliary DACs that can
pointer register selects the information that is output to these pins. be used for bias or other system functionality. The auxiliary
Signals used for manual gain mode, calibration flags, state machine DACs are 10 bits, have an output voltage range of approximately
states, and various receiver parameters are among the outputs that 0.7 V to VDDA_3P3 − 0.3 V, and have a current drive of 10 mA.
can be monitored on these pins. Additionally, certain pins can be
configured as inputs and used for various functions, such as setting JESD204B DATA INTERFACE
the receiver gain in real time. The digital data interface for the ADRV9008-1 uses JEDEC
JESD204B Subclass 1. The serial interface operates at speeds of
Twelve 3.3 V GPIO_x pins are also included on the device.
up to 12.288 Gbps. The benefits of the JESD204B interface
These pins provide control signals to external components.
include a reduction in required board area for data interface
AUXILIARY CONVERTERS routing, resulting in smaller total system size. Four high speed
AUXADC_x serial lanes are provided for the receiver. The ADRV9008-1
The ADRV9008-1 contains an auxiliary ADC that is multiplexed to supports single-lane and dual-lane interfaces and supports fixed
four input pins (AUXADC_x). The auxiliary ADC is 12 bits with and floating point data formats for receiver.
an input voltage range of 0.05 V to VDDA_3P3 − 0.05 V. When
Table 6. Example Receiver Interface Rates (Other Output Rates, Bandwidths, and JESD204B Lanes Also Supported)
Single-Channel Operation Dual-Channel Operation
Output Rate JESD204B Lane Rate JESD204B Number JESD204B Lane Rate JESD204B Number
Bandwidth (MHz) (MSPS) (Mbps) of Lanes (Mbps) of Lanes
80 122.88 4915.2 1 9830.4 1
100 153.6 6144 1 12288 1
100 245.76 9830.4 1 9830.4 2
200 245.76 9830.4 1 9830.4 2
200 245.76 4915.2 2 4915.2 4
RECEIVE RECEIVE RECEIVE FIR

HALF-BAND HALF-BAND HALF-BAND FILTER DC DIGITAL
ADC ESTIMATION GAIN JESD204B
FILTER FILTER FILTER (DECIMATION
16830-310
3 2 1 1, 2, 4)
Figure 169. Receiver Datapath Filter Implementation
APPLICATIONS INFORMATION
PCB LAYOUT AND POWER SUPPLY 13 are crucial to maintaining the RF signal integrity and,
RECOMMENDATIONS ultimately, the ADRV9008-1 performance. Layer 3 and Layer 12
Overview are used to route power supply domains. To keep the RF section
of the ADRV9008-1 isolated from the fast transients of the digital
The ADRV9008-1 is a highly integrated, RF, agile receiver with
section, the JESD204B interface lines are routed on Layer 5 and
significant signal conditioning integrated on one chip. Due to Layer 10. These layers have impedance control set to a 100 Ω
the increased complexity of the device and its high pin count, differential. The remaining digital lines from ADRV9008-1 are
careful PCB layout is important to achieve optimal performance.
routed on Inner Layer 7 and Inner Layer 8. RF traces on the outer
This data sheet provides a checklist of issues to look for and
layers must be a controlled impedance for optimal performance
guidelines on how to optimize the PCB to mitigate performance
of the device. The inner layers in this board use 0.5 ounce
issues. The goal of this data sheet is to help achieve optimal
copper or 1 ounce copper. The outer layers use 1.5 ounce
performance of the ADRV9008-1 while reducing board layout
copper so that the RF traces are less prone to pealing. Ground
effort. This data sheet assumes that the reader is an experienced
planes on this board are full copper floods with no splits except
analog and RF engineer with an understanding of RF PCB layout
for vias, through-hole components, and isolation structures.
and RF transmission lines. This data sheet discusses the following
The ground planes must route entirely to the edge of the PCB
issues and provides guidelines for system designers to achieve
under the Surface-Mount Type A (SMA) connectors to
optimal performance of the ADRV9008-1: maintain signal launch integrity. Power planes can be pulled
• PCB material and stackup selection back from the board edge to decrease the risk of shorting from
• Fanout and trace space layout guidelines the board edge.
• Component placement and routing guidelines
• RF and JESD204B transmission line layout
• Isolation techniques used on the ADRV9008-1W/PCBZ
• Power management considerations
• Unused pin instructions
PCB MATERIAL AND STACKUP SELECTION

Figure 170 shows the PCB stackup used for the ADRV9008-
1W/PCBZ. Table 7 and Table 8 list the single-ended and
differential impedance for the stackup shown in Figure 170. The
dielectric material used on the top and the bottom layers is 8
mil Rogers 4350B. The remaining dielectric layers are FR4-370
HR. The board design uses the Rogers laminate for the top and
the bottom layers for the low loss tangent at high frequencies.
The ground planes under the Rogers laminate (Layer 2 and
Layer 13) are the reference planes for the transmission lines
routed on the outer surfaces. These layers are solid copper 16830-434
planes without any splits under the RF traces. Layer 2 and Layer Figure 170. ADRV9008-1W/PCBZ Trace Impedance and Stackup
Table 7. Evaluation Board Single-Ended Impedance and Stackup1
Single-
Board Designed Trace Finished Trace Ended
Copper Starting Finished Single-Ended Single-Ended Single-Ended Calculated Reference
Layer (%) Copper (oz.) Copper (oz.) Impedance (Inches) (Inches) Impedance (Ω) Layers
1 N/A 0.5 1.71 50 Ω ±10% 0.0155 0.0135 49.97 2
2 65 1 1 N/A N/A N/A N/A N/A
3 50 0.5 1 N/A N/A N/A N/A N/A
4 65 1 1 N/A N/A N/A N/A N/A
5 50 0.5 0.5 50 Ω ±10% 0.0045 0.0042 49.79 4, 6
6 65 1 1 N/A N/A N/A N/A N/A
7 50 0.5 0.5 50 Ω ±10% 0.0049 0.0039 50.05 6, 9
8 50 0.5 0.5 50 Ω ±10% 0.0049 0.0039 50.05 6, 9
9 65 1 1 N/A N/A N/A N/A N/A
10 50 0.5 1 50 Ω ±10% 0.0045 0.0039 49.88 9, 11
11 65 0.5 1 N/A N/A N/A N/A N/A
12 50 1 1 N/A N/A N/A N/A N/A
13 65 1 1 N/A N/A N/A N/A N/A
14 0.5 1.64 50 Ω ±10% 0.0155 0.0135 49.97 13
1
N/A means not applicable.
Table 8. Evaluation Board Differential Impedance and Stackup1

Gap Differential Gap Differential
Differential Designed for Designed Finished for Finished Calculated Differential
Layer Impedance Trace (Inches) Trace (Inches) Trace (Inches) Trace (Inches) Impedance (Ω) Reference Layers
1 100 Ω ± 10% 0.008 0.006 0.007 0.007 99.55 2
50 Ω ± 10% 0.0032 0.004 0.0304 0.0056 50.11 2
2 N/A1 N/A N/A N/A N/A N/A N/A
3 N/A N/A N/A N/A N/A N/A N/A
5 100 Ω ±10% 0.0036 0.0064 0.0034 0.0065 99.95 4, 6
7 100 Ω ±10% 0.0036 0.0064 0.0034 0.0066 100.51 6, 9
8 100 Ω ±10% 0.0038 0.0062 0.0034 0.0066 100.51 6, 9
10 100 Ω ±10% 0.0036 0.0064 0.003 0.007 100.80 9, 11
13 100 Ω ±10% 0.008 0.006 0.007 0.007 99.55 13
14 50 Ω ±10% 0.032 N/A 0.004 N/A 50.11 13
1
N/A means not applicable.
FANOUT AND TRACE SPACE GUIDELINES The JESD204B interface signals are routed on two signal layers
The ADRV9008-1 uses a 196-ball chip scale ball grid array that use impedance control (Layer 5 and Layer 10). The spacing
(CSP_BGA), 12 mm × 12 mm package. The pitch between the between the BGA pads is 17.5 mil. After the signal is on the inner
pins is 0.8 mm. This small pitch makes it impractical to route all layers, a 3.6 mil trace (50 Ω) connects the JESD204B signal to the
signals on a single layer. RF pins are placed on the outer edges field programmable gate array (FPGA) mezzanine card (FMC)
of the ADRV9008-1 package. The location of the pins helps route connector. The recommended BGA land pad size is 15 mil.
the critical signals without a fanout via. Each digital signal is Figure 171 shows the fanout scheme of the ADRV9008-1W/PCBZ.
routed from the BGA pad using a 4.5 mil trace. The trace is As mentioned before, the ADRV9008-1W/PCBZ uses a via in
connected to the BGA using a via in the pad structure. The signals the pad technique. This routing approach can be used for the
are buried in the inner layers of the board for routing to other parts ADRV9008-1 if there are no issues with manufacturing
of the system. capabilities.
4.5mil TRACE
AIR GAP = 17.5mil
JESD204B INTERFACE
TRACE WIDTH = 3.6mil
PAD SIZE = 15mil
VIA SIZE = 14mil
16830-435
Figure 171. Trace Fanout Scheme on the ADRV9008-1W/PCBZ (PCB Layer Top and Layer 5 Enabled)
COMPONENT PLACEMENT AND ROUTING Figure 170 shows the general directions in which each of the
GUIDELINES signals must be routed so that they can be properly isolated
from noisy signals.
The ADRV9008-1 receiver requires few external components to
function, but those that are used require careful placement and The receiver baluns and the matching circuits affect the overall
routing to optimize performance. This section provides a RF performance of the ADRV9008-1 receiver. Make every effort
checklist for properly placing and routing critical signals and to optimize the component selection and placement to avoid
components. performance degradation. The RF Routing Guidelines section
describes proper matching circuit placement and routing in
Signals with Highest Routing Priority
more detail. Refer to the RF Port Interface Information section
RF lines and JESD204B interface signals are the signals that are for more information.
most critical and must be routed with the highest priority.
To achieve the desired level of isolation between RF signal paths,
use the technique described in the Isolation Techniques Used on
the ADRV9008-1W/PCBZ section in customer designs.
VSSA VSSA VSSA VSSA RX2_IN+ RX2_IN– VSSA VSSA RX1_IN+ RX1_IN– VSSA VSSA VSSA VSSA

RX_RF VSSA VSSA VSSA VSSA VSSA LO_I/O– LO_I/O+ VSSA VSSA VSSA VSSA VSSA VSSA
VDDA1P3_
GPIO_3p3_0 GPIO_3p3_3 VDDA1P3_RX VSSA RF_VCO_LDO VCO_LDO RF_VCO RF_LO VSSA LDO VSSA VDDA_3P3 GPIO_3p3_9 RBIAS
VDDA1P1_
GPIO_3p3_1 GPIO_3p3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSA AUX_VCO VSSA VSSA GPIO_3p3_8 GPIO_3p3_10
AUX_SYNTH_
GPIO_3p3_2 GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSA OUT AUXADC_3 VDDA1P8_AN GPIO_3p3_7 GPIO_3p3_11
VSSA VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA

CLOCK_ VDDA1P3_
VSSA VSSA VSSA VSSA VSSA RF_SYNTH AUX_SYNTH VTUNE VSSA VSSA VSSA VSSA VSSA
SYNTH
DNC VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA DNC
GP_
DNC VSSA GPIO_18 RESET INTERRUPT TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA DNC
VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CS GPIO_14 GPIO_9 VSSA VSSA

VSSA VSSA SYNCIN1– SYNCIN1+ GPIO_6 GPIO_7 VSSD DIG DIG VSSD GPIO_15 GPIO_8 SER SER

CLOCK_VCO VSSA SYNCIN0– SYNCIN0+ RX1_ENABLE VSSD RX2_ENABLE VSSD VSSA GPIO_17 GPIO_16 INTERFACE SER SER
VDDA1P3_
VCO_LDO VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA SER SER SER SER SER SER VSSA

VTUNE VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+ SER SER VSSA SER SER SER SER
16830-437
Figure 172. RF Input/Output, REF_CLK_IN±, and JESD204B Signal Routing Guidelines
Figure 173 shows placement for ac coupling capacitors and a 100 Ω The JESD204B Trace Routing Recommendations section
termination resistor near the ADRV9008-1 REF_CLK_IN± pins. outlines recommendations for JESD204B interface routing.
Shield the traces with ground flooding that is surrounded with vias Provide appropriate isolation between interface differential
staggered along the edge of the trace pair. The trace pair creates pairs. The Isolation Between JESD204B Lines section provides
a shielded channel that shields the reference clock from any guidelines for optimizing isolation.
interference from other signals. Refer to the ADRV9008-1W/PCBZ The RF_EXT_LO_I/O− pin (B7) and RF_EXT_LO_I/O+ pin
layout and board support files included with the evaluation board (B8) on the ADRV9008-1 are internally dc biased. If an external
software for exact details. LO is used, connect the LO to the device via ac coupling capacitors.
Route the JESD204B interface at the beginning of the PCB
design and with the same priority as the RF signals.
AC COUPLING
CAPS
100ΩTERMINATION
RESISTOR
TO
BGA BALLS
16830-439
Figure 173. REF_CLK_IN± Routing Recommendation
Signals with Second Routing Priority When the recommendation is to use a trace to connect power to
Power supply quality has a direct impact on overall system a particular domain, ensure that this trace is surrounded by
performance. To achieve optimal performance, follow ground.
recommendations for ADRV9008-1 power supply routing. The Figure 174 shows an example of such traces routed on the
following recommendations outline how to route different ADRV9008-1W/PCBZ on Layer 12. Each trace is separated
power domains that can be connected together directly and to from any other signal by the ground plane and vias. Separating
the same supply, but are separated by a 0 Ω placeholder resistor the traces from other signals is essential to providing necessary
or ferrite bead. isolation between the ADRV9008-1 power domains.
16830-440
Figure 174. Layout Example of Power Supply Domains Routed with Ground Shielding (Layer 12 to Power)
Each power supply pin requires a 0.1 µF bypass capacitor near placed. The recommendation is to connect a ferrite bead between a
the pin at a minimum. Place the ground side of the bypass power plane and the ADRV9008-1 at a distance away from the
capacitor so that ground currents flow away from other power device. The ferrite bead and the reservoir capacitor provide stable
pins and the bypass capacitors. voltage to the ADRV9008-1 during operation by isolating the pin
For domains shown in Figure 175, like the domains powered or pins that the network is connected to from the power plane.
through a 0 Ω placeholder resistor or ferrite bead (FB), place the Then, shield this trace with ground and provide power to the
0 Ω placeholder resistors or ferrite beads further away from the power pins on the ADRV9008-1. Place a 100 nF capacitor near the
device. Space 0 Ω placeholder resistors or ferrite beads apart from power supply pin with the ground side of the bypass capacitor
each other to ensure the electric fields on the ferrite beads do not placed so that ground currents flow away from other power
influence each other. Figure 176 shows an example of how the pins and the bypass capacitors.
ferrite beads, reservoir capacitors, and decoupling capacitors are
TRACE THROUGH 0Ω RES. TO 1.3V ANALOG PLANE (AP) TRACE THROUGH 0.1Ω RESISTOR TO AP
MAINTAIN LOWEST POSSIBLE IMPEDANCE
TRACE THROUGH 0Ω RESISTOR TO AP
TRACE THROUGH
0Ω TO AP VDDA1P3_
RX_RF VSSA VSSA VSSA VSSA VSSA
RF_EXT_
LO_I/O–
RF_EXT_
LO_I/O+ VSSA VSSA VSSA VSSA VSSA VSSA
TRACE THROUGH VDDA1P3_

TRACE THROUGH FB
0Ω TO AP
GPIO_3p3_0 GPIO_3p3_3 VDDA1P3_RX VSSA RF_VCO_LDO VCO_LDO RF_VCO RF_LO VSSA LDO VSSA VDDA_3P3 GPIO_3p3_9 RBIAS
TO 3.3V PLANE
TRACE THROUGH
0Ω TO AP GPIO_3p3_1 GPIO_3p3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSA
VDDA1P1_
AUX_VCO VSSA VSSA GPIO_3p3_8 GPIO_3p3_10
TRACE THROUGH
0Ω TO 1.8V PLANE AUX_SYNTH_ TRACE THROUGH 0Ω
GPIO_3p3_2 GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSA OUT AUXADC_3 VDDA1P8_AN GPIO_3p3_7 GPIO_3p3_11 TO 1.8V PLANE
TRACE THROUGH
1Ω RESISTOR TO AP VSSA VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA
TRACE THROUGH TRACE THROUGH 0Ω

VDDA1P3_
0Ω TO AP
VDDA1P3_
VSSA VSSA VSSA VSSA CLOCK_ VSSA RF_SYNTH
VDDA1P3_
AUX_SYNTH
RF_SYNTH_
VTUNE VSSA VSSA VSSA VSSA VSSA
TO PLANE
SYNTH
DNC VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA DNC
GP_
WIDE TRACE TO
1.3V DIGITAL SUPPLY
HIGH CURRENT
TRACE THROUGH FB
TO INTERFACE SUPPLY VDDA1P1_
CLOCK_VCO VSSA SYNCIN0– SYNCIN0+ RX1_ENABLE VSSD RX2_ENABLE VSSD VSSA GPIO_17 GPIO_16
VDD_
INTERFACE
VDDA1P3_
SER
VDDA1P3_
SER TRACE THROUGH
FB TO 1.3V
JESD204B SUPPLY
VDDA1P3_
TRACE THROUGH
0Ω TO AP
16830-441
Figure 175. Power Supply Domains Interconnection Guidelines
0Ω RESISTOR
PLACEHOLDERS
FOR FERRITE BEADS
RESERVOIR
CAPACITORS
DUT
1µ + 100nF bypass
CAPS ORIENTED SUCH
THAT CURRENTS FLOW
AWAY FROM OTHER
POWER PINS
0Ω RESISTOR
PLACEHOLDERS
16830-444
FOR FERRITE BEADS
Figure 176. Placement Example of 0 Ω Resistor Placeholders for Ferrite Beads, Reservoir and Bypass Capacitors on the ADRV9008-1W/PCBZ (Layer 12 to Power and
Bottom)
Signals with Lowest Routing Priority 4. Pull the RESET pin (J4) high with a 10 kΩ resistor to
As a last step while designing the PCB layout, route the signals VDD_INTERFACE for normal operation. To reset the
shown in Figure 177. The following list outlines the device, drive the RESET pin low.
recommended order of signal routing:
When routing analog signals such as GPIO_3p3_x or AUXADC_x,
1. Use ceramic 1 µF bypass capacitors at the VDDA1P1_ it is recommended to route the signals away from the digital
RF_VCO, VDDA1P1_AUX_VCO, and VDDA1P1_CLOCK_ section (Row H through Row P). Do not cross the analog section of
VCO pins. Place these pins as close as possible to the the ADRV9008-1, highlighted by a red dotted line in Figure 177, by
ADRV9008-1 device with the ground side of the bypass any digital signal routing.
capacitor placed so that ground currents flow away from
When routing digital signals from Row H and below, it is
other power pins and the bypass capacitors, if possible.
important to route the signals away from the analog section
2. Connect a 14.3 kΩ resistor to the RBIAS pin (C14). This
(Row A through Row G). Do not cross the analog section of the
resistor must have a 1% tolerance.
ADRV9008-1, highlighted by a red dotted line in Figure 177, by
3. Pull the TEST pin (J6) to ground for normal operation. any digital signal routing.
The device supports JTAG boundary scan, and this pin is
used to access that function. Refer to the JTAG Boundary
Scan section for JTAG boundary scan information.
1µF CAPACITOR 1µF CAPACITOR

RX_RF VSSA VSSA VSSA VSSA VSSA LO_I/O– LO_I/O+ VSSA VSSA VSSA VSSA VSSA VSSA
VDDA1P3_
GPIO_3p3_0 GPIO_3p3_3 VDDA1P3_RX VSSA RF_VCO_LDO VCO_LDO RF_VCO RF_LO VSSA LDO VSSA VDDA_3P3 GPIO_3p3_9 RBIAS 14.3kΩ RESISTOR
VDDA1P1_
GPIO_3p3_1 GPIO_3p3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSA AUX_VCO VSSA VSSA GPIO_3p3_8 GPIO_3p3_10
AUX_SYNTH_
GPIO_3p3_2 GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSA OUT AUXADC_3 VDDA1P8_AN GPIO_3p3_7 GPIO_3p3_11
VSSA VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA

CLOCK_ VDDA1P3_
VSSA VSSA VSSA VSSA VSSA RF_SYNTH VTUNE VSSA VSSA VSSA VSSA VSSA
SYNTH AUX_SYNTH
ALL DIGITAL
GPIO SIGNALS
DNC VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA DNC ROUTED BELOW
THE RED LINE
GP_


1µF CAPACITOR CLOCK_VCO VSSA SYNCIN0– SYNCIN0+ RX1_ENABLE VSSD RX2_ENABLE VSSD VSSA GPIO_17 GPIO_16 INTERFACE SER SER
VDDA1P3_

16830-445
Figure 177. AUXADC_x, Analog, and Digital GPIO Signals Routing Guidelines
RF AND JESD204B TRANSMISSION LINE LAYOUT
RF Routing Guidelines
The ADRV9008-1W/PCBZ uses microstrip type lines for
receiver traces. In general, Analog Devices does not
recommend using vias to route RF traces unless a direct line
route is not possible. Differential lines from the balun to the
receiver pins must be as short as possible. Keep the length of the
single-ended transmission line short to minimize the effects of
parasitic coupling. It is important to note that these traces are
the most critical when optimizing performance and are, therefore,
routed before any other routing. These traces have the highest
priority if trade-offs are needed.
Figure 178 shows pi matching networks on the single-ended
side of the baluns. The receiver front end is dc biased internally.
Therefore, the differential side of the balun is ac-coupled. The
system designer can optimize the RF performance with a proper
16830-448
selection of the balun, matching components, and ac coupling
capacitors. The external LO traces and the REF_CLK_IN±
Figure 178. Pi Network Matching Components Available on Different RF Nets
traces may also require matching components to ensure optimal
performance.
All the RF signals mentioned previously must have a solid ground
reference under each trace. Do not run any of the critical traces
over a section of the reference plane that is discontinuous. The
ground flood on the reference layer must extend all the way to
the edge of the board. This flood length ensures signal integrity
for the SMA launch when an edge launch connector is used.
Refer to the RF Port Interface Information section for more
information on RF matching recommendations for the
ADRV9008-1.
JESD204B Trace Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission
The ADRV9008-1 receiver uses the JESD204B, high speed serial Lines
interface. To ensure optimal performance of this interface, keep the Stripline trasmission lines have less signal loss and emit less
differential traces as short as possible by placing the ADRV9008-1 electromagnetic interference than microstrip trasmission lines.
as close as possible to the FPGA or BBP, and route the traces However, stripline trasmission lines require the use of vias that
directly between the devices. Use a PCB material with a low add line inductance, increasing the difficulty of controlling the
dielectric constant (< 4) to minimize loss. For distances greater impedance.
than 6 inches, use a premium PCB material, such as RO4350B
Microstrip trasmission lines are easier to implement if the
or RO4003C.
component placement and density allow routing on the top
Routing Recommendations layer. Microstrip trasmission lines make controlling the
Route the differential pairs on a single plane using a solid impedance easier.
ground plane as a reference on the layers above and/or below If the top layer of the PCB is used by other circuits or signals,
these traces. or if the advantages of stripline are more desirable over the
All JESD204B lane traces must be impedance controlled to advantages of microstrip, follow these recommendations:
achieve 50 Ω to ground. It is recommended that the differential • Minimize the number of vias.
pair be coplanar and loosely coupled. An example of a typical • Use blind vias where possible to eliminate via stub effects,
configuration is 5 mil trace width and 15 mil edge to edge and use micro vias to minimize via inductance.
spacing, with the trace width maximized as shown in Figure 179. • When using standard vias, use a maximum via length to
Match trace widths with pin and ball widths as closely as minimize the stub size. For example, on an 8-layer board,
possible while maintaining impedance control. If possible, use use Layer 7 for the stripline pair.
1 oz. copper trace widths of at least 8 mil (200 µm). The • Place a pair of ground vias near each via pair to minimize
coupling capacitor pad size must match JESD204B lane trace the impedance discontinuity.
widths as closely as possible. If trace width does not match pad
Route the JESD204B lines on the top side of the board as a
size, use a smooth transition between different widths.
differential 100 Ω pair (microstrip). For the ADRV9008-
The pad area for all connector and passive component choices 1W/PCBZ, the JESD204B differential signals are routed on
must be minimized due to a capacitive plate effect that leads to inner layers of the board (Layer 5 and Layer 10) as differential
problems with signal integrity. 100 Ω pairs (stripline). To minimize potential coupling, these
Reference planes for impedance controlled signals must not be signals are placed on an inner layer using a via embedded in the
segmented or broken for the entire length of a trace. component footprint pad where the ball connects to the PCB.
The ac coupling capacitors (100 nF) on these signals are placed
The REF_CLK_IN± signal trace and the SYSREF signal trace
near the connector and away from the chip to minimize
are impedance controlled for character impedance (ZO) = 50 Ω.
coupling. The JESD204B interface can operate at frequencies of
up to 12 GHz. Ensure that signal integrity from the chip to the
connector is maintained.
DIFF A DIFF B DIFF A DIFF B

16830-452
TIGHTLY COUPLED LOOSELY COUPLED

DIFFERENTIAL LINES DIFFERENTIAL LINES
Figure 179. Routing JESD204B, Diff A and Diff B Correspond to Differential Positive Signals or Negative Signals (One Differential Pair)
16830-453
Figure 180. Isolation Structures on the ADRV9008-1W-PCBZ
ISOLATION TECHNIQUES USED ON THE receivers. Spacing between square apertures must be no more
ADRV9008-1W/PCBZ than 1/10 of a wavelength. Calculate the wavelength using
Isolation Goals Equation 1:
Significant isolation challenges were overcome in designing the 300

Wavelength (m) = (1)
ADRV9008-1W/PCBZ. The following isolation requirement is Frequency (MHz) × ER
used to accurately evaluate the ADRV9008-1 receiver
where ER is the dielectric constant of the isolator material. For
performance: receiver to receiver, 65 dB out to 6 GHz.
RO4003C material, microstrip structure (+ air) ER = 2.8. For FR4-
To meet these isolation goals with significant margin, isolation 370HR material, stripline structure ER = 4.1.
structures are introduced.
For example, if the maximum RF signal frequency is 6 GHz,
Figure 180 shows the isolation structures used on the ADRV9008- and ER = 2.8 for RO4003C material, microstrip structure (+ air),
1W/PCBZ. These structures consist of a combination of slots and the minimum wavelength is approximately 29.8 mm.
square apertures. These structures are present on every copper
To follow the 1/10 wavelength spacing rule, square aperture
layer of the PCB stack. The advantage of using square apertures is
spacing must be 2.98 mm or less.
that signals can be routed between the openings without affecting
the isolation benefits of the array of apertures. When using these Isolation Between JESD204B Lines
isolation structures, make sure to place ground vias around the The JESD204B interface uses eight line pairs that can operate at
slots and apertures. speeds of up to 12 GHz. When configuring the PCB layout, ensure
Figure 181 outlines the methodology used on the ADRV9008- that these lines are routed according to the rules outlined in the
1W/PCBZ. When using slots, ground vias must be placed at the JESD204B Trace Routing Recommendations section. In addition,
ends of the slots and along the sides of the slots. When using use isolation techniques to prevent crosstalk between different
square apertures, at least one single ground via must be placed JESD204B lane pairs.
adjacent to each square. These vias must be through-hole vias Figure 182 shows a technique used on the ADRV9008-1W/PCBZ
from the top to the bottom layer. The function of these vias is to that involves via fencing. Placing ground vias around each
steer return current to the ground planes near the apertures. JESD204B pair provides isolation and decreases crosstalk. The
For accurate slot spacing and square apertures layout, use spacing between vias is 1.2 mm.
simulation software when designing a PCB for the ADRV9008-1
16830-454
Figure 181. Current Steering Vias Placed Next to Isolation Structures
16830-455
1.24mm
Figure 182. Via Fencing Around JESD204B Lines, PCB Layer 10
Figure 182 shows the rule provided in Equation 1. JESD204B lines The ADRV9008-1 is a highly integrated receiver device.
are routed on Layer 5 and Layer 10 so that the lines use stripline External impedance matching networks are required on the
structures. The dielectric material used in the inner layers of the receiver port to achieve performance levels indicated in the
ADRV9008-1W/PCBZ PCB is FR4-370HR. Specifications section.
For accurate spacing of the JESD204B fencing vias, use layout Analog Devices recommends the use of simulation tools in the
simulation software. Input the following data into Equation 1 to design and optimization of impedance matching networks. To
calculate the wavelength and square aperture spacing: achieve the closest match between computer simulated results and
measured results, accurate models of the board environment, SMD
• Maximum JESD204B signal frequency is approximately
components (including baluns and filters), and ADRV9008-1 port
12 GHz.
impedances are required.
• For FR4-370HR material, stripline structure, ER = 4.1, the
minimum wavelength is approximately 12.4 mm. RF Port Impedance Data
To follow the 1/10 wavelength spacing rule, spacing between vias This section provides the port impedance data for the receivers
must be 1.24 mm or less. The minimum spacing recommendation in the ADRV9008-1 integrated receiver. Note the following:
according to transmission line theory is 1/4 wavelength. • ZO is defined as 50 Ω.
RF PORT INTERFACE INFORMATION • The ADRV9008-1 ball pads are the reference plane for
this data.
This section details the RF receiver interfaces for optimal device
• Single-ended mode port impedance data is not available.
performance. This section also includes data for the anticipated
However, a rough assessment is possible by taking the
ADRV9008-1 RF port impedance values and examples of
differential mode port impedance data and dividing both
impedance matching networks used in the evaluation platform.
the real and imaginary components by 2.
This section also provides information on board layout techniques
and balun selection guidelines.
1.0
0.5 2.0
m15
FREQUENCY = 100MHz
S(1,1) = 0.390/–1.819
IMPEDANCE = 113.933 – j3.331 m20
FREQUENCY = 3GHz
m16 0.2 5.0 S(1,1) = 0.267/–64.650
FREQUENCY = 300MHz IMPEDANCE = 55.102 – j28.685
S(1,1) = 0.390/–5.495
IMPEDANCE = 112.803 – j9.931 m21
M23 FREQUENCY = 4GHz
m17 S(1,1) = 0.186/–104.336
M22 M15
S(1,1)
FREQUENCY = 500MHz IMPEDANCE = 42.821 – j16.026
S(1,1) = 0.388/–9.198 0 M16
IMPEDANCE = 110.398 – j16.107 M17 m22
M21 FREQUENCY = 5GHz
m18 M19 M18 S(1,1) = 0.164/–173.106
FREQUENCY = 1GHz IMPEDANCE = 35.977 – j1.455
S(1,1) = 0.377–18.643 M20
IMPEDANCE = 100.377 – j28.250 m23
–0.2 –5.0 FREQUENCY = 6GHz
m19 S(1,1) = 0.266/130.063
FREQUENCY = 2GHz IMPEDANCE = 32.890 + j14.399
S(1,1) = 0.336/–39.123
IMPEDANCE = 74.966 – j35.800
–0.5 –2.0
–1.0
16830-459
FREQUENCY (0Hz TO 6GHz)
Figure 183. Receiver 1 and Receiver 2 SEDZ and Parallel Equivalent Differential Impedance (PEDZ) Data
1.0
0.5 2.0
m1 350 900
FREQUENCY = 100MHz R_PEDZ
S(1,1) = 0.018/–149.643 L_OR_C_PE 800
IMPEDANCE = 48.491 – j0.866 M5 M6 300 X_STATUS
m2 0.2 5.0 m7 700
FREQUENCY = 750MHz FREQUENCY = 5GHz
S(1,1) = 0.074/–123.043 250 L_OR_C_PE = 1.336
IMPEDANCE = 45.753 – j5.744 m8 600
m3 FREQUENCY = 5GHz
L_OR_C_PE
M4
X_STATUS
FREQUENCY = 1.5GHz 200 R_PEDZ = 31.172
R_PEDZ
0 M1 500
S(1,1) = 0.147/–138.745 M2 m9
IMPEDANCE = 39.362 – j7.804 FREQUENCY = 5GHz
m4 M3 X_STATUS = 1 400
150
FREQUENCY = 3GHz
S(1,1) = 0.292/–175.424 300
IMPEDANCE = 27.426 – j1.397
m5 –0.2 –5.0 100
FREQUENCY = 6GHz 200
S(1,1) = 0.538/123.271
IMPEDANCE = 18.885 – j23.935 50
100
m6
FREQUENCY = 12GHz 0
S(1,1) = 0.757/46.679 –0.5 –2.0 0
IMPEDANCE = 40.002 – j103.036 0 2 4 6 8 10 12
FREQUENCY (GHz)
–1.0
16830-461
FREQUENCY (100MHz TO 12GHz)
Figure 184. RF_EXT_LO_I/O± SEDZ and PEDZ Data
1.0
0.5 2.0
m1 13E+5 1.0
FREQUENCY = 100MHz R_PEDZ
S(1,1) = 0.999/–1.396 1.2E+5 L_OR_C_PE 0.9
IMPEDANCE = 159.977 – j4.099E3 X_STATUS
m2 0.2 5.0 m7 0.8
FREQUENCY = 250MHz 1.1E+5
FREQUENCY = 1GHz
S(1,1) = 0.999/–3.480 L_OR_C_PE = 0.389 0.7
IMPEDANCE = 30.567 – j1.645E3 1.0E+5 m8
m3 FREQUENCY = 1GHz
L_OR_C_PE
0.6
X_STATUS
FREQUENCY = 500MHz M1 R_PEDZ = 4.761E4
R_PEDZ
S(1,1) = 0.999/–6.952 0 9.0E+4
M2 m9
IMPEDANCE = 9.723 – j823.070 FREQUENCY = 1GHz 0.5
M3
m4 M4 8.0E+4 X_STATUS = 0
FREQUENCY = 750MHz M5 0.4
S(1,1) = 0.998/–10.431 7.0E+4
IMPEDANCE = 5.273 – j547.733 0.3
m5 –0.2 –5.0
FREQUENCY = 1GHz 6.0E+4 0.2
S(1,1) = 0.999/–13.925
IMPEDANCE = 3.521 – j409.400 5.0E+4 0.1
–0.5 –2.0 4.0E+4 0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
–1.0
16830-462
FREQUENCY (0.000Hz TO 1.100GHz)
Figure 185. REF_CLK_IN± SEDZ and PEDZ Data—On Average, the Real Part of Parallel Equivalent Differential Impedance (RP) = ~70 kΩ
Advanced Design System (ADS) Setup Using the The mechanics of setting up a simulation for impedance
DataAccessComponent and SEDZ File measurement and impedance matching is as follows:
Analog Devices supplies the port impedance as an .s1p file that 1. The data access component block reads the RF port .s1p
can be downloaded from the ADRV9008-1 product page. This file. This file is the device RF port reflection coefficient.
format allows simple interfacing to the ADS by using the data 2. The two equations convert the RF port reflection coefficient
access component. In Figure 186, Term1 is the single-ended to a complex impedance. The result is the RX_SEDZ
input or output, and Term2 is the differential input or output variable.
RF port on the ADRV9008-1. The pi on the single-ended side 3. The RF port calculated complex impedance (RX_SEDZ) is
and the differential pi configuration on the differential side used to define the Term2 impedance.
allow maximum flexibility in designing matching circuits. The 4. Term2 is used in a differential mode, and Term1 is used in
pi configuration is suggested for all design layouts because the a single-ended mode.
pi configuration can step the impedance up or down as needed
with appropriate component population. Setting up the simulation this way allows one to measure the
input reflection (S11), output reflection (S22), and through
reflection (S21) of the three port system without complex math
operations within the display page.
For the highest accuracy, the electromagnetic momentum (EM)
modeling result of the PCB artwork and S parameters (S11, S22,
and S21) of the matching components and balun must be used in
the simulations.
16830-463
Figure 186 Simulation Setup in ADS with SEDZ .s1p Files and DataAccessComponent
General Receiver Path Interface CC
RX1_IN–
RECEIVER
The ADRV9008-1 receivers can support up to a 200 MHz INPUT
STAGE
bandwidth. CC (MIXER OR LNA)
16830-471
RX1_IN+
The ADRV9008-1 receivers support a wide range of operation
frequencies. In the case of the receiver channels, the differential Figure 188. Differential Receiver Interface Using a Transmission Line Balun
signals interface to an integrated mixer. The mixer input pins have
a dc bias of approximately 0.7 V and may need to be ac-coupled, Impedance Matching Network Examples
depending on the common-mode voltage level of the external Impedance matching networks are required to achieve the
circuit. ADRV9008-1 data sheet performance levels. This section provides
a description of the matching network topology and components
Important considerations for the receiver port interface are as
used on the ADRV9008-1W/PCBZ.
follows:
Device models, board models, and balun and SMD component
• The device to be interfaced (filter, balun, transmit/receive
models are required to build an accurate system level simulation.
(T/R) switch, external low noise amplifier (LNA), external
The board layout model can be obtained from an EM simulator.
PA, and so on).
The balun and SMD component models can be obtained from
• The receiver maximum safe input power is 23 dBm (peak).
the device vendors or built locally. Contact Analog Devices
• The receiver optimum dc bias voltage is 0.7 V bias to applications engineering for ADRV9008-1 modeling details.
ground.
The impedance matching network provided in this section is
• The board design (reference planes, transmission lines,
not evaluated in terms of mean time to failure (MTTF) in high
impedance matching, and so on).
volume production. Consult with component vendors for long-
Figure 187 and Figure 188 show possible differential receiver term reliability concerns. Consult with balun vendors to determine
port interface circuits. The options in Figure 187 and Figure 188 appropriate conditions for dc biasing.
are valid for all receiver inputs operating in differential mode,
Figure 190 shows three elements in parallel marked do not
though only the Receiver 1 signal names are indicated. Impedance
install (DNI). However, only one set of SMD component pads
matching may be necessary to obtain data sheet performance levels.
is placed on the board. For example, the R202, L202, and C202
Given wide RF bandwidth applications, SMD balun devices components only have one set of SMD pads for one SMD
function well. Decent loss and differential balance are available component. Figure 190 shows that, in a generic port impedance
in a relatively small (0603, 0805) package. matching network, the shunt or series elements may be a resistor,
RX1_IN– inductor, or capacitor.
RECEIVER
INPUT
STAGE
(MIXER OR LNA)
16830-470
RX1_IN+
Figure 187. Differential Receiver Interface Using a Transformer
Rx TOPOLOGY
3
1 1 BAL_OUT1 Rx +
Rx IN UNBAL_IN
4
BAL_OUT2
2 3 4 5
NC_6 GND GND_DC_FEED_RFGND
6 5 2
Rx –
R328
0Ω
16830-472
Figure 189. Impedance Matching Topology
RX1 T201
J201 C248 TCM1-83X+
1 R202 RX1_UNBAL 3 5 RX1_BAL+ R205 RX1_IN+
0Ω 18pF 2 4 0Ω
2 3 4 5
C201 C203
C204 C207
DNI DNI
DNI DNI
NC
AGND 6 1
AGND R206 RX1_IN-
AGND
C240 C241 RX1_BAL– 0Ω
10pF 27pF
DNI
AGND
RX2 T202
J202 RX2_UNBAL C249 TCM1-83X+
1 R209 3 5 RX2_BAL+ R212 RX2_IN+
0Ω 18pF 2 4 0Ω
2 3 4 5 C208 C210
DNI DNI C214
C211
DNI
DNI
NC
AGND 6 1
AGND AGND R213 RX2_IN-
C242 C243 RX2_BAL– 0Ω
DNI 27pF
16830-400
AGND
Figure 190. Receiver 1 (RX1) and Receiver 2 (RX2) Generic Matching Network Topology
Table 9 and shows the selected balun and component values The RF matching used in the ADRV9008-1W/PCBZ allows the
used for three matching network sets. Refer to the ADRV9008-1 ADRV9008-1 to operate across the entire chip frequency range
schematics for a wideband matching example that operates across with slightly reduced performance.
the entire device frequency range with somewhat reduced
performance.
Table 9. Receiver 1 and Receiver 2 Evaluation Board Matching Components for Frequency Band 75 MHz to 6000 MHz
Component Value
C201, C208 Do not install (DNI)
R202, R209 0Ω
C203, C210 DNI
C248, C249 18 pF
C204, C211 DNI
R205/R206, R212/R213 0Ω
C207, C214 DNI
T201, T202 Mini circuits TMC1-83X+
OUTLINE DIMENSIONS
12.10
12.00 SQ A1 BALL
A1 BALL 11.90 PAD CORNER
CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
PIN A1
INDICATOR 10.40 SQ F
7.755 REF G
H
J
0.80 K
L
M
N
P
TOP VIEW BOTTOM VIEW
0.80 REF
8.090 REF
DETAIL A
1.27 0.91
1.18 0.84
1.09 DETAIL A 0.77
0.39
0.34
0.29
0.44 REF
SEATING 0.50 COPLANARITY

PLANE 0.45 0.12
0.40
BALL DIAMETER
03-02-2015-A
PKG-004723
COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.
Figure 191. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-196-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range2 Package Description Package Option
ADRV9008BBCZ-1 −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-13
ADRV9008BBCZ-1REEL −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-13
ADRV9008-1W/PCBZ Pb-Free Evaluation Board, 75 MHz to 6000 MHz
1
Z = RoHS Compliant Part.
2
See the Thermal Management section.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D16830-0-9/18(0)

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Integrated Dual RF Receivers

Data Sheet ADRV9008-1

Rev. 0 Document Feedback

FUNCTIONAL BLOCK DIAGRAM

GPIOs, AUXILIARY ADCs, REF_CLK_IN +

CURRENT AND POWER CONSUMPTION SPECIFICATIONS

tH = –1.5ns CLK DELAY = 2ns t’H = +0.5ns

Figure 2. SYSREF_IN± Setup and Hold Timing

CUSTOMER CASE (HEAT SINK)

CUSTOMER THERMAL FILLER

Figure 4. Typical Thermal Management Solution

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDDA1P3_ RF_EXT_ RF_EXT_

VDDA1P3_ VDDA1P3_ RF_SYNTH_

VDDD1P3_ VDDD1P3_ VDDA1P3_ VDDA1P3_

VDDA1P1_ VDD_ VDDA1P3_ VDDA1P3_

AUX_SYNTH_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

RECEIVER NOISE FIGURE (dB)

RECEIVER NOISE FIGURE (dB)

RECEIVER NOISE FIGURE (dB)

RECEIVER IIP2 (dBm)

RECEIVER IIP2 SUM AND DIFFERENCE

ACROSS BANDWIDTH (dBm)

RECEIVER IIP3 (dBm)

75 Rx1 (SUM) = +25°C

70 Rx1 (SUM) = –40°C

RECEIVER IIP3 (dBm)

RECEIVER IIP3 (dBm)

20 Rx1 = +110°C 10 Rx1 = +110°C

RECEIVER IMAGE (dBc)

–40 RECEIVER IMAGE (dBc)

–25 –20 –15 –10 –5 0 5 10 15 20 25 0 5 10 15 20 25 30

RECEIVER GAIN STEP ERROR (dB)

RECEIVER GAIN STEP ERROR (dB)

22 +25°C 0.3 +25°C

75 125 175 225 275 320 375 425 475 525 0 3 6 9 12 15 18 21 24 27 30

RECEIVER DC OFFSET (dBFS)

RECEIVER HD2 LEFT (dBc)

–80 –40°C –60 ATTN = 0 +25°C

0 5 10 15 20 25 30 –30 –20 –10 0 10 20 30

RECEIVER HD3, LEFT AND RIGHT (dBc)

–60 ATTN = 0 +25°C –40°C Rx2 (RIGHT) –40°C Rx2 (LEFT)

–30 +25°C Rx2 (RIGHT) +25°C Rx2 (LEFT) +110°C

–25 –20 –15 –10 –5 5 10 15 20 25

–30 +25°C Rx2 (RIGHT) +25°C Rx2 (LEFT) +110°C

–25 –20 –15 –10 –5 5 10 15 20 25

PHASE NOISE (dBc/Hz)

10 –90 10kHz = –109.36dBc/Hz

100 1k 10k 100k 1M 10M 100M

RECEIVER NOISE FIGURE (dBc)

RECEIVER NOISE FIGURE (dBc)

RECEIVER ATTENUATION (dB)

RECEIVER LO FREQUENCY (MHz)

RECEIVER LO FREQUENCY (MHz)

RECEIVER NOISE FIGURE (dB)

ACROSS BANDWIDTH (dBm)

70 RX1 +25°C MAX OF IIP2_SUM_CF

RECEIVER IIP2 (dBm)

SUM AND DIFFERENCE ACROSS BANDWIDTH (dBm)

Rx2 +25°C MAX OF IIP2_SUM_CF