Professional Documents
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A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
1 TVPGTO26 Pull Up Network
(Tools / Tanner EDA)
A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
2 TVPGTO50 Pull Up Network
(Tools / Cadence EDA)
A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
3 TVMATO642 Pull Up Network
(Tools / Cadence EDA)
A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
4 TVMATO643 Pull Up Network
(Tools / Tanner EDA)
A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
5 TVREBE19_25 Pull Up Network
(Back End Domains / Low Power VLSI)
A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
6 TVREBE19_26 Pull Up Network
(Back End Domains / Transistor Logic)
Low Leakage Clock Tree with Dual-Threshold- Voltage Split Input–Output Repeaters
21 TVPGTO53
(Tools / Tanner EDA)
Low Leakage Clock Tree with Dual-Threshold- Voltage Split Input–Output Repeaters
22 TVMATO519
(Tools / Cadence EDA)
Low Leakage Clock Tree with Dual-Threshold- Voltage Split Input–Output Repeaters
23 TVMATO520
(Tools / Tanner EDA)
Low Leakage Clock Tree with Dual-Threshold- Voltage Split Input–Output Repeaters
24 TVREBE19_15
(Back End Domains / Transistor Logic)
Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
31 TVPGTO55
(Tools / Tanner EDA)
Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
32 TVPGTO221
(Tools / Cadence EDA)
Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
33 TVMATO203
(Tools / Cadence EDA)
Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
34 TVMATO204
(Tools / Tanner EDA)
Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
35 TVPGBE92
(Back End Domains / Transistor Logic)
VLSI-Standard Titles
Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
36 TVMABE91
(Back End Domains / Transistor Logic)
A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
37 TVPGTO56
(Tools / Tanner EDA)
A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
38 TVPGTO343
(Tools / Cadence EDA)
A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
39 TVMATO408
(Tools / Cadence EDA)
A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
40 TVMATO409
(Tools / Tanner EDA)
A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
41 TVPGBE82
(Back End Domains / Transistor Logic)
A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
42 TVMABE81
(Back End Domains / Transistor Logic)
A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
49 TVPGTO58
(Tools / Tanner EDA)
A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
50 TVPGTO235
(Tools / Cadence EDA)
A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
51 TVMATO217
(Tools / Cadence EDA)
A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
52 TVMATO218
(Tools / Tanner EDA)
A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
53 TVMABE88
(Back End Domains / Transistor Logic)
A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
54 TVPGBE88
(Back End Domains / Transistor Logic)
55 TVPGTO27 A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
VLSI-Standard Titles
in 130-nm CMOS
(Tools / Tanner EDA)
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
56 TVPGTO156 in 130-nm CMOS
(Tools / Cadence EDA)
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
57 TVMATO122 in 130-nm CMOS
(Tools / Cadence EDA)
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
58 TVMATO123 in 130-nm CMOS
(Tools / Tanner EDA)
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
59 TVPGBE95 in 130-nm CMOS
(Back End Domains / Low Power VLSI)
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
60 TVMABE95 in 130-nm CMOS
(Back End Domains / Low Power VLSI)