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Published in IET Power Electronics
Received on 19th May 2011
Revised on 12th August 2011
doi: 10.1049/iet-pel.2011.0189

ISSN 1755-4535

Common-mode voltage reduction in a motor drive

system with a power factor correction
J. Adabi1 A.A. Boora1 F. Zare1 A. Nami1 A. Ghosh1 F. Blaabjerg2
1
School of Electrical Engineering, Queensland University of Technology, GPO Box 2434, Brisbane, Australia
2
Institute of Energy Technology, Aalborg University, 9220 Aalborg East, Aalborg, Denmark
E-mail: j.adabi@nit.ac.ir

Abstract: Common-mode voltage generated by a power converter in combination with parasitic capacitive couplings is a
potential source of shaft voltage in an AC motor drive system. In this study, a three-phase motor drive system supplied with a
single-phase AC– DC diode rectifier is investigated in order to reduce shaft voltage in a three-phase AC motor drive system.
In this topology, the AC – DC diode rectifier influences the common-mode voltage generated by the inverter because the
placement of the neutral point is changing in different rectifier circuit states. A pulse width modulation technique is presented
by a proper placement of the zero vectors to reduce the common-mode voltage level, which leads to a cost-effective shaft
voltage reduction technique without load current distortion, while keeping the switching frequency constant. Analysis,
simulations and experimental implementation have been presented to investigate the proposed method.

1 Introduction common-mode voltage regardless of the motor impedance

Adjustable speed drive (ASD) systems are largely used in a
wide range of modern systems, from household appliances
to automated industry applications. The concept in the ASD
systems is the use of a power electronics module to convert
a constant frequency (50 or 60 Hz) AC voltage source to an
AC variable frequency waveform to achieve an adjustable
speed [1 – 2]. Regarding the growing requirements of speed
control, pulse width modulated (PWM) inverters are used in
ASD systems. The development of PWM-based drive
systems increased the efficiency, performance, and
controllability in AC motor applications, low acoustic noise
and more efficient power conversion. However, as the
switching speed of the power switches is increased to allow
higher carrier frequencies, new concerns arose because of
the interface of power converters and AC motor
characteristics, which was previously seen only in wave
transmission devices such as antenna and broadcast signal
equipments. The effects of the high-frequency voltage
components introduced by the PWM technique are usually
neglected when the electromechanical performance of the
motor is analysed. Many small capacitive couplings exist in
the motor drive systems that may be neglected in low-
frequency analysis, but the conditions are completely
different in high frequencies [3 – 6].
As a consequence of PWM patterns in three-phase inverter,
a voltage will be generated between a neutral point and the
ground, which is called common-mode voltage. This
voltage acts as a source for many unwanted problems in
motor drives such as shaft voltage and bearing currents
owing to the existence of parasitic capacitances in the
motor. It will be shown that the switching state creates the
[7, 8]. An LC filter can be used to eliminate the low-order
harmonics and remove the PWM signal from the pulse
shape generated by an inverter and the common-mode
voltage will therefore be eliminated. The main drawback of
using the filter is its bulky size especially in large motor
drive systems. Then, a proper PWM technique is the best
possible solution to reduce or eliminate the common-mode
voltage. Assuming no parasitic coupling, an induction
motor will only experience differential mode voltages and
will behave as an ordinary three-phase sinusoidal AC
supply [9, 10]. However, as the switching speeds of a
converter are increased because of switching device
improvements, the parasitic capacitive coupling becomes a
dominant side effect. Two major parasitic coupling paths
that can affect shaft voltage are the stator windings to the
stator iron and the stator windings to the rotor iron [11, 12].
The capacitive couplings in the motor structure and
common-mode voltage generated by the inverter forms a
model for the ASD system, which leads to a voltage across
the rotor and stator frames called shaft voltage [13 – 15].
Discussion on the origin of a shaft end-to-end voltage in an
inverter-driven motor has been presented in [16, 17]. A
practical method to find a high-frequency model of an AC
machine in order to predict leakage current and shaft
voltage is presented in [18] to extract all parameters (such
as capacitive couplings) in an AC motor based on
measuring input impedance across different terminals in a
broad frequency range using a network analyser.
In this paper, a single-phase diode rectifier is used to supply
a three-phase motor by a single-phase AC voltage source. As
the input current of the rectifier is highly distorted, a power
factor correction (PFC) unit with boost converter technique

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is used to improve the current quality of the AC source. and (vaN(t), vbN(t), vcN(t)) are the leg voltages and phase
A survey on PFC of the single-phase rectifiers is presented voltages of a three-phase converter, respectively. vNo(t) is
in [19] and the design of a single-phase rectifier with the voltage between the star point of the winding and the
improved power factor and low total harmonic distortion ground which is known as common-mode voltage. Note
(THD) using boost converter technique is investigated in that, in this configuration, ‘o ’ is assumed to be connected to
[20]. In the ASD system with single-phase rectifier the ground. Three leg voltages of the converter can be
topology, the AC – DC diode rectifier influences the calculated as follows
common-mode voltage generated by the inverter, because
the placement of the neutral point is changing in different ⎧
rectifier circuit states. Zero-switching vectors are the most ⎨ vao (t) = vaN (t) + vNo (t)
important vectors in terms of common-mode voltage v (t) = vbN (t) + vNo (t) (1)
⎩ bo
generations. Regarding the different placements of the vco (t) = vcN (t) + vNo (t)
neutral point, proper switching states will be applied in the
PWM pulse pattern to decrease the common-mode voltage.
By adding two sides of (2)

2 Common-mode voltage and shaft voltage

in ASD systems
Fig. 1a shows a DC – AC converter connected to an AC
motor. The switching combination of this inverter has eight
(¼ 23) permitted switching vectors which have been shown
in Table 1. In a three-phase system, (vao(t), vbo(t), vco(t))
vao (t) + vbo (t) + vco (t) = vaN (t) + vbN (t) + vcN (t) + 3 × vNo (t)
(2)
It is obvious that the sum of the three-phase voltages is equal
to zero (vaN(t) + vbN(t) + vcN(t) ¼ 0). Therefore the common-

Fig. 1 Common mode voltage in an ASD system

a Three-phase inverter with an AC motor
b Leg, common mode, line and phase voltages of the proposed switching pattern
c Structure of an AC motor with different parasitic capacitive couplings
d Common-mode model

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Table 1 Switching states, output leg voltage of three-phase inverter

Vector Sa1 Sb1 Sc1 vao(t) vbo(t) vco(t) vNo(t)

V1 1 0 0 Vdc /2 2Vdc /2 2Vdc /2 2Vdc /6

V2 1 1 0 Vdc /2 Vdc /2 2Vdc /2 +Vdc /6
V3 0 1 0 2Vdc /2 Vdc /2 2Vdc /2 2Vdc /6
V4 0 1 1 2Vdc /2 Vdc /2 Vdc /2 +Vdc /6
V5 0 0 1 2Vdc /2 2Vdc /2 Vdc /2 2Vdc /6
V6 1 0 1 Vdc /2 2Vdc /2 Vdc /2 +Vdc /6
V7 1 1 1 Vdc /2 Vdc /2 Vdc /2 +Vdc /2
V0 0 0 0 2Vdc /2 2Vdc /2 2Vdc /2 2Vdc /2

mode voltage can be calculated as
vao (t) + vbo (t) + vco (t)
vcom (t) = vNo (t) = (3)
3
This equation shows that the output voltage of the
converter is not sinusoidal. Switching states of the proposed
converter, the leg voltages and the resultant common-mode
voltage are given in Table. 1. The three-leg voltage of the
inverter and the common-mode voltage are shown in
Fig. 1b for a switching pattern of (V0 , V1 , V2 , V7 , V2 , V1 , V0).
The capacitive couplings in the motor structure and
common-mode voltage generated by the inverter forms a
model for the ASD system, which leads to a voltage across
the rotor and stator frames called shaft voltage. Fig. 1c
shows the structures of an AC motor where the parasitic
capacitive couplings exist between the stator winding and
rotor (Cwr), the winding and stator frame (Cws), the rotor
and stator frame (Crs) and outer and inner races of the ball
bearing (CBO , CBI). A simple high-frequency model of the
motor is shown in Fig. 1d and shaft voltage can be
calculated as
Cwr
Vshaft = × Vcom (4)
Cb + Crs + Cwr
Shaft voltage is the main cause of the motor bearing current
and leads to bearing damage and decrement of the bearing
lifetime. Any decrement of common-mode voltage or
elimination of maximum levels of common-mode voltage
leads to a shaft voltage decrement. Shaft voltage
measurement, its relationship with common-mode voltage
in a motor drive system, its effects on bearing currents and
relative bearing damages have been extensively presented at
[13 – 14] and [18] by the authors.
3 Common-mode voltage in a three-phase
ASD system supplied with a single-phase
diode rectifier and a front end PFC converter
In many low-power applications, such as home appliances
(under 3 kW), a single-phase AC voltage source is used
to supply a three-phase motor drive system via a front
end PFC. Further investigations in such a topology shows
that the common-mode voltage levels are not similar to
the one with a three-phase AC source (see Fig. 1 and
Table 1).
3.1 Circuit analysis
Fig. 2a shows a three-phase ASD system with a single-phase
AC power supply. As shown in Fig. 2b, the input current
of the rectifier is highly distorted and therefore such a
topology is not practical. Based on International
Electrotechnical Commission (IEC 60747) standards, this
type of converters is more practical at low power (below 75
watts) for specific applications and for higher-power
applications, a PFC unit or a passive filter is needed to
reduce input current harmonics.
Fig. 3a shows the structure of an ASD system with a single-
phase diode rectifier and a PFC system where the input
current is controlled using a boost converter technique. The
input current will be compared with a sinusoidal reference
current and a current control strategy determines switching
pattern. Current control technique benefits power electronic
converters. Hysteresis current control is a simple current
control with fast dynamic response [21]. Therefore in this
topology the inductor current will be compared to a
reference current and forced to be kept inside the upper and
lower hysteresis bands. This results in a sinusoidal current
waveform at the input side. In addition, a space vector
modulation strategy is employed for the inverter switching
control. The common-mode voltage of this system is
different from the one supplied with the three-phase rectifier
(the topology shown in Fig. 1 in which the middle point
has been considered as ground). Owing to the different
ground placement in the single-phase diode rectifier
topology, the voltage of point ‘o’ is not ground anymore
and has a voltage difference with actual ground ‘g’.
Therefore the common-mode voltage can be calculated as
vNg(t) ¼ vNo(t) + vog(t) where vNo(t) is the calculated
voltage given in Table 1 and vog(t) is the voltage between
the middle point of split capacitor and the ground. To
analyse the behaviour of the system, Figs. 3b and c show
the equivalent circuit of the ASD system of Fig. 3a in a
positive and negative half cycles of the input AC voltage,
respectively. Note that, in all analysis, the DC-link capacitor
is supposed to be big enough in order to keep the DC
voltage level at Vdc .
3.2 Different common-mode voltage levels
3.2.1 Positive half a cycle: Fig. 3b shows the behaviour of
the proposed system in the positive half a cycle. When the
input voltage is positive, the diodes D1 and D4 are in
forward bias and therefore the actual ground is connected to
the negative DC-link line (vng(t) ¼ 0). Table 2 shows the
switching states, vNo (t) from Table 1, vog(t) (which is Vdc/2)
and the common-mode voltages of this converter in the first
half a cycle (vNo(t) + vog(t)). As shown in this table, the
maximum common-mode voltage level is at zero-switching
vector V7 (111) and its minimum level is at the other zero-
switching vector V0 (111) with the magnitudes of Vdc and 0,
respectively.

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3.2.2 Negative half a cycle: Fig. 3c shows the behaviour
of the system in the negative half a cycle. When the input
voltage is negative, because of the forward bias across D2
and D3 , the ground is connected to the point ‘p ’ of the DC
link via an inductor. The negative DC-link line is also
connected to the AC voltage source (vNg(t) ¼ vin(t)) where
vin(t) ¼ Vinsin(vt). Table 2 shows the switching states,
vNo(t) from Table 1, vog(t) (which is Vdc/2 + vin(t)) and the
common-mode voltages (vNo(t) + vog(t)) of this converter in
the negative half a cycle.
As shown in Figs. 3b and c, the voltage between the positive
and negative DC-link points in the first half a cycle are

vpg (t) = Vdc
(5)
vng (t) = 0
These voltages in the negative half a cycle are
 vector generates maximum common-mode voltage level.
vpg (t) = Vdc + vin (t)
(6)
vng (t) = vin (t)
These voltages and the common-mode voltage of the proposed
Fig. 2 Three-phase ASD system with a single-phase AC power supply
a Three-phase inverter supplied with a single-phase diode rectifier
b Input current (Iin) of the single-phase diode-rectifier
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inverter with the switching pattern of (V0 , V1 , V2 , V7 , V2 , V1 , V0)
are shown in Fig. 4a. It varies between the voltages of positive
and negative points of the DC link with respect to the ground. In
the positive half a cycle, as shown in Fig. 4b and Table 2,
applying V7 creates the maximum common-mode voltage
level (vpg(t) ¼ Vdc) and applying V0 creates the common-
mode voltage of zero. In negative half cycle, as shown in
Fig. 4c and Table 2, common-mode voltage varies between
(vng(t) ¼ vin(t)) and (vpg(t) ¼ Vdc + vin(t)) by applying V7 and
V0 , respectively. It is clear that with this switching strategy,
which contains two zero-switching vectors, maximum
common-mode voltage levels have been generated.
3.3 Common-mode voltage reduction strategy
According to common-mode voltage levels in Table 2, one of
the zero-switching vectors in each half a cycle generate
minimum common-mode voltage level and the other zero
Thereby, we can allocate one of the zero-switching vectors
in each switching cycle instead of two zero vectors.
In the positive half a cycle, a solution to reduce the
common-mode voltage is to use only V0 voltage vector
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Fig. 3 Structure of an ASD system with a single-phase diode rectifier and a PFC system based on a boost converter technique
a Schematic of an ASD system supplied by a single-phase diode rectifier with PFC
b Positive half a cycle
c Negative half a cycle

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Table 2 Switching states, leg voltages and the common-mode voltages of proposed converter in the positive and negative half cycles

Switching states Positive half a cycle Negative half a cycle

Vector S1 S3 S5 vNo(t) vog(t) vNg(t) vNo(t) vog(t) vNg(t)

V1 1 0 0 2Vdc /6 Vdc /2 Vdc /3 2Vdc /6 Vdc /2 + vin(t) Vdc /3 + vin(t)

V2 1 1 0 +Vdc /6 Vdc /2 2Vdc /3 +Vdc /6 Vdc /2 + vin(t) 2Vdc /3 + vin(t)
V3 0 1 0 2Vdc /6 Vdc /2 Vdc /3 2Vdc /6 Vdc /2 + vin(t) Vdc /3 + vin(t)
V4 0 1 1 +Vdc /6 Vdc /2 2Vdc /3 +Vdc /6 Vdc /2 + vin(t) 2Vdc /3 + vin(t)
V5 0 0 1 2Vdc /6 Vdc /2 Vdc /3 2Vdc/6 Vdc /2 + vin(t) Vdc /3 + vin(t)
V6 1 0 1 +Vdc /6 Vdc /2 2Vdc /3 +Vdc /6 Vdc /2 + vin(t) 2Vdc /3 + vin(t)
V7 1 1 1 +Vdc /2 Vdc /2 Vdc +Vdc /2 Vdc /2 + vin(t) Vdc + vin(t)
V0 0 0 0 2Vdc /2 Vdc /2 0 2Vdc /2 Vdc /2 + vin(t) vin(t)

as a zero-switching state in the positive half a cycle. As
shown in Table 2 and Fig. 5b, using this vector to
eliminate V7 in the positive half a cycle leads to
elimination of the maximum common-mode voltage level
of vpg(t) ¼ Vdc . As shown in this figure using other
active vectors generates two common-mode voltage
levels of Vdc/3 and 2Vdc/3.
In the negative half a cycle, As shown in Fig. 4a, the
common-mode voltage varies between the two voltage
levels of (vng(t) ¼ vin(t)) and (vpg(t) ¼ Vdc + vin(t)) by
applying V7 and V0 , respectively. As vng(t) and vpg(t) are
varying by time, Depends on magnitude of which
voltage is greater than the other one, vectors one of the
zero-switching vectors V0 and V7 will be removed from a
switching cycle to remove the maximum common-mode
voltage level. As shown in Fig. 5a, If vin(t) is greater
than 2Vin/2, it is better to apply V0 and eliminate V7
because the magnitude of Vdc + vin(t) is greater than
vin(t) (see Fig. 5c). If the voltage vin(t) is lower than
2Vs/2, it is better to apply V7 and eliminate V0 because
the magnitude of vin(t) is getting to be maximum in this
half a cycle. Fig. 5a shows the common-mode voltage
for a switching strategy of (V0 , V1 , V2 , V1 , V0) when
vin(t) . 2Vin/2 and (V7 , V2 , V1 , V2 , V7) when
vin(t) , 2Vin/2.
Comparison of the common-mode voltage achieved in
this strategy with the one achieved in Fig. 5 is shown
that, this technique can help to reduce the amount of
common-mode voltage by keeping the zero-switching
vectors in the switching pattern and also keeping the
quality of the load current. In this figure, two maximum
levels of common-mode voltage have been eliminated. In
fact, in the inverter system connected to a single-phase
diode rectifier, some choices are possible to minimise the

Fig. 4 Common mode voltage achieved by the switching sequence of (V0, V1, V2, V7, V2, V1, V0)
a Voltages at positive and negative points of DC link with respect to the ground and common mode voltage
b Common mode voltage levels at fraction of positive half a cycle and related switching vectors
c Common mode voltage levels at fraction of negative half a cycle and related switching vectors

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common-mode voltage with keeping the zero vectors in the
switching sequences by using the different ground
placement as a benefit.

4 Simulation and experimental results

4.1 Simulation results

Simulations have been conducted for the circuit topology

shown in Fig. 3, in which a hysteresis current control is
used to control the PFC switch (to generate an 11A
sinusoidal current). A space vector modulation with a
switching frequency of 5 kHz is used to control the three-
phase inverter. A 300 V AC voltage is regulated through a
single-phase diode rectifier and a boost converter
connected to a DC-link capacitor of 2 mF. Space vector
modulation technique ( fs ¼ 5 kHz) is implemented in the
proposed system to reduce maximum levels of the
common-mode voltage. Fig. 6 shows the inductor and
input current controlled within the hysteresis bands that
generates a sine wave current. It is clear that the quality of
Fig. 6 Inductor and input currents with a PFC
the input current has been improved significantly with a
PFC unit.
A typical pulse pattern of (V0 , V1 , V2 , V7 , V2 , V1 , V0) has solution to reduce the shaft voltage is to use only V0
been employed for the inverter. Fig. 7a shows the DC-link voltage vector in the positive half a cycle in which it has
voltage and the voltages of the positive and negative points the lowest potential with respect to the neutral. V7 will be
of the DC link with respect to the ground (Vpg and Vng). applied in the negative half a cycle where the neutral line is
Applying V0 and V7 to the pulse pattern leads to maximum connected to PFC inductor and negative DC link is
common-mode voltage, which changes between voltages connected to the source voltage. Fig. 7 shows the leg
Vpg and Vng . As mentioned in the previous section, a voltages and the common-mode voltage of the system with

Fig. 5 Common mode voltage achieved by the switching sequence of (V0, V1, V2, V1, V0) when vin(t) .2Vin/2 and (V7, V2, V1, V2, V7) when
vin(t) , 2Vin/2
a Voltages at positive and negative points of DC link with respect to the ground and common mode voltage
b Common mode voltage levels at fraction of positive half a cycle and related switching vectors
c Common mode voltage levels at fraction of negative half a cycle and related switching vectors

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the proposed PWM strategy. Comparison of the common-
mode voltage achieved in Fig. 7b with the voltage shown in
Fig. 7a shows the effectiveness of proposed switching
strategy on the common-mode voltage.
As mentioned in previous sections, common-mode voltage
generated by inverter systems leads to shaft voltage in
existence of motor capacitive couplings. A simulation study
has been proposed for a typical motor parameters and shaft
voltage has been compared for two different switching
patterns. It is supposed that for a specific motor design,
Cwr , Crs , Cws and Cb are 90 pF, 760 pF, 4 nF and 50 pF,
Fig. 7 Diagrams of input and output voltages of inverter topology
with different switching sequences
a DC-link voltage, voltages at positive and negative points of DC link with
respect to the ground and common-mode voltage for switching sequence
of (V0 , V1 , V2 , V7 , V2 , V1 , V0)
b Leg voltages and common-mode voltage for switching sequence of (V0 , V1 ,
V2 , V1 , V0) for positive half a cycle and sequence of (V7 , V2 , V1 , V2 , V7)
for negative half a cycle
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respectively [13]. With the given parameters and according
to (4) and Fig. 1d, shaft voltage is about 10% of common-
mode voltages. According to Fig. 8, with applying the
proposed PWM strategy, maximum level of shaft voltage
has been decreased from 30 to 20 v in positive half a cycle.
The same scenario is valid in negative half a cycle as well.
4.2 Experimental results
As shown in Fig. 9a, a laboratory prototype of the proposed
circuit at low voltage level has been implemented. A three-
phase R– L load has been used as an AC motor to measure
the common mod voltage. All the circuit components have
been labelled in this figure. Hysteresis current control has
been applied to the boost converter with a 1 A reference
current and three-phase inverter has been switched with a
typical PWM strategy with 4 kHz switching frequency.
Fig. 9b shows the input voltage (20 V) and the
output voltage of the boost converter (DC-link
voltage of inverter), which has been increased to 30 V.
Inductor current and the input current are also shown in
this figure.
Fig. 9c shows the common-mode voltage of the proposed
with applying a PWM strategy with both V0 and V7 zero-
switching vectors (V0 , V1 , V2 , V7 , V2 , V1 , V0). As shown in
this figure the common-mode voltage is varying between
the vpg and vng which leads to a common-mode voltage
with two maximum levels. Fig. 9c shows a better view of
these voltages in which the pulse voltage are varying
between two proposed voltages. As shown in Figs. 10a and b,
by elimination of V7 or V0 , the common-mode voltage looses
one of its maximum levels and another level still exists. By
using the proposed switching strategy (elimination of V7
when vin(t) . 2Vin/2 and removing V0 at a fraction of
negative half a cycle when vin(t) . 2Vin/2), two maximum
levels of the common-mode voltage have been removed. This
Fig. 8 Comparison of shaft voltage with two different pulse
patterns for typical motor parameters
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Fig. 9 Test results of the proposed method

a Laboratory prototype of a three-phase inverter supplied with a single-phase AC source
b Input and output voltage of boost converter, input and inductor currents
c Common-mode voltage level with both V0 and V7 zero-switching vectors

Fig. 10 Common-mode voltage with

a Elimination of V7
b Elimination of V0
c Elimination of V7 when vin(t) . 2Vin/2 and removal of V0 at a fraction of negative half a cycle when vin(t) . 2Vin/2

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is a great achievement without distorting the input current and
keeping the switching frequency constant using at least one
zero-switching vector in the pulse pattern.
5 Conclusions
A three-phase inverter system supplied by a single-phase diode
rectifier with and without PFC has been studied in terms of
common-mode generation. Different placements of the ground
in different diode rectifier circuit intervals can influence the
common-mode voltage. Therefore a PWM technique is
presented by a proper placement of the zero vectors to reduce
the common-mode voltage level. This method leads to a cost
effective shaft voltage reduction technique without load
current distortion and keeping the switching frequency
constant. Analysis of the proposed method has been verified
via simulations and experimental examination.
6 Acknowledgment
The authors thank the Australian Research Council (ARC)
for the financial support for this project through the ARC
Discovery Grant DP0774497.
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