FOUNDATION UNIVERSITY ISLAMABAD

SIALKOT CAMPUS

Final-Term Examinations (Spring-2021)

Programme: BS (CS/SE/IET) Semester: Spring-2021

Course Title: Operating System Section/Batch: Fall-2019

Instructor Name: Dr. Nasrullah Max Marks: 25

Time Allowed: 03:00 hrs Date: 29-June-2021

➢ Be brief and to the point.

➢ Copy paste from any source will reward zero marks.

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Question No. 1. (04+04=08)

(a) A resource allocation graph is shown below

Determine whether the system will be in a deadlock state otherwise find a safe sequence.

(b) Consider a system has four processes and five allocatable resource. The present allocation
and maximum needs are as follows

If Available = [ 0 0 X 1 1], what is the minimum value of X for which this is a safe state?
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Question No. 2. (04+04=08)

(a) Suppose a system use paging-based memory management with 4GB virtual address
space for processes. The page size is of 4KB. The system has 8GB of RAM. The system
permits a maximum 1024 processes to run concurrently. Assuming the OS uses hierarchical
paging, compute the maximum memory space required to store the page tables of all
processes in the system. Assume that each page table entry requires an additional 06 bits to
store various flags. Assume page table entries are rounded up to the nearest byte. Consider
the memory required for both outer and inner page tables in your calculations.

(b) Consider a system with 1-byte logical and physical addresses with page size of 16 bytes.
A process in this system has 4 logical pages, which are mapped to 3 physical pages in the
following manner: logical page 0 map to physical page 6, 1 map to 3, 2 maps to 11, and
logical page 5 is not mapped to any physical page yet. All the other pages in the logical
address space of the process are marked invalid in the page table. The MMU is given a
pointer to this page table for address translation. Further, the MMU has a small TLB cache
that stores two entries, for logical pages 0 and 2. For each logical address shown below,
describe what happens when that address is accessed by the CPU. Specifically, you must
answer what happens at the TLB (hit or miss?), MMU (which page table entry is accessed?),
OS (is there a trap of any kind?), and the RAM (which physical address is accessed?). You
may write the translated physical address in binary format. (Note that it is not implied that the
accesses below happen one after the other; you must solve each part of the question
independently using the information provided above.)

(i) Logical address 7

(ii) Logical address 20
(iii) Logical address 70
(iv) Logical address 80

Question No. 3. (04+03+02=09)

(a) Consider a machine with the memory access time for RAM to be 90ns. You are running
processes that, on an average, have 1 page fault in 25,000 memory accesses. Out of these
page faults, 1 in 4 pages turn up with their dirty bit set. The disk has a seek time of 10ms
and is spinning at 14,400 rpm. Consider about 1ms for transfer time for data. At any time,
there are, on an average, two processes in the device queue. Compute the effective
memory access time for this system.
(b) Determine how the FIFO and MIN page replacement algorithms would handle the
following page access pattern: A, B, C, D, E, A, B, E, D, B, B, A. As in the figures
below, assume that the system has three frames of memory (each which can hold a single
virtual page). Fill in the frame contents for each step of the access pattern and report the
total number of page faults for each algorithm.
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(c) A counting semaphore S is initialized to 6. Then, 10 wait operations and 08 signal

operations are performed on S. What is the final value of S?