Synchronous 

sequential circuits were introduced in Section 5.1 where firstly

sequential circuits as a whole (being circuits with ‘memory’) and then the
differences between asynchronous and synchronous sequential
circuits were discussed. You should be familiar with these ideas, and in
particular the general form of a synchronous sequential circuit (see Figs
8.1 and 5.3) before continuing with this chapter.

Fig. 8.1. General form of a synchronous sequential circuit

As with asynchronous sequential circuits, the operation of synchronous

sequential systems is based around the circuit moving from state to state.
However, with synchronous circuits the state is determined solely by the
binary pattern stored by the flip-flops within the circuit. (In Chapter 5 this
was referred to as the internal state of the circuit.) Since each flip-flop can
store a 0 or 1 then a circuit with n flip-flops has 2n possible states. Note
that all states are stable since the present and next state variables
are not connected directly but isolated due to the (not-transparent) flip-
flops. The analysis and design of these circuits is based upon determining
the next state of the circuit (and the external outputs) given the present
state and the external inputs. This is therefore one application of the flip-
flops' next state equations introduced in Chapter 6.
Following the introduction to sequential circuits in Section 5.1, Chapter
5 then dealt exclusively with asynchronous sequential circuits, concluding
with an in-depth analysis of an SR flip-flop. Chapter 6 continued this theme
of flip-flops which then meant that we could begin to look at synchronous
sequential circuits since these use flip-flops as their ‘memory’.
Chapter 7 looked at counters, which themselves are often considered as
basic digital building blocks, and are therefore important digital circuits. The
synchronous counters designed in Chapter 7 are in fact (simple types of)
synchronous sequential circuits. In this chapter following a description of
the way that synchronous sequential circuits can be classified, we will look
at further examples of such circuits.

10.3.1 Timing Characteristics of Synchronous Circuits

In synchronous circuits, the clock signal provides a common time
reference for all of the sequential elements, orchestrating the flow of the
data signals within a circuit [312]. A number of clock network topologies
have been developed for 2-D circuits, which can be symmetric, such as H-
trees and X-trees, highly asymmetric, such as buffered tress and
serpentine shaped structures [318], [319], and gridlike structures, such as
rings and meshes. The clock distribution network is structured as a global
network with multiple smaller local networks. Within the global clock
network, the clock signal is distributed to specific locations across the
circuit. These locations are the source of the local networks that pass the
clock signal to the registers or other storage elements.
A symmetric structure such as an H-tree is often utilized in global
clock networks [319], as shown in Figure 10-15. The most attractive
characteristic of symmetric structures is that the clock signal ideally arrives
simultaneously at each leaf of the clock tree. Due to several reasons,
however, such as load imbalances, process variations, and crosstalk, the
arrival time of the clock signal at various locations within a symmetric tree
can be different, producing clock skew. More precisely, clock skew is
defined as the difference between the clock signal arrival time
of sequentially adjacent registers [312]. Two registers are sequentially
adjacent if these registers are connected with combinatorial logic (i.e., no
additional registers intervene between sequentially adjacent registers). An
illustration of this data path is provided in Figure 10-16. An expression for
the clock skew Tskew between these registers is also shown in Figure 10-16,
where TCi and TCj are the arrival times of the clock signal at
register Ri and Rj, respectively.
 Figure 10-15. Two-dimensional four
level H-tree.

Figure 10-16. A data path depicting a pair of sequentially

adjacent registers.

The clock signal typically traverses long distances to reach each sequential
element within a circuit. In symmetric structures, such as an H-tree, the
traversed distances are often longer to preserve symmetry. Due to these
extremely long interconnects and high clock frequencies, the clock network
is typically modeled as a transmission line, since inductive behavior is likely
to occur [278]. Such behavior can cause multiple reflections at the branch
points, directly affecting the speed and power consumed by the clock
network. In order to lessen the reflections at the branch points of the tree,
the interconnect width of the segments at each branch point is halved (for a
2× change in the line width) to ensure that the total impedance seen at that
branch point is maintained constant (matched impedance)