SISTEMAS DIGITALES I

Capítulo V
Principios de Diseño de Lógica Secuencial
Parte 1
Ing. Aurelio Morales Villanueva, PhD
E-mail: amorales@uni.edu.pe

Facultad de Ingeniería Eléctrica y Electrónica

Universidad Nacional de Ingeniería
https://fiee.uni.edu.pe

EE635O Ing. Aurelio Morales Villanueva, PhD 1 de 33

Agenda
• Introducción
• Circuitos secuenciales síncronos y asíncronos
• Metaestabilidad
• El circuito de reloj. Consideraciones de diseño
• Elementos biestables:
• Latch S-R (NOR y NAND)
• Latch S-R sincronizado
• Diagramas de tiempo

EE635O Ing. Aurelio Morales Villanueva, PhD 2 de 33

Introduction
Logic circuits are classified into two types, "combinational" and "sequential."
A combinational logic circuit is one whose outputs depend only on its
current inputs. A sequential logic circuit is one whose outputs depend not
only on its current inputs, but also on the past sequence of inputs, possibly
arbitrarily far back in time.(*)

Sequential switching circuits have the property that the output depends not
only on the present input but also on the past sequence of inputs. In effect,
these circuits must be able to “remember” something about the past history
of the inputs in order to produce the present output. Latches and flip-flops
are commonly used memory devices in sequential circuits. Basically,
latches and flip-flops are memory devices which can assume one of two
stable output states and which have one or more inputs that can cause the
output state to change.(**)

(*) John F. Wakerly, “Digital Design: Principles and Practices”, 3rd Edition, Pearson Prentice Hall, 1999.
(**) Charles H. Roth Jr. & Larry L. Kinney, “Fundamentals of Logic Design”, 7th Edition, Cengage Learning, 2014.
EE635O Ing. Aurelio Morales Villanueva, PhD 3 de 33
Introduction (cont.)
In such systems, it is common practice to synchronize the operation of all
flip-flops by a common clock or pulse generator. Each of the flip-flops has a
clock input, and the flip-flops can only change state in response to a clock
pulse. A memory element that has no clock input is often called a latch, and
we will follow this practice. We will then reserve the term flip-flop to describe
a memory device that changes its output in response to a clock input and
not in response to a data input.(**)
The state of a sequential circuit is a collection of state variables whose
values at any one time contain all the information about the past necessary
to account for the circuit's future behavior.(*)
In a digital logic circuit, state variables are binary values, corresponding to
certain logic signals in the circuit, as we'll see in later sections. A circuit with
n binary state variables has 2n possible states. As large as it might be, 2n is
always finite, never infinite, so sequential circuits are sometimes called
finite-state machines.(*)
(*) John F. Wakerly, “Digital Design: Principles and Practices”, 3rd Edition, Pearson Prentice Hall, 1999.
(**) Charles H. Roth Jr. & Larry L. Kinney, “Fundamentals of Logic Design”, 7th Edition, Cengage Learning, 2014.
EE635O Ing. Aurelio Morales Villanueva, PhD 4 de 33
Introduction (cont.)
The switching circuits that we have studied so far have not had feedback
connections. By feedback we mean that the output of one of the gates is
connected back into the input of another gate in the circuit so as to form a
closed loop. In order to construct a switching circuit that has memory, such
as a latch or flip-flop, we must introduce feedback into the circuit.(*)

(*) Charles H. Roth Jr. & Larry L. Kinney, “Fundamentals of Logic Design”, 7th Edition, Cengage Learning, 2014.
EE635O Ing. Aurelio Morales Villanueva, PhD 5 de 33
Introduction (cont.)
Synchronous digital circuits
All memory elements (latches and flip-flops) are controlled
(synchronized) with a unique and global clock signal.

Asynchronous digital circuits

These circuits do not use a clock, instead these circuits use
latches or combinational circuits with a feedback loop. These
circuits may use flip-flops, but each flip-flop uses a different
clock.

Globally asynchronous but locally synchronous circuit

Global system is divided in multiple subsystems, and each one
uses a different clock signal.

EE635O Ing. Aurelio Morales Villanueva, PhD 6 de 33

Metastability
The Cross-Coupled Inverter Pair (*)
The first thing that is needed in sequential logic is a storage device. The
fundamental storage device in sequential logic is based on a positive
feedback configuration. Consider the circuit in Fig. 7.1. This circuit
configuration is called the cross-coupled inverter pair.

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 7 de 33
Metastability (cont.)
The Cross-Coupled Inverter Pair (*)
The cross-coupled inverter pair in Fig. 7.1 exhibits what is called metastable behavior due to
its positive feedback configuration. Metastability refers to when a system can exist in a state of
equilibrium when undisturbed but can be moved to a different, more stable state of equilibrium
when sufficiently disturbed. Systems that exhibit high levels of metastability have an
equilibrium state that is highly unstable, meaning that if disturbed even slightly, the system will
move rapidly to a more stable point of equilibrium. The cross-coupled inverter pair is a highly
metastable system.
This system actually contains three equilibrium states. The first is when the input of U1 is
exactly between a logic 0 and logic 1 (i.e., VCC/2). In this state, the output of U1 is also exactly
VCC/2. This voltage is fed back to the input of U2, thus producing an output of exactly VCC/2 on
U2. This in turn is fed back to the original input on U1 reinforcing the initial state. Despite this
system being at equilibrium in this condition, this state is highly unstable. With minimal
disturbance to any of the nodes within the system, it will move rapidly to one of two more
stable states. The two stable states for this system are when Q = 0 or when Q = 1 (see Fig.
7.1). Once the transition begins between the unstable equilibrium state toward one of the two
more stable states, the positive feedback in the system continually reinforces the transition
until the system reaches its final state.

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 8 de 33
Metastability (cont.)
The Cross-Coupled Inverter Pair (*)

(*) John F. Wakerly, “Digital Design: Principles and Practices”, 3rd Edition, Pearson Prentice Hall, 1999.
EE635O Ing. Aurelio Morales Villanueva, PhD 9 de 33
Metastability (cont.)
The Cross-Coupled Inverter Pair (*)
We can find these equilibrium points graphically from Figure 7-3; they are
the points at which the two transfer curves meet. Surprisingly, we find that
there are not two but three equilibrium points. Two of them, labeled stable,
correspond to the two states that our "strictly digital" analysis identified
earlier, with Q either 0 (LOW) or 1 (HIGH).

The third equilibrium point, called a metastable state, occurs with Vout1 and
Vout2 about halfway between a valid logic 1 voltage and a valid logic 0
voltage; so Q and Q_L are not valid logic signals at this point. Yet the loop
equations are satisfied; if we can get the circuit to operate at the metastable
point, it could theoretically stay there indefinitely. This behavior is called
metastability.

(*) John F. Wakerly, “Digital Design: Principles and Practices”, 3rd Edition, Pearson Prentice Hall, 1999.
EE635O Ing. Aurelio Morales Villanueva, PhD 10 de 33
Metastability (cont.)
The Cross-Coupled Inverter Pair (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 11 de 33
Metastability (cont.)
The Cross-Coupled Inverter Pair (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 12 de 33
Metastability (cont.)
The Cross-Coupled Inverter Pair (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 13 de 33
Metastability (cont.)
The Cross-Coupled Inverter Pair (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 14 de 33
The clock (*)
The state changes of most sequential circuits occur at times specified by a
free-running clock signal. The clock period is the time between successive
transitions in the same direction, and the clock frequency is the reciprocal of
the period.

(*) John F. Wakerly, “Digital Design: Principles and Practices”, 3rd Edition, Pearson Prentice Hall, 1999.
EE635O Ing. Aurelio Morales Villanueva, PhD 15 de 33
The clock generator circuit
CMOS 74C14 (Inverting Schmitt Trigger) (*)

(*) MM74HC14 Hex Inverting Schmitt Trigger, Fairchild Semiconductor Corporation, May 2005.
EE635O Ing. Aurelio Morales Villanueva, PhD 16 de 33
The clock generator circuit (cont.)
The 555 Timer Integrated Circuit (*)
The 555 timer IC is an integrated circuit (chip) used in a variety of timer,
delay, pulse generation, and oscillator applications.

555 internal schematic of bipolar version

555 internal block diagram

(*) https://en.wikipedia.org/wiki/555_timer_IC 555 internal schematic of CMOS version

EE635O Ing. Aurelio Morales Villanueva, PhD 17 de 33
The clock generator circuit (cont.) (*)
The 555 Timer (astable mode)

(*) https://en.wikipedia.org/wiki/555_timer_IC
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Bistable elements: latches
Controlled memory element (*)
Figure 7.2 gives a rudimentary memory element,
consisting of a loop that has two inverters. If we
assume that A = 0, then B = 1. The circuit will
maintain these values indefinitely. We say that the
circuit is in the state defined by these values. If we
assume that A = 1, then B = 0, and the circuit will
remain in this second state indefinitely.

Thus the circuit has two

possible states. This circuit is
not useful, because it lacks
some practical means for
changing its state. A more
useful circuit is shown in Figure
7.3. It includes a mechanism for
changing the state of the circuit
in Figure 7.2

(*) S. Brown & Z. Vranesic, “Fundamentals of Digital Logic with VHDL Design”, 3 rd Edition, McGraw-Hill, 2009.
EE635O Ing. Aurelio Morales Villanueva, PhD 19 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NOR) (*)
While the cross-coupled inverter pair is the
fundamental storage concept for sequential logic,
there is no mechanism to set the initial value of Q. All
that is guaranteed is that the circuit will store a value
in one of two stable states (Q = 0 or Q = 1). The SR
Latch provides a means to control the initial values in
this positive feedback configuration by replacing the
inverters with NOR gates. In this circuit, S stands for
set and indicates when the output is forced to a logic
1 (Q = 1), and R stands for reset and indicates when
the output is forced to a logic 0 (Q = 0). When both S
Set-Reset latch with NOR
= 0 and R = 0, the SR Latch is put into a store mode
and it will hold the last value of Q. In all of these
input conditions, Qn is the complement of Q.

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 20 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NOR) (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 21 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NOR) (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 22 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NOR) (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 23 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NOR) (*)

(*) Charles H. Roth Jr. & Larry L. Kinney, “Fundamentals of Logic Design”, 7th Edition, Cengage Learning, 2014.
EE635O Ing. Aurelio Morales Villanueva, PhD 24 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NOR) (*)

(*) S. Brown & Z. Vranesic, “Fundamentals of Digital Logic with VHDL Design”, 3 rd Edition, McGraw-Hill, 2009.
EE635O Ing. Aurelio Morales Villanueva, PhD 25 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NOR) (*)

(*) Charles H. Roth Jr. & Larry L. Kinney, “Fundamentals of Logic Design”, 7th Edition, Cengage Learning, 2014.
EE635O Ing. Aurelio Morales Villanueva, PhD 26 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NAND) (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 27 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NAND) (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 28 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with NAND) (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 29 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with enable) (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 30 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with enable) (*)

(*) Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with VHDL”, 2nd edition, Springer, 2019.
EE635O Ing. Aurelio Morales Villanueva, PhD 31 de 33
Bistable elements: latches (cont.)
Set-Reset Latch (with enable) (*)

(*) S. Brown & Z. Vranesic, “Fundamentals of Digital Logic with VHDL Design”, 3 rd Edition, McGraw-Hill, 2009.
EE635O Ing. Aurelio Morales Villanueva, PhD 32 de 33
Resumen
• Circuitos secuenciales síncronos y asíncronos
• Metaestabilidad
• El circuito de reloj: consideraciones de diseño
• Elementos biestables:
• Latch S-R (NOR y NAND), latch S-R sincronizado
• Diagramas de tiempo

Bibliografía
• John F. Wakerly, “Digital Design: Principles and Practices”, 3rd Edition,
Pearson Prentice Hall, 1999.
• Brock J. LaMeres “Introduction to Logic Circuits and Logic Design with
VHDL”, 2nd Edition, Springer, 2019.
• S. Brown and Z. Vranesic, “Fundamentals of Digital Logic with VHDL Design”,
3rd Edition, McGraw-Hill, 2009.
• Charles H. Roth Jr. and Larry L. Kinney, “Fundamentals of Logic Design”, 7th
Edition, Cengage Learning, 2014.

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