Std : OAPJC Year : 2020-21

Subject : Computer Science – II

Chapter 1 : 8085 Instruction Set and Programs.
SUB TOPICS :
INSTRUCTION SETS:
1) Doubts in 3 groups?
2) Quick revise.
3) Programming.
INSTRUCTION SETS:

The instruction set of 8085 microprocessor is divided into 5 different groups as

following:

1) Data transfer group

2) Arithmetic group
3) Logic group
4) Branching group
5) Stack, I/O, Machine control group.

NOTE: in board examination any instruction out of the five groups are asked
every year.
4) Branching group :
This group of Instructions are used to Alter the normal sequence flow of the programs.
Instructions under this group does not affect any of the flags.
The two types of instructions under this group are Unconditional and Conditional.
Unconditional transfer simply performs the specific operation on the PC (Program Counter) Register.
Whereas Conditional transfer examines/observes one of four Flags and determines if the specific
branch to be executed.
The conditions as follows.
NC NO CARRY (CY=0)
C CARRY (CY=1)
PO PARITY ODD (P=0)
PE PARITY EVEV (P=1)
NZ NOT ZERO (Z=0)
Z ZERO (Z=1)
P PLUS (S=0)
M MINUS (S=1)
 The Main instructions under this Group are.

JUMP CALL RETURN

1) JMP Addr
Since this is Unconditional Jump instruction the control is transferred to the
instruction whose address is mentioned in the byte 3 and byte 2..

i.e. (PC) (BYTE 3)(BYTE2)

EG: JMP (16 Bit) Addr.

Instruction length: 3- byte

Addressing mode: Direct Addressing Mode
Flags affected : None .
2) Jcondition Addr (conditional jump)
Since this is Conditional Jump instruction the control is transferred to the instruction
whose address is mentioned in the byte 3 and byte 2 if the condition satisfies.

i.e. If condition satisfies then (PC) (BYTE 3)(BYTE2)

EG: JNC (16 Bit) Addr.

JNC JUMP IF NO CARRY (CY=0)
Instruction length: 3- byte JC JUMP IF CARRY (CY=1)
Addressing mode: Direct Addressing Mode
JPO JUMP IF PARITY ODD (P=0)
Flags affected : None .
JPE JUMP IF PARITY EVEV (P=1)
JNZ JUMP IF NOT ZERO (Z=0)
JZ JUMP IF ZERO (Z=1)
JP JUMP IF PLUS (S=0)
JM JUMP IF MINUS (S=1)
3) CALL Addr
This Call instruction pushes current PC (add) on Stack and then the control is
transferred to the instruction whose address is mentioned in the instruction by
loading its address into PC.

i.e. ((SP)-1)(PCH)
((SP)-2)(PCL)
(SP)(SP)-2
and
(PC)(BYTE3)(BYTE2)

EG: CALL (16 Bit) Addr.

Instruction length: 3- byte
Addressing mode: Direct Addressing Mode
Flags affected : None .
3) Ccondition Addr
If the condition satisfies then This Call instruction pushes current PC (add) on Stack
and then the control is transferred to the instruction whose address is mentioned in
the instruction by loading its address into PC.

i.e. If condition satisfies

Then ((SP)-1)(PCH)
((SP)-2)(PCL)
(SP)(SP)-2 CNC CALL IF NO CARRY (CY=0)
and CC CALL IF CARRY (CY=1)
(PC)(BYTE3)(BYTE2) CPO CALL IF PARITY ODD (P=0)
CPE CALL IF PARITY EVEV (P=1)
EG: CC(16 Bit) Addr. CNZ CALL IF NOT ZERO (Z=0)

Instruction length: 3- byte CZ CALL IF ZERO (Z=1)

Addressing mode: Direct Addressing Mode CP CALL IF PLUS (S=0)
Flags affected : None . CM CALL IF MINUS (S=1)
5) RET
This Return instruction loads the content of memory location whose address is
specified in SP reg. to lower-order eight bit of PC reg. ; the content of the very next
memory location (i,.e. SP+1) is loaded in the higher-order 8 bit of the PC and then SP is
again incremented by one (i.e. SPSP+2).

i.e. (PCL) ((SP)) ;

(PCH)((SP)+1)
and
(SP)(SP)+2

EG: RET
Instruction length: 1- byte
Addressing mode: Register indirect Addressing Mode
Flags affected : None .
3) Rcondition
If the condition satisfies then this Return instruction loads the content of memory
location whose address is specified in SP reg. to lower-order eight bit of PC reg. ; the
content of the very next memory location (i,.e. SP+1) is loaded in the higher-order 8
bit of the PC and then SP is again incremented by one (i.e. SPSP+2).

i.e. If condition satisfies

Then (PCL) ((SP)) ;
(PCH)((SP)+1) RNC RETURN IF NO CARRY (CY=0)
and RC RETURN IF CARRY (CY=1)
(SP)(SP)+2 RPO RETURN IF PARITY ODD (P=0)
RPE RETURN IF PARITY EVEV (P=1)
EG: RNZ RNZ RETURN IF NOT ZERO (Z=0)
Instruction length: 1- byte RZ RETURN IF ZERO (Z=1)
Addressing mode: Register indirect Addressing Mode RP RETURN IF PLUS (S=0)
Flags affected : None .
RM RETURN IF MINUS (S=1)
Q 1) A Block of data is stored in memory location starting from C040 H. Length of the block is stored in register D. Write
an Assembly language program to transfer the entire block of data to another memory location starting from
memory location C050 H.
Before execution of program
Source Destination
LABLE MNEMONICS COMMENTS
LXI H, C040H ; initialise source memory location C040 H = 01 H C050 H = 00 H
pointer in HL reg pair. C041 H = 02 H C051 H = 00 H
C042 H = 03 H C052 H = 00 H
LXI B, C050H ; initialise destination memory location C043 H = 04 H C053 H = 00 H
pointer in BC reg pair.
C044 H = 05 H C054 H = 00 H
MVI D,05H ; initialise counter of 05H in D reg.
D = 05H
UP: MOV A,M ; moving source data into A reg.
STAX B ; storing data on Destination via A. After execution of program
DCR D ; decrement the counter D. Source Destination
INX H ; increment source memory pointer. C040 H = 01 H C050 H = 01 H
INX B ; increment destination memory pointer. C041 H = 02 H C051 H = 02 H
C042 H = 03 H C052 H = 03 H
JNZ UP: ; if zero flag not set jump to UP: C043 H = 04 H C053 H = 04 H
HLT ; end program. C044 H = 05 H C054 H = 05 H
D = 00H
THANK YOU