Timing Verification and the Timing Analysis Program

Robert B. Hitchcock, Sr.

IBM General Technology Division

Endicott, New York 13760
ABSTRACT 1. All i n t e r n a l paths, which can be a c t i v a t e d from
storage element or PI to storage element or PO,
w i l l have delays n e i t h e r too long nor too short
Timing Verification consists of v a l i d a t i n g the path (Figure I ) .
delays ( p r i m a r y input or storage element to p r imar y
o u t p u t or storage element) to be sure they are not 2. All clock signals propagating though the repow-
too long or too short and checking the clock pulses ering c i r c u i t r y w i l l r e t a i n the required mini-
to be sure they are not too wide or too narrow. The mum pulse width despite the shrinking e f f e c t of
programs addressing these problems neither produce non-symmetric delays (Figure 2).
i n p u t patterns like test pattern generators nor re-
quire i n p u t patterns like tr a d i ti o n a l simulators.
Several programs (described here) operate by trac-
ing paths [Pl73, WO78, SA81, KA81]. One program
[MC80] extends simulation into a pessimistic analyz-
er not dependent on test patterns.
Timing Analysis, a program described recently in CLOCKi - -
[HI82a], is designed to analyze the timing of large
digital computers and is based, in p a r t , on the con-
cepts disclosed in a patented method [DO81] f o r de-
termining the extreme characteristics of logic block CLOCK2 I
diagrams. The o u t p u t of Timing Analysis includes
"slack" at each block to p r o v i d e a measure of the Figure 1 - The storage element timing problem:
severity of the timing problem. The program also Make sure that every transition stored
generates standard deviations for the times so that a by one clock will arrive at the next
statistical timing design can be produced rather storage element in time to be gated
than a worst case approach. in b y the other clock.

I INTRODUCTION

Product Verification consists of three main parts,

Functional Design V e r i f i c a t i o n , Physical Design Ver-
i f i c a t i o n , and Timing Verification. Functional De-
sign Verification means simulating at a high level
and/or low level to insure that the design as imple- Rising Delay 10 5 10 5
mented produces the desired results. Physical
Design Verification means checking the physical pa- Falling Delay 6 3 6 3
rameters: the separations of wires and other
physical shapes to be sure they meet the required Clock at Input: R i s e at t=O , Fall at t=lO.
minimums, the total capacitance in the nets to be
sure they are within the allowable bounds, the ge- Clock at Output: Rise at t=26 , Fall at t=32.
ometric arrangements of the physical nets to be sure
they f i t the configurations for which delays can be
predicted, and so on. Timing Verification consists Figure 2 - Clock Pulse Width Shrinkage
of validating the path delays (primary input or sto- Illustration: The Blocks are all
rage element to primary output or storage element) assumed to invert, so the asymmetric
to be sure they are not too long or too short and delay, coupled with the overall
checking the clock pulses to be sure they are not too differences in delay between blocks
wide or too narrow. in subsequent stages, causes the
clock to shrink f r o m a separation of
Problems found by any of these v e r i f i c a t i o n steps ten units to a separation of six units.
can impose changes to the design. As the onslaught
of VLSI continues, i t becomes more and.more impor-
tant to perform complete analyses of each of these Several automated approaches have been reported;
steps prior to the building of actual hardware. some of these have centered on the analysis of the
detailed e l e c t r i c a l properties of the components
To insure that a d i g i t a l computer w i l l operate at a along a path, using an approach which enumerateda l l
desired speed, the designer must v e r i f y that several paths [PI73, W078, SA81, KA81]. These so-called path
conditions are true within the design: oriented approaches w i l l be described in greater de-

19th Design Automation Conference

Paper 34.2
594 0420-0098/82/0000/0594500.75 © 1982 IEEE
tail laterl Others have taken the delays of the
blocks to be well defined numbers and have attempted
to optimize these delays w i t h i n a power c o n s t r a i n t
[AG17, RU17].
Techniques which tend to process each block a r ) l a -
t i v e l y small number of times have also been de-
scribed. [K166, MC80, D081, H182a] These so-called
block o r i e n t e d approaches w i l l also be described in
more detail l a t e r .
To i l l u s t r a t e how these types of algorithms operate,
a diagram used in [HI82a] w i l l be used. I t has been
redrawn with single letters designating the i n d i v i d -
ual blocks for more easy reference (Figure 3).
Figure 3 - Basic Logic Diagram: This diagram
is used to illustrate the operation
of several of the algorithms described.
The delays are shown at the bottom
of the block, mean first and standard
deviation (sigma) second.
The main emphasis of t h i s report is to f a m i l i a r i z e
the reader with the two main techniques f o r v e r i f y -
ing performance in computer designs: path enumer-
at i o n and block oriented techniques. Section I I
describes examples of each kind of algorithm in de-
t a i l using a small block diagram to i l l u s t r a t e some
of the features of each. Section I I I discusses the
Timing Analysis program developed at IBM. TA is a
block oriented program which not only i d e n t i f i e s the
most c r i t i c a l path(s), but also provides a value at
each block, called the slack, which is a measure of
the degree to which the worst path through that
block meets i t s timing constraints.
II PREVIOUSLY DESCRIBED APPLICATIONS
Previously described techniques tend to group into
two main categories: path enumeration techniques and
block oriented analysis techniques. T he s e main
techniques w i l l be introduced, and then the programs
themselves w i l l be described, with a small c i r c u i t
used to i l l u s t r a t e how they would operate. Both of
these techniques are quite d i f f e r e n t from simulators
or test generators. Contrary to what one would ex-
pect in a simulator, no attempt is made to prove that
a path can be sensitized before i t s delay is calcu-
lated and no values are assigned to inputs to
t r i g g e r actions along a path whose delay is being
c a lc ulat ed.
Path Enumeration Techniques
Path enumeration techniques are characterized by
programs which s t a r t at c e r t a i n " s t a r t p o i n t s " , and
trace back through the blocks feeding the s t a r t
points u n t i l a PI or a "terminal p o i n t " is reached.
At t h i s stage, the information is complete and the
data f o r the path can be accumulated. Data accumu-
l a t i o n can be done by simply adding up the delays, or
by combining the delays s t a t i s t i c a l l y .
Path enumeration techniques tend to have long run-
ning times since the number of paths through a graph
grows e x p o n e n t i a l l y with the size of the graph.
However, there is often an advantage in having an
e n t i r e path a v a i l a b l e when the analysis is to be
done: the delay of a given c i r c u i t may depend not
only on the input and output loading and the i n t r i n -
sic properties of the c i r c u i t , but also on the r i s e
time of the signal at i t s input. By knowing what
c i r c u i t is the primary d r i v e r of the path, one can
determine the rise time, and more accurately d e t e r -
mine the delays of a l l the c i r c u i t s . I t is also
easier to t e l l such a path oriented program to i g -
nore c e r t a i n paths which w i l l never be a c t i v a t e d in
the actual machine (unless, of course, there are an
excessive number of such ignorable paths).
NELTAS [SA81] includes a set of programs which tend
to be part path enumeration and part block oriented
analysis, since in one mode a l l paths are
enumerated, and in the other mode only " c r i t i c a l
paths" are evaluated, much as in the block oriented
techniques. The programs or papers describing sys-
tems which, f o r purposes of t h i s discussion, have
been assigned to the path enumeration category are:
I. Computer-Aided Prediction of Delays in LSI Log-
ic Systems- ( F a i r c h i l d and Amdahl), D. J. P i l l -
ing and H. B. Sun, [P173].
2. GRASP - Global Timing Analysis (Honeywell), M.
A. Wold [W078].
3. NELTAS - Network Delay Time Analysis Subsystem
(Nippon E l e c t r i c ) , T. Sasaki, et. a l . [SA81].
4. A C r i t i c a l Path Delay Check System - ( H i t a c h i ) ,
R. Kamikawai, et. a l . , [KA81]
Block O r i e n t e d Techniques
Block oriented analysis techniques are characterized
by programs ~hlch s t a r t with signals at given times
at Pls or at storage element outputs (note - the
times, when th~ signals are a v a i l a b l e at the storage
element outputs, w i l l depend on the time at which
the clocks permit data to be latched i n t o them). The
blocks, which these signals feed, are then processed
to f i n d the l a t e s t and/or e a r l i e s t time at which the
signal could propagate through them. The blocks are
processed so that the times at the output of each
block is calculated ( i d e a l l y ) once.
Block oriented analysis techniques tend to run much
quicker than enumerative path analysis techniques,
but tend to be very pessimistic. Whereas, a path
oriented algorithm can accept commands to ignore a
s p e c i f i c path, a block oriented algorithm cannot
without c u t t i n g many other paths at the same time.
The block oriented algorithm i d e n t i f i e s the worst
path leading up to each block (the c r i t i c a l path up
Paper 34.2
595
to t h a t p o i n t ) and then feeds t h a t i n f o r m a t i o n f o r - and standard d e v i a t i o n f o r the sum of independent
ward. Once the worst case delay or time has been random v a r i a b l e s i f they are assumed to s t a r t out
c a l c u l a t e d , the i d e n t i t y of any s p e c i f i c path caus- w i t h a "Gaussian" d i s t r i b u t i o n .
ing t h a t information to be what i t is has been l o s t .
The programs or papers describing systems which, f o r Considering the example (Figure 3), the s t a r t points
purposes of t h i s discussion, have been assigned to are defined as the set of PO's: (P01, P02, P03, a n d
the block o r i e n t e d category are: P04), and the terminal points as the set of PI~s:
( P I t , PI2, PI3, and PI4). The a n a l y s i s then i d e n t i -
f i e s a l l 32 paths (see Figure 4). As an example, we
I. PERT as an Aid to Logic Design - (IBM), T. I . w i l l focus on one of these paths, PII-A-B-C-H-P02.
K i r k p a t r i c k and N. R. Clark, [K166].
Pll - A - B - C - D - P01
2. SCALD Timing V e r i f i e r (Stanford), T. M. - H P02
-
McWilliams, [MC80]. G - H - P02
J - H - P02
PATH ENUMERATION TECHNIQUES - K - L - P03
- 0 - P - P04
C o m p u t e r - A i d e d Prediction of Delays in LSI Logic PI2 - A - B - C - D - P01
Systems - F a i r c h i l d and A m d a h l , D. J. Pilling and - H - P02
H. B. Sun, [PI73]. G - H - P02
J - H - P02
P i l l i n g and Sun [PI73] describe a program to take - K - L - P03
the d e s c r i p t i o n of the physical c i r c u i t s in a chip - 0 - P - P04
design (both before and a f t e r the physical masks had PI2 - E - B - C - D - P01
been designed) and c a l c u l a t e an estimated delay f o r - H - PO2
the c i r c u i t . This is then fed i n t o the simulation G - H - P02
program f o r more accurate simulation and, by l i s t i n g F - G - H - P02
the c i r c u i t s in a c r i t i c a l path, the t o t a l delays in - K - L - P03
t h a t path are determined. PI3 - E - B - C - D - P01
- H - P02
The delays predicted by t h i s approximation technique G - H - P02
are reported to be w i t h i n 5% of the delays measured F - G - H - P02
on actual c i r c u i t s under i d e n t i c a l conditions. - K - L - P03
PI3 - I - J - H - P02
The exact d e t a i l s of the method f o r determining the - K - L - P03
c r i t i c a l paths and adding up the delays is not de- - 0 - P - P04
scribed. One block in t h e i r Figure 7 i n d i c at es a PI4 - I - J - H - P02
process "Compute Total Delay A l o n g Signal Paths" - K - L - P03
where the path could be manually s p e c i fi e d or com- - 0 - P - P04
puter traced, we are not t o l d which. Since there is PI4 - M - J - H - P02
a great deal of ambiguity in t h i s , no attempt w i l l be - K - L - P03
made to show how the process would attack the simple - O - P - PO4
l o g i c diagram in Figure 3. N- L - P03
G R A S P (Global Timing A n a l y s i s ) - H o n e y w e l l , M. A . Figure 4 - BasicLogic Diagram Paths
Wold [W078].

The designer s p e c i f i e s the set of s t a r t points and
the set of terminal p o i n t s , as well as the boundary
values f o r path c l a s s i f i c a t i o n . GRASP enumerates
a l l possible paths from the set of s t a r t points to
the terminal points and c a l c u l a t e s the mean, MIN and
MAX delays of each. Paths are then c l a s s i f i e d as
"critical", " m a r g i n a l " , "normal", or " t r i v i a l " ac-
cording to the designer s p e c i f i e d values.
The delays are c a l c u l a t e d from the physical design
data by using l i n e a r approximation equations when
the physical design c o n f i g u r a t i o n s are w i t h i n the
c o n s t r a i n i n g parameters, and by "network s i m u l a t i o n "
(a Monte-Carlo a n a l y s i s of the behavior of the phys-
i c a l network, w i t h enough points taken to be able to
d e r i v e both a mean delay and a standard d e v i a t i o n
w i t h reasonable accuracy) when the r u l e s are not
met. The r e s u l t i n g delays include both a mean and
standard d e v i a t i o n .
For each path being evaluated, the mean path delay
is derived by t a k i n g the sum of the mean delays of
the blocks along the path. The standard d e v i a t i o n
of the path is c a l c u l a t e d by the root-sum-squared of
the standard d e v i a t i o n s of the blocks along the
path. This is the standard way to c a l c u l a t e the mean
In the program, the delay is a c t u a l l y calculated f o r
each block by looking at the d e t a i l e d d e s c r i p t i o n of
the physical design, but f or our purposes a delay
value has been assigned to each block in the path.
The delay values are w r i t t e n in the lower part of the
blocks. The means of these delays are,
r e s p e c t i v e l y , 2, 4, I , and 5. Adding these up, the
path nominal delay is 12. The sigma values f o r each
delay can be sizeable, the smaller delays often have
the l a r g e s t r e l a t i v e sigmas, so t h a t the i n d i v i d u a l
sigmas are assumed to be .3, .4, .2 and .45 respec-
tively. This y i e l d s an o v e r a l l sigma of .702, the
square r o o t of the sum of the i n d i v i d u a l sigmas
squared. For t h i s path, t h e r e f o r e , the t o t a l e f -
f e c t i v e (three-sigma) MAX delay is 14.1, the t o t a l
e f f e c t i v e MIN delay is 9.9. The o n l y remaining op-
e r a t i o n from t h i s p o i n t would be to categorize the
net as being c r i t i c a l , marginal, normal or t r i v i a l .
This would depend on the parameters set by the de-
signer using the program.
N E L T A S ( N e t w o r k D e l a y Time A n a l y s i s S u b s y s t e m ) -
Nippon Electric, T. Sasaki, et. al.
As described in [SA81], i t would appear t h a t , w i t h i n
each packaging l e v e l , the NELTAS programs evaluate

Paper 34.2
596
the paths from a PI or r e g i s t e r o u t p u t to a PO or r e - MAX MIN Current Trace-back
gister input. The d e l a y a n a l y s i s operates in two Block Mean Sigma Mean Sigma Block Input
modes: logical path mode where a l l p o s s i b l e paths
are enumerated, and each i s analyzed in d e t a i l , and 2 .3 2 3 H 2
critical path mode where a t each i n t e r m e d i a t e p o i n t 3 .35 3 35 G 2
the c h a r a c t e r i s t i c of the w o r s t path up t o t h a t 7 .532 6 5 F *
p o i n t i s d e t e r m i n e d , and whenever t h a t p o i n t is 8 .566 7 539
reached by another t r a c e , the c h a r a c t e r i s t i c o f the 11 .667 10 642
w o r s t path i s used, r a t h e r than t r a c i n g f u r t h e r . 4 .403 4 403
In logical p a t h mode, the o p e r a t i o n o f NELTAS would Now G can be c a l c u l a t e d from i t s i n p u t s (B and F),
be v i r t u a l l y i d e n t i c a l to Woldls GRASP system, w i t h and so on.
each path from s t a r t p o i n t to t e r m i n a l p o i n t being
t r a c e d and e v a l u a t e d . Since the p r e v i o u s s e c t i o n By e x t e n d i n g t h i s a n a l y s i s t o a l l o w f o r d i f f e r i n g
illustrated t h i s o p e r a t i o n , i t w i l l not be d u p l i - r i s i n g and f a l l i n g d e l a y s , the expansion a n d / o r con-
cated here. t r a c t i o n o f c l o c k pulses can be determined (see F i g -
In c r i t i c a l p a t h mode, the NELTAS process i s more of ure 2). Since c l o c k r e - p o w e r i n g networks u s u a l l y
a b l o c k o r i e n t e d approach in t h a t each i n t e r m e d i a t e are in the form o f an expanding t r e e s t r u c t u r e , the
p o i n t would have the w o r s t - c a s e (MIN and MAX) d e l a y MIN and MAX delays would be, f o r the most p a r t , the
t i m e c a l c u l a t e d only once. same and the main concern would be w i t h the com-
p r e s s i o n of pulse w i d t h s due t o the asymmetric d e l a y
The i n f o r m a t i o n r e g a r d i n g the d e l a y s d e r i v e d from values themselves.
the lower l e v e l s i s s t o r e d in a l i b r a r y f o r use by
the h i g h e r l e v e l a n a l y s i s r o u t i n e s . The s p e c i f i c A C r i t i c a l Path Delay Check System - H i t a c h i , R.
d e t a i l s of t h i s h i e r a r c h i c a l process were not p r e - K a m i k a w a i , et. al. [ K A 8 1 ] .
sented in [SA81].
In t h i s system, d e l a y checks are made a t each stage
To i l l u s t r a t e the c r i t i c a l path mode, a t r a c e back of the design process. Delays are approximated a t
from P01 w i l l be c o n s i d e r e d . To show what w o r s t case the e a r l y stages in the process, w i t h the a p p r o x i -
"means" and "sigmas" are known, a t a b l e o f blocks mations becoming more r e a l i s t i c as the design p r o -
w i t h known w o r s t cases w i l l be shown a f t e r each s i g - gresses t o the l a t e r stages. Although t h e r e i s an
nificant step in the a l g o r i t h m . The t r a c e would i n d i c a t i o n t h a t once the sub-network connecting a
proceed through blocks D and C, since they o n l y have s t a r t node to a t e r m i n a l node has been t r a c e d out,
one i n p u t each, and a t b l o c k B would f i r s t s e l e c t i n - the b l o c k s in t h a t sub-network are analyzed only
p u t 1, which comes from b l o c k A. In t h i s example, A once; t h e r e i s every i n d i c a t i o n t h a t a b l o c k may be
r e e v a l u a t e d every time i t appears in a sub-network.
i s fed d i r e c t l y from Pls so i t s o u t p u t mean and sigma T h e r e f o r e , t h i s a l g o r i t h m has been c l a s s i f i e d more
are also the w o r s t mean and sigma. as a path o r i e n t e d enumeration r o u t i n e than a b l o c k
oriented analysis routine.
MAX MIN Current Trace-back
Block Mean Sigma Mean Sigma Block Input The d e l a y check takes p a r t in several stages. The
s t a r t and end p o i n t s ( d e f i n e d by the user) are used
A 2 .3 2 .3 D I to guide the "path t r a c e " . The " p a t h t r a c e " i s s i m i -
C I l a r t o the standard w i r e - r o u t i n g maze-running a l g o -
B 1 rithm. I t extends the nodes in the forward and
A *(all) backward f r o n t i e r stage by stage unless:

a) the f r o n t i e r node i s a f l i p - f l o p
At each stage, a l l i n p u t s w i l l be t e s t e d . I f an i n -
put has had i t s value c a l c u l a t e d by a p r e v i o u s ac- b) the f r o n t i e r node goes no f u r t h e r , or
t i o n , i t s MIN (MAX) w i l l be used d i r e c t l y . At the
end o f the t r a c e b a c k from D, the t a b l e s w i l l be: c) the user c o n t r o l l e d maximum number o f f r o n -
t i e r s has been reached.
MAX MIN Current Trace-back
Block Mean Sigma Mean Sigma Block Input d) f o r purposes of t h i s d i s c u s s i o n , another
c o n d i t i o n has been borrowed from w i r i n g p r o -
A 2 .3 2 .3 D * grams: no node w i l l be i n c l u d e d in one f r o n t i e r
E 3 .35 3 .35 as a c a n d i d a t e f o r f u r t h e r e x t e n s i o n i f i t i s
B 7 .532 6 .5 a l r e a d y in the o t h e r one.
C 8 .566 7 .539
D 11 .667 10 .642 When an end p o i n t i s reached, a t r a c e back from i t to
the s t a r t p o i n t marks the nodes to be kept. The
To i l l u s t r a t e why t h i s i s so p o w e r f u l , c o n s i d e r the t u r n - o n and t u r n - o f f t r a n s i t i o n delays are then c a l -
t r a c e b a c k from P02. The f i r s t i n p u t from H comes culated for each net connecting the marked nodes.
from C which is a l r e a d y marked as being on the w o r s t
case l i s t , so the t r a c e goes d i r e c t l y to G. G's The problem then i s to f i n d the c r i t i c a l path. A l -
first i n p u t comes from B, another b l o c k a l r e a d y though the a l g o r i t h m i s o n l y h i n t e d a t , t h e r e i s an
marked as being on the l i s t , so i t s t r a c e goes d i - i n d i c a t i o n t h a t each node i s processed once - when
r e c t l y t o F. F's i n p u t comes from E which a l r e a d y the d e l a y time from the s t a r t node t o a l l nodes f e e d -
has i t s w o r s t case values c a l c u l a t e d , so F can be ad- ing i t have been d e t e r m i n e d . By t h i s means, the o u t -
ded d i r e c t l y to the l i s t : put o f the node being analyzed w i l l j u s t be i t s own

Paper 34.2
597
delay time plus the time of the maximal input (the
f i r s t input whose delay time equals or exceeds a l l PIt O ~
other inputs). When the maximum delay times f o r a l l
nodes have been determined, the maximum time f or the POl
end p o i n t w i l l be known. Determining the c r i t i c a l
path then corresponds to j u s t tr a c i n g back through
the maximal inputs feeding each node u n t i l the s t a r t
node ( f l i p - f l o p or PI) is reached.
To i l l u s t r a t e t h i s technique, we w i l l f i r s t select
PI3 as the s t a r t point and P02 as the end p o i n t . The
forward and backward f r o n t i e r s f o r the tr a c ing w i l l
be shown in two tables at each stage. The i n i t i a l
stage w i l l j u s t include the two primary connections:
PI3~ i P02

Forward F r o n t i e r Backward F r o n t i e r
Blocks I level Blocks 1 . level
PO3
PI3 0 P02 O

After tracing two levels from the start points, the

tables w i l l include the blocks d i r e c t l y connected to
PI3 and P02 and those connected one level further
back: P04
Forward Frontier BackwardFrontier
Blocks 1 level Blocks I level
Figure 5 - Result of Tracing Frontiers
PI3 0 P02 0
E, I 1 H 1
B, F, d 2 C, G,(J) 2
The entry (J) in the backward f r o n t i e r indicates
t h a t J could not be added to the t a b l e because i t a l -
ready was in the other t a b l e . I t t h e r e fo r e is a l i n k
between the two points. A f t e r one more step, the
backward f r o n t i e r can go no f u r t h e r , two a d d i t i o n a l
steps add the l a s t two l e v e l s to the forward f r o n -
tier:
Forward F r o n t i e r Backward F r o n t i e r Figure 6 - PERT Model for the Basic Logic
Blocks I level Blocks I level Diagram: To model the Basic Logic
Diagram, each block becomes a
PI3 0 P02 O NODE, and a START and END node
E, I 1 H 1 must be added.
B, F, J 2 C, G,(J) 2
(C) ,(G),K,O 3 (B) ,(F) 3 " t w o - r a i l " model of the logic designx. As described
L, P 4 in t h e i r a r t i c l e , i t would seem that to be able to
P03, P04 5 analyze for s t a t i s t i c a l a r r i v a l times on the c r i t -
ical path, one had to f i r s t know, for each gate,
After tracing from the connection points back to the whether the turn-on or t u r n - o f f delay was to be used
o r i g i n a t i o n points and marking the blocks one passes (or select the worst of the two delays) 2. The as-
through, a graph of marked blocks is produced con- sumption was also made that processing for
s i s t i n g of blocks B, C, E, F, G, H, I , and J (see worst-case values should be dependent on the logic
Figure 5 ). At t h i s p o i n t , the delays f o r the marked function of a gate ( l a t e s t at an AND, e a r l i e s t at an
blocks would be calculated and then the analysis of OR).
the sub-network would f i n d the c r i t i c a l path. Since
no e x p l i c i t algorithm was described, one can j u s t More recent analysis [MC80, HI82a] indicates that
p o i n t to the analysis in the previous section as one when looking for the worst-case late a r r i v a l time,
way in which t h i s could be accomplished. the function is irrelevant. All that is important
is the inverting properties of a functional element
and the individual turn-on and t u r n - o f f delays.
BLOCK ORIENTED TECHNIQUES
PERT as an Aid to Logic Design - IBM, T. I. K i r k - x A two-rail design is one where each signal and
patrick and N. R. Clark, [KI66] i t s compliment are computed independently by
complementary logic to avoid the need for extra
inverters. A two r a i l model would represent
Kirkpatrick and Clark [K166] describe a way to apply each block by two, one to take into account the
the PERT project scheduling tool to aid in analyzing rising signal and the other to take into account
logic designs for proper timing. Although the po- the f a l l i n g signal, each with i t s own delay.
t e n t i a l for selecting the worst a r r i v a l time (com- 2 I t should be remembered that at the time this
pletion time, in PERT's terminology) is there, the report was written, there was not the great dis-
a b i l i t y to handle two sets of delays ( f o r turn-on parity between rising and f a l l i n g delays in
and turn-off) would have required a, so-called, high-speed c i r c u i t s that there is today.

Paper 34.2
598
T y p i c a l l y , the information being handed to PERT is
the nominal, best-case and worst case time f o r com-
p l e t i o n of a tasK. For example, i f one is analyzing
the time i t would take to b u i l d a house, one task
could be the time i t takes to b u i l d concrete forms,
another could be the time i t takes to f i l l the forms
with concrete, a t h i r d could be the time i t takes the
concrete to dry, and so on. Note t h a t with respect
to the concrete hardening task, the other two tasks
would have had to be done ( i n order) before i t could
even s t a r t . K i r k p a t r i c and Clark consider a task to
be the time i t takes a signal t r a n s i t i o n to propa-
gate from the output of one block to the output of
the block i t feeds. See Figure 6 fo r the PERT model
of the Basic Logic Diagram.
One way to analyze a PERT model is to l e v e l i z e the
nodes (as we often l e v e l i z e l o g i c blocks in Design
Automation programs - a block is in level k i f the
maximum number of blocks back to a PI from that block
is k) and then process the blocks in level order:
f i r s t the blocks in level 1, then the blocks in level
2, and so on. K i r k p a t r i c k and Clark were p r i m a r i l y
interested in f i n d i n g the c r i t i c a l l y long paths, so
the analysis would have calculated the mean and sig-
ma f o r the MAX path from the START node.
Thus, blocks (nodes) being fed by the PI blocks of
Figure 6 w i l l have a worst case a r r i v a l time ( i n
PERT's terminology, t h i s is j u s t the "completion
time ,I ) equal to the time i t takes to get through the
block ("complete i t s task") plus the maximum a r r i v a l
time of any ]mary" input (which w i l l a l l be assumed
to be zero).PrBlock B, which has one input at time
two and the other at time three, is t y p i c a l of other
blocks in the f i g u r e . Three is greater, the i n t e r -
nal delay is four, therefore seven is the maximum
output a r r i v a l time f o r t h i s block. Thi~ is s i m i l a r
to the critical path analysis calculations shown to
describe the operation of NELTAS.
These calculations y i e l d the outputs of blocks D, H,
L and P, at times eleven, thirteen, nine and nine,
respectively.
SCALD Timing Verifier - Stanford, T. M.
McWilliams, [MC80].
The structure is presented to the Timing V e r i f i e r by
other programs in the SCALD ( Structured
Computer-Aided Logic Design, [MC78]) system along
with models f o r each wire or component and any de-
signer specifed overrides to wire delays.
What d i f f e r e n t i a t e s the Scald Timing V e r i f i e r from
the ordinary simulator is the extension of the simu-
l a t i o n algebra to contain the values STABLE, (a sig-
nal would be at the correct value, e i t h e r ZERO or
ONE) and CHANGING (the signal would be p o t e n t i a l l y
changing from one stable value to another but be un-
stable during t h i s time period)[MC80]. Using these
values, the designer is able to specify the equiv-
a l e n t of many combinations of input values by simply
d e f i n i n g them to be STABLE at a c e r t a i n time. Like-
wise, the timing checks f o r storage elements,
r e g i s t e r s , and the l i k e are in terms of a comparison
of the active time of the clock with the STABLE time
of the input data signal.
The evaluation tables are defined so that the most
dominant value is U (Undefined), with CHANGINGoften
running a close second. I f a l l inputs are defined
(non-U), then i f any input is CHANGING, the output
may be CHANGING. The exception to t h i s rule f o r an
OR, f o r example, is that a ONE on any input w i l l
force the output to be a ONE regardless of what the
other inputs do. Thus, f o r an OR, ONE dominates the
other inputs. S i m i l a r l y , a ZERO at any input of an
AND block dominates the other inputs. An
"exclusive-OR" block, on the other hand, has no sin-
gle value which dominates the others, and the
evaluation tables shown in [MC80] i n d i c a t e t h i s .
Thus, in the absence of a dominating signal, the
output of a block w i l l be CHANGINGat time t as long
as any of i t s inputs was CHANGINGat time t minus the
c i r c u i t delay. This means t h a t i f several inputs to
a block go from being CHANGINGto STABLE and back to
CHANGING, then the output w i l l not s t a r t being STA-
BLE u n t i l the l a s t input becomes STABLE (plus the
delay of the c i r c u i t ) and w i l l i n d i c a t e p o t e n t i a l
CHANGING when the f i r s t input indicates i t is CHANG-
ING (plus the c i r c u i t delay). Note that t h i s means
t h a t the leading edge of the STABLE time w i l l be the
maximum time at which any input signal becomes sta-
ble, and the t r a i l i n g edge w i l l become CHANGING at
the minimum time when any input signal becomes
CHANGING.
The use of "signal assertions" allows the designer
to drive portions of the logic, for which the d r i v -
ing c i r c u i t r y has not yet been completely designed,
and permits the driving c i r c u i t r y to be checked when
i t is f i n a l l y completed. A "signal assertion" is a
way of coding the timing f o r a clock or of asserting
the time during which a signal is expected to be STA-
BLE. The coding is appended to the end of the signal
name which f a c i l i t a t e s d i s p l a y i n g i t on the hardcopy
output of SCALD. Undefined signals, with no as-
sertions, are taken to be always STABLE to avoid
spurious timing e r r o r messages.
Timing checks are done by special blocks which check
setup times, hold times, and minimum pulse width
times. These blocks may be entered by the designer,
but more often they are added to the design by the
expansion of macro blocks used to c a l l out latches,
r e g i s t e r s or e n t i r e RAM's.
Due to the pessimistic nature of t h i s analysis, the
occurrence of unbalanced designs can cause the anal-
y s i s to p r e d ic t p o i n t - t o - p o i n t delays l a r g e r or
smaller than permitted. When these conditions are
i d e n t i f i e d , "case a n a ly s is " is used to introduce
some realism into the pessimistic analysis. For ex-
ample in Figure 7, taken from [MC80], the
pessimistic analysis would p r e d i c t the shortest path
to be 20ns and the longest to be 40ns. In f a c t , re-
gardless of which s p e c i f i c value is assigned to CTL,
the delay fromA to B w i l l always be 30ns.
~
lOns pat h l ~ [
20ns p a t h ~ I
CTL t-
Figure 7 - Case Analysis Example
Assuming these extremes (20ns and 40ns) cause annoy-
ing erroneous diagnostics, two cases are set up, the
f i r s t sets CTL to ZERO, the second sets i t to ONE.
( I f the extremes cause no extraneous diagnostics,
they can be ignored.) In each case, one path is ana-
lyzed and the other is ignored. The result is a more
accurate analysis (removing only enough ambiguity to
eliminate the erroneous diagnostics), without having
Paper 34.2
599
to go to the opposite extreme where a l l possible ZE-
RO and ONE patterns at the P l ' s are t r i e d to insure
proper timing.
To parallel the results to be shown for the Timing
Analysis i n i t i a l results, the PI assertions w i l l a l l
be OS (STABLE starting at time t=O).
The r e s u l t of processing the blocks fed d i r e c t l y by
these primary inputs w i l l be derived assertions f o r
Blocks A, E, I , and M (see below). Since we are as-
suming t h a t the signals are CHANGINGu n t i l the f i r s t
assertion that they are STABLE, t h i s means t h a t in
c a l c u l a t i n g the derived assertion f o r each block,
several choices w i l l have to be made. At block B, at
le a s t one input remains CHANGING u n t i l time 3, so
i t s output cannot become STABLE u n t i l time 7. Simi-
l a r l y , block J cannot become STABLE u n t i l time 3.
As indicated, the Timing V e r i f i e r does not do sta-
t i s t i c a l c a l c u l a t i o n s , so the times shown represent
the mean r e s u l t . S i m i l a r c a l c u l a t i o n s f o r the re-
maining blocks give assertions as f o l l o w s :
Signal Derived
Name Assertion
. . . . . . . . . . . . . . . . . . . . . .
A $2
B S7
C $8
D $11
E $3
F $4
G $8
H $13
where Sn means STABLE s t a r t i n g at t=n
Note, t h a t although the r e s u l ts here are rather
s t r a i g h t - f o r w a r d , the Timing V e r i f i e r has many more
sophisticated features incorporated in i t . Checks
are made to be sure t h a t clock pulse widths are main-
tained. Checks are made at special blocks to be sure
t h a t data signals are STABLE during c r i t i c a l por-
ti o n s of clock signals ( e s p e c i a l l y during the setup
and hold time periods). And, as mentioned before,
the use of signal assertions allows the designer to
specify what is a n t i c i p a t e d to come out of a y et un-
completed p o rt i o n of the design, and l a t e r on use
the same assertions to check to be sure t h a t what was
expected a c t u a l l y occurred.
III TIMING ANALYSIS IBM, R. B. HITCHCOCK,
G. L. SMITH, AND D. D. CHENG, [HI82A].
Timing Analysis (TA) is a design automation program
t h a t assists computer design engineers in l o c a t i n g
problem timing in a clocked, sequential machine.
The program is e f f e c t i v e fo r large machines because,
in part, the running time is p r o p o r t i o n a l to the
number of c i r c u i t s . Thus, in comparing with what
has been discussed p r e v i o u s l y , the Timing Analysis
program is a b l o c k - o r i e n t e d algorithm. What d i s t i n -
guishes i t from the others is t h a t the output of
Timing Analysis includes slack at each block as a
measure of the s e v e r i t y of any timing problem. The
program also generates standard d e v i a t i o n s f o r the
times so t h a t a s t a t i s t i c a l timing design can be
produced rather than a worst case approach. This
system has successfully detected a l l but a few tim-
ing problems f o r the IBM 3081 system ( c o n sis t ing of
over 700K c i r c u i t s ) p r i o r to the hardware debugging
of timing. The 3081 system is characterized by a
t i g h t s t a t i s t i c a l timing design.
Paper 34.2
600
THE TIMING ANALYSIS CONCEPTS
Timing Analysis is a program which establishes
whether a l l paths w i t h i n th~ design meet stated tim-
ing c r i t e r i a , t h a t is , t h a t data signals a r r i v e at
storage elements e a r l y enough f o r v a l i d gating but
not so e a r l y as to cause premature gating (see Fig-
ure 1). The output of the TA program not only iden-
tifies any l o g i c with timing problems, but also
provides slack as a measure of the s e v e r i t y of each
problem. By t r e a t i n g the delays s t a t i s t i c a l l y , TA
permits the creation of a design with a shorter
clock cycle than would a worst case analysis.
As with the other programs mentioned e a r l i e r , t h e
program does not require the input of a set of t e s t
patterns, nor does i t overlook paths because pat-
terns were omitted. In a d d i t i o n , the program pro-
vides a mechanism, using delay modifiers, to a l t e r
the propagation c h a r a c t e r i s t i c s of i n d i v i d u a l blocks
when i t is known t h a t l o g i c causes paths to never be
sensitized or to c o r r e c t l y analyze abnormal timing
c r i t e r i a (such as a two-cycle path).
Signal Derived In order to apply the TA program, the design must be
Name Assertion a synchronous, sequential machine and i t must be
. . . . . . . . . . . . . . . . . . . . . .
possible to associate e x p l i c i t clock times with each
I Sl storage element.
J $3
K $8 THE TA BLOCK-ORIENTED ALGORITHM
L $9
M $2 Our d e s c r i p t i o n of the basic algorithm assumes t h a t
N $5 the analysis is t r y i n g to generate l a t e signals,
0 $8 t h a t is , we are looking f o r long paths. Figure 3
P $9 shows a simple example of combinational l o g i c which
serves as a basis f o r the discussion.
The lower por t ion of Figure 8 contains a key d e f i n -
ing the three values associated with each of the
blocks on the diagram. For t h i s p o r t i o n of the de-
s c r i p t i o n , the c a l c u l a t i o n w i l l be l i m i t e d to the
mean delays associated with the block and the c r i t -
i c a l paths. For example, only one delay D is shown
f o r a block, rather than one f o r r i s i n g and one f o r
falling transitions. The number, AT, w r i t t e n be-
neath the output of each block, is the maximum
a r r i v a l time ( i n whatever units of time are chosen
as a p p r o p r ia t e ) . The primary input (PI) a r r i v a l
times and the primary output (PO) required a r r i v a l
times, which are normally derived from clock a r r i v a l
times, are assumed to be e x p l i c i t l y given. The
slack S is discussed subsequently.
The blocks are processed by Timing Analysis in an
order f u n c t i o n a l l y e q u i v a l e n t to the l e v e l i z i n g or-
der mentioned in the discussion of NELTAS so t h a t i t
is guaranteed that every input feeding a block w i l l
have i t s a r r i v a l time defined before the block i t -
s e l f is processed. The a r r i v a l time of a block is
computed by:
Establishing the a r r i v a l time at the block out-
put f o r each input to the block by propagating
each input signal through the block delay,
Selecting the maximum such a r r i v a l time.
These c a l c u l a t i o n s are i d e n t i c a l to the ones i l l u s -
t r a t e d under the section describing PERT and y i e l d
the outputs of blocks D, H, L and P, at times eleven,
t h i r t e e n , nine and nine, r e s p e c t i v e l y . Note t h a t we
have e x p l i c i t l y stated a required a r r i v a l time of
ten f or a l l the outputs. This means t h a t two signals
are l a t e and two signals are e a r l y .
At t h i s p o i n t , we d e f i n e the s l a c k S as the d i f f e r -
ence between the r e q u i r e d a r r i v a l time and the a c t u -
al a r r i v a l t i m e . The s l a c k value i s computed so t h a t
a n e g a t i v e number i n d i c a t e s a problem; t h a t i s , the
s i g n a l i s too l a t e . The o u t p u t o f b l o c k D a r r i v e s a t
time eleven, one u n i t l a t e ( s l a c k = - 1 ) . Block H i s
t h r e e u n i t s l a t e ( s l a c k = - 3 ) ; b l o c k L is one e a r l y
( s l a c k = +1); and P i s t h r e e e a r l y ( s l a c k = +3). The
+I +I
P14 --~ 10
KEY
D = Block Delay
S
S = Slack
AT
AT = Arrival Time.
Figure 8 - Basic Diagram with Delays, Arrival
Times and Slacks
s l a c k i n f o r m a t i o n i s then propagated back through
the b l o c k graph, w i t h a l l blocks being reprocessed
in o r d e r o p p o s i t e t o t h a t used f o r g e n e r a t i o n of the
arrival times.
When each b l o c k i s processed in the backward d i r e c -
t i o n , the slacks are computed f o r the sources f o r
each i n p u t , one a t a t i m e . For example, b l o c k D has
a d e l a y o f t h r e e and a r e q u i r e d a r r i v a l time a t i t s
o u t p u t of ten; t h e r e f o r e , the r e q u i r e d a r r i v a l time
a t i t s i n p u t i s seven ( t h e o u t p u t r e q u i r e d a r r i v a l
time minus the i n t e r n a l d e l a y ) . With r e s p e c t t o
t h i s b l o c k , the o u t p u t o f b l o c k C i s one u n i t l a t e ,
so the s l a c k i s minus one. Block H has a d e l a y o f
f i v e , so the r e q u i r e d a r r i v a l time a t i t s i n p u t s i s
f i v e , and the s i g n a l feeding from b l o c k C i s t h r e e
u n i t s l a t e . Three u n i t s l a t e ( s l a c k = - 3 ) i s worse
than one u n i t l a t e , so the program s t o r e s the most
n e g a t i v e value ( - 3 ) a t the o u t p u t o f b l o c k C. The
slack value s t o r e d a t the o u t p u t of the b l o c k c o r r e -
sponds t o the s l a c k value f o r the w o r s t path going
though t h a t b l o c k .
Note t h a t each b l o c k i s processed once f o r w a r d and
once backward; t h e r e f o r e , the process runs in a time
p r o p o r t i o n a l to the number o f b l o c k s . Note a l s o ,
t h a t in a d d i t i o n t o c a l c u l a t i n g the a r r i v a l time f o r
the w o r s t path to a b l o c k , we have a l s o c a l c u l a t e d a
measure o f how bad t h a t path i s .
From Figure 8, one can observe a f u n n e l i n g o f nega-
t i v e s l a c k values through b l o c k B. I f B c o u l d be r e -
placed by a c i r c u i t having a s m a l l e r d e l a y , a l l the
n e g a t i v e slacks could be e l i m i n a t e d w i t h o u t changing
the f u n c t i o n a l design a t a l l . C l e a r l y , t h e r e are
also alternative techniques for resolving this tim-
ing problem.
In a d d i t i o n , n o t i c e t h a t t h e r e are many b l o c k s w i t h
positive slacks. These blocks could use c i r c u i t s
w i t h increased d e l a y and s t i l l be w i t h i n the t i m i n g
c o n s t r a i n t s [AG77, RU77].
I f we are looking f o r e a r l y s i g n a l s caused by short
paths, the above procedures are modified s l i g h t l y .
The a r r i v a l time o f a block is based on the minimum
a r r i v a l time o f any input to the block ( r a t h e r than
the maximum). The d e f i n i t i o n o f slack is set up so
t h a t once again a negative slack i n d i c a t e s a
problem; t h a t i s , the signal is too e a r l y . The r e a -
son f o r changing t h i s d e f i n i t i o n was based on a
human f a c t o r c o n s i d e r a t i o n , i t i s e a s i e r to spot a
negative number in a column o f p o s i t i v e numbers than
to spot a p o s i t i v e number in a column o f negative
numbers, and i t is more c o n s i s t e n t to say t h a t a neg-
a t i v e slack always i n d i c a t e s a problem.
- - RD= Delay if output
is rising
(RD,FD) FD: Delay if output
is falling
(RA,FA) RA= Rising Arrival
Time
FA = Falling Arrival
Time
2, 3) •
7, 4)
I, D) 3, 4)
8,12)
o, o) 2, 5)
Figure 9 - Using Rising and Falling Delays
Figure 9 shows how the Timing A n a l y s i s program j u s t
d e s c r i b e d can a l s o handle r i s i n g and f a l l i n g delays
and the i n v e r t i n g p r o p e r t i e s o f a b l o c k w i t h o u t r e -
q u i r i n g the " t w o - r a i l " model mentioned e a r l i e r in
the d i s c u s s i o n o f PERT. As the key a t the top of
Figure 9 i n d i c a t e s , the f i r s t number i n s i d e the
b l o c k i s the d e l a y i f the o u t p u t i s r i s i n g ; the sec-
ond number i s the d e l a y i f the o u t p u t i s f a l l i n g ; and
the a r r i v a l times are kept in a t w o - t u p l e w i t h the
r i s i n g a r r i v a l time in the f i r s t p o s i t i o n and the
falling arrival time in the second p o s i t i o n . The
f a c t t h a t b l o c k 2 i n v e r t s i s i n d i c a t e d by the t r i a n -
g u l a r wedge symbol a t i t s o u t p u t . This means t h a t
the r i s i n g o u t p u t w i l l be the g r e a t e r o f the two
falling i n p u t s ( a t times t h r e e and f o u r ) plus the
b l o c k d e l a y ( t h r e e ) , so t h a t the r i s i n g a r r i v a l time
w i l l be seven. The f a l l i n g o u t p u t w i l l be the g r e a t -
er of the two r i s i n g i n p u t s ( a t times two and t h r e e )
plus the d e l a y ( o n e ) , so the f a l l i n g a r r i v a l time
w i l l be f o u r . The same c a l c u l a t i o n can be done f o r
each of these blocks so t h a t we can compute the r i s -
ing and f a l l i n g p r i m a r y o u t p u t a r r i v a l time o f e i g h t
and t w e l v e , r e s p e c t i v e l y . Note t h a t i f ten were the
r e q u i r e d a r r i v a l time f o r both the r i s i n g and f a l l -
ing a r r i v a l times, one would be e a r l y and the o t h e r
Paper 34.2
601
late. For t h i s reason the TA diagnostics d i s t i n -
guish between block output "wising and f a l l i n g
a r r i v a l times, not j u s t between blocks.
The calculation of a r r i v a l times also includes sta-
t i s t i c s . As indicated e a r l i e r , each block delay ac-
t u a l l y consists of two values - a mean delay and a
delay standard deviation (sigma). The calculation
of a r i s i n g or f a l l i n g a r r i v a l time at each block of
the model involves the calculation of a mean a r r i v a l
time and an a r r i v a l time sigma. Mean a r r i v a l times
are computed by simply adding block mean delays to
previous mean a r r i v a l times. The a r r i v a l - t i m e sig-
mas are computed by applying standard convolutions.
The a r r i v a l time actually stored at a block output
is the r e s u l t of propagating one of the input ar-
r i v a l times through the block. When the TA program
is looking for long paths, the one selected is the
one having the l a t e s t output a r r i v a l time. The l a t -
est a r r i v a l time is the one for which the expression
+ Bo where ~ = nominal a r r i v a l time
B = confidence l e v e l , p r o v i d e d by
the d e s i g n e r
o = a r r i v a l time sigma
i s the g r e a t e s t . This e x p r e s s i o n i s used t o compute
an a r r i v a l time whenever one i s to be p r i n t e d o r a
s l a c k i s to be computed. Conclusions about the
probability o f a t i m i n g f a i l u r e can be drawn from
the c o n f i d e n c e l e v e l under the assumption t h a t the
distributions are Gaussian. When the program i s
l o o k i n g f o r s h o r t p a t h s , the e x p r e s s i o n i s m o d i f i e d
by r e p l a c i n g the plus sign w i t h a minus s i g n .
THE T I M I N G A N A L Y S I S SYSTEM
A complete TA model c o n s i s t s o f the c o m b i n a t i o n a l
l o g i c , the storage elements, and the c l o c k s .
The c l o c k s are d e f i n e d using two b a s i c t i m e i n t e r -
v a l s , the propagate time and the compare time (see
Figure 10). The propagate time i s d e f i n e d so t h a t
the storage elements, which t r i g g e r the o r i g i n a t i o n
o f data s i g n a l s based on the times a t which the c l o c k
a r r i v e , w i l l know a t what time and in what time p e r i -
od the p r o p a g a t i o n should s t a r t . The compare time
i s d e f i n e d so t h a t the storage element w i l l know
when t o expect data s i g n a l s ~o a r r i v e a t i t s i n p u t s .
Figure 10 a l s o shows two storage elements, A and B,
and some c o m b i n a t i o n a l l o g i c connecting them i n t o a
loop. Clock 1 (C1) gates storage element A, and
c l o c k 2 gates storage element B. The propagate and
compare times are shown in the lower h a l f o f the f i g -
ure. The path from A to B and the path back from B
to A can be checked in the same Timing A n a l y s i s run
w i t h o u t r e q u i r i n g a s p e c i a l t e s t - f o r each of the se-
parate loops; the only requirement is a lem paths. This follows from the TA approach which
specification of the clocks in a consistent manner
so that the signals resulting from the propagate
time from CI w i l l be compared with the compare time
of C2, and the signals resulting from the propagate
time of C2 w i l l be comparedwith the compare time for
C1.
To f a c i l i t a t e the rapid analysis of the TA results,
an i n t e r a c t i v e analysis program is included in the
TA system (see Figure 11):
Timing Analysis Results Analyzer [Ht82b]
The c h i e f elements o f the TARA (TA Results A n a l y z e r )
p o r t i o n o f TA are the use o f a non-APL s o f t w a r e pag-
ing system, APL ( f o r r a p i d a l g o r i t h m i c d e v e l o p m e n t ) ,
Paper 34.2
602
a f u l l screen manager, and a 618 storage tube w i t h
GRAPHPAK used t o draw r e l a t e d f i g u r e s .
The i n - c o r e formats from the Timing A n a l y s i s program
are placed in a s o f t w a r e paging space f o r l a t e r ac-
cess. This process i s done w h i l e the r e g u l a r batch
j o b i s r u n n i n g , and removes the need t o produce a de-
CI LOGIC...(S.~E.) ,-.LOGIC~
(S. E.)
C2
C1propagate~ .
I . L__
C1compare
.L_ . . . . . .
C2propagate
C2compare
Figure 10 - Clock Descriptions
t a i l e d summary o f the t i m e s , come-froms, and g o - t o s
f o r each b l o c k ( t h i s can be q u i t e e x t e n s i v e f o r
large block graphs).
The data ( s t o r e d e a r l i e r ) i s then accessed by an
auxiliary p r o c e s s o r w r i t t e n to i n t e r f a c e w i t h the
s o f t w a r e paging package and r e f o r m a t the accessed
data i n t o APL v a r i a b l e f o r m a t s .
The e x t r a c t e d data i s i n t e r r o g a t e d by APL programs
which do the more mundane f u n c t i o n s o f name o r index
s e a r c h i n g , r e f o r m a t t i n g of numbers t o be d i s p l a y e d
and f i e l d i n g of user r e q u e s t s .
The b l o c k s e x t r a c t e d are d i s p l a y e d using the same
techniques used by the r e p o r t g e n e r a t i o n a l g o r i t h m s
w i t h i n Timing A n a l y s i s so t h a t the r e s u l t s may be
compared d i r e c t l y to any l i s t i n g s t h a t have been ob-
tained.
Completeness
As with the other techniques j u s t described, TA pro-
gram is a complete system in the sense that a l l paths
are potential candidates for i d e n t i f i c a t i o n as prob-
views storage elements as special functions and i g -
nores the actual Boolean properties of other logic
blocks with the exception of t h e i r inverting proper-
ties.
There may be p a t h s , however, which are i d e n t i f i e d as
problem paths by TA which can never be s e n s i t i z e d by
l o g i c o r which meet s p e c i a l t i m i n g c r i t e r i a a t the
path o u t p u t s . One such example was shown in the d i s -
cussion o f the SCALD Timing V e r i f i e r . Another exam-
p l e o f a s p e c i a l t i m i n g c r i t e r i a i s r e p r e s e n t e d by
the s o - c a l l e d t w o - c y c l e path in which the path from
one s t o r a g e element t o another exceeds one c y c l e
t i m e b u t l o g i c always ensures t h a t two machine cy-
c l e s are a v a i l a b l e f o r data t o propagate through the
path. By inserting delay modifiers at the inputs to
selected blocks of the block model, one can e f f e c -
t i v e l y block the propagation of a r r i v a l times or
a d j u s t a r r i v a l times by f i x e d constants ( e . g . , minus
one cycle f o r the two cycle path). These delay modi-
f i e r s are placed in the model based upon an
understanding of the l o g i c . The m o d i f i c a t i o n s im-
p l i e d are handled during the delay e x t r a c t i o n
p o r t i o n of the basic block a l g o r i t h m of TA.
I SelectLogicto be Analyzed I
I' CalculateDelays
I Bui,d Mode,s
~r"'User
Controls
~J~ Run Timing
~ Analysis
I ti User II]I ~
User
O=el
Figure 11 - Timing Analysis System
In c e r t a i n cases, i t may not be p o s s i b l e to place de-
lay m o d i f i e r s in a model w i t h o u t having an undesira-
ble e f f e c t on other paths. For example, i t may not
be possible to locate any block pin where the place-
ment of a delay m o d i f i e r w i l l not adversely e f f e c t a
non-two-cycle path. I t is then necessary to make
one or more extra runs in which delay m o d i f i e r s are
set to d i f f e r e n t values.
Due to the use of a software paging system, i t is
possible to handle very large (over 100,000
c i r c u i t s ) models in a single run. I f , f o r reasons
d i c t a t e d by machine a v a i l a b i l i t y , a model is too
large to process in a single run, i t is broken up in-
to more manageablepieces and the values computed at
the primary outputs (inputs) of one piece are saved
and automatically fed to the primary inputs
(outputs) of the other pieces to which i t is con-
nected. Thus, the total analysis is the same as i f
the whole model were processed at once.
TIMING ANALYSIS A P P L I C A B I L I T Y
There are three main concerns in evaluating the ap-
p l i c a b i l i t y of the timing analysis method. These
were described in detail in [HI82a] and can be sum-
marized as:
• The accuracy of the answers are only as good as
the accuracy of the delays c a l c u l a t e d f o r each
b l o c k , and upon the assumption t h a t the delays
can be combined as one would f o r Gaussian d i s -
tributions.
• Analyzing a path s t a t i s t i c a l l y is not the same
as analyzing a machine s t a t i s t i c a l l y . What we
r e a l l y want is the p r o b a b i l i t y t h a t the machine
produced w i l l be free of t i m i n g problems. What
we have c a l c u l a t e d i n d i c a t e s t h a t each path w i l l
be w i t h i n the desired bounds, w i t h a c e r t a i n
probability.
I • Delay m o d i f i e r s can be used, and abused. They
are necessary, as was i n d i c a t e d e a r l i e r , to cut
paths t h a t w i l l never be a c t i v e or to a d j u s t de-
1 lays for "two-cycle ~ paths. However, inserting
them is a manual process, and the fewer times
] they have to be inserted, the more l i k e l y the
design w i l l be t r u l y free of timing problems.
Timing Analysis is a b l o c k - o r i e n t e d a l g o r i t h m which
e f f e c t i v e l y checks a l l paths by computing output a r -
r i v a l times and provides a measure of on-timeness by
computing slacks f o r each block. The TA program
does i t s c a l c u l a t i o n s using s t a t i s t i c a l approxi-
mations and provides methods f o r d e a l i n g w i t h l o g i c
w i t h special timing problems.
IV SUMMARY AND CONCLUSIONS
Timing V e r i f i c a t i o n , the v a l i d a t i o n of path delays
and the checking of clock pulse w i d t h s , can be ac-
complished by path o r i e n t e d and block o r i e n t e d tech-
niques. The path o r i e n t e d techniques, which
enumerate paths, tend to run considerably longer
than the block o r i e n t e d or non-enumerative path
methods, due to the explosive growth in the number
of paths as the number of blocks in the design i n -
creases.
Several of the previous techniques have been de ~
scribed along with b r i e f i l l u s t r a t i o n s showing how
they would apply to a s i n g l e problem.
A d d i t i o n a l l y , the Timing Analysis approach has been
described in some d e t a i l as a method which not only
u t i l i z e s the less time consuming block o r i e n t e d
method f o r a n a l y s i s , but also provides a new mech-
anism ( s l a c k c a l c u l a t i o n ) f o r h i g h l i g h t i n g a l l prob-
lems w i t h i n a design.
V ACKNOWLEDGMENTS
Many people have c o n t r i b u t e d to the Timing Analysis
p r o j e c t since i t s i n c e p t i o n in 1973. In the e a r l y
f o r m u l a t i o n of the ideas, R. Bahnsen, W. Donath and
G. L. Smith were major c o n t r i b u t o r s . In helping to
design a working program, D. D. Cheng, G. L. Smith
and H. Ofek c o n t r i b u t e d h e a v i l y . I t is not possible
to name a l l the many others on the 3081 p r o j e c t and
in the design automation (EDS), and technology areas
who c o n t r i b u t e d to TA.
Vl REFERENCES
B. J. Agule, J. D. Lesser, A. E. Ruehli, and
[AG77]
P. K. Wolff, Sr., "An Experimental System
for Power/Timing Optimization of LSI Chips,"
Proceedings of the 14th Design Automation
Conference, New Orleans, (pp 147-152), 1977.
Paper 34.2
603
[DO81] W. E. Donath and R. B. Hitchcock, Sr.,
"Method for determining the characteristics
of a logic block graph diagram to provide an
indication of path delays between the
blocks," U. S. Patent No. 4,263,651, April
1981.
[H182a] R. B. Hitchcock, G. L. Smith, and D. D.
Cheng, "Timing Analysis of Computer
Hardware," IBM Journal of Research and De-
velopment, Vol. 26, No. i , (pp 100-105),
1982.
[H182b] R. B. Hitchcock, B. L. Keller, E. Kellerman,
J. F. Schroeder, and A. M. Stankosky, "Tim-
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[KA81] R. Kamikawai, M. Yamada, T. Chiba, K. Furu-
maya and Y. Tsuchiya, "A C r i t i c a l Path Delay
Check System," Proceedings of the 18th De-
sign Automation Conference, Opryland, (pp
118-123), 1981.
[K166] T. I. Kirkpatrick and N. R. Clark, "PERT as
an Aid to Logic Design," IBM Journal of Re-
search and Development, Vol I0, No. 2, (pp
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[MC78] T. M. McWilliams and L. C. Widdoes J r . ,
,,J458
"SCALD: Structured Computer-Aided Logic De-
sign," Proceedings of the 15th Design Auto-
mation Conference, Las Vegas, (pp 271-277),
1978.
[MC80] T. M. McWilliams, " V e r i f i c a t i o n of Timing
Constraints on Large Digital Systems," Pro-
ceedings of the 17th Design Automation Con-
ference, Minneapolis, (pp 139-147), 1980.
[P173] D. J. P i l l i n g , and H. B. Sun, "Computer -
Aided Prediction of Delays in LSI Logic Sys-
tems," Proceedings of the lOth ACM/IEEE De-
sign Automation Workshop, Portland, Oregon
(pp 182-186), 1973.
[RU77] A. E. Ruehli, P. K. Wolff, Sr., and G.
Goertzel, "Analytical Power/Timing Opti-
mization Technique for Digital Systems,"
Proceedings of the 14th Design Automation
Conference, New Orleans, (pp 142-146), 1977.
[SA81] T. Sasaki, A. Yamada, T. Aoyama, K Hasegawa,
S. Kato and S. Sato, "Hierarchical Design
V e r i f i c a t i o n for Large Digital Systems,"
Proceedings of the 18th design Automation
Conference, Nashville, (pp 105-112), 1981.
[W078] M. A. Wold, "Design V e r i f i c a t i o n and Per-
formance A n a l y s i s , " Proceedings of the 15th
Design Automation Conference, Las Vegas, (pp
264-270), 1978.