Dr.

BABASAHEB AMBEDKAR MARATHWADA UNIVERSITY, AURANGABAD

(M.S.)

FPGA IMPLEMENTATION OF DISTANCE MEASUREMENT USING

ULTRASONIC SENSOR

Submitted by

Pallavi Nalawade

Under the guidance of Dr.

Abhilasha Mishra

In partial fulfillment of the award of

Master of Technology (Electronics & Telecommunication Engineering)

Department of Electronics & Telecommunication Engineering Maharashtra Institute

of Technology,
Aurangabad (Maharashtra) 2021
 CERTIFICATE

This is to certify that the minor project report entitled “FPGA Implementation Of Distance
measurement Using Ultrasonic Sensor”, submitted by Pallavi Ajinath Nalawade is the bonafied work
completed under my supervision and guidance in partial fulfillment for the award of Bachelor of Technology
(Electronics & Telecommunication Engineering) of Dr. Babasaheb Ambedkar Marathwada University,
Aurangabad (M.S.).

Place: Aurangabad Date: 13-05-

2021

Dr. Abhilasha Mishra Prof. Sarita Verma Dr. G. S. Sable

Guide Project Co-ordinator Head of Department

Dr. S. P. Bhosle
Principal
Maharashtra Institute of Technology
Aurangabad (M.S.) – 431 005
 CONTENTS

CHAPTERS TITL PAGE NO

E

List of Figures I

Abstract II

1. INTRODUCTION 1

1.1 Introduction 1

1.2 Need of project 2

1.3 Pre-lab 5

2. SYSTEM MODELING 6

2.1 Steps to be followed 9

2.2 Working 10
2.3 Procedure 11
2.4 VHDL Code for Clock Dividee3er
13
2.5 VHDL Testbench code for Clock Divider
15

3. RESULT ANALYSIS 15

3.1 Simulation of Verilog code in EDA playground 15

CONCLUSIONS 16
4.

4.1 Conclusions 16

References

Acknowledgement
 I

List of Figures

Figure Illustration Page

1.1 4 bit binary up counter 1

2.1 J1 Pinout for the Spartan 3E Board courtesy of 14

Xilinx
3.1 Result of Verilog coading 15

The simulation waveform of half-integer frequency

3.2 15
division
 ABSTRACT

FPGA is a high-precision logic device with fast running speed, rich internal resources and
reconfigurable strength.This paper puts forward some new ideas for realizing high performance ultrasonic
ranging system.This paper investigates the high precision and real-time ultrasonic ranging technology, and
designs and completes the design and hardware realization of an ultrasonic system based on FPGA.The system
can effectively solve the shortcomings of traditional ultrasonic ranging system in reliability, debugging, real
time and measuring accuracy.The system can meet the requirement of the vehicle avoiding, automatic
navigation,etc.
 1.INTRODUCTION

1.1 Introduction :
Along with the progress of science and technology, ultrasonic ranging technology has been widely used
in all walks of life, especially in the safety warning, automatic navigation and obstacle avoidance vehicles such
as areas of non-contact technology requirements.Because of the advantages such as convenience, safety and
easy real-time control, the ultrasonic ranging is slowly becoming a mainstream measurement
technology.However, in the concrete conditions of the actual work, there are obvious disadvantages to
ultrasonic ranging.In today's market, the system is typically based on traditional single-chip
computers.Although resource consumption is reduced, there is a great deal of limitation in measuring accuracy
and measuring efficiency.

1. 2 The system design

In the design of the system, according to the function of the system, there are five main
modules.Each is the high-speed counter module, the dual-core FFT module, the time sequence
generator module, the echo signal identification module and the waveform generator module.

1.3 The overall framework of system design

The range module USES the hc-sr04 module, the controller USES Altera's Cyclone series
FPGA development board, and USES the digital tube as the module to display.The hc-sr04 launch
module produces sound waves and is detected by the receiving module when the object is
reflected.The FPGA chip will be counted, and the measured distance will be calculated by the
digital tube showing the current test results.

Figure 1 Ultrasonic system structure diagram

In the design of the system, because of the ability to program and debug through the JTAG
download line, this is very handy in design.The working process of the whole system as follows, the
FPGA development board control clock drive signals and to count at the same time, the ultrasonic
drive signal through transmitter, sensor and signal detection, ultrasonic signals emitted by analyte
then; Amplifying and enabling the FPGA development board to detect the echo signal through the
receiver. Finally, the calculations are shown[2].

1.4 Timing generator module

The effective clock is especially important when designing the sequence generator.This
system USES a global clock operation to control timing. In the process of use, the synchronous
clock or global clock is a particularly reliable and convenient clock.The global clock is often the
first choice for all FPGA design implementations.When used, special clocks are used as input
control timing devices. The FPGA development board is dedicated to use as a clock input.
 Given that the design USES an external clock to vibrate to a 48-mhz, the subfrequency generates
an initial signal of 40KHz as the basis. The frequency splitter is achieved by directly calling the IP
kernel of Altera company FPGA.

1.5 Echo identification module

The echo signal recognition module mainly USES the dual-core FFT module to deal with the
echo signal, and adopts the design of anti-interference.When the module design is implemented, the
logical circuit signal is transformed. When the input signal changes, the output signal does not
change at the same time, mainly due to the delay. In this process, the burr signal is produced. This
kind of burr signal interferes with the circuit and causes a logical disorder. So, in this process, the
solution is to solve the burrs.
A combination of various factors determines the use of locking method to eliminate burrs. The
occurrence of the burr is due to the counter output. When the counting bit widens, the variety and
quantity of the burrs become more complex. In this case, the output and D triggers are
eliminated[3].
In the design of this system, the method of setting the frequency gate valve is used to ensure that
the detection is effective and reduce the influence of the interference wave. The function of the
threshold valve method is mainly to use the idea of sampling method to determine whether the echo
is true based on the measured echo frequency. Assuming that the detection value is smaller than the
value of the valve, then the echo signal is identified. Otherwise, ignore it.
The echo signal module is used by the dual-core FFT module to process the signal and use the
frequency counting module implementation. In the implementation of the system, the noise of the
system itself is not very influential. The ultrasonic receiver is more susceptible to high voltage when
the distance of the distance is slowly changing. The better way to identify the echo signal of
ultrasound is the frequency discrimination method. The principle of a specific frequency resolution
is to set up a valve signal. That when the design similar to the principle of the frequency divider, is
set the global clock signal counts, detection of echo signal value range is within the scope of the
valve signal. This implementation mainly USES the three-phase state machine to detect the echo
signal.
Figure 2 symbols schematic diagram for echo recognition module, the system clock CLK, rst_n
as the reset signal, the echo signal for the receiving end, trig end signal for launch, short [23:0] for
calculating the distance display variables.

Figure 2 The symbol diagram of the echo signal module

1.6 Dual-core FFT computing module

This module mainly completes the DE2 development board dual-core FFT calculation, which is
divided into five main modules by the implementation of the two core FFT modules by the specific
requirements of the system. Cordic modules, generator modules, assembly line modules, storage
modules, and data conversion modules. As shown in figure 15, the five large modules will also be
subdivided to better implement this section. This part of the design is often compared to the FFT
implementation. However, the operational control of the data and the flow of data in the design
process need to be carefully improved[4]. The two core FFT that is implemented on this basis will
meet our requirements.

1.7 Waveform generator module

When designing, the waveform generator module is implemented, mainly on the basis of
implementing the sequence generator module. The global clock operates on the frequency division
to obtain the drive square wave pulse. After receiving the square wave pulse, the D trigger feature is
adopted, and the square wave frequency operation is set up to 50%. And then you get the sensor
pulse. This approach can have two benefits: one is to ensure that the driver signal is a square wave
of 40KHZ; The second is that the signal can be subdivided and the number of firing pulse counts.

1.8 High speed counter module

The system is designed with a high-speed counter similar to the counter/timer in a single chip.
When the FPGA produces a driver signal, the high-speed counter operates. The count stops when
the echo signal is transmitted to the high speed counter. In this process, the frequency of counting is
known. Finally, the distance of ultrasonic distance is calculated by the method of ranging and
ranging.
Counting process, FPGA has the characteristics of running speed and high calculation accuracy,
make it easily in the moment to capture the signal echo, so finally the result has the very high
precision. After doubling the frequency, the FPGA can be improved. Another advantage is that the
FPGA counts more flexible, which can implement any number of counters.
 The counter USES the counting operation to achieve this method using the count driver signal
pulse number. Because there is no command system in the FPGA, this makes the function of the
counter primarily designed in the various submodules, and the function of the count by calling each
other.
In a stable environment, this property of the speed of the ultrasound, given what we know, is
constant. The sound velocity is 340m/s, and ultrasonic sensors are detected. By the principle of
ranging, we can calculate the number of single time range pulse counting:
N  2 * 10m 1  2353
* 40KH
340m / (1)
z
s
The N value is 2 and the width is about 12. Thus, the global variable is set to a variable of 20
bits. The following program is for data processing, primarily to convert binary data into actual
output data.
assign hundred=distance[8:0]/100
assign decade=distance[8:0]%100/10
assign unit=distance[8:0]%10

2 System Commissioning and Test Results

In this system, the debugging work mainly revolves around the timing of ultrasonic sensors
and the timing of FPGA development board. The core of the whole system is to correctly capture
and identify ultrasonic sensor reflections. To make system debugging easier, use the method of
online debugging to debug the configuration method of the JTAG download line. First, simple and
complicated. Debugging begins with simple logical functions such as frequency, count, etc. The
system was designed to be programmed and compiled by the Quartus II 12.0 software. The
following sections mainly introduce the system debug method and the test result analysis.

2.1 Embedded logic analyzer

The development of chip manufacturing technology enables FPGA chips to be widely used in
a variety of systems, which is also a measure of the complexity of product design. But as the FPGA
has become widely available, there have been many problems. Such as: the FPGA's internal signals
are difficult to logic analyzer and oscilloscope is detected, the FPGA encapsulation showed a trend
of miniaturization and makes noise circuit board itself, etc., these can lead to product validation of
the difficulty. For these situations, Altera has developed a dedicated tool, Signaltap II, also known
as an embedded logic analyzer. There is a Signaltap II in Quartus. The embedded logic analyzer
functions like an embedded oscilloscope and does not take up the I/O port to detect the required
signals. Using the analysis and judgment of system performance, the logical analyzer can be
removed when the test results conform to the design requirements.

2.2 Module Debug Waveform

The following diagram is a simulation of high-speed counters, echo recognition, and dual-
core FFT modules using logic analyzers.

2.3 High-speed Counter Module Debugging

This module by echo, CNT and CLK three synchronous signal is right acquisition and the
data flow through the HC - SR04 sensor module to the FPGA, and the data stream processing and
then passed on to the next data flow. The high speed counter module waveform is shown in figure 3.
 Figure 3 simulation of a high-speed counter
When the system is designed, a filtering operation is performed to filter the redundant signals.
The set filtering threshold is 19, which means that the ultrasonic signal is recognized as an
ultrasonic signal when there are eight continuous signal pulses. After the system works, the counter
will work, and it will always jump between states.
2.4The Echo Identification Module Debugging
This module adopts the design of the frequency meter gate valve, and the method of the three-
state state machine is used to detect the frequency of real echoes by counting the global clock
signal. As shown in figure 4.

Figure 4 Simulation of echo identification module

When the system is designed, the main function of the echo identification module is to detect the
frequency of the echo signal in the set value. Since the echo is emitted by the ultrasound, it sends
back the signal, which is needed to detect its validity. As you can see in the diagram, the state signal
always goes back to the state_ldle state. This also means that the echo signal detected is not in the
threshold, which means that the signal is filtered.

2.5 Dual-core FFT module debugging

Figure 5 is the waveform of the dual-core FFT module. As shown, the implementation is the
dual core FFT module, which is the FFT operation twice. The result of the counter in address
true_addr_a and true_addr_b, will result in high in line_addr_a, low in line_addr_c, transpose
line_addr_a line before the address, line_addr_b. The variable qa_data, qb_data is the data that is
obtained after passing the module.
 2.6 Debugging Problems and Solutions

The whole system has a lot of problems in debugging. These problems are solved by the debug
method implementation. Start by not doing any processing of the ultrasonic signal, which will be
collected directly from the original signal and displayed in real time. Is randomly appear garbled
words at first, by modifying the CNT count the value of the parameter in the echo recognition
module, can see the acquisition of ultrasonic signal, on the digital tube display there is a slight
change. It should be a three-phase state machine, the counter signal and the echo detect the result of
not synchronization, and then redebug the modules. Modified can be seen in the digital tube
ultrasonic distance data real-time acquisition, real-time data on the digital tube, however, shows that
the effect is very unstable, change a lot. This big reason is because the frequency meter gate set
unreasonable, caused by fixed gate value, set up the most appropriate threshold to detect the effect
of echo signal is better. The process of debugging is a tedious and time-consuming process that
often requires careful observation and consideration
2
right half of the debounce circuit. While the Synchronized signal is LOW, the counter is held in reset
(i.e. Count = 0). Likewise, the mostsignificant-bit (msb) of the counter is LOW; therefore, notMsb is
HIGH. When the Synchronized signal transitions to HIGH, the reset of the counter is released so the
counter will begin counting. Figure 5 illustrates this behavior. Assuming the bit width of the counter
is sufficiently sized, the msb of the counter will never become HIGH while the Synchronized signal
bounces because the counter will continually be reset. Thus, the Debounced signal should remain
LOW during this period. Once the Synchronized signal smooths out, the counter will saturate. In
other words, the msb of the counter will become HIGH, which will in turn force En to go LOW,
stopping the counter from counting. At this point, the Debounced signal will be HIGH until the
Synchronized signal goes LOW again, in which case the process repeats.

We deferred the discussion concerning the Synchronizer circuit until the end because it is mostly of
practical matters and rarely discussed in theory. The signal created by the push-button is not only
bouncy but also asynchronous. In other words, the signal could rise or fall at any point in time
regardless of the clock signal. This can be problematic in a synchronous circuit because the input to a
flip-flop must be stable for a small window of time before (setup-time) and after (hold-time) the
active edge of the clock. For a risingedge triggered flip-flop, the active edge is the rising-edge. If the
setup or hold-time of a flip-flop is violated, the flip-flop will remain in a metastable state (i.e. not
really ‘1’ or ‘0’) for one or two clock cycles. The probability of the flip-flop remaining metastable
falls off rapidly as time goes on so for most applications, a synchronizer circuit can be created with
two cascaded flip-flops. Simply put, the
synchronizer circuit serves to align the signal from the button with the active edge of the clock. This
ensures that by the time the button signal propagates into the rest of the synchronous circuit, it is not
violating setup/hold time and will not cause the flip-flops after the synchronizer to become
metastable. The remaining components in Figure 4 should look familiar. For example, the pull-down
resistor brings the output of the push- button circuit to a LOW state when the button is not pressed.
This configuration is similar to that of the DIP switches from earlier labs. For the experiments in lab,
we will use the push-buttons on the Spartan 3E board and the UCF to specify the use of the pull-
down resistor within the FPGA.
 5

3 SYSTEM MODELING

3.1The System Design

In the design of the system, according to the function of the system, there are five main
modules.Each is the high-speed counter module, the dual-core FFT module, the time sequence
generator module, the echo signal identification module and the waveform generator module.

3.1 The Overall Framework of System Design

The range module USES the hc-sr04 module, the controller USES Altera's Cyclone series
FPGA development board, and USES the digital tube as the module to display.The hc-sr04 launch
module produces sound waves and is detected by the receiving module when the object is
reflected.The FPGA chip will be counted, and the measured distance will be calculated by the
digital tube showing the current test results.

Figure 1 Ultrasonic system structure diagram

In the design of the system, because of the ability to program and debug through the JTAG download line, this
is very handy in design.The working process of the whole system as follows, the FPGA development board
control clock drive signals and to count at the same time, the ultrasonic drive signal through transmitter, sensor
and signal detection, ultrasonic signals emitted by analyte then; Amplifying and enabling the FPGA
development board to detect the echo signal through the receiver. Finally, the calculations are shown.
3.2 VHDL code for Clock Divider

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sonar is
Port ( clk : in STD_LOGIC;
trig : out STD_LOGIC;--trigger
echo : in STD_LOGIC;
cm1 : out unsigned(3 downto 0); --most significant bit of distance in binary form
cm0 : out unsigned(3 downto 0));
end sonar;
architecture sonar_arch of sonar is
begin
process(clk)
variable count: integer range 0 to 10000;
variable tmpcm1: unsigned(3 downto 0) := "0000";
variable tmpcm0 : unsigned(3 downto 0) := "0000";
variable sendTrig: std_logic := '1';
 6
variable echoPrev: std_logic:= '0';
variable echoCurrent : std_logic:= '0';
begin
if rising_edge(clk) then
if sendTrig = '1' then -- send 10us trig
if count = 1000 then -- 10 us trig is completed, reset tmp signals for the new calculation
trig <= '0';
sendTrig := '0';
count := 0;
tmpcm0 := "0000";
tmpcm1 := "0000";
else
trig <= '1';
count := count + 1;
end if;
else -- stop sending trig, do the calculation (5800 clk cycle = 1cm)(count enters here as 0)
if echo = '1' then -- we can start calculating the width of the echo
if count = 5799 then--we measuered 1 cm
if tmpcm0 = "1001" then
if tmpcm1 = "1001" then
sendTrig := '1';--max distance to be measured(100 cm), stop measuring, re-send the
trig(also update the output)
cm0 <= tmpcm0;
cm1 <= tmpcm1;
else
tmpcm1 := tmpcm1 + "0001";
tmpcm0 := "0000";
end if;
else
tmpcm0 := tmpcm0 + "0001";
end if;
count := 0;
else
count := count + 1;
end if;
if echoPrev = '1' and echoCurrent = '0' then --falling edge of echo, edit the output, start sending
new trigger
sendTrig := '1';
cm0 <= tmpcm0;
cm1 <= tmpcm1;
end if;
end if;
end if;
echoPrev := echoCurrent;
echoCurrent := echo;
end if;
end process;

end sonar_arch;
 7

3.3 VHDL Testbench code for Clock Divider

view source print?

LIBRARY ieee;
USE
ieee.std_logic_1164.ALL;

ENTITY Tb_clock_divider IS END

Tb_clock_divider;

ARCHITECTURE behavior OF Tb_clock_divider IS

– Component Declaration for the Unit Under Test (UUT)

COMPONENT
Clock_Divider
PORT(

clk : IN
std_logic;
reset : IN
std_logic;
clock_out : OUT std_logic 8
);

END COMPONENT;

--Inputs
signal clk : std_logic :=
'0';

signal reset : std_logic := '0';

--Outputs
signal clock_out :
std_logic;

– Clock period definitions constant

clk_period : time := 20 ns;

BEGIN

– Instantiate the Unit Under Test

(UUT)
uut: Clock_Divider PORT MAP (

clk => clk,

reset =>
reset,

clock_out =>
clock_out
);

– Clock process definitions

clk_process
:process
begin

clk <= '0';

wait for
clk_period/2;
clk <= '1';
wait for
clk_period/2;

end process;
 – Stimulus
process
stim_proc:
process

begin
wait for 100
ns;

reset <= '1';

wait for 100
ns;

reset <=
'0';
wait;

end process;

END;
Clock Divider is also known as frequency divider, which divides the input clock frequency
and produce output clock. In our case let us take input frequency as 50MHz and divide the
clock frequency to generate 1KHz output signal.

VHDL code consist of Clock and Reset input, divided clock as output. Count is a signal to
generate delay, Tmp signal toggle itself when the count value reaches 25000. Output
produce 1KHz clock frequency.

Reference count values to generate various clock frequency output

Count Value Output Frequency

1 25MHz

25 1MHz

50 500KHz

1000 25KHz

25000000 1Hz

The output of the counter changes far too rapidly for us to view with LEDs so we will need to
employ the logic analyzer on our work bench. Unlike the oscilloscope, the logic analyzer on your
workbench can probe up to 32 digital signals at once. It also has the capability of grouping signals
into buses, which can be viewed in decimal or hexadecimal format. The waveforms that you will see
on the logic analyzer today have many similarities to the waveforms you have previously seen in
simulation. The difference, however, is that the signals you see on the logic analyzer are being
created with actual hardware! The following steps will direct you through the process of connecting
the logic analyzer to the Spartan 3E board as well as the initial setup of the logic analyzer.
In design of digital circuit, clock pulse of all frequencies is often indispensable. If we have to design
an oscillating circuit or install a crystal oscillator for every clock pulse,
it will both the complicacy and cost of the circuit. So, in practical circuit design, ready- made clock source is
often used to obtain desired frequency[4]. Implementing integer frequency division is quite simple, which is
often made of counters or counter cascade connection. But implementing half-integer frequency division is
more difficult, in this paper the basic design idea is :designing a modulus N counter and a pulse deducting .

Fig 2.1: J1 Pinout for the Spartan 3E Board courtesy of Xilinx

 4 RESULT ANALYSIS
4.1. Simulation of Verilog code

Fig 4.1 : Result of Verilog coading

Fig 4.2 : The simulation waveform of half-integer frequency division

 5. CONCLUSION

5.1 Conclusion

EPF10K10LC84-3 of FLEX series produced by ALTERA has a working frequency of 85.5MHZ, "inclk" is
13.6ns ahead of "outclk", "inclk" has delay of 15.9ns behind "outclk1". Assuming inclk is 6M, then outclk
yield HZ N 6M , HZ N M 5.0 6 N=23——255more than 508 clock frequencies through frequency division,
that the lowest can reach 23.5KHZ. On the other hand,"outclk_1" is the two frequency division of "outclk",
that the lowest frequency reaches 11.75KHZ. Only changing values of parameter "N" and "SEL" we can
have integer and half-integer frequency dividers, so it's very convenient to use this method.
 17

REFERENCES

[1] Tong Yu, Shexiang Ma and Kun Guo, “Design of the equal duty ratio arbitrary integer frequency
divider based on FPGA”, Journal of Tianjin University of Technology, vol24, 2008, p.86 [2]
Xiaohong Yu, Qingxin Cao and Tao Yang, “Design and precision analysis of dual-modules
frequency divider with regulable duty ratio”, Application of Electronic Technique, vol8,2009, p.49
[3] Rong Wang and Weimin Li, “The design of the Half-integer Frequency Divider Based on
CPLD/FPGA”, Microcomputer Information, vol26,2010, p.131 [4] Fan Gao and Leilei Jia, “The
Design of the Half Integer Frequency Divider Based on FPGA” 㧘 Science & Technology
Information, Vol19,2010, p.133 [5] Peijun Gao, “Design and realization of various frequency
dividers based on FPGA”, Electronic Products, vol 5, 2004, p.32-34.
Junying Tang, EDA Technology Example Tutorial, Chengdu: Electronic Industry Press,2008 [7]
Xuesong Jiang and Dongsheng Liu, hardware description language VHDL course, xi’an: xi'an jiao
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technology, Beijing: Sciences Press, 2002.