OPA454
SBOS391 – DECEMBER 2007

High-Voltage (100V), High-Current (50mA)

OPERATIONAL AMPLIFIERS, G = 1 Stable
1FEATURES DESCRIPTION
• WIDE POWER-SUPPLY RANGE:
23

The OPA454 is a low-cost operational amplifier with

±5V (10V) to ±50V (100V) high voltage (100V) and relatively high current drive
• HIGH OUTPUT LOAD DRIVE: IO > ±50mA (25mA). It is unity-gain stable and has a
gain-bandwidth product of 2.5MHz.
• WIDE OUTPUT VOLTAGE SWING: 1V to Rails
• INDEPENDENT OUTPUT DISABLE OR The OPA454 is internally protected against
SHUTDOWN over-temperature conditions and current overloads. It
is fully specified to perform over a wide power-supply
• WIDE TEMPERATURE RANGE: –40°C to +85°C range of ±5V to ±50V or on a single supply of 10V to
• PACKAGES: SO and HSOP PowerPAD™ 100V. The status flag is an open-drain output that
allows it to be easily referenced to standard
APPLICATIONS low-voltage logic circuitry. This high-voltage op amp
• TEST EQUIPMENT provides excellent accuracy, wide output swing, and
is free from phase inversion problems that are often
• AVALANCHE PHOTODIODE: found in similar amplifiers.
High-V Current Sense
• PIEZOELECTRIC CELLS The output can be independently disabled using the
Enable/Disable Pin that has its own common return
• TRANSDUCER DRIVERS
pin to allow easy interface to low-voltage logic
• SERVO DRIVERS circuitry. This disable is accomplished without
• AUDIO AMPLIFIERS disturbing the input signal path, not only saving power
• HIGH-VOLTAGE COMPLIANCE CURRENT but also protecting the load.
SOURCES Featured in a small exposed metal pad package, the
• GENERAL HIGH-VOLTAGE OPA454 is easy to heatsink over the extended
REGULATORS/POWER industrial temperature range, –40°C to +85°C.
Status
Flag Table 1. OPA454 RELATED PRODUCTS
V+ PRODUCT DESCRIPTION
Enable/Disable (E/D) (1)
OPA445 80V, 15mA
-IN OPA452 80V, 50mA
OPA454 VO
OPA547 60V, 750mA
+IN
Enable/Disable Common
OPA548 60V, 3A
(E/D Com) OPA549 60V, 9A
V-
OPA551 60V, 200mA
OPA567 5V, 2A
OPA569 5V, 2.4A

(1) The OPA445 is pin-compatible with the OPA445, except in

applications using the offset trim, and NC pins other than
open.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PowerPAD is a trademark of Texas Instruments, Inc.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas Copyright © 2007, Texas Instruments Incorporated
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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SBOS391 – DECEMBER 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
OPA454 SO-8 DDA OPA454
OPA454 HSOP-20 (2) DWD OPA454

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Available Q2, 2008.

ABSOLUTE MAXIMUM RATINGS (1)

OPA454 UNIT
Supply Voltage VS = (V+) – (V–) 120 V
Signal Input Terminals, Voltage (2) (V–) – 0.3 to (V+) + 0.3 V
(2)
Signal Input Terminals, Current ±10 mA
E/D to E/D Com Voltage +5.5 V
Output Short-Circuit (3) ISC Continuous
Operating Temperature TJ –55 to +125 °C
Storage Temperature –55 to +125 °C
Junction Temperature TJ +150 °C
Human Body Model (HBM) 4000 V
ESD Rating: Charged Device Model (CDM) 500 V
Machine Model (MM) 150 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3V beyond the supply rails should
be current limited to 10mA or less.
(3) Short-circuit to ground.

PIN ASSIGNMENTS
DDA PACKAGE DWD PACKAGE(1)
SO-8 PowerPAD HSOP-20 PowerPAD
(TOP VIEW) (TOP VIEW)

E/D Com (Enable/Disable Common) 1 8 E/D (Enable/Disable) V- 1 20 V-

(1)
PowerPAD (3) (3)
-IN 2 Heat Sink 7 V+ NC 2 19 NC
(Located on NC
(3)
3 18 NC
(3)
+IN 3 6 OUT
bottom side)
V- 4 17 Status Flag
V- 4 5 Status Flag (2)
PowerPAD
+IN 5 Heat Sink 16 VOUT
(3) (Located on
NC 6 15 V+
(1) PowerPAD is internally connected to V–. top side)
(3)
Soldering the PowerPAD to the PCB is -IN 7 14 NC

always required, even with applications that NC

(3)
8 13 NC
(3)

have low power dissipation. E/D Com (Enable/Disable Common) 9 12 E/D (Enable/Disable)

V- 10 11 V-

(1) Available Q2, 2008.

(2) PowerPAD is internally connected to V–.
(3) NC = No internal connection

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ELECTRICAL CHARACTERISTICS: VS = ±50V

Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TP (1) = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
OPA454
PARAMETER CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input Offset Voltage VOS IO = 0 ±0.2 ±4 mV
vs Temperature (2)
dVOS/dT ±1.6 ±10 µV/°C
vs Power Supply PSRR VS = ±4V to ±60V, VCM = 0V 25 100 µV/V
INPUT BIAS CURRENT
Input Bias Current IB ±1.4 ±100 pA
vs Temperature See Typical Characteristics
Input Offset Current IOS ±0.2 ±100 pA
NOISE
Input Voltage Noise Density, f = 10Hz en 300 nV/√Hz
Input Voltage Noise Density, f = 10kHz 35 nV/√Hz
f = 0.01Hz to 10Hz 15 µVPP
Current Noise Density, f = 1kHz in 40 fA/√Hz
INPUT VOLTAGE RANGE
(3)
Common-Mode Voltage Range VCM Linear Operation (V–) + 2.5 See Note (V+) – 2.5 V
Common-Mode Rejection CMRR VS = ±50V, –25V ≤ VCM ≤ +25V 100 146 dB
VS = ±50V, –45V ≤ VCM ≤ +45V 100 147 dB
Over Temperature VS = ±50V, –25V ≤ VCM ≤ +25V 80 88 dB
Over Temperature VS = ±50V, –45V ≤ VCM ≤ +45V 72 82 dB
INPUT IMPEDANCE
Differential 1013 || 10 Ω || pF
Common-Mode 1013 || 9 Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain (4) AOL
(V–) + 1V < VO < (V+) – 1V,
100 130 dB
RL = 49kΩ, IO = ±1mA
(V–) + 1V < VO < (V+) – 1V,
112 dB
RL = 49kΩ, IO = ±1mA
(V–) + 1V < VO < (V+) – 2V,
100 115 dB
RL = 4.8kΩ, IO = ±10mA
(V–) + 1V < VO < (V+) – 2V,
106 dB
RL = 4.8kΩ, IO = ±10mA
(V–) + 2V < VO < (V+) – 3V,
80 102 dB
RL = 1880Ω, IO = ±25mA
(V–) + 2V < VO < (V+) – 3V,
84 dB
RL = 1880Ω, IO = ±25mA

(1) TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package.
(2) See typical characteristic curve, Offset Voltage Drift Production Distribution (Figure 14).
(3) Typical range is (V–) + 1.5V to (V+) – 1.5V.
(4) Measured using low-frequency (<10Hz) ±49V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 24).

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ELECTRICAL CHARACTERISTICS: VS = ±50V (continued)

Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TP = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
OPA454
PARAMETER CONDITIONS MIN TYP MAX UNIT
FREQUENCY RESPONSE (5)
Gain-Bandwidth Product GBW Small-Signal 2.5 MHz
Slew Rate SR G = ±1, VO = 80V Step, RL = 3.27kΩ 13 V/µs
Full-Power Bandwidth (6) 35 kHz
Settling Time: ±0.1% (7) G = ±1, VO = 20V Step 3 µs
Settling Time: ±0.01% (7) G = ±5 or ±10, VO = 80V Step 10 µs
VS = +40.6V/–39.6V, G = ±1,
Total Harmonic Distortion + Noise (8) THD+N 0.0008 %
f = 1kHz, VO = 77.2VPP
OUTPUT
Voltage Output Swing From Rail (9) VO RL = 49kΩ, AOL ≥ 100dB, IO = 1mA (V–) + 1 (V+) – 1 V
RL = 4.8kΩ, AOL ≥ 100dB, IO = 10mA (V–) + 1 (V+) – 2 V
RL = 1880Ω, AOL ≥ 80dB, IO = 26mA (V–) + 2 (V+) – 3 V
Continuous Current Output, dc Depends on Circuit Conditions See Figure 6
Maximum Peak Current Output, Current
IO +120/–150 mA
Limit (10)
Over Temperature +140/–170 mA
Capacitive Load Drive (5) CLOAD 200 pF
Open-Loop Output Impedance RO See Figure 5 Ω
Output Disabled
Output Capacitance 18 pF
Feedthrough Capacitance (11) 150 fF
STATUS FLAG PIN (Referenced to E/D Com) (12)
Status Flag Delay Enable → Disable 6 µs
Disable → Enable 4 µs
Over-Current Delay (13) 15 µs
Over-Current Recovery Delay (13) 10 µs
Junction Temperature TJ
Alarm (status flag high) +150 °C
Return to Normal Operation (status flag low) +130 °C
Output Voltage (5) Normal Operation E/D Com + 2 V
RL = 100Ω During Thermal Overdrive,
(V+) – 2.5 V
Alarm

(5) See Typical Characteristic curves.

(6) See typical characteristic curve, Maximum Output Voltage vs Frequency (Figure 12).
(7) See the Applications Information section, Settling Time.
(8) Supplies reduced to allow closer swing to rails due to test equipment limitations. See typical characteristic curve Total Harmonic
Distortion + Noise vs Temperature (Figure 30 and Figure 31) for additional power levels.
(9) See typical characteristic curve, Output Voltage Swing vs Output Current (Figure 11).
(10) Measured using low-frequency (<10Hz) ±49V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 24).
(11) Measured using Figure 1.
(12) 100kΩ pull-up resistor to (V+). E/D common to (V–). Status flag indicates an over temperature or over-current condition.
(13) See Typical Characteristic curves for current limit behavior.

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ELECTRICAL CHARACTERISTICS: VS = ±50V (continued)

Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TP = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
OPA454
PARAMETER CONDITIONS MIN TYP MAX UNIT
E/D (ENABLE/DISABLE) PIN
E/D Pin, Referenced to E/D Com Pin (14) (15)
High (output enabled) VSD Pin Open or Forced High E/D Com + 2.5 E/D Com + 5 V
E/D Com +
Low (output disabled) VSD Pin Forced Low E/D Com V
0.65
Output Disable Time 4 µs
Output Enable Time 3 µs
E/D COM PIN
Voltage Range (V–) (V+) – 5 V
POWER SUPPLY
Specified Range VS ±50 V
Operating Voltage Range ±5 ±50 V
Quiescent Current IQ IO = 0 3.2 4 mA
Quiescent Current in Shutdown Mode IO = 0, VE/D = 0.65V 150 210 µA
TEMPERATURE RANGE
Specified Range TA –40 +85 °C
Operating Range TA –55 +125 °C
Thermal Resistance, Junction-to-Case (16)
SO-8 PowerPAD (17) θJC 10 °C/W
HSOP-20 10 °C/W
Thermal Resistance, Junction-to-Ambient θJA
SO-8 PowerPAD (17) 24/52 °C/W
HSOP-20 (18) 65 °C/W

(14) See typical characteristic curve, IENABLE vs VENABLE (Figure 46).

(15) High enables the outputs.
(16) TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package.
(17) Lower value is for land area of 1-inch × 1-inch, 2-oz copper. Upper value is for exposed-pad sized area of 1-oz copper.
(18) Value given is for DW-20 package, similar to the DWD package, but without an exposed pad. Actual θJA may approach θJC by selection
of external heatsink and airflow.

+50V
E/D

VOUT
RL
50kW
100VPP
E/D Com
10kHz

-50V

Figure 1. Feedthrough Capacitance Circuit

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SBOS391 – DECEMBER 2007

TYPICAL CHARACTERISTICS
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

OPEN-LOOP GAIN AND PHASE

vs FREQUENCY PHASE MARGIN vs TEMPERATURE
180 70
CL = 30pF VCM = -45V
160
Open-Loop Gain, Phase (dB, °)

VCM = 0V
65
140 VCM = +45V
120

Phase Margin (°)

60
100
Phase
80 55
60
50
40 CL = 100pF
Gain CL = 200pF
RLOAD = 4.87kW
20 45
CLOAD = 50pF
0 VCM = 0V
-20 40
0.1 1 10 100 1k 10k 100k 1M 10M -75 -50 -25 0 25 50 75 100 125
Frequency (Hz) Exposed Thermal Pad Temperature (°C)
Figure 2. Figure 3.

UNITY-GAIN BANDWIDTH OPEN-LOOP OUTPUT IMPEDANCE

vs TEMPERATURE vs FREQUENCY
3.8 1M
Open-Loop Output Impedance (W)

3.6
100k
3.4
Bandwidth (MHz)

3.2 10k
VCM = 0V
3.0
1k
2.8
VCM = 45V
2.6 100
VCM = -45V
2.4
10
2.2
CL = 30pF. 100pF, and 200pF
2.0 1
-75 -50 -25 0 25 50 75 100 125 1 10 100 1k 10k 100k 1M 10M
Exposed Thermal Pad Temperature (°C) Frequency (Hz)
Figure 4. Figure 5.

OPEN-LOOP GAIN vs PEAK-LOAD CURRENT OPEN-LOOP GAIN vs TEMPERATURE

140 140

130 130
VS = ±50V
120 120

110
110 RLOAD = 48kW
AOL (dB)

AOL (dB)

VS = ±15V 100 VOUT = ±49V (dc)

100 IOUT = ±1mA
90
RL = 4.8kW
90
VS = ±4V 80 VOUT = +48V, -49V (dc)
80 IOUT = +9.9mA to -10mA
70
RL = 1.88kW RL = 900W
70 VOUT = +47V, -48V (dc) VOUT = +45V, -47V (dc)
60
IOUT = ±25mA IOUT = 50mA to -52mA
60 50
0 5 10 15 20 25 -75 -50 -25 0 25 50 75 100 125
Peak IL (mA) Exposed Thermal Pad Temperature (°C)
Figure 6. Figure 7.

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TYPICAL CHARACTERISTICS (continued)

At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

POWER-SUPPLY AND COMMON-MODE

COMMON-MODE REJECTION RATIO vs FREQUENCY REJECTION RATIO vs TEMPERATURE
140 120
PSRR
120 100
1kHz, CMRR

PSRR and CMRR (dB)

100 10kHz, CMRR
80
CMRR (dB)

80
VCM = -45V 60
100kHz, CMRR
60
40
40 1.3MHz, CMRR
VCM = +45V
20 20 VCM = +45V
VCM = -45V
0 0
0.001 0.01 0.1 1 10 100 1k 10k -75 -50 -25 0 25 50 75 100 125
Frequency (Hz) Exposed Thermal Pad Temperature (°C)
Figure 8. Figure 9.

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT

POWER-SUPPLY REJECTION RATIO vs FREQUENCY (Measured When Status Flag Transitions From Low to High)
140 50
-55°C
120 49

100 48
PSRR (dB)

VOUT (V)

80 47
+125°C +85°C +25°C
60 -47

40 -48

20 -49
-55°C
0 -50
1 10 100 1k 10k 100k 1M 0 10 20 30 40 50
Frequency (Hz) IOUT (mA)
Figure 10. Figure 11.

DDA PACKAGE OFFSET VOLTAGE

MAXIMUM OUTPUT VOLTAGE vs FREQUENCY PRODUCTION DISTRIBUTION
120 Average = 111mV
VOUT = ±49V Standard Deviation = 142mV
100 RL = 4.8kW
IOUT = ±10mA
Output Voltage (VPP)

80
Population

60

40

20

0
0 50 100 150 200 250 300 -4000 -3000 -2000 -1000 0 1000 2000 3000 4000
Frequency (kHz) Offset Voltage (mV)
Figure 12. Figure 13.

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SBOS391 – DECEMBER 2007

TYPICAL CHARACTERISTICS (continued)

At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

DDA PACKAGE OFFSET VOLTAGE

DRIFT PRODUCTION DISTRIBUTION DDA PACKAGE, SOLDER-ATTACHED, VOS TC SHIFT
Average = 1.57mV/°C Average = 0.34mV/°C
Standard Deviation = 0.84mV/°C Standard Deviation = 0.44mV/°C
Population

Population

-0.8

-0.4
-2.0

0
-1.6

-1.2

0.8

1.2

1.6

2.0
0.4
0 1 2 3 4 5 6 7 8 9 10
Offset Voltage Drift (mV/°C) Output Voltage Shift (mV/°C)
Figure 14. Figure 15.

OFFSET VOLTAGE WARMUP

DDA PACKAGE, SOLDER-ATTACHED, VOS SHIFT (60 Devices)
Average = 48mV/°C 200
Standard
150
Deviation = 28mV/°C
100
Offset Voltage (mV)

VS = ±50V
Population

50
PowerPAD Attached
0 9in ´ 12in 0.062
Layer Metal PCB FR10
-50

-100

-150

-200
-400

-200
-1000

400

600

800

1000
-800

-600

200

100s/div

Offset Voltage Shift (mV)

Figure 16. Figure 17.

QUIESCENT CURRENT PRODUCTION DISTRIBUTION QUIESCENT CURRENT vs SUPPLY VOLTAGE

3.25

3.20

3.15
Population

3.10
IQ (mA)

3.05

3.00

2.95

2.90
3.0
3.1

3.5
3.2

3.8
2.5
2.6
2.7
2.8
2.9

3.4

3.9
3.3

3.6
3.7

0 10 20 30 40 50 60 70 80 90 100 110 120

Quiescent Current (mA) Total Supply Voltage (V)

Figure 18. Figure 19.

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TYPICAL CHARACTERISTICS (continued)

At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

QUIESCENT CURRENT vs TEMPERATURE SHUTDOWN CURRENT vs TEMPERATURE

4.0 200
3.8 5 Typical Units Shown
3.6 180

Shutdown Current (mA)

3.4
3.2 160
IQ (mA)

3.0
2.8 140
2.6
2.4 120
2.2
2.0 100
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
Exposed Thermal Pad Temperature (°C) Exposed Thermal Pad Temperature (°C)
Figure 20. Figure 21.

INPUT BIAS CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE

100 20

15

10
10
5
IB (pA)
IB (pA)

-5
1 Common-Mode Voltage Range
-10

-15

0.1 -20
-75 -50 -25 0 25 50 75 100 125 -50 -40 -30 -20 -10 0 10 20 30 40 50
Exposed Thermal Pad Temperature (°C) VCM (V)
Figure 22. Figure 23.

STATUS FLAG VOLTAGE vs TEMPERATURE

CURRENT LIMIT vs TEMPERATURE (E/D Com Connected to V–) (1)
200 8

7
180 RP = 20kW, IP = 5mA
6
Sourcing
5
VFLAG to V-
ILIMIT (mA)

160
4
RP = 50kW, IP = 2mA
140 3
RP = 100kW, IP = 100mA
2
120 RP = 200kW, IP = 50mA
1
Sinking
100 0
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
Exposed Thermal Pad Temperature (°C) Exposed Thermal Pad Temperature (°C)
Figure 24. Figure 25.

(1) See Figure 57 in the Applications Information section.

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TYPICAL CHARACTERISTICS (continued)

At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

MAXIMUM POWER DISSIPATION

vs TEMPERATURE WITH MINIMUM ATTACH AREA SLEW RATE vs TEMPERATURE
2.0 16
SO-8 PowerPAD:
TJ(max) = +125°C 15

1.5 14

Slew Rate (V/ms)

Dissipation (W)

13

1.0 12

TJ (+125°C max) = TA + [(|VS| - |VO|) IO ´ qJA] 11

qJA = +52°C/W, SO-8 PowerPAD G = +1
0.5 10
(1in ´ 0.5in [25.4mm x 12.7mm] VS = ±45V
Heat-Spreader, 1oz Copper) 9 VIN = 80V Step
TJ = +25°C + (1.93W ´ 52°C/W) = +125°C RLOAD = 4.8kW
0 8
-50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
Exposed Thermal Pad Temperature (°C) Exposed Thermal Pad Temperature (°C)
Figure 26. Figure 27.

INPUT VOLTAGE NOISE SPECTRAL DENSITY 0.01Hz TO 10Hz INPUT VOLTAGE NOISE
1000
Voltage Noise (nV/ÖHz)

100
5mV/div

10

1
10 100 1k 10k 100k 20s/div
Frequency (Hz)
Figure 28. Figure 29.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs TEMPERATURE vs TEMPERATURE
0.040 0.0030
G = +10 G = +1
RI = 4.75kW RI = 4.75kW
0.035 VPP = 38.6V 0.0025 VPP = 38.6V
VS = +41.6, -40.6

0.030 0.0020
THD + N (%)
THD + N (%)

0.025 0.0015
VS = +40.6,
VS = -55, +55 -39.6
0.020 0.0010
VS = -49, +50
0.015 0.0005

0.010 0
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)
Figure 30. Figure 31.

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TYPICAL CHARACTERISTICS (continued)

At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE

VIN VIN

G = +1 G = +1
TC = +60°C TC = +105°C
CLOAD = 50pF CLOAD = 50pF
500mV/div

500mV/div
VCM = +30V VCM = +30V
RF = 10kW RF = 10kW

VOUT VOUT

Time (1ms/div) Time (1ms/div)

Figure 32. Figure 33.

LARGE-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE

TC = +125°C

TC = +25°C
VOUT (400mV/div)
VIN (200mV/div)

TC = -55°C
50mV

G = +2
TC = +100°C G = +1
CLOAD = 100pF CLOAD = 100pF
VIN
VCM = +40V VCM = 0V
VOUT RF = 10kW RF = 0W

Time (2.5ms/div) Time (500ns/div)

Figure 34. Figure 35.

GAIN PEAKING vs CLOAD

STEP RESPONSE (G = +1, VCM = 0V) (2)
2.0 180
G = +1 RF = 0 W
1.5 160 RF = 10kW
G = +2 TC = -55°C
1.0 140
TC = +25°C
120
0.5
Peaking (%)

TC = +85°C
VOUT (V)

100
0 TC = +125°C
80
-0.5
60
-1.0
RF = 10kW 40
-1.5 CLOAD = 100pF, 125°C 20
VCM = +40V
-2.0 0
1ms/div 0 100 200 300 400 500
CLOAD (pF)
Figure 36. Figure 37.

(2) See Application section Unity-Gain Noninverting Configuration.

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TYPICAL CHARACTERISTICS (continued)

At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

GAIN PEAKING vs CLOAD

(G = +2, RF = 10kΩ, VCM = 0V) GAIN OF +1 vs FREQUENCY (3)
30 10
CF = 0pF TC = -55°C TA = +25°C CL = 200pF
25 CF = 2.5pF 8
CF = 5pF TC = +25°C
6
20
CL = 100pF
TC = +85°C
Peaking (%)

Gain (dB)
15
TC = +125°C 2
10
0
5
-2
0 RF = 10kW, CF = 50pF
-4
RF = 0W
CL = 50pF
-5 -6
0 100 200 300 400 500 10k 100k 1M 10M
CLOAD (pF) Frequency (Hz)
Figure 38. Figure 39.

SETTLING TIME, POSITIVE STEP

GAIN OF +2 vs FREQUENCY (4) (20V Step, Gain = 1, RF = 10kΩ) (5) (6)
10 20 0.08
TA = +25°C CL = 500pF
8 15 0.06
V1 (Inverting)

Voltage at V1 and V2 (V)

6 10 0.04

4 5 0.02
Gain (dB)

V2 (Noninverting)
VIN (V)

CL = 50pF
2 0 0

0 -5 -0.02

-10 -0.04
-2 CF = 0pF VIN
CF = 2.5pF -15 -0.06
-4
CF = 5pF
-20 -0.08
-6
Time (1ms/div)
10k 100k 1M 10M
Frequency (Hz)
Figure 40. Figure 41.

(3) See Application section Unity-Gain Noninverting Configuration.

(4) See Application section Unity-Gain Noninverting Configuration.
(5) See the Settling Time section.
(6) The grid for voltage at V1 and V2 is scaled 20mV or 0.1% per division.

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TYPICAL CHARACTERISTICS (continued)

At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

SETTLING TIME, NEGATIVE STEP

(20V Step, Gain = 1, RF = 10kΩ) (7) (8) ENABLE RESPONSE TIME
20 0.08

15 0.06
VIN

Voltage at V1 and V2 (V)

10 0.04
OUT
5 0.02

4mV/div
VIN (V)

0 0
V2 (Noninverting) Status Flag
-5 -0.02

-10 -0.04
V1 (Inverting)
Enable
-15 -0.06

-20 -0.08
Time (1ms/div) Time (1ms/div)
Figure 42. Figure 43.

DISABLE RESPONSE TIME ENABLE RESPONSE

OUT

OUT
4mV/div

4mV/div

Status Flag Status Flag

Enable Enable

Time (1ms/div) Time (1ms/div)

Figure 44. Figure 45.

IENABLE vs VENABLE ENABLE/DISABLE THRESHOLD vs TEMPERATURE

10 1.00

0.95
0
0.90
Threshold (V)

-40°C
IENABLE (mA)

-10 0.85
+25°C

+85°C 0.80
-20
0.75

-30 0.70
0 1 2 3 4 5 -75 -50 -25 0 25 50 75 100 125
VENABLE (V) Temperature (°C)
Figure 46. Figure 47.

(7) See the Settling Time section.

(8) The grid for voltage at V1 and V2 is scaled 20mV or 0.1% per division.

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TYPICAL CHARACTERISTICS (continued)

At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

ILIMIT SHOWING FLAG DELAY ILIMIT SHOWING FLAG DELAY

(TP = +125°C) (9) (TP = +25°C) (10)
60 200 60 150
VFLAG VFLAG
50 150 50 100

40 100 40 50
IOUT
VFLAG (V)

VFLAG (V)
IOUT (mA)

IOUT (mA)
30 50 30 0

20 0 20 -50
IOUT
10 -50 10 -100

0 -100 0 -150
RP = 100kW RP = 100kW
-10 -150 -10 -200
10ms/div 10ms/div
Figure 48. Figure 49.

ILIMIT SHOWING FLAG DELAY APPLY LOAD

(TP = –55°C) (11) (25mA Sink Response)
60 150 1.6
VFLAG +125°C
1.4 +85°C 0.988VPP +50V
50 100 0.01Hz
-
+25°C OPA454
1.2
-55°C 2Hz
+

40 50 2ms Pulse

IOUT 1.0 -50V Mercury

Wetted
VFLAG (V)

IOUT (mA)

Relay
VOUT (V)

30 0 0.8

20 -50 0.6

0.4
10 -100
0.2
0 -150
RP = 100kW 0
-10 -200 -0.2
10ms/div 10ms/div
Figure 50. Figure 51.

REMOVE LOAD APPLY LOAD

(25mA Sink Response) (25mA Source Response)
0.2 0.2

0 0

-0.2 -0.2

-0.4 -0.4
VOUT (V)

VOUT (V)

-0.6 -0.6

-0.8 -0.8
0.988VPP +50V 0.988VPP +50V
-1.0 0.01Hz -1.0 0.01Hz

+125°C +125°C
- -

OPA454 OPA454
-1.2 +85°C + 2Hz
2ms Pulse
-1.2 + 2Hz
2ms Pulse
+85°C
+25°C -50V Mercury -50V Mercury +25°C
-1.4 Wetted -1.4 Wetted
-55°C Relay Relay -55°C
-1.6 -1.6
10ms/div 10ms/div
Figure 52. Figure 53.

(9) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown.
(10) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown.
(11) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown.

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TYPICAL CHARACTERISTICS (continued)

At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.

REMOVE LOAD
(25mA Source Response) POWER ON
1.6
+125°C RL = 1.8kW V+
1.4 +85°C
+25°C VOUT
1.2
-55°C
1.0 0.988VPP +50V
0.01Hz
- Flag

20V/div
VOUT (V)

OPA454
0.8 + 2Hz
2ms Pulse 0
0.6 -50V Mercury
Wetted
Relay

0.4
Delay in V- is due to
0.2 V-
test equipment.
Power supplies may be
0
applied in any sequence.
-0.2
10ms/div 20ms/div
Figure 54. Figure 55.

POWER OFF
V+ RL = 1.8kW

VOUT

Flag
20V/div

V-

20ms/div
Figure 56.

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APPLICATIONS INFORMATION
POWER SUPPLIES
Figure 57 shows the OPA454 connected as a basic
noninverting amplifier. The OPA454 can be used in The OPA454 may be operated from power supplies
virtually any ±5V to ±50V op amp configuration. It is up to ±50V or a total of 100V with excellent
especially useful for supply voltages greater than performance. Most behavior remains unchanged
36V. throughout the full operating voltage range.
Parameters that vary significantly with operating
Power-supply terminals should be bypassed with voltage are shown in the Typical Characteristics.
0.1µF (or greater) capacitors, located near the
power-supply pins. Be sure that the capacitors are Some applications do not require equal positive and
appropriately rated for the power-supply voltage negative output voltage swing. Power-supply voltages
used. do not need to be equal. The OPA454 can operate
with as little as 10V between the supplies and with up
V+ to 100V between the supplies. For example, the
0.1mF IP positive supply could be set to 90V with the negative
V+ supply at –10V, or vice-versa (as long as the total is
less than or equal to 100V).
(1) R2
R1 RP R2 G = 1+
R1 INPUT PROTECTION
V+
Status The OPA454 has increased protection against
-IN Flag damage caused by excessive voltage between op
VOUT
OPA454 VOUT amp input pins or input pin voltages that exceed the
+IN E/D
VIN power supplies; external series resistance is not
E/D Com RL
V-
needed for protection. Internal series JFETs limit
0.1mF input overload current to a non-destructive 4mA, even
with an input differential voltage as large as 120V.
Additionally, the OPA454 has dielectric isolation
V- V- between devices and the substrate. Therefore, the
amplifier is free from the limitations of junction
(1) Pull-up resistor with at least 10µA (choose isolation common to many IC fabrication processes.
RP = 1MΩ with V+ = 50V for IP = 50µA).

Figure 57. Basic Noninverting Amplifier LOWERING OFFSET VOLTAGE AND DRIFT
Configuration The OPA454 can be used with an OPA735 zero-drift
series op amp to create a high-voltage op amp circuit
that has very low input offset temperature drift. This
circuit is shown in Figure 58.

Low Offset, 5mV, Drift, High-Voltage Op Amp

0.05mV/°C, Self-Zeroing Op Amp Gain 2nd = 9.45V/V
Gain 1st = 4.9V/V
R1, 2nd R2, 2nd
R1, 1st R2, 1st 10kW 84.5kW
10kW 39.1kW

V+
V+ 2nd Stage, +50V
1st Stage, +5V
VOUT 2nd Stage
VOUT 1st Stage
OPA454
OPA735 A2, 2nd Stage RLOAD
A1, 1st Stage 10kW
V-
VG = ±1V VOUT 1st Stage ±4.9V, Max 2nd Stage, -50V
V-
1st Stage, -5V VOUT 2nd Stage ±46V (92VPP), Max

VINPUT = ±1VPP

Figure 58. Two-Stage, High-Voltage Op Amp Circuit With Very Low Input Offset Temperature Drift

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INCREASING OUTPUT CURRENT R1 R2

The OPA454 drives an output current of a few

(1)
milliamps to greater than 50mA while maintaining MASTER RS
good op amp performance. See Figure 7 for 10W
open-loop gain versus temperature at various output A1 OPA454
current levels. VIN

In applications where the 25mA output current is not

sufficient to drive the required load, the output current (1)
RS
can be increased by connecting two or more
10W
OPA454s in parallel, as Figure 59 shows. Amplifier A2 OPA454
A1 is the master amplifier and may be configured in
virtually any op amp circuit. Amplifier A2, the slave, is RL
SLAVE
configured as a unity-gain buffer. Alternatively,
external output transistors can be used to boost
output current. The circuit in Figure 60 is capable of
supplying output currents up to 1A, with the (1) RS resistors minimize the circulating current that always flows
transistors shown. between the two devices because of VOS errors.

Figure 59. Parallel Amplifiers Increase Output

UNITY-GAIN NONINVERTING Current Capability
CONFIGURATION
When in the noninverting unity-gain configuration, the
OPA454 has more gain peaking with increasing
positive common-mode voltage and increasing
temperature. It has less gain peaking with more
negative common-mode voltage. As with all op amps,
gain peaking increases with increasing capacitive
load. A resistor and small capacitor placed in the
feedback path can reduce gain peaking and increase
stability.

R1 R2

+50V

NPN
TIP29C, MJL21194,
MJE15003, MJL3281
CF
R4
(1) 0.2W
-IN V+ R3
(2) 20W
VOUT
(3)
OPA454 VO = VOUT - ILRL
+IN
VIN
V- R5
RL IL
0.2W
PNP
TIP30C, MJL21193,
MJE15004, MJL1302A

-50V

(1) Provides current limit for OPA454 and allows the amplifier to drive the load when the output is between +0.7V and –0.7V.
(2) Op amp VOUT swings from +47V to –48V.
(3) VO swings from +44.1V to –45.1V at IL = 1A.

Figure 60. External Output Transistors Boost Output Current Greater Than 1A

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INPUT RANGE -46.0

TA = +25°C
The OPA454 is specified to give linear operation with -46.5
input swing to within 2.5V of either supply. Generally, -47.0
a gain of +1 is the most demanding configuration. -47.5
Figure 61 and Figure 62 show output behavior as the

Voltage (V)
VOUT
input swings to within 0V of the rail, using the circuit -48.0
RS = 50kW
shown in Figure 64. Figure 63 shows the behavior -48.5
with an input signal that swings beyond the specified -49.0
input range to within 1V of the rail, also using the VIN VOUT
circuit in Figure 64. Notice that the beginning of the
-49.5
f = 1kHz RS = 0W
phase reversal effect may be reduced by inserting -50.0
V-
series resistance (RS) in the connection to the -50.5
positive input. Note that VOUT does not swing all the 0 20 40 60 80 100
way to the opposite rail. Time (ms)

50.5 Figure 63. Output Voltage With Input Voltage

V+ TA = +25°C
Down To (V–) + 1V
50.0
VIN VOUT
49.5 f = 1kHz RS = 50kW RF
Voltage (V)

49.0 10kW

48.5 V+ = +50V

48.0
VOUT RS OPA454 VOUT
47.5
R S = 0W RL
4.8kW
47.0 V- = -50V
VIN
0 20 40 60 80 100
Time (ms)

Figure 61. Output Voltage With Input Voltage Up

To V+ Figure 64. Input Range Test Circuit

-46.0
OUTPUT RANGE
TA = +25°C
-46.5 The OPA454 is specified to swing to within 1V of
-47.0
VOUT either supply rail with a 49kΩ load while maintaining
RS = 0W excellent linearity. Swing to the rail decreases with
-47.5
increasing output current. The OPA454 can swing to
Voltage (V)

VOUT
-48.0
RS = 50kW
within 2V of the negative rail and 3V of the positive
-48.5 rail with a 1.88kΩ load. The typical characteristic
-49.0
curve, Output Voltage Swing vs Output Current
VIN (Figure 11), shows this behavior in detail.
-49.5
f = 1kHz
-50.0
V-
-50.5
0 20 40 60 80 100
Time (ms)

Figure 62. Output Voltage With Input Voltage

Down To V–

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OPEN-LOOP GAIN LINEARITY SETTLING TIME

Figure 65 shows the nonlinear relationship of AOL and The circuit in Figure 66 is used to measure the
output voltage. As Figure 65 shows, open-loop gain is settling time response. The left half of the circuit is a
lower with positive output voltage levels compared to standard, false-summing junction test circuit used for
negative voltage levels. Specifications in the settling time and open-loop gain measurement. R1
Electrical Characteristics table are based upon the and R2 provide the gain and allow for measurement
average gain measured at both output extremes. without connecting a scope probe directly to the
summing junction, which can disturb proper op amp
AOL is a Function of VOUT and ILOAD
function by causing oscillation.
TP = +25°C The right half of the circuit looks at the combination of
both inverting and noninverting responses. R5 and R6
RL = 1880W, 1mV/div remove the large step response. The remaining
|(VIN+) - (VIN-)|

RL = 900W, 2mV/div 74dB 89dB voltage at V2 shows the small-signal settling time that
is centered on zero. This test circuit can be used for
incoming inspection, real-time measurement, or in
designing compensation circuits in system
applications.
RL = 4.87kW, 200mV/div 106dB

Table 2. Settling Time Measurement Circuit

Configuration Using Different Gain Settings for
-50 -40 -30 -20 -10 0 10 20 30 40 50 Figure 66
Output Voltage (V)
GAIN
COMPONENT 1 5 10
Figure 65. Differential Input Voltage (+IN to –IN)
versus Output Voltage R1 (Ω) 10k 2k 1k
R3 (Ω) 10k 2k 1k
R7 (Ω) 10k 4k 9k
R8 (Ω) ∞ 1k 1k
VIN (VPP) 20 16 8

Inverting Response
Measured Here, V1

R2
R1 10kW

R4 Combination of Both
R3 10kW Inverting and R7 R8
Noninverting Responses, V2

R5 R6
-IN 10kW 10kW -IN
VOUT VOUT
OPA454 OPA454
+IN +IN
A1 A2

VIN

Figure 66. Settling Time Test Measurement Circuit

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avoided to maximize reliability. It is always best to

ENABLE AND E/D Com
If left disconnected, E/D Com is pulled near V–
(negative supply) by an internal 10µA current source.
When left floating, ENABLE is held approximately 2V
above E/D Com by an internal 1µA source. Even
though active operation of the OPA454 results when
the ENABLE and E/D Com pins are not connected, a
moderately fast, negative-going signal capacitively
coupled to the ENABLE pin can overpower the 1µA
pull-up current and cause device shutdown. This
behavior can appear as an oscillation and is
encountered first near extreme cold temperatures. If
the enable function is not used, a conservative
approach is to connect ENABLE through a 30pF
capacitor to a low impedance source. Another
alternative is the connection of an external current
source from V+ (positive supply) sufficient to hold the
enable level above the shutdown threshold. Figure 67
shows a circuit that connects ENABLE and E/D Com.
Choosing RP to be 1MΩ with a +50V positive power
supply voltage results in IP = 50µA.
V+
(Positive Op Amp Supply)
IP
RP
DVDD
(Digital Supply)
provide proper heat-sinking (either by a physical plate
or by airflow) to remain considerably below the
thermal shutdown threshold. For longest operational
life of the device, keep the junction temperature
below +125°C.
THERMAL PROTECTION
Figure 68 shows the thermal shutdown behavior of a
socketed OPA454 that internally dissipates 1W.
Unsoldered and in a socket, θJA of the DDA package
is typically +128°C/W. With the socket at +25°C, the
output stage temperature rises to the shutdown
temperature of +150°C, which triggers automatic
thermal shutdown of the device. The device remains
in thermal shutdown (output is in a high-impedance
state) until it cools to +130°C where it again is
powered. This thermal protection hysteresis feature
typically prevents the amplifier from leaving the safe
operating area, even with a direct short from the
output to ground or either supply. The rail-to-rail
supply voltage at which catastrophic breakdown
occurs is typically 135V at +25°C. However, the
absolute maximum specification is 120V, and the
OPA454 should not be allowed to exceed 120V under
any condition. Failure as a result of breakdown,
caused by spiking currents into inductive loads
(particularly with elevated supply voltage), is not
prevented by the thermal protection architecture.

40 140
V+
20 120
-IN E/D 5V Logic VOUT
OPA454 VOUT 0 100

+IN E/D Com -20 80

VFLAG (V)
VOUT (V)

V-
-40 60

-60 40

-80 20
VFLAG
V- -100 0
(Negative Op Amp Supply)
-120 -20
0 200 400 600 800 1000
Figure 67. ENABLE and E/D Com (ms)

10kW 100kW
CURRENT LIMIT
+50V
Figure 24 and Figure 48 to Figure 50 show the +2.5V
10Hz Square Wave
current limit behavior of the OPA454. Current limiting
RP
is accomplished by internally limiting the drive to the 1MW
output transistors. The output can supply the limited VFLAG
current continuously, unless the die temperature rises -IN V+ Flag
to +150°C, which initiates thermal shutdown. With VOUT
VOUT
adequate heat-sinking, and use of the lowest possible +IN OPA454
E/D Com
supply voltage, the OPA454 can remain in current V- 625W
limit continuously without entering thermal shutdown. -50V
Although qualification studies have shown minimal
parametric shifts induced by 400 hours of thermal
shutdown cycling, this mode of operation should be Figure 68. Thermal Shutdown
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POWER DISSIPATION HEATSINKING

Power dissipation depends on power supply, signal,
and load conditions. For dc signals, power dissipation
is equal to the product of the output current times the
voltage across the conducting output transistor,
PD = IL (VS – VO). Power dissipation can be
minimized by using the lowest possible power-supply
voltage necessary to assure the required output
voltage swing.
For resistive loads, the maximum power dissipation
occurs at a dc output voltage of one-half the
power-supply voltage. Dissipation with ac signals is
lower because the root-mean square (RMS) value
determines heating. Application Bulletin SBOA022
explains how to calculate or measure dissipation with
unusual loads or signals. For constant current source
circuits, maximum power dissipation occurs at the
minimum output voltage, as Figure 69 shows.
The OPA454 can supply output currents of 25mA and
larger. Supplying this amount of current presents no
problem for some op amps operating from ±15V
supplies. However, with high supply voltages, internal
power dissipation of the op amp can be quite high.
Operation from a single power supply (or unbalanced
power supplies) can produce even greater power
dissipation because a large voltage is impressed
across the conducting output transistor. Applications
with high power dissipation may require a heatsink, or
heat spreader.
Power dissipated in the OPA454 causes the junction
temperature to rise. For reliable operation, junction
temperature should be limited to +125°C, maximum.
Maintaining a lower junction temperature always
results in higher reliability. Some applications require
a heatsink to assure that the maximum operating
junction temperature is not exceeded. Junction
temperature can be determined according to
Equation 1:
TJ = TA + PD qJA (1)
Package thermal resistance, θJA, is affected by
mounting techniques and environments. Poor air
circulation and use of sockets can significantly
increase thermal resistance to the ambient
environment. Many op amps placed closely together
also increase the surrounding temperature. Best
thermal performance is achieved by soldering the op
amp onto a circuit board with wide printed circuit
traces to allow greater conduction through the op
amp leads. Increasing circuit board copper area to
approximately 0.5in2 decreases thermal resistance;
however, minimal improvement occurs beyond 0.5in2,
as shown in Figure 70.
For additional information on determining heatsink
requirements, consult Application Bulletin SBOA021
(available for download at www.ti.com).
60
Thermal Resistance, qJA (°C/W)

R1 R2 50
100kW 10kW
V1
40
+50V

-IN V+ 30
VOUT
OPA454 20
+IN
V- R5
R3 R4
100W 10
100kW -50V 9.9kW
V2
0
0 0.5 1.0 1.5 2.0 2.5 3.0
2
IL RL Copper Area (inches ), 2 oz
IL = [(V2 - V1)/R5] (R2/R1)
= (V2 - V1)/1kW Figure 70. Thermal Resistance versus Circuit
Compliance Voltage Range = +47V, -48V Board Copper Area

NOTE: R1 = R3 and R2 = R4 + R5.

Figure 69. Precision Voltage-to-Current Converter

with Differential Inputs

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PowerPAD THERMALLY-ENHANCED BOTTOM-SIDE PowerPAD PACKAGE

PACKAGES
The OPA454 comes in SO-8 and HSOP-20
PowerPAD versions that provide an extremely low
thermal resistance (θJC) path between the die and the
exterior of the package. These packages feature an
exposed thermal pad. This thermal pad has direct
thermal contact with the die; thus, excellent thermal
performance is achieved by providing a good thermal
path away from the thermal pad.
TOP-SIDE PowerPAD PACKAGE
The OPA454 DWD, HSOP-20, PowerPAD package
has the exposed pad on the top side of the package,
as Figure 71b shows. The top-side thermal pad can
be used with commercially available heat-sinks and
moving air to dissipate heat. The use of an external
top-side heat-sink increases the effective surface
area of the package face, which increases convection
and radiation off the top surface of the package.
Top-side heatsinking also avoids unnecessary
heating of the printed circuit board (PCB), and
permits installation of other PCB components onto
the side opposite of the OPA454.
The OPA454 SO-8 PowerPAD is a standard-size
SO-8 package constructed using a downset
leadframe upon which the die is mounted, as
Figure 71a shows. This arrangement results in the
lead frame being exposed as a thermal pad on the
underside of the package. The thermal pad on the
bottom of the IC can then be soldered directly to the
PCB, using the PCB as a heatsink. In addition,
plated-through holes (vias) provide a low thermal
resistance heat flow path to the back side of the PCB.
This architecture enhances the OPA454 power
dissipation capability significantly, eliminates the use
of bulky heatsinks and slugs traditionally used in
thermal packages, and allows the OPA454 to be
easily mounted using standard PCB assembly
techniques. NOTE: Because the SO-8 PowerPAD is
pin-compatible with standard SO-8 packages, the
OPA454 is a drop-in replacement for operational
amplifiers in existing sockets. Soldering the
bottom-side PowerPAD to the PCB is always
required, even with applications that have low power
dissipation. Soldering the device to the PCB provides
the necessary thermal and mechanical connection
between the leadframe die pad and the PCB.

Leadframe (Copper Alloy)

IC (Silicon) Die Attach (Epoxy)
External Heatspreader
Die Pad
Die Thermal
Attach Chip Paste

Power Transistor

Leadframe Die Pad

Mold Compound (Plastic) Exposed at Base of the Package Board
(Copper Alloy)

a) SO-8 PowerPAD cross-section view. b) HSOP-20 PowerPAD cross-section view.

Figure 71. Cross-Section Views of a PowerPAD Package

22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): OPA454


www.ti.com
BOTTOM-SIDE PowerPAD LAYOUT
GUIDELINES
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
must be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other
heat-dissipating device. Soldering the PowerPAD to
the PCB is always required, even with applications
that have low power dissipation. Follow these steps
to attach the device to the PCB:
1. The PowerPAD must be connected to the most
negative supply voltage on the device, V–.
2. Prepare the PCB with a top-side etch pattern.
There should be etching for the leads as well as
etch for the thermal pad.
3. Use of thermal vias improves heat dissipation,
but are not required. The thermal pad can
connect to the PCB using an area equal to the
pad size with no vias, but externally connected to
V–.
4. Place recommended holes in the area of the
thermal pad. Recommended thermal land size
and thermal via patterns for the SO-8 DDA
package are shown in the thermal land pattern
mechanical drawing appended at the end of this
document. These holes should be 13 mils in
diameter. Keep them small, so that solder wicking
through the holes is not a problem during reflow.
The minimum recommended number of holes for
the SO-8 PowerPAD package is five.
5. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. These vias help dissipate the heat
generated by the OPA454 IC. These additional
vias may be larger than the 13-mil diameter vias
directly under the thermal pad. They can be
larger because they are not in the thermal pad
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): OPA454
OPA454
SBOS391 – DECEMBER 2007
area to be soldered; thus, wicking is not a
problem.
6. Connect all holes to the internal power plane of
the correct voltage potential (V–).
7. When connecting these holes to the plane, do not
use the typical web or spoke via connection
methodology. Web connections have a high
thermal resistance connection that is useful for
slowing the heat transfer during soldering
operations, making the soldering of vias that have
plane connections easier. In this application,
however, low thermal resistance is desired for the
most efficient heat transfer. Therefore, the holes
under the OPA454 PowerPAD package should
make the connections to the internal plane with a
complete connection around the entire
circumference of the plated-through hole.
8. The top-side solder mask should leave the
terminals of the package and the thermal pad
area exposed. The bottom-side solder mask
should cover the holes of the thermal pad area.
This masking prevents solder from being pulled
away from the thermal pad area during the reflow
process.
9. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
10. With these preparatory steps in place, the
PowerPAD IC is simply placed in position and run
through the solder reflow operation as any
standard surface-mount component. This
preparation results in a properly installed part.
For detailed information on the PowerPAD package,
including thermal modeling considerations and repair
procedures, see technical brief SLMA002 PowerPAD
Thermally-Enhanced Package, available for download
at www.ti.com.
Submit Documentation Feedback 23
OPA454

www.ti.com
SBOS391 – DECEMBER 2007

TYPICAL APPLICATIONS
Figure 72 and Figure 73 illustrate the OPA454 in a programmable voltage source and a bridge circuit,
respectively.

+95V
0.1mF

45.3kW

0-2mA V+
DAC8811 -IN
or
DAC7811 OPA454
+IN VOUT = 0V to +91V
Protects DAC
During Slewing V- RL
0.1mF

-5V

Figure 72. Programmable Voltage Source

R1 R2 R3
1kW 9kW 10kW

R4
10kW

+50V +50V
Up To
-IN V+ 195V V+ -IN
VOUT VOUT
MASTER OPA454 OPA454 SLAVE
VIN +IN A1 A2 +IN
(1)
±4V V- Piezo V-
Crystal
-50V -50V

(1) For transducers with large capacitance, stabilization may become an issue. Be certain that the Master amplifier is stable before stabilizing
the Slave amplifier.

Figure 73. Bridge Circuit Doubles Voltage for Exciting Piezo Crystals

24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): OPA454

 OPA454

www.ti.com
SBOS391 – DECEMBER 2007

Figure 74 uses three OPA454s to create a V+

high-voltage instrumentation amplifier. VCM ± VSIG V1
must be between (V–) + 2.5V and (V+) – 2.5V. The
maximum supply voltage equals ±50V or 100V total. OPA454
A1
Figure 75 uses three OPA454s to measure current in R4 R5
a high-side shunt application. VSUPPLY must be V-
greater than VCM. VCM must be between (V–) + 2.5V R2 V+
and (V+) – 2.5V. Adhering to these restrictions keeps
V1 and V2 within the voltage range required for linear
VSIG OPA454 VOUT
operation of the OPA454. For example, if V+ = 50V R1 (1)
A3
and V– = 50V, then V1 = +47.5V (maximum) and
V2 = –47.5V (minimum). The maximum supply R2
voltage equals ±50V, or 100V total. V-
R6 R7
V+
See Figure 76 and Figure 79 for example circuits that
use the OPA454 in an output voltage boost
configurations in three and six op amp output stages, OPA454
respectively. A2
V2 VOUT = (1 + 2R2/R1) (V2 - V1)
VCM V-

(1) The linear input range is limited by the output swing on the
input amplifiers, A1 and A2.

Figure 74. High-Voltage Instrumentation Amplifier

RSHUNT

V+
Plus V1 Load
VSUPPLY or
Minus
OPA454
(1)
A1
R4 R5

V-
R2 V+

OPA454 VOUT
R1 (2)
A3
R2
V-
R6 R7
V+

OPA454
(1)
A2
V2 VOUT = (1 + 2R2/R1) (V2 - V1)

V-

(1) To increase the linear input voltage range, configure A1 and A2 as unity-gain followers.
(2) The linear input range is limited by the output swing on the input amplifiers, A1 and A2.

Figure 75. High-Voltage Instrumentation Amplifier for Measuring High-Side Shunt

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Link(s): OPA454
OPA454

www.ti.com
SBOS391 – DECEMBER 2007

+100V +100V
10kW 10kW

+100V +100V
100kW 100kW
V+ V+
V01 V04
OPA454 OPA454
A1 A4
V- V-
10kW 190kW 10kW 200kW

100kW 100kW

VLOAD = +97V, -98V VIN VLOAD = +97V, -98V

V+ V+
VOUT (195VPP) VOUT (195VPP)
OPA454 OPA454
A3 A6
RLOAD RLOAD
V- 3.75kW V- 3.75kW
VIN

10kW 10kW

100kW 100kW

V02 V+ V05 V+
OPA454 OPA454
A2 A5

V- V-
100kW 100kW
-100V -100V

-100V -100V

a) Noninverting, G = +20V/V b) Inverting, G = -20V/V

Figure 76. Output Voltage Boost With +97V, –98V (195VPP) Across Load Connected to Ground (3 Op Amp
Output Stage, see Figure 77 and Figure 78)

100
100 6
75
V01 80
VOUT 4
50 60
VLOAD VIN
40
25 2
Voltage (V)

20
VOUT (V)

VIN (V)
0 0 0
-25 -20
V02 -2
-40
-50
-60
-4
-75 -80

-100 -100 -6
Time (20ms/div) Time (10ms/div)

Figure 77. 195VPP On 3.75kΩ Load to Ground Figure 78. 3.75kΩ Load to Ground
20kHz, Uses 3 OPA454s, 100V Supplies G = +20, 3 OPA454s, 100V Supplies
(Note SR of 18V/µs, which is slightly higher than
the specified 13V/µs due to tracking of the
power-supply voltage)

26 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): OPA454

 OPA454

www.ti.com
SBOS391 – DECEMBER 2007

+100V +100V
10kW 10kW

+120V +120V
100kW 100kW
V+ V+
OPA454 OPA454
A1 A4
V- V-
10kW 190kW 200kW 10kW
100kW 100kW
V+ RLOAD V+
(+97V, -98V) 7.5kW (-98V, +97V)
OPA454 OPA454
A3 A6
VLOAD
V- (±195V, 390VPP) V-

10kW 10kW
VIN
100kW 100kW

V+ V+
OPA454 OPA454
A2 A5

V- V-
100kW 100kW
-100V -100V

-100V -100V

Figure 79. Output Voltage Boost With ±195V (390VPP) Across Bridge-Tied Load (6 Op Amps, see
Figure 80 and Figure 81)

200
VLOAD 200 6
150
150
VIN VOUT 4
100
100
50 2
50
VOUT (V)

VOUT (V)

VIN (V)
0 0 0

-50 -50
-2
-100 -100
-4
-150 -150

-200 -6
-200
Time (10ms/div)
Time (20ms/div)

Figure 81. 7.5kΩ Load

Figure 80. 390VPP Across 7.5kΩ Load G = +20, 6 OPA454s, 100V Supplies
20kHz, Uses 6 OPA454s, 100V Supplies (Note SR of 34V/µs, which is significantly higher
than the specified 13V/µs due to tracking of the
power-supply voltage)

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Link(s): OPA454
OPA454

www.ti.com
SBOS391 – DECEMBER 2007

R1 R2 A red light emitting diode (LED) was used to generate

25kW 25kW Figure 84.
V1
Gain of the avalanche photodiode (APD) is adjusted
by changing the voltage across the APD. Gain starts
to increase when reverse voltage is increased beyond
OPA454 VOUT = V2 - V1
130V for this API diode. Figure 85 shows this
structure.
R3 R4
25kW 25kW
V2 6V 14

12
VOUT
10

VOUT (1V/div)
Figure 82. High-Voltage Difference Amplifier 8

VLED (V)
6

4
HIGH-COMPLIANCE VOLTAGE CURRENT VLED
SOURCES 0V 2

This section describes four different applications 0

utilizing high compliance voltage current sources with -2V -2

differential inputs. Figure 69 and Figure 83 illustrate 5ms/div
the different applications.
Figure 84. Avalanche Photodiode Circuit
25kW 25kW
V1

OPA454
A1

25kW 25kW R
V2 OPA454
A2

Load IO
IO = (V2 - V1)/R

Figure 83. Differential Input Voltage-to-Current

Converter for Low IOUT

28 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): OPA454

 OPA454

www.ti.com
SBOS391 – DECEMBER 2007

R7 R1
10kW 90kW

+100V
+100V
R2 R4
V+
V+ 1kW 100kW
OPA454
OPA454 A2
A1 V- +100V
V- VOUT = 100 ´ RSENSE ´ ID
V+

OPA454 VOUT +100V

+ A4
Gain Adjust Voltage RSENSE
V1 2.5V to 9.5V 100W V-
+100V R8
198kW
R3
V+
1kW
OPA454 R9
A3
4.9kW
V- R5
100kW
LM4041D
Adjusted for 2.0V 100W

APD

LED VLED R10

3.1kW
-200V
Advanced Photonix, Inc.
SD 036-70-62-531
Example Circuit For Reverse Biasing APD Digi-Key
(130V to 280V, max) SD 036-70-62-531

Figure 85. APD Gain Adjustment Using the OPA454, High-Voltage Op Amp

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Link(s): OPA454
 PACKAGE OPTION ADDENDUM
www.ti.com 31-Dec-2007

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
OPA454AIDDA ACTIVE SO DDA 8 75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
Power no Sb/Br)
PAD
OPA454AIDDAR ACTIVE SO DDA 8 2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
Power no Sb/Br)
PAD
OPA454AIDWD PREVIEW HSOP DWD 20 75 TBD Call TI Call TI
OPA454AIDWDR PREVIEW HSOP DWD 20 2000 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
OPA454AIDDAR SO DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA454AIDDAR SO PowerPAD DDA 8 2500 346.0 346.0 29.0

Pack Materials-Page 2
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