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Closed Loop Design and Implementation of ZVS

High Gain Super Boost DC DC Converter

Article · December 2016

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International Journal of Printing, Packaging & Allied Sciences, Vol. 4, No. 2, December 2016 735

Closed Loop Design and Implementation of ZVS

High Gain Super Boost DC-DC Converter
R. Senthilkumar and G. Mageswaran

Abstract--- Voltage Lift (VL) technique with Zero Voltage Switching (ZVS) the output voltage is increased in
arithmetic progression and it has been used in the design of DC-DC converters. Super-Lift (SL) technique with Zero
Voltage Switching(ZVS) is used to increase the voltage transfer gain using geometric progression than VL
technique. In this paper analysis, design and implementation of ZVS super boost DC-DC converter is carried out
with lower switching losses and increased efficiency. Simple control method is used to improve the power packing
density using dSpic micro controller. The soft switched super boost DC-DC converter offer greater benefits by
giving higher output voltage with small ripples. To verify the concept simulation and experimentation are carried
out. The performance of this converter is experimented for different duty cycles. Closed loop operation of the
converter is also verified experimentally for different inputs. The results reveal that the ZVS is achieved in all
aspects thereby resulting in reducing the switching losses and increased efficiency of 93% at rated load.

Keywords--- Arithmetic Progression, Duty Cycle, Geometric Progression, Super Boost, Soft Switching, Voltage
Lift, Zero Voltage Switching.

I. INTRODUCTION
In current scenario, converting dc to dc voltage with high-efficiency, high power density and cheap topology
with simple structure becomes a challenging task. Voltage and current stress across the switching devices Switching
stresses and switching losses of semiconductor devices in high-frequency high-power conversion greatly impair the
reliability and performance of the converter. A successful soft-switching scheme should be able to reduce the
switching losses, diode reverse recovery, and switching stresses without increasing device voltage and current
stresses. In order to achieve the above mentioned targets , many techniques have been used in recent years [1]–
[8].The methodology used in [4] requires two additional switches, which have more current stress and the diode
used in circuit in [6] suffers from increased voltage stress. Energy which is wasted in the circuit of soft switched
topologies were proposed in [5] and [7] and it is difficult to achieve at light load. However, stress due to current is
increased and the design becomes tough. Also, lossless, soft switching cannot be achieved when output voltage
exceeds double the input voltage, and the duty cycle range in[9] is restricted by the soft-switching resonant
commutation for the method proposed in [8] and [9].The DC-DC converters said in [11-15] were having greater
switching losses, decreased reliability and Electromagnetic Interference (EMI) .

R. Senthilkumar Department of Electrical & Electronics Engineering, Saveetha Engineering College, Thandalam, Chennai, India.
G. Mageswaran, Department of Electrical & Electronics Engineering, Saveetha Engineering College, Thandalam, Chennai, India.

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The switching devices in the converters are controlled using Pulse Width Modulation(PWM) to have a desired
output voltage. These devices are switched on and off at the load current with a high di/dt value. The switching loss
could be a significant portion of the total power loss in the converter circuits. Also the converters when operated at
high switching frequencies are subjected to high switching losses and high voltage stress across the devices.

EMI is also produced due to high di/dt and dv/dt in the converter [18]. To reduce the switching losses, EMI and
to increase the power density, soft switched Quasi Resonant (QR) DC-DC converters with high voltage conversion
ratio are used [10].These converters offer improved efficiency then the hard switched converters by having either
Zero Voltage Switching (ZVS) or Zero Current Switching (ZCS) in the converter operation[16, 17].

The soft switching has many advantages over the hard switching such as decrease in stress of the voltage and
current across the switching devices, dv/dt and di/dt problems can be minimized so that EMI can be reduced. Many
soft switching methods are present to implement resonance characteristics. Most popularly ZVS-QR technique is
used to have two zero crossing points for turning switch on and off[18].To improve the efficiency and increase the
converter output voltage it is proposed to have ZVS techniques to the new voltage boost DC-DC converter.

The positive output super boost DC-DC converter performs the voltage conversion using Voltage Lift (VL)
technique. The converter operates in the first quadrant with large voltage amplification. These converters are driven
by a PWM signal and can transfer power with high power density. However, the switching power losses are usually
high during the transfer of power. The soft switching technique is an effective way to reduce the converter power
losses and improve the efficiency.

II. PRINCIPLE OF OPERATION OF ZVS SUPER BOOST DC-DC CONVERTER

The circuit diagram of Zero Voltage Switching super boost DC-DC converter is shown in Fig.1.It contains a
static switch S with resonating components Cr and Lr; an inductor L1; two diodes D1 and D2; twocapacitorsC1 and C2
and the load resistance R. The PWM signal is given with conduction duty ratio k and repeating switching frequency
fs.Vin and Iin are the input voltage and current and V0 and I0are output voltage and current. The voltage transfer gain
is Ms= V0/Vin.

To analyze the steady-state values of the converter operating in conduction mode continuously, the following are
to be taken into account:

1. Ideal - Semiconductor switches’

2. Ideal -Reactive elements.
3. Value of L1is more than Lr.
4. C2 and R act as a constant voltage sink.
The period of switching time is T = 1/fs, so that kT is the switch-on period and(1 – k)Tis switch-off period. The
converter has voltage increasing componentsD1-C1-L1-D2and acapacitorfilterC2.Capacitor C1is to increase voltage
VC by twice the input voltage Vin.

Four modes of operation is used to analyze and determine the steady-state values of the converter and it is given
below:

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Figure 1: Circuit Diagram of ZVS Super Boost DC-DC Converter

A. Mode1: Voltage Rising Interval (t0- t1)

When switch Sis put off at t = t0, the vCr(t)linearly increases with the slope Im/Cr where Im is the magnetizing
current. The deduced diagram of this mode is shown in Fig. 2a.In this mode D1diodeconductsand D2is in turn off
state. The vCr(t) and iLr(t)are given by

Im t
vCr (t ) = (1)
Cr
i Lr (t ) = I m (2)
At t= t1 ,VCr(t1)= Vin , thetime period of this mode is T1and it is given as

Vin C r
T1 = (3)
Im
B. Mode2:Resonance Interval (t1 - t2 )
In this mode as the switch S remains turned off, the components Lr and Cr form a resonant series circuit and
resonance will occur; as shown in Fig: 3. The current iLr starts decreasing, the diodeD1goesto off state and D2enters
in the conducting state. The exact circuit diagram of this mode is shown in Fig: 2b. Current iL1goes through inductor
L1to increase the charge capacitor C1. Stored energy in Inductor L1is moved to capacitor C1. In that time,
currentiD2pass through(C2– R) circuit, to keep the current continuous. The difference in currentsiL1and iC1aremeager,
so iL1 = IL1and iC1 = IC1 ,it is given as

Vin t1
I L1 = (4)
L1
The capacitor current is given as

VC C1
I C1 = (5)
t1
When the voltage across the capacitor vCr(t)> Vin, the components Lr and Cr start resonating. This interval is
called as resonance interval. The capacitor voltage waveform is a alternating and reaches its maximum value VCr(peak)
and then reduces to zero at time t= t2.

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The peak resonating capacitor voltage is given as

VCr ( peak ) = Vin + Z 1 I m (6)

The resonating capacitor voltage is given as

vCr (t ) = Vin + Z 1 I m Sinω r t (7)

The resonating inductor current is given as

i Lr (t ) = I m Cosω r t (8)

Lr 1
Where, Z 1 = ωr =
Cr Lr C r
At t = t2, the vCr(t)decreases to zero and achieves ZVS for switch S.

vCr (t 2 ) = 0 (9)
i Lr (t 2 ) = − I m Cosα (10)

 Vin 
Where, α = Sin  
−1
I Z (11)
 m 0 
Period of this mode is given by

(π +α )
T2 = (t 2 − t1 ) = (12)
ω0
C. Mode 3 : Linear Recovery Interval (t2 - t3 )
When time t=t2, the device S is switched on at zero voltage condition. The resonating inductor current starts
linearly increasing with the slope Vin/(Lr+L1) .This is the linear recovery interval.

The circuit diagram for this mode is shown in Fig. 2c. Here, the D1 does not allow the vCr(t) to go negative,
vCr(t)= 0. Since load current I0 is constant, the current iLr increases linearly from-Im Cosα to+Im Cosα .A t = t3,the
diode D2becomes reverse biased and stops conducting. The time duration of this mode is given by,

( 2 I m Cosα ) ( Lr + L1 )
T3 = (13)
Vin
D. Mode 4: Conduction Interval (t3 - t4 )

The diode D1starts conducting and D2is blocked till t = t4, this is the usual turn on interval as shown in Fig: 3.
The input currenti1 = iL1+ iC1.The circuit diagram of this mode is shown in Fig: 2d. In this mode, iLr linearly increases
from 0 toI0 and it continues till the S is turned off at t = t4 and the cycle repeats. The time period of this mode is
given by

T4 = Ts − ( T1 + T2 + T3 ) (15)

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International Journal of Printing, Packaging & Allied Sciences, Vol. 4, No. 2, December 2016 739

Figure 2a: Mode 1: (t0 – t1)

Figure 2b: Mode 2: (t1 – t2)

Figure 2c: Mode 3: (t2 – t3)

Figure 2d: Mode 4: (t3 –t4)

Figure 2: Equivalent circuits of ZVS Super Boost Converter in four topological mode(a)Mode 1– t0≤ t ≤ t1
(b)Mode 2 – t1≤ t ≤ t2 (c)Mode 3 – t2≤ t ≤ t3(d) Mode 4 – t3≤ t ≤ t4

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III. ANALYSIS OF THE ZVS SUPER BOOST DC-DC CONVERTER

Consider the output power is equal to the input power

Pin = Po (or ) Vin I in = Vo I o (16)

Conservation of energy theory says that under ideal condition, the input energy Ein is equal to the output energy
E0over a switching period and they can be given by the following expressions:

T1 2 T4

Ein = Vin  ∫ i Lr (t ) dt + ∫ i Lr (t ) dt  (17)
 0 0 
E 0 = V0 I 0 Ts (18)

Therefore, the DC-DC transformation ratio is defined as

V0 1 I in  T 
Ms = = Ts − 1 − T2 − T3  (19a)
Vin Ts I 0  2 

By substituting the values of T1 – T3, (19a) is changed and it is given as

I in  Vin C r f s (π + α ) f s (2 I m cos α ) ( Lr + L1 ) f s 
Ms = 1 − − −  (19b)
Io  2 Im 2π f o Vin 

1
Resonant Frequency f r = (19c)
2 π Lr C r
Normalized Switching Frequency

fs
f ns = (19d)
fr
Characteristic circuit impedance

Lr
Zo = (19e)
Cr
Normalized Load Resistance

Ro
R= (19f)
Zo
Equation (19b) gives double solutions of Ms, of which, the maximum value (Mmax) is taken for design. Note that,
Ms is a function of R0 and fs. The value of Ms can be adjusted by varying fs.

Therefore, the change on iL1 is

Vin (V − 2Vin )
∆i L1 = kT = 0 (1 − k )T (20)
L1 L1

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(2 − k )
V0 = Vin (21)
(1 − k )
The voltage transfer gain in continuous mode is given by

V0 (2 − k )
Ms = = (22)
Vin (1 − k )
The source current iinis equal to (iL1 + iC1) during turn-on, and equal to iL1 during turn-off. Capacitor current iC1 is
equal to iL1 during turn-off. Under constant condition, the average charge should not change across capacitor C1.

The following relations are obtained:

iin −off = i L1−off = iC1−off (23)

iin −on = i L1−on + iC1−on (24)

kT iC1−on = (1 − k )T iC1−off
If inductance L1 is more then,iL1 is approximately same as average current IL1.

Therefore,

iin −off = iC1−off = I L1 (25)

(1 − k ) I
iin −on = I L1 + I L1 = L1 (26)
k k
(1 − k )
iC1−on = I L1 (27)
k
Average input current

I in = k iin −on + (1 − k )iin −off

(28)
= I L1 + (1 − k ) I L1 = (2 − k ) I L1

Figure 3: Theoretical Waveforms of ZVS Super Boost DC-DC Converter

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VCr

Vpulse

ILr
Time (sec)

Figure 4: Simulated Waveforms of Resonating Capacitor Voltage, Generated Pulse Signal and Resonating Inductor
Current of Switch S.

IV. DESIGN OF THE ZVS SUPER BOOST DC-DC CONVERTER

The ZVS Super Boost DC-DC Circuit as shown in Fig. 1 is designed with the following values:

Vin=10 V, Lr= 7μH, Cr= 0.25μF,L1=32μH,C1=1μF, C2=2200μF, I0=0.06A to 0.072,V0=30V–36V and R0 = 500 Ω
for k= 0.5.The converter is simulated using the MATLAB/ Simulink with the calculated values. Fig.4 shows the
waveforms of generated gate pulse, resonant capacitor voltage and resonant inductor current. From the graph it is
noted that the switch S is turned on at zero voltage. Theoretical waveforms shown in Fig.3and the simulated
waveforms are closely same. The voltage and current at the output under open-loop operation for duty cycle of k =
0.5areshown in Fig. 5.

Figure 5: Output Voltage and Current for the duty cycle k=0.5

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V. EXPERIMENTATION OF ZVS SUPER BOOST DC-DC CONVERTER

To verify the design outline of ZVS Super Boost DC-DC Converter, a model of this circuit is developed and
validated. The inductors in the circuit are of ferrite type and the capacitors are of plain polyester. The diode FR107
is placed in the circuit which is a fast recovery diode with high flexibility. The IRF540N is power MOSFET which
is used as an active switch which can carry high current at high frequency and can be turned on easily. The open
loop experimental waveforms are shown in the Figures: 9(a) to 9(d). It is noted that the device is switched on when
the voltage across resonant capacitor goes zero to have ZVS condition. The practical waveforms obtained resemble
the simulated waveforms as shown in the Fig.4 and 5. The deviations observed between the simulation and
experimental waveforms is due to parasitic and noise. The triggering pulse at 50 kHz with variable duty cycle is
generated using dSpic30F4011 controller and it is fed to the driver circuit which consists of opto-coupler(TLP250),
Fast recovery diode (FR107) , Transistors (2N222 and BC558) and Zener Diode.

Figure 6: Driver Circuit

The driver circuit is shown in Fig. 6. The performance of the converter is studied under constant load condition
for different duty cycles.

With fs=50 kHz, Vin = 10 V and RO= 500 Ω, the output voltages and gain values for varying duty cycle are
shown in Table: I and they are graphically shown in Figures 7 and 8.

Table 1

Iin (A) VO (V) IO (A) Duty Cycle (K) MS %η

0.211 30 0.06 0.4 3.0 85.3
0.227 32 0.064 0.43 3.2 90.2
0.239 33 0.066 0.46 3.3 91.1
0.251 34 0.068 0.5 3.4 92.1
0.262 35 0.07 0.53 3.5 93.5
0.278 36 0.072 0.56 3.6 93.2
0.297 37 0.074 0.6 3.7 92.1

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International Journal of Printing, Packaging & Allied Sciences, Vol. 4, No. 2, December 2016 744

4
3.5
3

Gain (Ms)
2.5
2
1.5
1
0.5
0
0.4 0.43 0.46 0.5 0.53 0.56 0.6
Duty Cycle (k)

Figure 7: Variation of Gain for Different Duty Cycles

40
35
Output Voltage ( Vo)

30
25
20
15
10
5
0
0.4 0.43 0.46 0.5 0.53 0.56 0.6
Duty Cycle (k)

Figure 8: Variation of Output Voltage for Different Duty Cycles

Figure 9(a): Pulse Generated using dSpicMicrocontroller X-axis: 9μs/div , Y-axis: 2 Volts/div

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International Journal of Printing, Packaging & Allied Sciences, Vol. 4, No. 2, December 2016 745

Figure 9(b): Resonating Capacitor Voltage across Switch S, X-axis: 10μs/div, Y-axis: 5 Volts/div

Figure 9(c): Resonating Inductor Current (Switch S). X-axis: 10.8μs/div, Y-axis:100mV/div

Figure 9(d): Output Voltage (33 V) X-axis: 9.8ms/div, Y-axis: 5 Volts/div

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International Journal of Printing, Packaging & Allied Sciences, Vol. 4, No. 2, December 2016 746

VI. EXPERIMENTAL CLOSED LOOP- ZVS SUPER BOOST DC-DC CONVERTER

Super Boost ZVS DC –DC Converter closed-loop block is shown in Fig. 10.In this, the voltage at output is
sensed using the potential divider and fed through a signal conditioner and then to the A to D Converter. The output
from A to D converter is fed to the error detector. Error detector compares the reference voltage with the actual
output and fed to the PI controller (Kp=0.099 and Ki=0.0099). Output from the PI controller will determine the on
off time of the PWM signal. This is applied to the switch of the converter circuit without losing the Zero Voltage
Switching condition. The closed-loop performance is studied with a load of 500 ohms. The PI controller will keep
the output equal to the set value of 35 V for changes in the input supply voltage of 2 V (20%) and the input voltage
waveforms are shown in Fig.11. The dSpic controller is effective and makes the output voltage to theset value of 35
V with ZVS condition and the waveforms are shown in Fig. 12 and 13. This shows, dSpic control scheme for the
regulating the is effective in this converter. The efficiency of the ZVS Super Boost DC-DC Converter is calculated
by measuring the input and output power. The proposed ZVS Super Boost DC-DC Circuit has less switching losses,
increased voltage transfer gain, good reliability and low electromagnetic interference.

Figure 10 : Closed Loop Control of ZVS Super Boost DC – DC Converter

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Figure 11: Input Voltages - 8 V & 10 V (5V/division) Vs time (14μs/division).

Figure 12 : Resonating Capacitor Voltages for Two Different Input Voltages (5V/division) Vs time(14μs/division)

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Figure 13: Output Voltage (5V/division) Vs time (500ms/division) – 35 Volts

VII. CONCLUSION
This paper gives a detailed design of ZVS voltage boost circuit wit constant load and variable duty cycle. The
theoretical, simulated and practical output waveforms under open and closed loops are obtained for variable duty
cycle and input voltage. The method used reduces the effects of parasitic and greatly boost the output voltage and
efficiency (93%) is achieved. This circuit has the good power density and cost is comparatively less with easy
control.

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