UNISONIC TECHNOLOGIES CO.

, LTD
UC3842B/3843B LINEAR INTEGRATED CIRCUIT

HIGH PERFORMANCE
CURRENT MODE
CONTROLLERS

 DESCRIPTION DIP-8

The UTC UC3842B/3843B are specifically designed for

off-line and dc-to-dc converter applications offering the designer
a cost-effective solution with minimal external components.
The UC3842B has UVLO thresholds 16V (on) and 10V(off),
ideally suited for off-line converters. The UC3843B is tailored for
lower voltage applications having UVLO thresholds of 8.4V(on) SOP-8
and 7.6V(off).

 FEATURES
* Trimmed oscillator for precise frequency control
* Oscillator frequency guaranteed at 250kHz
* Current mode operation to 500kHz
* Automatic feed forward compensation
* Latching PWM for cycle-by-cycle current limiting
* Internally trimmed reference with undervoltage lockout
* High current totem pole output
* Undervoltage lockout with hysteresis
* Low startup and operating current

 ORDERING INFORMATION
Ordering Number
Package Packing
Lead Free Halogen Free
UC3842BL-D08-T UC3842BP-D08-T DIP-8 Tube
UC3842BL-S08-R UC3842BP-S08-R SOP-8 Tape Reel
UC3843BL-D08-T UC3843BP-D08-T DIP-8 Tube
UC3843BL-S08-R UC3843BP-S08-R SOP-8 Tape Reel

UC3842BP-D08-T
(1)Packing Type (1) T: Tube, R: Tape Reel

(2)Package Type (2) D08: DIP-8, S08: SOP-8

(3)Green Package (3) P: Halogen Free and Lead Free, L: Lead Free

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT

 MARKING
Package UC3842B UC3843B
8 7 6 5 8 7 6 5
Date Code Date Code
UTC UTC

□
□

□
□
UC3842B L: Lead Free UC3843B L: Lead Free
DIP-8
P: Halogen Free P: Halogen Free
Lot Code Lot Code
1 2 3 4 1 2 3 4

8 7 6 5 8 7 6 5
Date Code Date Code
UTC UTC
SOP-8 UC3842B L: Lead Free UC3843B L: Lead Free
P: Halogen Free P: Halogen Free
Lot Code Lot Code
1 2 3 4 1 2 3 4

 PIN CONFIGURATION

COMP 1 8 VREF

VFB 2 7 VCC

CS 3 6 OUTPUT

RTCT 4 5 GND

 PIN DESCRIPTIONS
PIN NO. PIN NAME I/O DESCRIPTION
1 COMP O Error amp output to provide loop compensation maintaing VFB at 2.5V
Error amp inverting input, The non-inverting input of error amp is 2.5V band
2 VFB I
gap reference
3 CS I Current sense input to PWM control gate drive of output
4 RTCT I To set oscillator frequency and maximum output duty cycle
5 GND Power ground
6 OUTPUT O To direct drive power MOSFET
7 VCC Power supply
8 VREF O 5V regulated output provides charging current for CT through RT

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT
 BLOCK DIAGRAM

VCC
7
VCC
VREF 8 5.0V
Undervoltage
Reference
R Lockout
VREF
R Undervoltage
Lockout

RTCT 4 Oscillator 6 Output

Latching
PWM
+
VFB 2 -
Error
Amplifier 3 CS
COMP 1
5
GND

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT

 ABSOLUTE MAXIMUM RATINGS (TA=25°C, unless otherwise specified)

PARAMETER SYMBOL RATINGS UNIT
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 2) IO 1.0 A
Output Energy (capacitive load per cycle) W 5.0 μJ
Current Sense and Voltage Feedback Inputs VIN -0.3 ~ +5.5 V
Error Amp. Output Sink Current IO(SINK) 10 mA
DIP-8 1250 mW
Power Dissipation PD
SOP-8 800 mW
Operating Junction Temperature TJ +150 °C
Operating Temperature TOPR -40 ~ +125 °C
Storage Temperature TSTG -65 ~ +150 °C
Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. Maximum Package power dissipation limits must be observed.
 THERMAL DATA
PARAMETER SYMBOL RATINGS UNIT
DIP-8 100 C/W
Junction to Ambient θJA
SOP-8 156 C/W

 ELECTRICAL CHARACTERISTICS
(0°C ≤TA≤70°C, VCC=15V (Note 1), RT=10k, CT=3.3nF, unless otherwise specified)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE SECTION
Output Voltage VREF IO=1.0mA, TJ =25°C 4.9 5.0 5.1 V
Line Regulation ΔVLINE VCC=12V ~ 25V 2.0 20 mV
Load Regulation ΔVLOAD IO=1.0mA ~ 20mA 15 35 mV
Temperature Stability TS 0.2 mV/°C
Total Output Variation VREF Line, Load, Temperature 4.82 5.18 V
Output Noise Voltage eN F=10kHz ~ 10Hz, TJ =25°C 50 μV
Long Term Stability S TA=125°C,1000Hrs 5 mV
Output Short Circuit Current ISC -100 -155 -245 mA
OSCILLATOR SECTION
TJ =25°C 49 52 55
Frequency F TA=0°C ~ 70°C 48 56 kHz
TJ =25°C (RT=6.2k, CT=1.0nF) 225 250 275
Frequency Change with Voltage fOSC/V 12 ≤ VCC ≤25V 0.2 1.0 %
Frequency Change with
fOSC/T 0°C ≤TA ≤70°C 0.5 %
Temperature
Oscillator Voltage Swing
VOSC 1.6 V
(Peak to Peak)
TJ =25°C 7.8 8.3 8.8
Discharge Current IDISCHG mA
0°C ≤TA ≤70°C 7.6 8.3 8.8

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT

 ELECTRICAL CHARACTERISTICS (Cont.)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
ERROR AMPLIFIER SECTION
Voltage Feedback Input VFB Vo=2.5V 2.42 2.50 2.58 V
Input Bias Current II(BIAS) VFB=5.0V -0.1 -2.0 μA
Open Loop Voltage Gain GVO 2 ≤VO≤4V 65 90 dB
Unity Gain Bandwidth GBW TJ =25°C 0.7 1.0 MHz
Power Supply Rejection Ratio PSRR I2V≤VCC≤25V 60 70 dB
Output Sink Current ISINK VO=1.6V,VFB =2.7V 2.0 12 mA
Output Source Current ISOURCE VO=5.0V,VFB=2.3V -0.5 -1.0 mA
Output Voltage Swing High State VOH VFB=2.3V, RL=15k to GND 5.0 6.2 V
Output Voltage Swing Low State VOL VFB=2.7V, RL=15k to VREF 0.8 1.1 V
CURRENT SENSE SECTION
Current Sense Input Voltage Gain GV (Note 2, 3) 2.85 3.0 3.15 V/V
Maximum Current Sense Input
VI(THR) (Note 2) 0.9 1.0 1.1 V
Threshold
Power Supply Rejection Ratio PSRR 12≤Vcc≤25V (Note 2) 70 dB
Input Bias Current II(BIAS) -2 -10 μA
Propagation Delay tD(IN/OUT) Current Sense Input to Output 150 300 ns
OUTPUT SECTION
ISINK=20mA 0.1 0.4 V
Output Low Voltage VOL
ISINK=200mA 1.6 2.2 V
ISOURCE=20mA 13 13.5 V
Output High Voltage VOH
ISOURCE=200mA 12 13.4 V
Output Voltage with UVLO
VOL (UVLO) VCC=6.0V,ISINK=1.0mA 0.1 1.1 V
Activated
Output Voltage Rise Time tR TJ =25°C, CL=1nF 50 150 ns
Output Voltage Fall Time tF TJ =25°C, CL=1nF 50 150 ns
UNDER-VOLTAGE LOCKOUT SECTION
UC3842B 14.5 16 17.5 V
Startup Threshold VTHR
UC3843B 7.8 8.4 9 V
Min. Operating Voltage After UC3842B 8.5 10 11.5 V
VCC(MIN)
Turn-on(VCC) UC3843B 7.0 7.6 8.2 V
PWM SECTION
MAX 94 96 %
Duty Cycle DC
MIN 0 %
Total DEVICE
Power Startup Supply Current ICC+IC VTHR -0.05V 0.25 0.5 mA
Power Operating Supply Current ICC+IC Note 1 12 17 mA
Power Supply Zener Voltage VZ ICC=25mA 30 36 V
Note: 1. Adject VCC above the Startup threshold before setting to 15V.
2. This parameter is measured at the latch trip point with VFB=0V.
V Output Compensation
3. Comparator gain is defined as : GV
V Current Sense Input

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT

 TYPICAL APPLICATION CIRCUIT

Open Loop Test Circuit
All of the parameters are not all tested in production, although been guaranteed. The timing and bypass capacitors
must be connected to Pin 5 in a single point ground very closely. To sample the oscillator waveform, the transistor
and 5kΩ potentiometer are used, and also can apply an adjustable ramp to ISENSE Pin.

VREF
2N UTC
2222 RT UC3842B/3843B

1 COMP VREF 8
100K

2 VFB VC 7 A V1
4.7K

3 ISENSE OUTPUT 6 OUTPUT

E/A 1K
0.1
ADJUST
ISENSE 5K 4 RT/CT GND 5
ADJUST
4.7K CT 0.1

1K/1W

Under Voltage Lockout

Under-Voltage Lock-Out: the output driver is biased to a high impedance state. To prevent activating the power
switch with output leakage current, Pin 6 should be shunted to ground with a bleeder resistor.

ON/OFF COMMAND ICC

7 TO REST OF IC

<15mA
VON VOFF
UC3842B 16V 10V
<1mA
UC3843B 8.4V 7.6V VCC
VOFF VON

Error Amp Configuration

0.5mA

2.5V

ZI VFB
2

COMP
1
ZF

Error amp can source sink up to 0.5mA

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT

 APPLICATION INFORMATION (Cont.)

Current Sense Circuit

ERROR
IS AMP
2R 1V
COMP
1
CURRENT
R SENSE
COMPARATOR
R
3
CURRENT
RS SENSE
C
GND
5

Peak current (IS) is equaled:

IS(MAX)=1.0V/RS
There should be a small RC filter to suppress switch transients.

Oscillator Waveforms and Maximum Duty Cycle

LARGE RT
SMALL CT V4
VREF 8

RT
RT/RC 4 INTERINAL CLOCK

CT SMALL CT
LARGE RT
V4
GND 5

INTERINAL CLOCK

CT (Oscillator timing capacitor) can be charged by VREF through RT and discharged by an internal current source. At
discharge time, the internal clock signal blanks the output to the low. Both oscillator frequency and maximum duty
cycle can be determined by Selection of RT and CT.

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT

 APPLICATION INFORMATION (Cont.)

Shutdown Techniques

1KΩ
8 VREF
1 COMP

3 ISENSE
SHUTDOWN
330Ω

TO CURRENT
SHUTDOWN
SENSE-RESISTOR
500Ω
(Deadtime vs CT RT > 5kΩ)

The UTC UC3842B’s shutdown can be accomplished by two ways: raise Pin 3 above 1V; or pull Pin 1 below a
voltage two diode drops above ground. Either method can cause the PWM comparator’s output to be high. Because
the PWM latch is reset dominant, the output will remain low until the next clock cycle after the shutdown condition at
Pins 1 and/or 3 is removed.

Slope Compensation

UC3842B/UC3843B

VREF 8
0.1µF
RT
RT/RC 4

CT
R1 ISENSE

R2
ISENSE 3
C RSENSE

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT

 TYPICAL CHARACTERISTICS

Fig. 1 Timing Resistor vs. Fig. 2 Output Deadtime vs.

Oscillator Frequency Oscillator Frequency
80
100
4

Percent Output Deadtime, %DT.

50 C
T=
50 1.CT=10nF
Timing Resistor, RT (KΩ)

0p 50
F 2.CT=5.0nF

CT
3

=2
3.CT=2.0nF

0
0p
2

F
4.CT=1.0nF
CT

20
=5
.

20 5.CT=500pF
0n

C
F

T=
2.0
nF 6.CT=200pF 1
7.CT=100pF
CT

8.0
=1

10
7
0n
F

CT

6
=1

5.0
.0n

5
F

5.0

2.0 Vcc=15V
TA=25˚C 2.0 VCC=15V
TA=25˚C
0.8 1.0
10k 20k 50k 100k 200k 500k 10M 10k 20k 50k 100k 200k 500k 1.0M
Oscillator Frequency, fosc (kHz) Oscillator Frequency, fosc (kHz)

Fig. 3 Oscillator Discharge Current Fig. 4 Maximum Output Duty Cycle

vs. Temperature vs. Timing Resistor
Maximum Output Duty Cycle, Dmax (%)

9.0 100
Discharge Current, Idischg (mA)

VCC=15V
VOSC=2.0V 90
8.5

80 IDISCHG=7.5mA

8.0 70

60 IDISCHG=8.8mA
7.5 VCC=15V
CT=3.3nF
50
TA=25˚C
7.0
40
-55 -25 0 25 50 75 100 125 0.8 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

Ambient Temperature, TA (˚C) Timing Resistor, RT (kΩ)

Fig. 5 Error Amp Small Signal Fig. 6 Error Amp Large Signal
Transient Response Transient Response
VCC=15V, AV=1.0, TA=25°C VCC=15V, AV=1.0, TA=25°C
2.55V
3.0V
20mV/DIV

2.50V
2.5V

2.45V
2.0V

0.5µs/DIV 1.0µs/DIV

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT

 TYPICAL CHARACTERISTICS (Cont.)

Fig. 7 Error Amp Open Loop Gain Fig. 8 Current Sense Input Threshold
Phase vs. Frequency vs. Error Amp Output Voltage

Current Sense Input Threshold, VTH (V)

100 0 1.2
Vcc=15V Vcc=15V
Openloop Voltage Gain, GVO (dB)

VOUT=2.0V to 4.0V
1.0

Φ Excess Pahse (Degrees)

80 30
Gain RL=100K
TA=25˚C
60 60 0.8 TA=25°C

40 90 0.6
Phase TA=125°C
20 120 0.4 TA=-55°C

15 0.2
0 0

-20 180 0
10 100 1.0k 10k 100k 1.0M 10M 0 2.0 4.0 6.0 8.0
Frequency, f (Hz) Error Amp Output Voltage, VO (V)

Fig. 9 Reference Voltage Change Fig. 10 Reference Short Circuit Current

vs. Source Current vs. Temperature
Reference Short Circuit Current, ISC (mA)
Reference Voltage Change, ∆VREF (mV)

0 110 VCC=15V
VCC=15V RL≤ 0.1Ω
-4.0

-8.0 90
TA=-55°C
-12
TA=125°
C
-16 70

-20 TA=25°
C
-24 50
0 20 40 60 80 100 120 -55 -25 0 25 50 75 100 125
Reference Source Current, IREF (mA) Ambient Temperature, TA (°C)

Fig. 11 Reference Load Regulation Fig. 12 Reference Line Regulation

Output Voltage Change, ∆VO (2.0mV/DIV)
Output Voltage Change, ∆VO (2.0mV/DIV)

VCC=15V VCC=12V to 25V

IOUT=1.0mA to 20mA TA=25°C
TA=25°C

2.0ms/DIV 2.0ms/DIV

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UC3842B/3843B LINEAR INTEGRATED CIRCUIT

 TYPICAL CHARACTERISTICS (Cont.)

Fig. 13 Output Saturation Voltage Versus Load Current Fig. 14 Output Waveform

0 Source Saturation
Output Saturation Voltage, VSAT (V)

VCC (Load to Ground) VCC=15V 90 VCC=15V

-10 TA=25°C 80µs Pulsed Load CL=1.0nF
120Hz Rate %
TA=25°C
-20
TA=-55°C

30
TA=-
20 55°C
TA=25°
C 10
10 %
Sink Saturation GND
(Load to VCC)
0
0 200 400 600 800 50ns/DIV
Output Load Current, IOUT (mA)

Fig. 15 Output Cross Conduction Fig. 16 Supply Current vs. Supply Voltage
Output Voltage, VO

25
VCC=30V
CL=15pF
TA=25°C 20
Supply Current, ICC (mA)
20V/DIV

15

10
Supply Current, ICC

RT=10k
UC3843B

UC3842B
100mA/DIV

CT=3.3nF
5 VFB=0V
ISENSE=0V
TA=25°C
0
0 10 20 30 40
Supply Voltage, VCC (V)

UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all UTC products described or contained herein .
UTC products are not designed for use in life support appliances, devices or systems where malfunction
of these products can be reasonably expected to result in personal injury. Reproduction in whole or in
part is prohibited without the prior written consent of the copyright owner. UTC reserves the right to
make changes to information published in this document, including without limitation specifications and
product descriptions, at any time and without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.

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