EEE1026 Electronics II: Experiment EB1

Experiment EB1: FET Amplifier Frequency Response

Learning Outcome

• LO4: Analyze the operation of JFET, MOSFET and BJT amplifiers and switching circuits

1.0 Apparatus
Equipment required Components required
Power Supply –1 N-channel JFET 2N5457 –1
Oscilloscope –1 Resistor 10kΩ (1/4W) –2
Digital Multimeter –1 Resistor 3.3kΩ (1/4W) –1
Breadboard –1 Resistor 3.9kΩ (1/4W) –1
Function Generator –1 Resistor 22kΩ (1/4W) –1
Mylar Capacitor 0.47µF –2
Mylar Capacitor 0.1µF –1
Mylar Capacitor 0.01µF –1
50 kΩ potentiometer -- 1

Objectives:

1. Construct and test a voltage amplifier using N-channel JFET device in a common source
configuration
2. Apply the voltage divider biasing method to set the DC operating point (VGSq ,IDSq) .
Verify the estimated DC operating point with the measured data.
3. Investigate the effect of frequency changes on the voltage gain of the amplifier, measure
its frequency response and obtain its operating bandwidth.
4. Investigate the capacitance effect on the frequency response of the common source JFET
amplifier

Important Notes

All related calculation questions that does not require experimental data must be
answered before coming to the lab. You are required to show all the calculation steps when
requested by the lab instructor. During the evaluation session, your lab instructor may request
you to demonstrate how the measurement data is obtained and explain your experimental
results.

Report Submission

Submit your report on the same day immediately after the experiment.
EEE1026 Electronics II: Experiment EB1

2.0 Background Theory

An amplifier is a circuit that increases/decrease the input signal value and in this experiment
the signal to be amplified is the voltage. In this experiment you are going to investigate
frequency response characteristic of a voltage amplifier circuit using the N-channel JFET
device

Most amplifiers have relatively constant gain over a certain range of frequencies. This range
of frequencies is called the bandwidth of the amplifier. The bandwidth for a given amplifier
depends on the circuit component values, the type of active components and the dc operating
point of the active component. When an amplifier is operated within its bandwidth, the
( )
current gain ( Ai ) , voltage gain ( Av ) , and power gain A p values are referred to as midband
gain values. A simplified frequency-response curve that represents the relationship between
amplifier gain and operating frequency is shown in Figure 1.

Apdrops at Apdrops at higher

Power Gain lowerfrequencies
Mid-band frequencies
Ap(mid)

0.5Ap(mid) Bandwidth

fc1 fc2
Frequency
Figure 1: A simplified frequency response curve
As the frequency-response curve shows, the power gain of an amplifier remains
relatively constant across a band of frequencies. When the operating frequency starts to go
outside this frequency range, the gain begins to drop. Two frequencies of interest, f c1 and f c 2
, are the frequencies at which power gain decreases to approximately 50% of A p (mid ) . The
frequencies labeled f c1 and f c 2 are called the lower and upper cutoff frequencies of an
amplifier, respectively. These frequencies are considered to be the bandwidth limits for the
amplifier and thus bandwidth BW is given by

BW = f c 2 − f c1 .
The geometric average of f c1 and f c 2 is called the geometric center frequency foof an
amplifier, given by
f0 = f c1 f c 2 .
When the operating frequency is equal to f 0 , the power gain of the amplifier is at its
maximum value.
Frequency response curves and specification sheets often list gain values that are
measured in decibels (dB). The dB power gain of an amplifier is given by
EEE1026 Electronics II: Experiment EB1

Pout .
A p ( dB ) = 10 log A p = 10 log
Pin
Positive and negative decibels of equal magnitude represent reciprocal gains and losses. A
+3dB gain caused power to double while a –3dB gain caused power to be cut in half.
v2 v2
Using the basic power relationships, Pout = out and Pin = in , the power gain may be
RL Rin
rewritten as
2
Pout v out RL v R
A p ( dB ) = 10 log = 10 log 2 = 20 log out + 10 log in
Pin v in Rin vin RL

The voltage component of the equation is referred to as dB voltage gain. When the amplifier
input and out resistances are equal
v
A p ( dB ) = 20 log out = Av ( dB ) . ( Rin = R L )
vin
Thus, when the voltage gain of an amplifier changes by –3dB, the power gain of the amplifier
also changes by –3dB.

Low Frequency Response of FET Amplifier

In the low frequency region of a single stage FET amplifier as shown in Figure 2(a), it is the
RC combinations formed by the network capacitors and the network resistive parameters that
determine the cutoff frequency. There are three capacitors – two coupling capacitor CG and
C D , and one bypass capacitor, C S . Let us assume that CG , C D and C S are arbitrarily large
and can be represented by short-circuit. The total resistance in series with CG is given by
RCG = RG + Rin
where Rin = R1 || R2 is the input impedance of the amplifier circuit. The power supplied by the
2
signal generator is Pin = Vgen /( RG + Rin ) . However, the reactance XCG of capacitance CG is not
negligible at very low frequencies. The frequency at which Pin is cut in half is when
X CG = RG + Rin . Thus the lower half-power point for gate circuit occurs at frequency
1 1
f LG = =
2πRCG C G 2π (RG + Rin )C G

+VDD

R2 RD CD
RG CG G D

S RL
Vgen
Vin R1 CS
RS

Figure 2(a): Schematic diagram of a JFET amplifier

EEE1026 Electronics II: Experiment EB1

CD

RG CG VG G D

S RD RL
Vgen Vin R1||R2 RS CS

Figure 2(b): JFET amplifier low-frequency ac equivalent circuit

D
VD
CD
gmVgs RD RL
S

Figure 2(c): Approximate drain circuit of JFET amplifier (assuming the resistance of
the JFET drain terminal, rd, is much larger than RD).

When CG and C S are arbitrarily large and can be represented by short-circuit, the drain
circuit of the JFET amplifier is as shown in Figure 2(c). At high frequency where CD can also
be represented by a short-circuit, the output power to load resistor RLis Pout = V D2 / R L . At low
frequencies where the reactance XCD of capacitance C D is not negligible, Pout is cut in half
when X CD = R L . Thus the lower half-power point for drain circuit occurs at frequency
1
f LD =
2πR L C D

At the half-power point, the output voltage reduces to 0.707 times its midband value. The
actual lower cutoff frequency is the higher value between fLG (determined by CG) and fLD
(determined by CD).

High Frequency Response of FET Amplifier

The high frequency response of the FET is limited by values of internal capacitance,
as shown in Figure 3(a). There is a measurable amount of capacitance between each terminal
pair of the FET. These capacitances each have a reactance that decreases as frequency
increases. As the reactance of a given terminal capacitance decreases, more and more of the
signal at the terminal is bypassed through the capacitance.
EEE1026 Electronics II: Experiment EB1

+VDD

R2 RD CD
Cgd
RG CG
Cds
RL CL
Cgs
Vgen
R1 RS CS

Figure 3(a): JFET amplifier with internal capacitors that affect the high frequency
response.

RG
Cout(M) Cds CL RL||RD

Vgen R1||R2 Cgs Cin(M)

Figure 3(b): FET amplifier high frequency ac equivalent circuit.

The high frequency equivalent circuit for the FET amplifier in Figure 3(a) is shown in Figure
3(b), including all the terminal capacitance values. C gd is replaced with the Miller equivalent
input and output capacitance values given as
Av + 1
Cin ( M ) = C gd ( Av + 1) and Cout ( M ) = C gd
Av
Cgd

G AV D

G AV D Cin(M) Cout(M)

Figure 4: Miller equivalent circuit for a feedback capacitor.

EEE1026 Electronics II: Experiment EB1

Note the absence of capacitors CG , C D and C S in Figure 3(b), which are all assumed to be
short circuit at high frequencies. From this figure, the gate and drain circuit capacitance are
given by
CG′ = C gs + Cin (M ) and C D′ = C out ( M ) + C ds + C L

where C L is the input capacitance of the following stage. In general the capacitance C gs is
the largest of the parasitic capacitances, with C ds the smallest. The high cutoff frequencies
for the gate and drain circuits are then given by
1 1
f HG = and f HD =
′ CG′
2πRin 2πR ' L C D′

where Rin′ = RG || Rin and R ' L = R D || RL . At very high frequencies, the effect of CG′ is to
reduce the total impedance of the parallel combination of R1 , R2 and CG′ in Figure 3(b). The
result is a reduced level of voltage across the gate-source terminals. Similarly, for the drain
circuit, the capacitive reactance of C D ′ will decrease with frequency and consequently
reduces the total impedance of the output parallel branches of Figure 3(b). It causes the
output voltage to decrease as the reactance becomes smaller.

3.0 Procedures

1. Before connecting the circuit of Figure 5, measure the actual resistance of R1, R2, RD, RS
and RL as accurate as possiblewith a digital multimeter (set it to the best resistance range)
and record the measured values.
2. Connect the common source JFET amplifier circuit as shown in Figure 5 using a
breadboard (refer to Appendix B). Do not connect the power supply and the function
generator to the circuit yet. Keep the connecting wires on the breadboard as short as
possible (< 3 cm) to reduce unwanted inductance and capacitance in your circuit.
3. Set the power supply output to +12V. Connect its output to the circuit and measure its
voltage VDD(meas) as accurate as possible with the multimeter. Calculate the gate DC
voltage VG(cal) using the voltage-divider rule.
4. Measure the DC voltages VG, VD and VS at G, D, and S pins of the transistor as accurate as
possible. Note that the measured VG should be closed to the calculated VG(cal), and VS
should be >VG since VGS must be < 0 V for N-channel JFET.
5. Before connecting the function generator to the circuit, use an oscilloscope to
measure the output voltage of the generator and set it to 200 kHz sine-wave with a
peak-to-peakvoltage of 0.1V. Press the attenuation button (ATT) of the generator for
easy adjustment of its output voltage.
6. Connect the generator output to the circuit. Using Channel 1 (CH1) of the oscilloscope
(set at AC input coupling), probe the input voltage vin. Using Channel 2 (CH2) of the
oscilloscope, probe the load resistor RL, as shown in Figure 5. Set the trigger source of the
oscilloscope to CH2. Adjust the trigger level on the oscilloscope to obtain stable
waveforms. Make sure the variable (VAR) knobs of the oscilloscope are set at the
calibrated (CAL’D) positions.
EEE1026 Electronics II: Experiment EB1

+VDD=12V

0.1µF
CH1 R1=22kΩ RD=3.3kΩ
(vin) CD=0.01µF
Function Generator D

50Ω G CH2
(vL)
CG=0.47µF S RL=10kΩ
Vgen R2 =10kΩ CS=0.47µF
RS=3.9kΩ

D
Figure 5: A Common source JFET amplifier S
G

7. Adjust the Volts/div and Time/div to display the waveforms on the oscilloscope
screen as big as possible with one to two cycles. Sketch the input AC voltage (vin) and
the load voltage (vL) waveforms on the graph. Record the Time/div and Volts/div used.
Note that the input and output waveforms should be approximately 180o out of
phase.
8. From your graph, determine VL(pp) and Vin(pp) which are the peak-to-peak voltages ofvL and
vin, respectively. Calculate the voltage gain (Av) of the JFET amplifier circuit at 200
kHz.Ask the instructor to check all of your results. You must show the oscilloscope
waveforms to the instructor.
9. Sweep the frequency of the function generator from 1 kHz to 550 kHz (use smaller
frequency steps near the half-power point while larger steps can be used at mid-band
frequencies). Record the peak-to-peak voltages of vin (CH1) and vL (CH2) and calculate
the dB magnitude of the voltage gain Av. Use both coarse and fine adjustment knobs of
the function generator for frequency adjustment.
10. Plot a curve of Av versus frequency.
11. Calculate the lower cutoff frequency fLD(cal) (use the measured RD and RL values). Set the
frequency to 20 kHz. To measure the lower cutoff frequency (fLD), decrease the generator
frequency until VL(pp) decreases to 0.707VL,mid-band(pp), where VL,mid-band(pp) is the VL(pp) value
in the mid-band.
12. Set the frequency to 300 kHz. To measure the upper cutoff frequency (fHD), increase the
generator frequency until VL(pp) decreases to 0.707VL,mid-band(pp).
13. Determine the bandwidth (BW) and the geometric center frequency (fo) of the amplifier
from the above measurements. Ask the instructor to check all of your results. You
must show the oscilloscope waveforms at 550 kHz to the instructor.
14. Design or modify the circuit in Figure 5 in order to measure the parameter of the device,
namely Gate-Source Cutoff Voltage (VGS(off) or Vp) and Zero-Gate Voltage Current (IDSS).
These two values can be used in the Shockley equation ID = IDSS(1 – VGS/Vp)2 . Hint: You
can use a potentiometer and/or negative power source in the circuit. By solving the
simultaneous equation of the Shockley equation and the load line equation, you can
obtain the calculated value for the Q point VGSQ, VDSQ, IDQ. . Compare this with the
measured value.
EEE1026 Electronics II: Experiment EB1

APPENDIX A

The Resistor color code chart Capacitance

ABC .abc

AB x 10C pF µF
0.abcµ

Potentiometer

A Var B

Log Scale
The distance in a decade of the log scale in the figure below is x mm. Since log101 = 0, it is
used as a refernce point (0 mm) in the linear scale. Then, the reading 10 is located at x mm
and the reading 0.1 is located at –x mm. For a reading F, it is located at [1og10(F)]*x mm.
E.g.:
Reading 0.25 is located at [1og10(0.25)]*x mm = -0.602x mm
Reading 2.5 is loacted at [1og10(2.5)]*x mm = 0.398x mm
Reading 25 is located at [1og10(25)]*x mm = 1.398x mm (not shown in the figure)
Reading 250 is located at [1og10(250)]*x mm = 2.398x mm (not shown)

Conversely, a point at z mm location is read as 10 z / x .

E.g.:
-0.3x mm is read as 10(-0.3x/x)= 0.501
0.6x mm is read as 10(0.6x/x)= 3.98
1.5x mm is read as 10(1.5x/x)= 31.6 (not shown)
2.7x mm is read as 10(2.7x/x)= 501 (not shown)

-0.3x 0.398x0.6x
-x -0.602x 0 x
Linear scale
(mm)

Log scale
0.1 0.2 0.3 0.5 1 2 3 4 5 6 7 8910
0.4 0.6 (unit)
0.25 0.7 0.9 2.5
0.501 0.8 3.98
EEE1026 Electronics II: Experiment EB1

Appendix B: Breadboard Internal Connections

Internal
Horizontally connected connections Horizontally connected

+VCC

0.1 µF

Vertically
connected 8 7 6 5

555

1 2 3 4
Vertically
connected

0V
GND

Internal
connections
General mistakes:
The legs of the resistors and the transistor are shorted
by the breadboard internal connections.
MultimediaUniversity FOE
EEE1026 Electronics II:
STUDENT'S NAME:
ID NO:
SUBJECT CODE AND TITLE: EEE1026 ELECTRONICS 2
EXPERIMENT TITLE: EB1 - FET Amplifier Frequency Response
EXPERIMENT DATE:
Criteria
1 Ability to construct the
amplifier circuit on the
breadboard
2 Ability to set-up the power
supply for the circuit, the
function generator to the
amplifier and to connect the
oscilloscope to display the
waveform
3 Ability to extract the mid-
band amplifier's
characteristics.
4 Ability to extract the
amplifier's complete
frequency response.
5 Ability to answer the
questions in by Oral
Assessment
Experiment EB1
TIME:
Rating Awarded
1 (Need Improvement) 2 (Satisfactory) 3 (Good) 4 (Excellent) by Assessor
Data Collection and Setting up the Experiment
Unable to construct the Able to construct the Able to construct the Able to construct the amplifier
amplifier circuit, and not amplifier circuit amplifier circuit. circuit correctly, with neat and
asking for help. partially. tidy placement of components
and jumper wires
Unable to setup the DC Able to setup the DC and DC and AC input to the DC and AC input to the
or AC input to the AC input to the amplifier amplifier is correctly amplifier is correctly setup and
amplifier, and not asking partially. setup. the waveforms are visible in the
for help. oscilloscope.
Analysis and Conclusions
No voltage gain is No voltage gain is Voltage gain is more than The voltage gain is fair, with
observed, and not asking observed, but the unity, with the input and the input and output at opposite
for help. waveforms are output at approximately phase.
approximately at opposite phase.
opposite phase.
There is no difference Minor differences Low-, mid- and high- Low-, mid- and high-frequency
between the low-, mid- between the low-, mid- frequency response of the response of the amplifier is
and high-frequency and high-frequency amplifier shows some clearly seen on a graph.
response of the response of the difference.
amplifier. amplifier.
Not able to answer the Able to answer questions Able to answer most part Answered all correctly with
question, no attempt was with some basics of the questions, with proper explanations and
made to answer answers and some explanations and elaborations, without a need to
demonstrate some elaborations and refer to any references.
attempts to refer to the demonstrate some
text books, notes, lab attempts to refer to text
sheet books, notes or lab sheet
 EEE1026 Electronics II
Experiment EB1: FET Amplifier Frequency Response
Lab Report
(Submit your report on the same day immediately after the experiment)

Name: ________________________Student I.D.: _______________Date: __________

Majoring: ____________________ Group: ____________ Table No.: ____________

1. Table E1: Measured resistance values

R1 R2 RD RS RL

[5 marks]
3. VDD(meas) = ________ V, VG(cal) = ________ V [2 marks]

4. Table E2: Measured DC voltages

VG VD VS

[3 marks]
7. Graph E1: vin and vL waveforms at 200 kHz

Time base : ______ s/div, CH1 (vin) : ______ V/div, CH2 (vL) : ______ V/div

CH1 & CH2

ground

[5 marks]

VL ( pp )
8. Av = = ________ at 200 kHz [1 mark]
Vin ( pp )
EEE1026 Electronics II Experiment EB1

9. Table E3: Measure VL(pp) and Vin(pp), and calculated AV

f /kHz 1 2 5 10 20 40 60 80 100 200 500 550

VL(pp) /V
Vin(pp) /V
Av(dB)
[6 marks]
10. Graph E2: Av versus frequency

[5 marks]
1
11. f LD ( cal ) = = _________ Hz
2π (RL + RD )C D
f LD ( meas ) = _________ Hz

12. f HD ( meas ) = _________ kHz

13. BW = fHD – fLD = _________ kHz

fo = f LD f HD = _________ kHz

[5 marks]

2
EEE1026 Electronics II Experiment EB1

Questions
1. Identify the sources of error in the calculated VG(cal).
________________________________________________________________________
________________________________________________________________________

2. Calculate the actual DC currents flowing through RD and RS, respectively, IRD and IRS
(calculation steps must be included). Explain why they are the same.
________________________________________________________________________
________________________________________________________________________

3. What is the measured Q-point value (VGSQ, VDSQ, IDQ) of the JFET amplifier circuit?
Analyze and compare this with the calculated one.
________________________________________________________________________
________________________________________________________________________

4. Estimate the lower cutoff frequency of the input circuit, fLG (show your calculation steps).

________________________________________________________________________

5. Estimate the total output capacitance which determines the upper cutoff frequency fHD
________________________________________________________________________

[15 marks]

Discussion

1. Identify how the vin and vL waveforms in Step 7 are related in terms of positive and
negative peak voltages, waveform shapes and phase shift.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

3
EEE1026 Electronics II Experiment EB1

2. Describe the Av versus frequency characteristic.

________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

3. Explain the difference between the calculated fLD(cal) and the measured fLD.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

4. Propose why fHDcannot be calculated and as to what factor determines this fHD.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
[16 marks]

Conclusion
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
__________________________________________________________________________.

[7 marks]