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A New Approach To Extracting The RF Parameters of Asymmetric DG MOSFETs With The NQS Effect
A New Approach To Extracting The RF Parameters of Asymmetric DG MOSFETs With The NQS Effect
Abstract: In analog circuit design an important parameter, from the perspective of superior device performance,
is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addi-
tion to that it provides, at the discretion of analog circuit designer, an additional degree of freedom, by providing
independent bias control for the front and the back gates. Here a non-quasi-static (NQS) small signal model for
DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD sim-
ulations. The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance, Cgd1
and Cgd2 , the intrinsic front and back distributed channel resistance, Rgd1 and Rgd2 respectively, the transport de-
lay, m , and the inductance, Lsd . The parameter extraction model for an asymmetric DG MOSFET is validated with
pre-established extracted parameter data, for symmetric DG MOSFET devices, from the available literature. The
device simulation is performed with respect to frequency up to 100 GHz.
Key words: asymmetric DGMOSFET; RF modeling; small signal analysis; parameter extraction
DOI: 10.1088/1674-4926/34/11/114002 EEACC: 2570
114002-1
J. Semicond. 2013, 34(11) Sudhansu Kumar Pati et al.
Fig. 1. The cross sectional view of double gate MOSFET. tsi , tox and
tov are the body, oxide and overlap of the gate thickness respectively. Fig. 3. Extrinsic parasitic source and drain resistances (Rs and Rd /
Lg is gate length. Ns , Nd and Nb are doping concentration of source, extracted using the channel resistance method.
drain and body respectively. In this work we consider Lg D 45 nm,
tox D 1.9 nm, tov D 3 nm, tg D 10 nm, xsd D 50 nm, tsi D 16 nm, Ns
D 1020 cm 3 D Nd and Nb D 1016 cm 3 .
Fig. 2. The equivalent circuit of the device shows that the extrinsic
components can be evaluated at off condition of the device. Cgdo and
Cgso are the gate to drain and the gate to source overlap capacitances
respectively. Cinnerfringe is the inner fringing capacitance of the de-
vice. Rs and Rd are the source and drain extrinsic parasitic resistance
respectively.
114002-2
J. Semicond. 2013, 34(11) Sudhansu Kumar Pati et al.
ˇ
int ˇ j!Cgdy
Y12 Gz D0
D ; (2)
1 C j!Rgdy Cgdy
ˇ
int ˇ gmy j!Cgdy
Y21 Gz D0
D ; (3)
1 C j!m 1 C j!Rgdy Cgdy
ˇ
int ˇ j!Cgdy j!Cgdz
Y22 Gz D0
D C
1 C j!Rgdy Cgdy 1 C j!Rgdz Cgdz
gds
C : (4)
1 C j!Lsd gds
Fig. 5. Small signal equivalent circuit of an asymmetric DGMOSFET The Y int -parameter expressions can be simplified by as-
for two port analysis. Asymmetric analysis contains two conditions 2 2
suming ! 2 Rgsy 2 2
Cgsy 1, ! 2 Rgdy Cgdy 1, ! 2 m2 1,
for evaluation of intrinsic components. Condition1: Gate 2 and source
grounded, i.e. GyD1 ¤ 0, D ¤ 0, GzD2 D 0 and S D 0. Condition 2: ! 2 Rgsz2 2
Cgsz 1, and ! 2 L2sd gds 2
1. This is because the small
Gate 1 and source grounded, i.e. GyD2 ¤ 0, D ¤ 0, GzD1 D 0 and signal parameters are extracted for low frequency. The simpli-
S D 0. fied expressions can be written as
ˇ
int ˇ 2 2 2
Y11 Gz D0
! Cgsy R gsy C C gdy R gdy C j! Cgsy C Cgdy ;
account the effect of the time constant m as a result of the non ˇ (5)
int ˇ 2 2
quasi static (NQS) effect. Here, the NQS effect is the delay in Y12 Gz D0
! Cgdy R gdy j!C gdy ; (6)
charging of the terminal capacitances because of the high fre- ˇ
int ˇ 2 2
Y21 Gz D0 gmy ! Cgdy Rgdy j! m gmy C Cgdy ; (7)
quency operationŒ15 . This delay is incorporated in the small
ˇ
signal model considering Lsd . In a DGMOSFET electrostatic int ˇ
Y22 g ds C ! 2
C 2
R gdz C C 2
R gdy
Gz D0 gdz gdy
control over the channel is better and drain-induced barrier
loweringŒ16 21 is highly subsidized and hence not considered 2
C j! Cgdz C Cgdy Lsd gds : (8)
here.
The small signal parameters such as Cgsy , Cgdy , Cgdz , Rgsy ,
The small signal equivalent circuit of the device here is
Rgdy , gmy , gds ; m and Lsd of the equivalent circuit are extracted
represented as a four terminal device, which is difficult to ana-
from real and imaginary parts of Y int -parameters and are given
lyze in mixed mode analysis. Thus, for the analysis of the four
by
terminal devices, the circuit is converted to two port networks
considering two separate bias conditions. Figure 5 represents int
Im Y12
the two port representation of the small signal equivalent cir- Cgdy D ; (9)
cuit of Fig. 4 considering the bias conditions where the suffixes !
y and z in Fig. 5 signify two conditions. The two conditions Im Y11 int
considered to convert the network in Fig. 4 into a two port net- Cgsy D Cgdy ; (10)
!
work are stated as follows:
int
First condition: Gate 2 and source grounded i.e. GyD1 ¤ Re Y12
Rgdy D 2
; (11)
0, D ¤ 0, GzD2 D 0 and S D 0. ! 2 Cgdy
Second condition: Gate 1 and source grounded i.e. GyD2 " #
int
¤ 0, D ¤ 0, GzD1 D 0 and S D 0. 1 Re Y11 2
Rgsy D 2 Cgdy Rgdy ; (12)
However, the analysis of the two cases is similar, since the Cgsy !2
structure of the device is symmetrical about the gates. ˇ
int ˇ
gmy D Re Y21 ! 2 D0
; (13)
ˇ
4. Extraction of intrinsic parameters int ˇ
gds D Re Y22 ; (14)
! 2 D0
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J. Semicond. 2013, 34(11) Sudhansu Kumar Pati et al.
Fig. 6. The equivalent capacitance Cgd and resistance Rgd are ex- Fig. 7. The intrinsic capacitance (Cgd / and intrinsic resistance (Rgd /
tracted from both symmetric and asymmetric analysis. By using the with frequency are found to be constant. The capacitance and resis-
superposition principle, the equivalent capacitance and resistance are tance are extracted at Vds D 0.5 V.
evaluated from the asymmetric analysis and compared to symmetric
analysis. These parameters are extracted are found to be constant with
frequency.
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J. Semicond. 2013, 34(11) Sudhansu Kumar Pati et al.
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