International Conference on

Information, Communications and Signal Processing 1D1.6

ICICS ‘97
Singapore, 9-12 September 1997

Frequency Hopping Spread Spectrum Communication System

over the Power Lines
Fernando A. Cardoso’, Jorge P. Ferreira2, Luis S . Silva’, JosC B. Gerald’*2

I.N.E.S.C.,Rua Alves Redo1 9, 1000 Lisboa, Portugal

Tel: 35 1-1-3 100368; E-mail: jabg@eniac.inesc.pt; Fax: 35 1-1-3 155843
2
I.S.T.,Dep. of Elect. and Computer Eng., AV. Rovisco Pais, 1000 Lisboa, Portugal

Abstract data transmission over noisy channels, as for instance, the

This paper describes the implementation of a
communication system that uses the power lines as the
channel. The system consists of an emitterheceiver
operating with Frequency Hopping Spread Spectrum
(FHSS), and allows data transmission at low rates. It were
built 2 prototypes to communicate between them. The
transmission rate was 200 Hz in a 76,2 kHz bandwidth
(18,9 kHz to 95,4 lcHz).
1. Introduction
The communication over the electric power lines has the
advantage of the transmission channel be already installed
in all buildings. However, we are limited to the available
bandwidth (from 9 lcHz to 95 kHz, in our case, according
to the European rule CENELEC [l]), as well as to all the
existing noise, resultant of all kind of equipment connected
to them.
The most important noises that were found on the power
lines were:
0 50 Hz (power signal frequency in Europe) noise,
produced by the power sources of the electric devices,
with the respective harmonic components in multiple
frequencies of this value.
0 Smooth noise, which has a continuous spectral
distribution, and it is produced, for instance, by electric
motors.
0 Pulse noise, generated by the switch devices and
capacitor banks. This noise, by its amplitude and
duration (it can achieve 40 dB over the background
noise) was the most relevant noise.
0 Harmonic noise, usually gaussian, which decreases
-
about 25 dB/dec in the 10 kHz 100 MHz bandwidth.
electric power lines.
There are several kinds of SS techniques, differing from
each other on the type of modulation used: Direct
Sequence @S), Frequency Hopping (FH),Time Hopping
(TH), Chirp, and hybrids methods [2]-[4]. From these
techniques, it was chosen FH because it is the simplest
technique that can achieve a great amount of spreading
even when a pseudo-noise (PN) sequence with small period
is used, and so, it allows a fast acquisition time in the
receiver. FH systems can also be designed to avoid part of
the reserved bandwidth and they are not very sensitive to
the “near-far” problcm 151. The major problem when using
FH is tlic frequcncy synthcsiser, which must be very
accurate and to pcrform a fast switch from frequency to
frequency.
2. System Description
2.1 Emitter
In the FH emitter (Fig. l), the emitted signal results from
the frequency modulation (FSK) of the binary data signal
m(t) with a discrctcly varying frequency carrier. The
carrier frequency is determined, at each instant. according
to the value of a PN sequence, periodic in time and known
to the receiver.
Digital Frequency
m(t) multiplier
synthesizer
m-1 bits

The Spread Spectrum (SS) modulation techniques, initially Fig. 1 - Frequency Hopping emitter block diagram.
developed for military communications, only recently
started to be applied on non-military applications. Those
techniques allow multiple access (CDMA), which allied to
high rejection to interference, makes the SS suitable for

0-7803-3676-3/97/$10.000 1997 IEEE

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PN Generator: The PN generator originates an apparently
non-predictable bit sequence b(t), however, accordingly to
well defined criteria. This sequence gives the SS system its
security and spreading criterion, which are its major
characteristics.
The simplest way of generating this sequence is using a
shift register, with some of its outputs module 2 added to
the first register entry, as shown in Fig. 2. In this way, the
sequence period can easily be doubled, simply by adding a
register to the series. So, with few hardware components, it
is possible to built extremely long sequences.
-
Fig. 2 PN sequence generator with length N=2L-I.
For a shift register with lengtli L, the resulting sequence
has length N=2L-1. All tlie groups of L bits make part of
the sequence, except the one consisting just of zeros [GI.
The groups sequence depends on tlie outputs chosen for
feedback.
Tlie implemented PN generator is based on a sliift register
with length L=8, and so, originating a sequence with
length N=2*-1=255. Tliis number corresponds to tlie
number of different frequencies used. The registers are
implemented by D type flip-flops, and tlie module 2 adder
is implemented by an XOR (exclusive OR). Eacli eiiiittcr
generates a different PN sequence, niaking possible the
existence of 2 siinultaneous coni~nirnicationsin the sanic
cliannel (CDMA).
Freauencv svnthesiser: A major problem in FH is tlie
frequency synthesis, which, as we will see, is a
fundamental point in this system. In order to built the
frequency synthesiser, one must t'ake a look into some
aspects, such as the transmitting bandwidth and tlie
number of synthesised frequencies. Regarding that 255
different frequencies have to be syntliesised in an 80 kHz
bandwidth, tlie ' synthesis precision must be very high.
Also, tlie transition time between frequencies is dcsired to
be as short as possible. The best way to achieve these goals
is using digital frequency syntliesis [ 31. Basically, tlie
sinusoid is generated by tlie cyclic reading of a table
recorded in memory. It is only necessary to store the
samples corresponding to half period of tlie wave, once in
tlie other half period tlie samples are tlie same plus a minus
signal. In Fig. 3 is represented tlie block diagram of tlie
synthesiser.
95
FL$,$,Ezb,
Accumulator PN generator
-
Fig. 3 Digital synthesiser block diagram.
Tlie biliary code supplied by the PN generator is, at each
clock period, added to the accuinulator content. Tlie result
is used to address a ineinory table with tlie values of the
sinusoid. Tlie digital values in the memory are then
converted to analogue using a digitallanalogue converter
(DAC).
The generated frequency is directly related to the clock
used to drive tlie PN generator. Tliis is the unique external
factor influencing the frequency synthesis precision. Using
a crystal generator to generate tlie clock, we achieved the
desired precision.
Tlie generated frequency depends on the number of
samples of tlie sinusoid addressed in the memory. In turn,
this number depends on the binary code driving the
accuinulator, which is constant during each code word.
Different code words result in different distances among
acceded samples, and, consequently, in a different
frequency. Thus, we have fsynthasized=f~~*Cm\I/Naamples,where:
CpNis tlie PN code value, varying from 1 to 255.
Nsanl,,les
is tlie niaximum number of samples in 1 period
of tlie sinusoid, in our case 4096 (the double of the
number of samples in memory, which is 2048).
fGkis tlie clock frequency, which is 1.2288 MHz (a sub-
niultiple of a crystal value).
In ordcr to satisfy tlic sampling tlieorern conditions, it must
be 2*CPN$Nsrunples. Tlie quotient N,,,I,$C~~ is the number
of samples uscd to synthesise 1 period of each frequency.
The greater this value is, the smaller is tlie harmonic
distortion of the synthesised wave. The synthesised
frequency varies froin a minimum of 300 Hz
(1.2288e6*1/4096) to a maximum of 76.5 kHz
(1.2288e6*255/4096). Tlie average number of samples per
period goes froin 16.0627 (upper frequency) to 4096 (lower
frequency). Tlie used bandwidth is 76.2 kHz, and it can be
shifted to the most convenient place in the available band.
Tlie accumulator lias 12 bits, those necessary to address
4096 ineniory positions (although the memory lias only
2048 samples, corresponding to 11 address bits, the 1 2 ~bit '
will decide tlie sign of tlie sinusoid arcade). The
accumulator consists of an adder with one of the entries
coining froin tlie PN generator and tlie other coming from
the output of the accumulator itself.
To produce the band shift, we add a constant value (offset),
63 in tlie emitter and 55 in the receiver, to the
accumulator. In this way, the synthesised frequencies band
goes from 18.9 kHz to 95.4 kHz in the emitter and from
16.5 kHz to 93 kHz in the receiver. This results in a
reduction on the number of samples per period, which, in
the worst case, becomes 13.2129, in average. The 2.4 kHz
difference between the emitter and the receiver
synthesisers is essential to the synchronisation of the
system, as it will be seen later.
The PN generator and the accumulator were entirely built
on a Field Programmable Gate Array (FPGA), that allows
the programming of digital logic circuits and state
machines. The configuration program can be loaded from
an external memory, or from an output port of a computer.
This technique is very versatile once it allows tlie P G A
program to enter either in a serial or a parallel way, and
also because the F'PGA itself can be the master or tlie slave
in this process.
This way, it is achieved a high level of integration, saving
space and hardware. Using a FPGA, an EPROM and a
DAC we implemented 2 frequency synthesisers, one for the
emitter and the other for the receiver. The EPROM and
DAC accesses are digitally multiplexed, using multiplexers
implemented in the F'PGA. The de-multiplexing of the 2
signals is performed in an analogue way, after tlie DAC.
The multiplexing uses the accumulator clock, putting on
the multiplexer output the emitter data (when the clock is
high) or the receiver data (when tlie clock is low), in each
period. The de-multiplexing procedure is driven by the
same clock.
The electric power lines (which have a very low
impedance, 4n)interface circuit, which is based on a 4:2
wires hybrid circuit, consists of a gain circuit for the
emission, a transformer with 2 secondary bobbins, one for
the emission and another for the reception. Filters and
protection circuits were also added to make it sure tliat the
power signal, which has 220 Vrms and a frequency of 50
Hz, does not interfer with the data processing.
2.2 Receiver
The receiver is represented in Fig. 4. It is composed by a
frequency synthesiser, a PN generator equal to tlie emitter
one, and a frequency multiplier.
Fig. 4 -Frequency Hopping receiver block diagram.
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The received signal is multiplied by the local generated
one, and, if there is synchronism between the emitter and
the receiver, the resulting signal can be de-modulated in
order to obtain tlie original information. On tlie other
hand, the multiplier output helps to perform tlie PN
generator rate adjustment.
The receiver operation is based on a PLL (Phase Locked
Loop). The received and locally generated signals are first
multiplied. In synchronism, tlie resultant signal has a
spectral component with one of the three possible values:
1.2 kHz, 2.4 kHz or 3.6 kHz, as it will be explained later.
The sy~iclironisationfilter let this frequency pass, and, at
tlie enveloping detector output, we have a synchronism
indicator signal. This signal allows the local PN generator
to run, driven by the VCO, only in case of synchronism. If
there is no synchronism, tlie receiver stands still in the
saltie frequency, in order to make it easy for the
synclironism acquisition.
The synclironism indicator signal multiplied with the VCO
output allows its own frequency (centred in 200 Hz) to be
adjusted, by compensating the phase differences between
the emitter and the receiver.
2.3 Data Signal Processing
The data signal is transniittcd by replacing one of tlie
eniittcr PN gcncralor bits, for the data bit. It is sent one bit
for each syntlicsiscd frcqucncy. Thus, the transmission rate
is 200 bps, once the frequency used to drive the PN
generator is 200 Hz. This replacing causes tlie synthesised
frequency to change. As we replaced tlie 3rdLSB of the PN
generator, two diffcrent situations may occur:
0 The information bit equals the PN generator original
bit, making tlie diffcrcnce between tlie emitter and the
receiver synthesised frequencies to be 2.4 kHz;
0 The data bit differs from tlie PN generator original one,
resulting on a k1.2 kHz additional difference between
tlie synthesised frequcncies, which are now 1.2 kHz or
3.6 kHz.
The bandpass filter centred at 2.4 kHz (synchronisation
filter) must have a bandwidth large enough to
accommodate all the possible frequencies once in
synclironism (1.2 kHz, 2.4 kHz and 3.6 kHz), and ignore
all the rest, to make the synchronism acquisition easier. If
this filter output drives another bandpass filter, equally
centred in 2.4 kHz,but now rejecting the 1.2 kHz and 3.6
kHz frequencics (detection filter), followed by an
envcloping dctcctor, tlic resultant signal is a signal
identifier of tlic cquality bctween the data bit and tlie 3rd
PN generator original bit. To better understand this
method see Table 1, where the synthesised frequencies (in
the emitter and in tlie receiver) for each data bit are
represented.
 The system worked well for halfduplex transmission.
However, it resulted to be necessary to insert an auxiliary
cancelling system in the line interface block, which is still
not implemented, in order it may work in fullduplex
operation.
0 0 f+Eo f f0 The system is fast in acquiring the synchronism, about 5 s,
0 1 f+fo+fi f fo+f; and after synchronised it showed a robust behaviour, once
1 0 f+fo-fi f fo-f; it can keep the synchronism in hostile conditions
1 1 f+fo f 4 (signaVnoise ratio <O).
Observing the incoming signal to the receiver, we noted it
-
Table 1 Synthesised frequencies for each data bit. f0=2.4 is deformed in magnitude and wave shape. Those
deformations result from the electric power line noise, as
kHz, fi=1.2 kHz.
shown in Fig. 5, where it can be seen a sequence of
different frequency signals, as it was emitted and as it has
The synchronisation filter is composed by a cascade of two arrived to the receiver.
second order filters, and the consequent bandpass detection
filter is composed by a cascade of six second order sections
emitted signal
(this filter must be very selective, once it must let pass the
2.4 kHz signal and reject either the 1.2 kHz or the 3.6 kHz -received signal
signals).
The decoding of the data bit is simply achieved by an XOR
of the 3d PN generator bit and the equality identifier
signal, as shown in Table 2.

SeC

-
Fig. 5 Emitted and received signals, showing some
different frequencies.
2.4 kHz I 1 0 0
2.4kHz I 1 1 1
In Fig. 6 is represented the synchronisation filter output for
3.6 kHz and 2.4 kHz signals. It can be seen the short time
Table 2 - Data bit decoding. interval without synchronism, because of the switching
among frequencies.
The choice of the 3"1 bit to transmit the information makes
it possible to have the same frequency with different PN
10
codes. This can make the synchronism acquisition harder
by fooling the reception system. But once we have
synchronism, there's no place for ambiguities. The data bit
-B 5

decoder output is valid only in case of synchronism.
We used the 3"1 LSB bit of the PN generator in order to
achieve a greater additional difference (1.2 kHz) between
the frequencies synthesised in the emitter and in the
receiver. If we had used the 1"' or the 2* LSB bits, that
difference would be smaller and it would be more difficult
to built the referred 2.4 kHz centred bandpass filter, which
does not sense the 1.2 kHz and 3.6 kHz frequencies.
3. Experimental Results
Next, we present some experimental results obtained with
the implemented prototypes in a noisy environment.
o
5
-10 ~YYUI'uuuuuuuuuu I uuuu vu uuuuu uuuuuu uu
-15 1 s&
Fig. 6 - Synchronisation filter output.
It was achieved a transmission almost free of errors, as
shown in Fig. 7, bctween 2 points 30 m apart, connected
to the same electric phase. The amplitude of the emitted
signal was slightly bigger than GOO mV. To note that the
power line used in these tests belongs to an Institute
building containing many scientific. computer, office, and
even factory equipment.

97
 -
--...
emitted data bit stream
received data bit stream
5. References
%
.
CEMLEC, European Standard EN50065-1.
5
G. R Cooper &, C. D. McGillem, Modem
4
Communications and Spread Spectrum. McGraw-
Hill, 1996, Chap. 8.
r 3
g 2
R C. Dixon, Spread Spectrum Systems with
1
Commercial Applications. John Wiley & Sons, 1994,
0
Chap. 4.
-1 b 0.02 0.04 0.06 0.08 0.1 0.12 B. SMar, Digital Communications. Prentice-Hall,
1988, Chap 10.
sec M. K. Simon, J. K. Omura, R. A. Scholtz, B. K.
Levitt, Spread Spectrum Communications Handbook.
-
Fig. 7 Emitted and received data bits (about 200 bits on McGraw-Hill, 1994, Part 5, Chap. 5.
each period of the transmitted stream). J. K Holmes, Coherent Spread Spectrum Systems
John Wiley & Sons, 1982, Chap 7.
Z. Kostic, E. L. Titlebaum, “The Design and
When the 2 connected points belong to different electric Performance Analysis for Several New Classes of
phases, the system has some difficulties on decoding the Code for Optical Synchronous CDMA and for
data bit, as shown in Fig. 8. To solve this problem we must Arbitrary-Medium Time-Hopping Synchronous
make a bypass network on the power distribution CDMA Communication Systems,” IEEE Trans. On
transformer. Communication. Vol. 42, pp. 2608-26 17, August
1994.
-
---- emitted data bit stream
received data bit stream

1 1.5 2 25 3
Sec

-
Fig. 8 Emitted and received data bits with connection
between different electric phases (about 200 bits on each
period of the transmitted stream).

4. Conclusions
It was implemented a prototype system for data
transmission over the electric power lines, using the
Frequency Hopping Spread Spectrum (FHSS) technique.
The system is very simple, with a big part of the processing
performed by a FPGA and an EPROM. The system worked
well up to 30 m distances in the same electric phasc in a
very noisy environment.
We are complementing the prototype with an auxiliary
cancelling system, an automatic gain control and an crror
correction code [7l, in order to improve its performance in
fullduplex transmission and also to achieve longer
distances.

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