CHAPTER 34

Fabrication of Microelectronic Devices*

*By Kent M. Kalpakjian

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 Printed Circuit Boards

Figure 34.1 A collection of

printed circuit boards. Source:
Phoenix Technologies, Inc.

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 Fabrication
Sequence of
and Integrated
Circuit

Figure 34.2
General fabrication
sequence for
integrated circuits.
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 MOS Transistor Cross-Sections
Figure 34.3 Cross-
sectional views of the
fabrication of a MOS
transistor. Source: R. C.
Jaeger.

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 Chemical Vapor Deposition

Figure 34.4 Schematic diagrams of (a) continuous, atmospheric-pressure CVD reactor and (b) low-pressure
CVD. Source: S. M. Sze.

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 Silicon Dioxide Growth

Figure 34.5 Growth of

silicon dioxide, showing
consumption of silicon.
Source: S. M. Sze.

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 Pattern Transfer by Lithography

Figure 34.6 Pattern transfer by lithography. Note that the mask in step three can be a positive or negative image
of the pattern. Source: After W. C. Till and J. T. Luxon.

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 Etching and Ion Implantation
Figure 34.7 Etching profiles resulting from (a) isotropic wet etching and (b) anisotropic dry
etching. Source: R. C. Jaeger.

Figure 34.8 Apparatus for ion

implantation

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 pn Junction Diode

Figure 34.9 (continued)

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 pn Junction Diode (cont.)

Figure 34.9

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 Two-Level Metal Interconnect

(a) (b)

Figure 34.10 (a) Scanning electron microscope

photograph of a two-level metal interconnect. Note
the varying surface topography. Source: National
Semiconductor Corporation. (b) Schematic drawing
of a two-level metal interconnect structure. Source: R.
C. Jaeger.

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 Bonding and Packaging

(a) (b) (c)

Figure 34.11 (a) SEM photograph of wire bonds connecting package leads (left-hand side) to die bonding
pads. (b) and (c) Detailed views of (a). Source: Courtesy of Micron Technology, Inc.

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 Integrated Circuit Packages

Figure 34.12 Schematic illustrations of different IC packages: (a) dual-in-line (DIP), and (b) ceramic flat pack,
and (c) common surface mount configuration. Sources: R. C. Jaeger and A. B. Glaser; G. E. Subak-Sharpe.

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