Addressing modes of 8051:

Addressing mode is a way to address an operand. Â Operand means the data we are operating
upon (in most cases source data). It can be a direct address of memory, it can be register names,
it can be any numerical data etc.

MOV A,#6AH

Here the data 6A is the operand, often known as source data. When this instruction is executed,
the data 6AH is moved to accumulator A. There are 5 different ways to execute this instruction
and hence we say, we have got 5 addressing modes for 8051. They are 
1) Immediate addressing mode 
2) Direct addressing mode 
3) Register direct addressing mode 
4) Register indirect addressing mode 
5) Indexed addressing mode.

1. Immediate Addressing Mode:  In this type, the operand is specified in the instruction along
with the opcode. In simple way, it means data is provided in instruction itself.

Ex: MOV A,#05H -> Where MOV stands for move, # represents immediate data. 05h is the data.
It means the immediate date 05h provided in instruction is moved into A register.

2. Register addressing mode: Here the operand in contained in the specific register of
microcontroller. The user must provide the name of register from where the operand/data need to
be fetched. The permitted registers are A, R7-R0 of each register bank. 

Ex: MOV A,R0-> content of R0 register is copied into Accumulator.

3. Direct addressing mode:

In this mode the direct address of memory location is provided in instruction to fetch the
operand. Only internal RAM and SFR's address can be used in this type of instruction.

Ex: MOV A, 30H => Content of RAM address 30H is copied into Accumulator.

4. Register Indirect addressing mode:

Here the address of memory location is indirectly provided by a register. The '@' sign indicates
that the register holds the address of memory location i.e. fetch the content of memory location
whose address is provided in register.

Ex: MOV A,@R0 => Copy the content of memory location whose address is given in R0
register.

5. Indexed Addressing mode:

This addressing mode is basically used for accessing data from look up table. Here the address of
memory is indexed i.e. added to form the actual address of memory.
Ex: MOVC A,@A+DPTR => here 'C' means Code. Here the content of A register is added with
content of DPTR and the resultant is the address of memory location from where the data is
copied to A register.
Instruction set
Writing a Program for any Microcontroller consists of giving commands to the Microcontroller
in a particular order in which they must be executed in order to perform a specific task. The
commands to the Microcontroller are known as a Microcontroller’s Instruction Set.
Just as our sentences are made of words, a Microcontroller’s (for that matter, any computer)
program is made of Instructions. Instructions written in a program tell the Microcontroller which
operation to carry out.
An Instruction Set is unique to a family of computers. As the 8051 family of Microcontrollers
are 8-bit processors, the 8051 Microcontroller Instruction Set is optimized for 8-bit control
applications. As a typical 8-bit processor, the 8051 Microcontroller instructions have 8-bit
Opcodes. As a result, the 8051 Microcontroller instruction set can have up to 2 8 = 256
Instructions.
An 8051 Instruction consists of an Opcode (short of Operation – Code) followed by Operand(s)
of size Zero Byte, One Byte or Two Bytes.The Op-Code part of the instruction contains the
Mnemonic, which specifies the type of operation to be performed. All Mnemonics or the Opcode
part of the instruction are of One Byte size.
Coming to the Operand part of the instruction, it defines the data being processed by the
instructions. The operand can be any of the following:
 No Operand
 Data value
 I/O Port
 Memory Location
 CPU register
There can multiple operands and the format of instruction is as follows:
 MNEMONIC DESTINATION OPERAND, SOURCE OPERAND 

DATA ARITHMETI LOGICA BOOLEA PROGRAM

TRANSFER C L N BRANCHING
MOV ADD ANL CLR LJMP
MOVC ADDC ORL SETB AJMP
MOVX SUBB XRL MOV SJMP
PUSH INC CLR JC JZ
POP DEC CPL JNC JNZ
XCH MUL RL JB CJNE
XCHD DIV RLC JNB DJNZ
  DA A RR JBC NOP
    RRC ANL LCALL
    SWAP ORL ACALL
      CPL RET
        RETI
         JMP
A simple instruction consists of just the opcode. Other instructions may include one or more
operands. Instruction can be one-byte instruction, which contains only opcode, or two-byte
instructions, where the second byte is the operand or three-byte instructions, where the operand
makes up the second and third byte.
Based on the operation they perform, all the instructions in the 8051 Microcontroller Instruction
Set are divided into five groups. They are:
 Data Transfer Instructions
 Arithmetic Instructions
 Logical Instructions
 Boolean or Bit Manipulation Instructions
 Program Branching Instructions
We will now see about these instructions briefly.
Data Transfer Instructions
The Data Transfer Instructions are associated with transfer with data between registers or
external program memory or external data memory. The Mnemonics associated with Data
Transfer are given below.
MOV - The MOV instruction moves data bytes between the two specified operands. The byte
specified by the second operand is copied to the location specified by the first operand. The
source data byte is not affected.
Example MOV A, R6
MOVC - The MOVC instruction moves a byte from the code or program memory to the
accumulator
Example         MOVC A, @A+DPTR MOVC A, @A+PC
MOVX - The MOVX instruction transfers data between the accumulator and external data
memory. External memory may be addressed via 16-bits in the DPTR register or via 8-bits in the
R0 or R1 registers. When using 8-bit addressing, Port 2 must contain the high-order byte of the
address.
Example         MOVX A, @DPTR
PUSH - The PUSH instruction increments the stack pointer and stores the value of the specified
byte operand at the internal RAM address indirectly referenced by the stack pointer. No flags are
affected by this instruction.
Example         PUSH A
POP - The POP instruction reads a byte from the address indirectly referenced by the SP
register. The value read is stored at the specified address and the stack pointer is decremented.
No flags are affected by this instruction.
Example         POP 34h
XCH - The XCH instruction loads the accumulator with the byte value of the specified operand
while simultaneously storing the previous contents of the accumulator in the specified operand.
Example         XCH A, 45h
XCHD - The XCHD instruction exchanges the low-order nibble of the accumulator with the
low-order nibble of the specified internal RAM location. The internal RAM is accessed
indirectly through R0 or R1. The high-order nibbles of each operand are not affected.
Example         XCHD A, @R1
Arithmetic Instructions
Using Arithmetic Instructions, you can perform addition, subtraction, multiplication and
division. The arithmetic instructions also include increment by one, decrement by one and a
special instruction called Decimal Adjust Accumulator.
The Mnemonics associated with the Arithmetic Instructions of the 8051 Microcontroller
Instruction Set are:
ADD-The ADD instruction adds a byte value to the accumulator and stores the results back in
the accumulator. Several of the flag registers are affected.
Example         ADD A, #03h
ADDC - The ADDC instruction adds a byte value and the value of the carry flag to the
accumulator. The results of the addition are stored back in the accumulator. Several of the flag
registers are affected.
Example         ADDC A, #23h (A = A + C + immediate value 23h)
SUBB - The SUBB instruction subtracts the specified byte variable and the carry flag from the
accumulator. The result is stored in the accumulator. This instruction sets the carry flag if a
borrow is required for bit 7 of the result. If no borrow is required, the carry flag is cleared.
Example         SUBB A, #01h (A = A - C – immediate value 01h)
INC - The INC instruction increments the specified operand by 1. An original value of 0FFh or
0FFFFh overflows to 00h or 0000h. No flags are affected by this instruction.
 Note - When this instruction is used to modify an output port, the value used as the port data is
read from the output data latch, not the input pins of the port.
Example         INC DPTR
DEC - The DEC instruction decrements the specified operand by 1. An original value of 00h
underflows to 0FFh. No flags are affected by this instruction.
 Note - When this instruction is used to modify an output port, the value used as the port data is
read from the output data latch, not the pins of the port.
Example         DEC A
MUL - The MUL instruction multiplies the unsigned 8-bit integer in the accumulator and the
unsigned 8-bit integer in the B register producing a 16-bit product. The low-order byte of the
product is returned in the accumulator. The high-order byte of the product is returned in the B
register. The OV flag is set if the product is greater than 255 (0FFh), otherwise it is cleared. The
carry flag is always cleared.
Example MUL AB
DIV - The DIV instuction divides the unsigned 8-bit integer in the accumulator by the unsigned
8-bit integer in register B. After the division, the quotient is stored in the accumulator and the
remainder is stored in the B register. The carry and OV flags are cleared.
If the B register begins with a value of 00h the division operation is undefined, the values of the
accumulator and B register are undefined after the division, and the OV flag will be set
indicating a division-by-zero error.
Example DIV AB
DA - The DA instruction adjusts the eight-bit value in the Accumulator resulting from the earlier
addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD
or ADDC instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxx1010-xxx1111), or if the AC flag is one, six is
added to the Accumulator, producing the proper BCD digit in the low-order nibble. This internal
addition would set the carry flag if a carry-out of the low-order four-bit field propagated through
all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxx-111xxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order
nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but
would not clear the carry. The carry flag thus indicates if the sum of the original two BCD
variables is greater than 100, allowing multiple precision decimal addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentially, this instruction performs the
decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial
Accumulator and PSW conditions.
 Note
 DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation,
nor does it apply to decimal subtraction.
Example DA A

DA
IF (A3-0 > 9) OR (AC = 1)
  A = A + 6
IF (A7-4 > 9) OR (C = 1)
  A = A + 60h

The arithmetic instructions has no knowledge about the data format i.e. signed, unsigned, ASCII,
BCD, etc. Also, the operations performed by the arithmetic instructions affect flags like carry,
overflow, zero, etc. in the PSW Register.
Logical Instructions
ANL  - The ANL instruction performs a bitwise and byte wise logical AND operation between
the specified byte or bit operands and stores the result in the destination operand.
Example ANL A, #3Fh (byte level)
ANL C, 1 (bit level)
ORL  - The ORL instruction performs a bitwise and byte wise logical OR operation on the
specified operands, the result of which is stored in the destination operand.
Example ORL A, #01h (byte level)
 ORL C, 0 (bit level)
XRL  - The XRL instruction performs a logical exclusive OR operation between the specified
operands. The result is stored in the destination operand.
Example XRL A, #0FFh
CLR  - The CLR instruction sets the specified destination operand or bit to a value of 0.
Example CLR A (byte wise)
` CLR C (bit wise)
CPL  - The CPL instruction logically complements the value of the specified destination
operand and stores the result back in the destination operand. Bits that previously contained a 1
will be changed to a 0 and bits that previously contained a 0 will be changed to a 1.
Example CPL 55h (byte wise)
CPL C (bit wise)
RL  - The RL instruction rotates the eight bits in the accumulator left one bit position. Bit 7 of
the accumulator is rotated into bit 0, bit 0 into bit 1, bit 1 into bit 2, and so on. No flags are
affected by this instruction.
Example RL A
RLC  - The RLC instruction rotates the eight bits in the accumulator and the one bit in the carry
flag left one bit position. Bit 7 of the accumulator is rotated into the carry flag while the original
value of the carry flag is rotated into bit 0 of the accumulator. Bit 0 of the accumulator is rotated
into bit 1, bit 1 into bit 2, and so on. No other flags are affected by this operation.
Example RLC A
RR  - The RR instruction rotates the eight bits in the accumulator right one bit position. Bit 0 of
the accumulator is rotated into bit 7, bit 7 into bit 6, and so on. No flags are affected by this
instruction.
Example RR A
RRC  - The RRC instruction rotates the eight bits in the accumulator and the one bit in the carry
flag right one bit position. Bit 0 of the accumulator is rotated into the carry flag while the
original value of the carry flag is rotated in to bit 7 of the accumulator. Bit 7 of the accumulator
is rotated into bit 6, bit 6 into bit 5, and so on. No other flags are affected by this instruction.
Example RRC A
SWAP  - The SWAP instruction exchanges the low-order and high-order nibbles within the
accumulator. No flags are affected by this instruction.
Example SWAP A
Boolean Instructions
CLR, ANL, ORL , CPL are same operation of above logical operations but it performs
operations on bits.
SETB  - The SETB instruction sets the bit operand to a value of 1. This instruction can operate
on the carry flag or any other directly addressable bit. No flags are affected by this instruction.
Example SETB C
MOV  - The MOV instruction moves data bits between the two specified operands. The bit
specified by the second operand is copied to the location specified by the first operand. The
source data bit is not affected.
Example MOV C, bit

JC  - The JC instruction branches to the specified address if the carry flag is set. Otherwise,
execution continues with the next instruction. No flags are affected by this instruction.
Example JC LABEL
JNC  - The JNC instruction transfers program control to the specified address if the carry flag is
0. Otherwise, execution continues with the next instruction. No flags are affected by this
instruction.
Example JNC LABEL
JB  - The JB instruction branches to the address specified in the second operand if the value of
the bit specified in the first operand is 1. The bit that is tested is not modified. No flags are
affected by this instruction.
Example JB P1.2 LABEL
JNB  - The JNB instruction branches to the specified address if the specified bit operand has a
value of 0. Otherwise, execution continues with the next instruction. No flags are affected by this
instruction.
Example JNB P1.2 LABEL
JBC  - The JBC instruction branches to the address specified in the second operand if the value
of the bit specified in the first operand is 1.Otherwise, execution continues with the next
instruction.
If the bit specified in the first operand is set, it is cleared. No flags are affected by this
instruction.
Example JBC 44h

Branching Instructions
LJMP  - The LJMP instruction transfers program execution to the specified 16-bit address. The
PC is loaded with the high-order and low-order bytes of the address from the second and third
bytes of this instruction respectively. No flags are affected by this instruction.
Example LJMP addr16

AJMP  - The AJMP instruction transfers program execution to the specified address. The

address is formed by combining the 5 high-order bits of the address of the following instruction
(for A15-A11), the 3 high-order bits of the opcode (for A10-A8), and the second byte of the
instruction (for A7-A0). The destination address must be located in the same 2KByte block of
program memory as the opcode following the AJMP instruction. No flags are affected.

Example AJMP addr11

SJMP  - The SJMP instruction transfers execution to the specified address. The address is
calculated by adding the signed relative offset in the second byte of the instruction to the address
of the following instruction. The range of destination addresses is from 128 before the next
instruction to 127 bytes after the next instruction.
Example SJMP LABEL
JZ  - The JZ instruction transfers control to the specified address if the value in the accumulator
is 0. Otherwise, the next instruction is executed. Neither the accumulator nor any flags are
modified by this instruction.
Example JZ LABEL
JNZ  - The JNZ instruction transfers control to the specified address if the value in the
accumulator is not 0. If the accumulator has a value of 0, the next instruction is executed. Neither
the accumulator nor any flags are modified by this instruction.
Example JNZ LABEL
CJNE  - The CJNE instruction compares the first two operands and branches to the specified
destination if their values are not equal. If the values are the same, execution continues with the
next instruction.
Example CJNE R6, #12H, LABEL
DJNZ  - The DJNZ instruction decrements the byte indicated by the first operand and, if
the resulting value is not zero, branches to the address specified in the second operand.
Example DJNZ 40h, LABEL
NOP  - The NOP instruction does nothing. Execution continues with the next instruction. No
registers or flags are affected by this instruction. NOP is typically used to generate a delay in
execution or to reserve space in code memory.
Example NOP
LCALL  - The LCALL instruction calls a subroutine located at the specified address. This
instruction first adds 3 to the PC to generate the address of the next instruction. This result is
pushed onto the stack low-byte first and the stack pointer is incremented by 2. The high-order
and low-order bytes of the PC are loaded from the second and third bytes of the instruction
respectively. Program execution is transferred to the subroutine at this address. No flags are
affected by this instruction.
Example LCALL addr16
ACALL  - The ACALL instruction calls a subroutine located at the specified address. The PC is
incremented twice to obtain the address of the following instruction. The 16-bit PC is then stored
on the stack (low-order byte first) and the stack pointer is incremented twice. No flags are
affected.

The address of the subroutine is calculated by combining the 5 high-order bits of the incremented
PC (for A15-A11), the 3 high-order bits of the ACALL instruction opcode (for A10-A8), and the
second byte of the instruction (for A7-A0). The subroutine that is called must be located in the
same 2KByte block of program memory as the opcode following the ACALL instruction.
Example ACALL addr11
RET  - The RET instruction pops the high-order and low-order bytes of the PC from the stack
(and decrements the stack pointer by 2). Program execution resumes from the resulting address
which is typically the instruction following an ACALL or LCALL instruction. No flags are
affected by this instruction
Example RET
RETI  - The RETI instruction is used to end an interrupt service routine. This instruction pops
the high-order and low-order bytes of the PC (and decrements the stack pointer by 2) and
restores the interrput logic to accept additional interrupts. No other registers are affected by this
instruction.

The RETI instruction does not restore the PSW to its value before the interrupt. The interrupt
service routine must save and restore the PSW.

Execution returns to the instruction immediately after the point at which the interrupt was
detected. If another interrupt was pending when the RETI instruction is executed, one
instruction at the return address is executed before the pending interrupt is processed.
Example RETI
JMP  - The JMP instruction transfers execution to the address generated by adding the 8-bit
value in the accumulator to the 16-bit value in the DPTR register. Neither the accumulator nor
the DPTR register are altered. No flags are affected by this instruction.
Example JMP @A+DPTR