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Ec8691 Microprocessors and Microcontrollers MCQ
Ec8691 Microprocessors and Microcontrollers MCQ
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b) 1 byte
EC8691 c) 3 bytes
d) 4 bytes
MICROPROCESSORS
AND Answer: b
Explanation: This format is only one byte
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MICROCONTROLLERS long.
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d) 4 bytes
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Explanation: This format is 2 bytes long.
MICROPROCESSOR
5. The R/M field in a machine instruction
TOPIC 1.1 INTRODUCTION TO pa format specifies
a) another register
8086 MICROPROCESSOR b) another memory location
ARCHITECTURE c) other operands
d) all of the mentioned
1. Operation code field is present in :
Answer: d
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a) programming language instruction
b) assembly language instruction Explanation: The LSBs(least significant bits)
c) machine language instruction from 0 to 3 represent R/M field that specifies
d) none of the mentioned another register or memory location i.e. the
other operand.
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Answer: c
Explanation: Machine language instruction 6. In a machine instruction format, S-bit is the
format has one or more fields. The first one is a) status bit
the operation code field. b) sign bit
c) sign extension bit
2. A machine language instruction format d) none of the mentioned
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consists of
a) Operand field Answer: c
b) Operation code field Explanation: The S-bit known as sign
extension bit is used along with W-bit to
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a) 8 bits instruction.
b) 4 bits
c) 16 bits
d) 2 bits
TOPIC 1.2 ADDRESSING
MODES
Answer: c
Explanation: If W-bit is ‘1’ then the operand 1. The instruction, Add #45,R1 does _______
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is of 16-bits, and if it is ‘0’ then the operand a) Adds the value of 45 to the address of R1
is of 8-bits. and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in
9. The instructions which after execution R1
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transfer control to the next instruction in the c) Finds the memory location 45 and adds
sequence are called that content to that of R1
a) Sequential control flow instructions d) None of the mentioned
b) control transfer instructions
instructions
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c) Sequential control flow & control transfer Answer: b
Explanation: The instruction is using
d) none of the mentioned immediate addressing mode hence the value
is stored in the location 45 is added.
Answer: a
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Explanation: The sequential control flow 2. In the case of, Zero-address instruction
instructions follow sequence order in their method the operands are stored in _____
execution. a) Registers
b) Accumulators
10. The instructions that transfer the control c) Push down stack
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instructions
d) none of the mentioned 3. Add #45, when this instruction is executed
the following happen/s _______
Answer: b a) The processor raises an error and requests
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b) Index addressing mode Answer: d
c) Relative addressing mode Explanation: In the case of, auto increment
d) Offset addressing mode the increment is done afterward and in auto
decrement the decrement is done first.
Answer: a
Explanation: In this addressing mode, the 8. The addressing mode, where you directly
value of the register serves as another specify the operand value is _______
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memory location and hence we use pointers a) Immediate
to get the data. b) Direct
c) Definite
5. In the following indexed addressing mode d) Relative
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instruction, MOV 5(R1), LOC the effective
address is ______ Answer: a
a) EA = 5+R1 Explanation: None.
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]
pa 9. The effective address of the following
instruction is MUL 5(R1,R2).
a) 5+R1+R2
Answer: d b) 5+(R1*R2)
Explanation: This instruction is in Base with c) 5+[R1]+[R2]
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offset addressing mode. d) 5*([R1]+[R2])
Answer: b b) Indirect
Explanation: In this, the contents of the PC c) Index with Offset
are directly incremented. d) Immediate
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1. The assembler directives which are the allocating memory locations in the available
hints using some predefined alphabetical memory.
strings are given to
a) processor 4. The directive that marks the end of an
b) memory assembly language program is
c) assembler a) ENDS
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d) processor & assembler b) END
c) ENDS & END
Answer: c d) None of the mentioned
Explanation: These directives help the
assembler to correctly understand the Answer: b
assembly language programs to prepare the Explanation: The directive END is used to
codes. denote the completion of the program.
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2. The directive used to inform the assembler, 5. The directive that marks the end of a
the names of the logical segments to be logical segment is
assumed for different segments used in the a) ENDS
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program is b) END
a) ASSUME c) ENDS & END
b) SEGMENT pa d) None of the mentioned
c) SHORT
d) DB Answer: a
Explanation: The directive ENDS is used to
Answer: a end a segment where as the directive END is
Explanation: In ALP, each segment is given used to end the program.
a name by using the directive ASSUME
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SYNTAX: ASSUME segment:segment_name 6. The directive that updates the location
Eg: ASSUME CS:Code counter to the next even address while
here CS is the Code segment and code is the executing a series of instructions is
name assumed to the segment. a) EVN
b) EVEN
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a) OFFSET
d) a-3, b-1, c-4, d-2 b) LABEL
c) ORG
Answer: d d) GROUP
Explanation: These directives are used for
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location counter is initialized to 0000H. d) Converter
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d) PROC 2. The instructions like MOV or ADD are
called as ______
Answer: b a) OP-Code
Explanation: The directive SEGMENT b) Operators
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indicates the beginning of the segment. c) Commands
d) None of the mentioned
9. The recurrence of the numerical values or
constants in a program code is reduced by Answer: a
a) ASSUME
b) LOCAL
pa Explanation: This OP – codes tell the system
what operation to perform on the operands.
c) LABEL
d) EQU 3. The alternate way of writing the
instruction, ADD #5,R1 is ______
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Answer: d a) ADD [5],[R1];
Explanation: In this, the recurring/repeating b) ADDI 5,R1;
value is assigned with a label. The label is c) ADDIME 5,[R1];
placed instead of the numerical value in the d) There is no other way
entire program code.
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Answer: b
10. The labels or constants that can be used Explanation: The ADDI instruction, means
by any module in the program is possible the addition is in immediate addressing mode.
when they are declared as
a) PUBLIC 4. Instructions which won’t appear in the
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by any module in the program. Explanation: The directives help the program
in getting compiled and hence won’t be there
in the object code.
TOPIC 1.4 ASSEMBLY
LANGUAGE PROGRAMMING
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200 execution of a program.
c) Re-assigns the address of Sum by adding a) End
200 to its original address b) Return
d) Assigns 200 bytes of memory starting the c) Stop
location of Sum d) Terminate
Answer: b Answer: b
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Explanation: This basically is used to replace Explanation: This instruction directive is
the variable with a constant value. used to terminate the program execution.
6. The purpose of the ORIGIN directive is 10. The last statement of the source program
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__________ should be _______
a) To indicate the starting position in memory, a) Stop
where the program block is to be stored b) Return
c) OP
code
pa
b) To indicate the starting of the computation
a) Reserve satisfied
b) Store c) Finds the Branch offset and replaces the
c) Dataword Branch target with it
d) EQU d) Replaces the target with the value specified
by the DATAWORD directive
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Answer: c
Explanation: None. Answer: c
Explanation: When the assembler comes
8. _____ directive is used to specify and across the branch code, it immediately finds
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assign the memory required for the block of the branch offset and replaces it with it.
code.
a) Allocate 12. The assembler stores all the names and
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______ Explanation: All of the mentioned principles
a) Main memory are known as constructive design principles.
b) Cache
c) RAM 2. What is the Aesthetic principle among the
d) Magnetic disk following?
a) High quality programs can be constructed
Answer: d from self contained, understandable parts or
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Explanation: After compiling the object modules
code, the assembler stores it in the magnetic b) A design will be more or less easy to be
disk and waits for further execution. build
c) Beauty is one of the important factor to be
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14. The utility program used to bring the acknowledged as design principle
object code into memory for execution is d) None of the mentioned
______
a) Loader Answer: c
b) Fetcher
c) Extractor
pa Explanation: Aesthetic principle states
Beauty as one of the most important factor to
d) Linker be acknowledged.
b) Coupling
PROGRAMMING c) Cohesion
d) All of the mentioned
1. Which of the following fall under
constructive design principles?
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between pair of module
b) Coupling is the degree to which a module’s Answer: d
part are related to one another Explanation: All of the mentioned statements
c) All of the mentioned violated principle of least privilege.
d) None of the mentioned
9. Which of these is correct with context to
Answer: a coupling?
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Explanation: Coupling is the degree of a) Failure to hide information leads to loose
connection between pair of module. coupling and cannot be avoided
b) Modules that communicate using special
6. Which of the following is true? data types and structures are less tightly
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a) Module coupling should be maximized coupled than modules with simple values
b) Module cohesion should be minimized c) When modules communicate only through
c) Modules should not have access to public module interface, their coupling
unneeded resources
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d) Design with small modules are not better
strength is proportional to the number of
messages and number of data passed in
between
Answer: c d) All of the mentioned
Explanation: Module coupling should be
minimized, module cohesion should be Answer: c
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maximized, design with small modules are Explanation: Failure to hide information
always better, modules should not access leads to tight coupling, Modules with special
unneeded resources( principle of least data types are more tightly coupled.
privilege).
10. Which of these is correct with the context
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Answer: d Answer: c
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through the main program, then to reduce the b) to represent directives
length of the program, __________ is used. c) to represent statements
a) procedure d) all of the mentioned
b) subroutine
Answer: d
c) macro
Explanation: A macro may be used in data
d) none of the mentioned
segment and can also be used to represent
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Answer: c statements and directives.
Explanation: For a certain number of
6. The end of a macro can be represented by
instructions that are repeated in the main
the directive.
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program, when macro is defined then the
a) END
code of a program is reduced by placing the
b) ENDS
name of the macro at which the set of
c) ENDM
instructions are needed to be repeated.
d) ENDD
Answer: b Answer: c
Explanation: The time required for execution Explanation: An interrupt function is to
of a macro is less than that of procedure as it break the sequence of operation.
does not contain CALL and RET instructions
as the procedures do. 2. An interrupt breaks the execution of
instructions and diverts its execution to
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9. Which of the following statements is a) Interrupt service routine
incorrect? b) Counter word register
a) complete code of instruction string is c) Execution unit
inserted at each place, wherever the d) control unit
macroname appears
b) macro requires less time of execution than Answer: a
that of procedure Explanation: An interrupt transfers the
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c) macro uses stack memory control to interrupt service routine (ISR).
d) macroname can be anything except After executing ISR, the control is transferred
registers and mnemonics back again to the main program.
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Answer: c 3. While executing the main program, if two
Explanation: Macro does not require stack or more interrupts occur, then the sequence of
memory and hence has less time for appearance of interrupts is called
a) multi-interrupt
execution.
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10. The beginning of the macro can be
b) nested interrupt
c) interrupt within interrupt
represented as d) nested interrupt and interrupt within
a) START interrupt
b) BEGIN
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c) MACRO Answer: d
d) None of the mentioned Explanation: If an interrupt occurs while
executing a program, and the processor is
Answer: c executing the interrupt, if one more interrupt
Explanation: The beginning of the macro is occurs again, then it is called a nested
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Answer: c
1. While CPU is executing a program, an
Explanation: The processor if handles more
interrupt exists then it
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nonmaskable interrupt.
Answer: c
7. If any interrupt request given to an input Explanation: If a microprocessor wants to
pin cannot be disabled by any means then the serve any interrupt then interrupt flag, IF=1.
input pin is called If interrupt flag, IF=0, then the processor
a) maskable interrupt ignores the service.
b) nonmaskable interrupt
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c) maskable interrupt and nonmaskable
interrupt TOPIC 1.8 BYTE AND STRING
d) none of the mentioned MANIPULATION.
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Answer: b 1. Which of these methods of Byte wrapper
Explanation: A nonmaskable interrupt input can be used to obtain Byte object from a
pin is one which means that any interrupt string?
request at NMI (nonmaskable interrupt) input
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cannot be masked or disabled by any means.
a) toString()
b) getString()
c) decode()
8. The INTR interrupt may be d) encode()
a) maskable
b) nonmaskable Answer: c
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c) maskable and nonmaskable Explanation: decode() methods returns a
d) none of the mentioned Byte object that contains the value specified
by string.
Answer: a
Explanation: the INTR (interrupt request) is 2. Which of the following methods Byte
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both Byte and Short wrappers? 6. What will be the output of the following
a) intValue() Java program?
b) isInfinite()
c) toString() 1. class Output
d) hashCode()
2. {
Answer: b
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Explanation: isInfinite() methods is defined 3. public static void main(Str
ing args[])
in Integer and Long Wrappers, returns true if
specified value is an infinite value otherwise 4. {
it returns false.
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5. Double i = new Double(2
5. What will be the output of the following 57.5);
Java code?
6. Double x = i.MIN_VALUE;
1. class Output
pa 7. System.out.print(x);
2. {
8. }
3. public static void main(Str
9. }
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ing args[])
4. { a) 0
b) 4.9E-324
5. Double i = new Double(2 c) 1.7976931348623157E308
57.5); d) None of the mentioned
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6. Double x = i.MAX_VALUE;
Answer: b
7. System.out.print(x); Explanation: The super class of Byte class
defines a constant MIN_VALUE below
8. } which a number is considered to be negative
infinity. MIN_VALUE is 4.9E-324.
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9. } Output:
a) 0 $ javac Output.java
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Java program?
Answer: b
Explanation: The super class of Double class 1. class Output
defines a constant MAX_VALUE above
which a number is considered to be infinity. 2. {
3. public static void main(Str 1. The mnemonic that is placed before the
ing args[]) arithmetic operation is performed is
a) AAA
4. {
b) AAS
5. Double i = new Double(2 c) AAM
57.578123456789); d) AAD
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6. float x = i.floatValue( Answer: d
); Explanation: The AAD instruction converts
two unpacked BCD digits in AH and AL to
7. System.out.print(x);
the equivalent binary number in AL.
8. }
2. The Carry flag is undefined after
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9. } performing the operation
a) AAA
a) 0 b) ADC
b) 257.0 c) AAM
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c) 257.57812 d) AAD
d) 257.578123456789
Answer: d
Answer: c Explanation: Since the operation, AAD is
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Explanation: floatValue() converts the value
of wrapper i into float, since float can
performed before division operation is
performed, the carry flag, auxiliary flag and
measure till 5 places after decimal hence overflow flag are undefined.
257.57812 is stored in floating point variable
x. 3. The instruction that performs logical AND
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Output: operation and the result of the operation is not
available is
$ javac Output.java a) AAA
$ java Output
257.57812 b) AND
c) TEST
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d) XOR
Java Mock Tests & Certification Test | 1000
Java MCQs | 1000 Java Programs | 1000 Java Answer: c
Algorithms | Best Java Books Explanation: In the TEST instruction, the
logical AND operation is performed and the
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Answer: a Answer: c
Explanation: In RCL(Rotate right through Explanation: At each CALL instruction, the
carry), for each operation, the carry flag is IP and CS of the next instruction are pushed
pushed into LSB and the MSB of the operand onto the stack, before the control is
is pushed into carry flag. transferred to the procedure. At the end of the
procedure, the RET instruction must be
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5. The instruction that is used as prefix to an executed to retrieve the stored contents of IP
instruction to execute it repeatedly until the & CS registers from a stack.
CX register becomes zero is
a) SCAS 8. The instruction that unconditionally
b) REP transfers the control of execution to the
c) CMPS specified address is
d) STOS a) CALL
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b) JMP
Answer: b c) RET
Explanation: The instruction to which the d) IRET
REP is prefix, is executed repeatedly until CX
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register becomes zero. When CX becomes Answer: b
zero, the execution proceeds to the next Explanation: In this the control transfers to
instruction in sequence. pa the address specified in the instruction and
flags are not affected by this instruction.
6. Match the following
9. Which instruction cannot force the 8086
A) MOvSB/SW 1) loads AL/AX register processor out of ‘halt’ state?
by content of a string
a) Interrupt request
B) CMPS 2) moves a string of by
b) Reset
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tes stored in source to destination
C) SCAS 3) compares two strings c) Both interrupt request and reset
of bytes or words whose length is stored d) Hold
in CX register
D) LODS 4) scans a string of by Answer: d
tes or words
Explanation: Only an interrupt request or
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Answer: d b) Delay
Explanation: By using the string instructions, c) Memory location
the operations on strings can be performed. d) None of the mentioned
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function are operation for the clock cycle and thus there
a) CALL, JMP exists a delay.
b) JMP, IRET
11. Which of the following is not a machine
c) CALL, RET
controlled instruction?
d) JMP, RET
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Explanation: Since CLC is a flag b) write operation on output data
manipulation instruction where CLC stands c) read operation on input data
for Clear Carry Flag. d) read operation on output data
Answer: b
TOPIC 2.2 SYSTEM BUS Explanation: IOWR (active low) operation
TIMING - SYSTEM DESIGN means writing data to an output device and
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USING 8086 - I/O not an input device.
PROGRAMMING
5. The latch or IC 74LS373 acts as
a) good input port
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1. The device that enables the microprocessor b) bad input port
to read data from the external devices is c) good output port
a) printer d) bad output port
b) joystick
c) display
d) reader
pa Answer: c
Explanation: If the output port is to source
large currents, the port lines must be buffered.
Answer: b So, the latch is used as it acts as a good output
Explanation: Since joystick is an input port.
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device, it reads data from the external
devices. 6. While performing read operation, one must
take care that much current should not be
2. The example of output device is a) sourced from data lines
a) CRT display b) sinked from data lines
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c) buffer
c) read, write d) tristate buffer
d) write, read
Answer: d
Answer: c Explanation: A tristate buffer is used as an
Explanation: The input activity is similar to
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d) all of the mentioned hardware (wire) required and thereby
reducing the cost.
Answer: d
Explanation: The chip 74LS245 is a 2. ______ are used to overcome the
bidirectional buffer that contains 8 buffers difference in data transfer speeds of various
and may be used as an 8-bit input port. But devices.
while using as an input device, only one a) Speed enhancing circuitory
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direction is useful. b) Bridge circuits
c) Multiple Buses
9. In 74LS245, if DIR is 1, then the direction d) Buffer registers
is from
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a) inputs to outputs Answer: d
b) outputs to inputs Explanation: By using Buffer registers, the
c) source to sink processor sends the data to the I/O device at
d) sink to source the processor speed and the data gets stored in
Answer: a
pa the buffer. After that the data gets sent to or
from the buffer to the devices at the device
Explanation: If DIR is 1, then the direction is speed.
from A(inputs) to B(outputs).
3. To extend the connectivity of the processor
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10. In memory-mapped scheme, the devices bus we use ________
are viewed as a) PCI bus
a) distinct I/O devices b) SCSI bus
b) memory locations c) Controllers
c) only input devices d) Multiple bus
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MULTIPROGRAMMING - b) M-bus
SYSTEM BUS STRUCTURE c) ISA
d) None of the mentioned
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10. The ISA standard Buses are used to
Answer: b connect ___________
Explanation: SCSI BUS is usually used to a) RAM and processor
connect video devices to the processor. b) GPU and processor
c) Harddisk and Processor
6. ANSI stands for __________ d) CD/DVD drives and Processor
a) American National Standards Institute
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b) American National Standard Interface Answer: c
c) American Network Standard Interfacing Explanation: None.
d) American Network Security Interrupt
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Answer: a
TOPIC 2.4 MULTIPROCESSOR
Explanation: None. CONFIGURATIONS -
COPROCESSOR, CLOSELY
7. _____ register Connected to the Processor
pa
bus is a single-way transfer capable.
a) PC
COUPLED AND LOOSELY
COUPLED CONFIGURATIONS
b) IR
c) Temp 1. The processors used in the multi-
d) Z microprocessor are
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a) coprocessors
Answer: d b) independent processors
Explanation: The Z register is a special c) coprocessors or independent processors
register which can interact with the processor d) none of the mentioned
BUS only.
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Answer: c
8. In multiple Bus organisation, the registers Explanation: The processors used in the
are collectively placed and referred as ______ multi-microprocessor are either coprocessors
a) Set registers or independent processors.
b) Register file
2. The processor that executes the instructions
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c) Register Block
d) Map registers fetched for it by the host processor is
a) microprocessor
Answer: b b) coprocessor
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a) Reduction in the number of cycles for Explanation: The coprocessor executes the
execution instructions fetched for it by the host
b) Increase in size of the registers processor.
3. The processor that asks for bus access or its own bus control logic. The bus arbitration
may itself fetch the instructions and execute is handled by an external circuit, common to
them is all the processors.
a) microprocessor
b) coprocessor 7. The loosely coupled system has an
c) independent processor advantage of
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d) coprocessor and independent processor a) more number of CPUs can be added
b) system structure is modular
Answer: c c) more fault-tolerant and suitable for parallel
Explanation: The independent processor may applications
ask for bus access, may fetch the instructions d) all of the mentioned
itself, and execute them independently.
Answer: d
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4. In tightly coupled systems, the Explanation: The loosely coupled system is
microprocessors share advantageous than the tightly coupled system
a) common clock as it has advantages of more number of CPUs
b) bus control logic can be added to improve the system
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c) common clock and bus control logic performance. A fault in a single module does
d) none of the mentioned not lead to a complete system breakdown.
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d) clock pulse control transfer, required stack manipulations,
privilege level and its type.
Answer: c
Explanation: The microprocessor in a closely 4. The gate that is used to alter the privilege
coupled system either uses a status bit in levels is
memory or interrupts the host to inform it a) call gate
about the completion of task allotted to it. b) task gate
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c) interrupt gate
d) trap gate
TOPIC 2.5 INTRODUCTION TO
ADVANCED PROCESSORS. Answer: a
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Explanation: Call gates are used to alter the
1. Which of the following is a type of system privilege levels.
segment descriptor?
5. The gate that is used to specify a
a) system descriptor
b) gate descriptor
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c) system descriptor and gate descriptor
corresponding service routine is
a) call gate and trap gate
d) none of the mentioned b) task gate and interrupt gate
c) interrupt gate and trap gate
Answer: c d) task gate and trap gate
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Explanation: The system segment descriptors
are of seven types. The types 1 to 3 are called Answer: c
system descriptors and the types 4 to 7 are Explanation: Interrupt gates and trap gates
called gate descriptors. are used to specify corresponding service
routines.
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types namely, call gate, task gate, interrupt Explanation: Task gate is used to switch
gate and trap gate. from one task to another.
Answer: d a) LDT
Explanation: The word count field is only b) LGDT and LLDT
used by a call gate descriptor, to indicate the c) GDT
number of bytes to be transferred from the d) None of the mentioned
stack of the calling routine to the stack of the
called routine. Answer: b
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Explanation: The LGDT and LLDT
8. The memory that maintains the most instructions are privileged, and may be
frequently required data for execution, in a executed only at privilege level 0.
high speed memory is called
a) virtual memory 12. The instruction that loads a selector which
b) physical memory refers to a local descriptor table, containing
c) cache memory the base address and limit for LDT is
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d) ROM (read only memory) a) LGT
b) GDT
Answer: c c) LGDT
Explanation: To minimize the time required d) LLDT
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for fetching the frequently required descriptor
information, from the main memory, cache Answer: d
memory is used in which the most frequently Explanation: The LLDT instruction loads a
selector, which refers to a local descriptor
15. The number of bytes required for an data from the microprocessor to the external
interrupt in an IDT is devices.
a) 2
b) 4 3. The input and output operations are
c) 6 respectively similar to the operations,
d) 8 a) read, read
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b) write, write
Answer: c c) read, write
Explanation: Six bytes are required for each d) write, read
interrupt in an interrupt descriptor table.
Answer: c
Explanation: The input activity is similar to
read operation and the output activity is
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similar to write operation.
UNIT III I/O
4. The operation, IOWR (active low)
INTERFACING performs
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a) write operation on input data
TOPIC 3.1 MEMORY b) write operation on output data
c) read operation on input data
INTERFACING AND I/O pa d) read operation on output data
INTERFACING - PARALLEL
COMMUNICATION INTERFACE Answer: b
- SERIAL COMMUNICATION Explanation: IOWR (active low) operation
means writing data to an output device and
INTERFACE not an input device.
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1. The device that enables the microprocessor 5. The latch or IC 74LS373 acts as
to read data from the external devices is a) good input port
a) printer b) bad input port
b) joystick c) good output port
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device, it reads data from the external So, the latch is used as it acts as a good output
devices. port.
2. The example of output device is 6. While performing read operation, one must
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sourced or sinked from data lines while the devices are viewed as memory locations
reading to avoid loading. and are addressed likewise.
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b) flipflop
c) buffer 1. How many control lines are present in
d) tristate buffer analog to digital converter in addition to
reference voltage?
Answer: d a) Three
Explanation: A tristate buffer is used as an b) Two
input device to overcome loading. c) One
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d) None of the mentioned
8. The chip 74LS245 is
a) bidirectional buffer Answer: b
b) 8-bit input port Explanation: ADC usually has two
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c) one that has 8 buffers additional control lines
d) all of the mentioned 1. Start input-tell ADC when to start
conversion.
Answer: d
Explanation: The chip 74LS245 is a
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bidirectional buffer that contains 8 buffers
2. EOC- end of conversion.
4. Which A/D converter is considered to be required almost doubles for each added bit.
simplest, fastest and most expensive? For example – 2 -bit ADC requires three
a) Servo converter comparators, 3 -bit ADC needs seven
b) Counter type ADC comparators and a 4 -bit ADC requires fifteen
c) Flash type ADC comparators.
d) All of the mentioned
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8. Drawback of counter type A/D converter
Answer: c a) Counter clears automatically
Explanation: The simplest possible A/D b) More complex
converter is flash type converter and is c) High conversion time
expensive for high degree of accuracy. d) Low speed
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a) Parallel non-inverting A/D converter Explanation: In counter type ADC counter
b) Parallel counter A/D converter frequency is kept low enough to give
c) Parallel inverting A/D converter sufficient time for DAC to settle and for the
d) Parallel comparator A/D converter comparator for respond. So, low speed is the
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most serious drawback.
Answer: d
Explanation: The flash type A/D converter 9. Calculate the conversion time of a 12-bit
are also called as parallel comparator A/D counter type ADC with 1MHz clock frequent
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converter because the purpose of the circuit is
to compare the analog input voltage with each
to convert a full scale input?
a) 4.095 µs
node voltage. b) 4.095ms
c) 4.095s
6. What is the advantage of using flash type d) None of the mentioned
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A/D converter?
a) High speed conversion Answer: b
b) Low speed conversion Explanation: conversion time = 2n -1 clock
c) Nominal speed conversion
periods = (12n-1) = 4.095ms.
d) None of the mentioned
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Answer: a
flash type A/D converter Explanation: In servo converter, the circuit
a) Triples for each added bit consist of an up/down counter with
b) Reduce by half for each added bit comparator controlling direction of the count.
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c) Double for each added bit So, if the input voltage is greater than DAC
d) Doubles exponentially for each added bit output signal, the output of comparator goes
Answer: c high and counter is caused to count up.
Explanation: The number of comparator
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Explanation: In this mode, each key code of
Answer: b the pressed key is entered in the order of the
Explanation: As long as the analog input entry, and in the meantime, read by the CPU,
changes slowly, the tracking A/D converter till the RAM becomes empty.
will be within one LSB of the corrected
value. When the input changes rapidly, the 3. The registers that hold the address of the
tracking A/D converter cannot keep up with word currently being written by the CPU
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change and error occurs. from the display RAM are
a) control and timing register
12. How many clock pulses do a successive b) control and timing register and timing
approximation converter requires for control
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obtaining a digital output. c) display RAM
a) Twelve d) display address registers
b) Six
Answer: d
c) Eight
d) None of the mentioned
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holds the address of the word currently being
Answer: d written or read by the CPU to or from the
Explanation: The successive approximation display RAM.
technique uses a very efficient code search
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strategy to compute n-bit conversion in just n- 4. When a key is pressed, a debounce logic
clock period. comes into operation in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
TOPIC 3.3 KEYBOARD c) scanned keyboard mode with 2 key lockout
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a) I/O control and data buffers is pressed, a debounce logic comes into
b) Control and timing registers operation. During the next two scans, other
c) Return buffers keys are checked for closure and if no other
d) Display address registers key is pressed then the first pressed key is
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identified.
Answer: b
Explanation: The control and timing register 5. The mode that is programmed using “end
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to store the keyboard and display modes and interrupt/error mode set command” is
other operations programmed by CPU. a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
2. The sensor RAM acts as 8-byte first-in- c) scanned keyboard mode with 2 key lockout
first-out RAM in d) sensor matrix mode
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6. When a key is pressed, the debounce d) WF
circuit waits for 2 keyboard scans and then
checks whether the key is still depressed in Answer: c
a) scanned keyboard special error mode Explanation: AI refers to auto increment
b) scanned keyboard with N-key rollover flag.
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode 10. If any change in sensor value is detected
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at the end of a sensor matrix scan, then the
Answer: b IRQ line
Explanation: In this mode, When a key is a) goes low
pressed, the debounce circuit waits for 2 b) goes high
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keyboard scans and then checks whether the c) remains unchanged
key is still depressed. If it is still depressed, d) none
the code is entered in FIFO RAM.
Answer: b
mode, as in a type-writer the first character 1. The number of hardware interrupts that the
typed appears at the left-most position, while processor 8085 consists of is
the subsequent characters appear successively a) 1
to the right of the first one. b) 3
c) 5
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c) keyboard and strobed input mode hardware interrupt pins. Out of these five,
d) scanned sensor matrix mode four pins were alloted fixed vector addresses
but the pin INTR was not alloted by vector
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2. The register that stores all the interrupt vectored interrupts. In cascade mode, 64
requests in it in order to serve them one by vectored interrupts can be provided.
one on a priority basis is
a) Interrupt Request Register 6. When the PS(active low)/EN(active low)
b) In-Service Register pin of 8259A used in buffered mode, then it
c) Priority resolver can be used as a
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d) Interrupt Mask Register a) input to designate chip is master or slave
b) buffer enable
Answer: a c) buffer disable
Explanation: The interrupts at IRQ input d) none
lines are handled by Interrupt Request
Register internally. Answer: b
Explanation: When the pin is used in
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3. The register that stores the bits required to buffered mode, then it can be used as a buffer
mask the interrupt inputs is enable to control buffer transreceivers. If it is
a) In-service register not used in buffered mode, then the pin is
b) Priority resolver used as input to designate whether the chip is
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c) Interrupt Mask register used as a master or a slave.
d) None
7. Once the ICW1 is loaded, then the
Answer: c initialization procedure involves
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Explanation: Also, Interrupt Mask Register
operates on IRR(Interrupt Request Register)
a) edge sense circuit is reset
b) IMR is cleared
at the direction of the Priority Resolver. c) slave mode address is set to 7
d) all of the mentioned
4. The interrupt control logic
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a) manages interrupts Answer: d
b) manages interrupt acknowledge signals Explanation: The initialization procedure
c) accepts interrupt acknowledge signal involves
d) all of the mentioned i) edge sense circuit is reset.
ii) IMR is cleared.
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d) 64 Answer: b
Explanation: When non-specific EOI
Answer: d command is issued to 8259A it will
Explanation: A single 8259A provides 8 automatically reset the highest ISR.
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the entire process.
Answer: a
Explanation: The automatic rotation is used 4. After the completion of the DMA transfer,
in the applications where all the interrupting the processor is notified by __________
devices are of equal priority. a) Acknowledge signal
b) Interrupt signal
c) WMFC signal
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TOPIC 3.5 DMA (DIRECT d) None of the mentioned
MEMORY
ACCESS)CONTROLLER Answer: b
Explanation: The controller raises an
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interrupt signal to notify the processor that
1. The DMA differs from the interrupt mode
the transfer was complete.
by __________
a) The involvement of the processor for the
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operation a) 4
b) The method of accessing the I/O devices b) 2
c) The amount of data transfer possible c) 3
d) None of the mentioned d) 1
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Answer: d Answer: c
Explanation: DMA is an approach of Explanation: The Controller uses the
performing data transfers in bulk between registers to store the starting address, word
memory and the external device without the count and the status of the operation.
intervention of the processor.
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a) True a) Optimizers
b) False b) BUS arbitrators
c) Multiple BUS structure
Answer: a d) None of the mentioned
Explanation: The DMA controller can
perform operations on two different disks if Answer: b
the appropriate details are known. Explanation: The BUS arbitrator is used to
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overcome the contention over the BUS
9. The technique whereby the DMA possession.
controller steals the access cycles of the
processor to operate is called __________ 13. The registers of the controller are ______
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a) Fast conning a) 64 bits
b) Memory Con b) 24 bits
c) Cycle stealing c) 32 bits
d) Memory stealing d) 16 bits
Answer: c
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Explanation: The controller takes over the Explanation: None.
processor’s access cycles and performs
memory operations. 14. When the process requests for a DMA
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transfer?
10. The technique where the controller is a) Then the process is temporarily suspended
given complete access to main memory is b) The process continues execution
__________ c) Another process gets executed
a) Cycle stealing d) process is temporarily suspended &
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Explanation: The controller is given full performed, meanwhile another process is run
control of the memory access cycles and can on the processor.
transfer blocks at a faster rate.
15. The DMA transfer is initiated by _____
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b) Signal enhancers d) OS
c) Bridge circuits
d) All of the mentioned Answer: c
Explanation: The transfer can only be
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STUDIES: TRAFFIC LIGHT Explanation: For writing commands on an
CONTROL, LED DISPLAY , LCD LCD, RS pin is reset.
DISPLAY, KEYBOARD DISPLAY 5. Which command of an LCD is used to shift
INTERFACE AND ALARM the entire display to the right?
CONTROLLER. a) 0x1C
b) 0x18
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1. How many rows and columns are present c) 0x05
in a 16*2 alphanumeric LCD? d) 0x07
a) rows=2, columns=32
Answer: a
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b) rows=16, columns=2
Explanation: 0x1C is used to shift the entire
c) rows=16, columns=16
display to the right.
d) rows=2, columns=16
6. Which command is used to select the 2
Answer: d
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Explanation: 16*2 alphanumeric LCD has 2
rows and 16 columns.
lines and 5*7 matrix of an LCD?
a) 0x01
b) 0x06
2. How many data lines are there in a 16*2 c) 0x0e
alphanumeric LCD? d) 0x38
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a) 16
Answer: d
b) 8
Explanation: 0x38 is used to select the 2
c) 1
lines and 5*7 matrix of an LCD.
d) 0
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Explanation: Pin no 3 is used for controlling has to be displayed (i.e. write to the LCD).
the contrast of the LCD. High to low pulse must be applied to the E
pin when data is supplied to data pins of the
4. For writing commands on an LCD, RS bit LCD.
is
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d) none of the mentioned a) 0xFF
b) 0x00
Answer: c c) 0x01
Explanation: For reading operations, R/W d) A port is by default an output port
pin should be made high and added to it, a
low to high pulse is also generated at the E Answer: d
pin. Explanation: In 8051, a port is initialized by
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default in its output mode no need to pass any
9. Which instruction is used to select the first value to it.
row first column of an LCD?
a) 0x08 2. Which out of the four ports of 8051 needs a
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b) 0x0c pull-up resistor for using it is as an input or an
c) 0x80 output port?
d) 0xc0 a) PORT 0
b) PORT 1
Answer: c
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Explanation: 0x80 is used to select the first
c) PORT 2
d) PORT 3
row first column of an LCD.
Answer: a
10. The RS pin is _________ for an LCD. Explanation: These pins are the open drain
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a) input pins of the controller which means it needs a
b) output pull-up resistor for using it as an input or an
c) input & output output ports.
d) none of the mentioned
3. Which of the ports act as the 16 bit address
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Answer: c
UNIT IV Explanation: PORT 0 and PORT 2 are used
as the 16 bit address lines where PORT0 act
MICROCONTROLLER
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Explanation: Register indirect addressing
5. Which instruction is used to check the mode is useful if a series of data is to be
status of a single bit? assigned to that address, with the help of this
a) MOV A,P0 quality the number of instructions decreases
b) ADD A,#05H as a result of which performance increases.
c) JNB PO.0, label
d) CLR P0.05H 9. Which of the following comes under the
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indexed addressing mode?
Answer: c a) MOVX A, @DPTR
Explanation: JNB which stands for Jump if b) MOVC @A+DPTR,A
no bit checks the status of the bit P0.0 and c) MOV A,R0
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jumps if the bit is 0. d) MOV @R0,A
b) #
c) @
d) & TOPIC 4.2 ASSEMBLY
LANGUAGE PROGRAMMING.
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Answer: c
Explanation: In register, indirect mode data 1. __________ converts the programs written
is copied at that location where R0 or R1 are in assembly language into machine
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called as ______
a) OP-Code 6. The purpose of the ORIGIN directive is
b) Operators __________
c) Commands a) To indicate the starting position in memory,
d) None of the mentioned where the program block is to be stored
b) To indicate the starting of the computation
Answer: a code
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Explanation: This OP – codes tell the system c) To indicate the purpose of the code
what operation to perform on the operands. d) To list the locations of all the registers used
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instruction, ADD #5,R1 is ______ Explanation: This does the function similar
a) ADD [5],[R1]; to the main statement.
b) ADDI 5,R1;
c) ADDIME 5,[R1]; 7. The directive used to perform initialization
d) There is no other way
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a) Reserve
Answer: b b) Store
Explanation: The ADDI instruction, means c) Dataword
the addition is in immediate addressing mode. d) EQU
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4. Instructions which won’t appear in the Answer: c
object program are called as _____ Explanation: None.
a) Redundant instructions
b) Exceptions 8. _____ directive is used to specify and
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in the instruction: Sum EQU 200 does allocate a block of memory and to store the
________ object code of the program there.
a) Finds the first occurrence of Sum and
9. _____ directive specifies the end of
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c) Stop b) Cache
d) Terminate c) RAM
d) Magnetic disk
Answer: b
Explanation: This instruction directive is Answer: d
used to terminate the program execution. Explanation: After compiling the object
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code, the assembler stores it in the magnetic
10. The last statement of the source program disk and waits for further execution.
should be _______
a) Stop 14. The utility program used to bring the
b) Return object code into memory for execution is
c) OP ______
d) End a) Loader
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b) Fetcher
Answer: d c) Extractor
Explanation: This enables the processor to d) Linker
load some other process.
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Answer: a
11. When dealing with the branching code the Explanation: The program is used to load the
assembler ___________ program into memory.
a) Replaces the target with its address
satisfied
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b) Does not replace until the test condition is 15. To overcome the problems of the
assembler in dealing with branching code we
c) Finds the Branch offset and replaces the use _____
Branch target with it a) Interpreter
d) Replaces the target with the value specified b) Debugger
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by the DATAWORD directive c) Op-Assembler
d) Two-pass assembler
Answer: c
Explanation: When the assembler comes Answer: d
across the branch code, it immediately finds Explanation: This creates entries into the
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the branch offset and replaces it with it. symbol table first and then creates the object
code.
12. The assembler stores all the names and
their corresponding values in ______
a) Special purpose Register
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b) Symbol Table
c) Value map Set UNIT V INTERFACING
d) None of the mentioned
MICROCONTROLLER
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Answer: b
Explanation: The table where the assembler TOPIC 5.1 PROGRAMMING 8051
stores the variable names along with their
TIMERS - SERIAL PORT
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parallel to serial respectively? computer about the start and the end of the
a) timers data.
b) counters
c) registers 4. Which of the following signal control the
d) serial communication flow of data?
a) RTS
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Answer: c b) DTR
Explanation: Some registers like the parallel c) RTS & DTR
in serial out and serial in parallel out are used d) None of the mentioned
to convert serial data into parallel and vice
versa respectively. Answer: a
Explanation: RTS is a request to send control
2. What is the difference between UART and signal which is a control for the flow of data.
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USART communication? On the other hand DTR is a Data Terminal
a) they are the names of the same particular Ready control signal which tells about the
thing, just the difference of A and S is there current status of the DTE.
in it
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b) one uses asynchronous means of 5. Which of the following is the logic level
communication and the other uses understood by the micro-controller/micro-
synchronous means of communication processor?
a) TTL logic level
c) one uses asynchronous means of
communication and the other uses
asynchronous and synchronous means of
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c) None of the mentioned
communication d) TTL & RS232 logic level
d) one uses angular means of the
communication and the other uses linear Answer: a
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means of communication Explanation: TTL logic or the transistor
logic level is the logic that is understood by
Answer: c the micro-controllers/microprocessors.
Explanation: UART stands for Universal
Asynchronous receiver-transmitter and 6. What is a null modem connection?
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communication? Answer: c
a) it binds the data properly Explanation: In null modem connection the
b) it tells us about the start and stops of the RxD of one is the TxD for the other.
data to be transmitted or received
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c) it is used for error checking 7. Which of the following best states the
d) it is used for flow control reason that why baud rate is mentioned in
serial communication?
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mentioned in the serial communication so that
the transmission becomes easy and error free. c) easier than software
d) none of the mentioned
8. With what frequency UART operates(
where f denoted the crystal frequency )? Answer: a
a) f/12 Explanation: For both software and
b) f/32 hardware, the method of defining the
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c) f/144 interrupt service routine is the same.
d) f/384
2. While programming for any type of
Answer: d interrupt, the interrupt vector table is set
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Explanation: UART frequency is the crystal a) externally
frequency f/12 divided by 32, that comes out b) through a program
to be f/384. c) either externally or through the program
d) externally and through the program
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b) output data the main routine and the same should be
c) constants declared EXTRN in the procedure.
d) input data or constants
9. The technique to estimate the size of an
Answer: d executable program, before it is assembled
Explanation: Procedures require input data and linked is
or constants for their execution. Their data or a) memory location technique
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constants may be passed to the subroutine by b) global variable technique
the main program. c) stack
d) none
6. The technique that is used to pass the data
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or parameter to procedures in assembly Answer: d
language program is by using Explanation: There is no technique to
a) global declared variable estimate the size of an executable program
b) registers before it is assembled and linked.
c) stack
d) all of the mentioned
pa 10. To estimate the size of an executable
program before it is assembled and linked, the
Answer: d programming methodology concerned is by
Explanation: The techniques that are used to writing
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pass the data or parameter to procedures are a) programs with more than one segment for
by using global declared variable, registers of data and code
CPU, memory locations, stack, PUBLIC & b) programs with FAR subroutines each of
EXTRN. size up to 64KB
c) programs with more than one segment for
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d) it uses memory locations than one segment for data, code or stack or by
writing programs with FAR subroutines each
Answer: a of size 64KB, the size of an executable
Explanation: If a procedure is interactive, program can be estimated.
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controlled gains, motor speed controls and Answer: c
programmable gain amplifiers. Explanation: Stepper motor employs rotation
of its shaft in terms of steps, rather than
2. To save the DAC from negative transients continuous rotation as in case of AC or DC
the device connected between OUT1 and motors.
OUT2 of AD 7523 is
a) p-n junction diode 6. The internal schematic of a typical stepper
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b) Zener motor has
c) FET a) 1 winding
d) BJT (Bipolar Junction transistor) b) 2 windings
c) 3 windings
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Answer: b d) 4 windings
Explanation: Zener is connected between
OUT1 and OUT2 pins of AD7523 to save Answer: d
from negative transients. Explanation: The internal schematic of a
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3. An operational amplifier connected to the
typical stepper motor has 4 windings.
4. The DAC 0800 has a settling time of internal teeth on its rotor.
a) 100 milliseconds
b) 100 microseconds 8. A simple scheme for rotating the shaft of a
c) 50 milliseconds stepper motor is called
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are applied with the required voltage pulses, moment of the start of conversion is called
in a cyclic fashion. conversion delay.
9. The firing angles of thyristors are 2. The popular technique that is used in the
controlled by integration of ADC chips is
a) pulse generating circuits a) successive approximation
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b) relaxation oscillators b) dual slope integration
c) microprocessor c) successive approximation and dual slope
d) all of the mentioned integration
d) none
Answer: d
Explanation: In early days, the firing angles Answer: c
were controlled by a pulse generating circuits Explanation: Successive approximation and
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like relaxation oscillators and now, they are dual slope integration are the most popular
accurately fired using a microprocessor. techniques that are used in the integrated
ADC chips.
10. The Isolation transformers are generally
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used for 3. The procedure of algorithm for interfacing
a) protecting low power circuit ADC contain
b) isolation a) ensuring stability of analog input
c) protecting low power circuit and isolation b) issuing start of conversion pulse to ADC
d) none
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equivalent digital output
Answer: c d) all of the mentioned
Explanation: Any switching component of a
high power circuit may be sufficient to Answer: d
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damage the microprocessor system. So, to Explanation: The general algorithm for
protect the low power circuit isolation interfacing ADC contains ensuring the
transformers are used. They are also used if stability of analog input, issuing start of
isolation is necessary. conversion pulse to ADC, reading end of
conversion signal to mark the end of a
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1. The time taken by the ADC from the active 4. Which is the ADC among the following?
edge of SOC(start of conversion) pulse till the a) AD 7523
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100microseconds which is low as compared
to other converters. Answer: a
Explanation: A feedback loop is closed
6. The number of inputs that can be around the system to charge the autozero
connected at a time to an ADC that is capacitor to compensate for the offset
integrated with successive approximation is voltages in the buffer amplifier, integrator and
a) 4 comparator.
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b) 2
c) 8 10. In the signal integrate phase, the
d) 16 differential input voltage between IN
LO(input low) and IN HI(input high) pins is
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Answer: c integrated by the internal integrator for a
Explanation: As these converters internally fixed period of
have 3:8 analog multiplexer, at a time 8 a) 256 clock cycles
different analog inputs can be connected to
the chip.
pa b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
7. ADC 7109 integrated by Dual slope
integration technique is used for Answer: c
a) low cost option Explanation: The internal integrator needs
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b) slow practical applications 2048 clock cycles to integrate voltage
c) low complexity difference between input low and input high.
d) all of the mentioned
Answer: d Answer: c
Explanation: The output device transfers Explanation: More current should not be
data from the microprocessor to the external sourced or sinked from data lines while
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devices. reading to avoid loading.
3. The input and output operations are 7. To avoid loading during read operation, the
respectively similar to the operations, device used is
a) read, read a) latch
b) write, write b) flipflop
c) read, write c) buffer
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d) write, read d) tristate buffer
Answer: c Answer: d
Explanation: The input activity is similar to Explanation: A tristate buffer is used as an
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read operation and the output activity is input device to overcome loading.
similar to write operation.
8. The chip 74LS245 is
4. The operation, IOWR (active low) a) bidirectional buffer
performs
a) write operation on input data
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c) one that has 8 buffers
b) write operation on output data d) all of the mentioned
c) read operation on input data
d) read operation on output data Answer: d
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Explanation: The chip 74LS245 is a
Answer: b bidirectional buffer that contains 8 buffers
Explanation: IOWR (active low) operation and may be used as an 8-bit input port. But
means writing data to an output device and while using as an input device, only one
not an input device. direction is useful.
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large currents, the port lines must be buffered. Explanation: If DIR is 1, then the direction is
So, the latch is used as it acts as a good output from A(inputs) to B(outputs).
port.
10. In memory-mapped scheme, the devices
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and are addressed likewise. of 36º and a step angle of 9º, the number of
its phases must be
a) 4
TOPIC 5.5 STEPPER MOTOR b) 2
AND WAVEFORM c) 3
GENERATION d) 6
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1. A variable reluctance stepper motor is Answer: a
constructed of ______________ material with Explanation: Step angle is defined as =(Ns-
salient poles. Nr)/(Ns+Nr)*360.
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a) Paramagnetic
b) Ferromagnetic 5. The rotor of a stepper motor has no
c) Diamagnetic a) Windings
d) Non-magnetic pa b) Commutator
c) Brushes
Answer: b d) All of the mentioned
Explanation: A variable reluctance stepper
motor is the motor that has motion in steps Answer: d
with respect to increase in time and Explanation: The rotor is the rotatory part of
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constructed of ferromagnetic material with the motor of a stepper motor and has no
salient poles. windings, commutator and brushes.
a) 15º a) Mechanical
b) 30º b) Electrical
c) 45º c) Analogue
d) 60º d) Incremental
Answer: c Answer: d
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8. Which of the following phase switching
sequence represents half-step operation of a 1. A microcontroller at-least should consist
VR stepper motor ? of:
a) A, B, C,A…….. a) RAM, ROM, I/O ports and timers
b) A, C, B,A……. b) CPU, RAM, I/O ports and timers
c) AB, BC, CA, AB…….. c) CPU, RAM, ROM, I/O ports and timers
d) A, AB, B, BC…….. d) CPU, ROM, I/O ports and timers
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Answer: d Answer: c
Explanation: In the half step operation of a Explanation: A microcontroller at-least
Variable reluctance motor physical step consists of a processor as its CPU with RAM,
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resolution is multiplied by 2 and control ROM, I/O ports and timers. It may contain
signals appear to be digital rather than analog. some additional peripherals like ADC, PWM,
etc.
9. A stepper motor may be considered as a
____________ converter.
a) Dc to dc
pa 2. Unlike microprocessors, microcontrollers
make use of batteries because they have:
b) Ac to ac a) high power dissipation
c) Dc to ac b) low power consumption
d) Digital-to-analogue c) low voltage consumption
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d) low current consumption
Answer: d
Explanation: A stepper motor is a motor in Answer: b
which the motion is in steps and it is an Explanation: Micro Controllers are made by
increemental device and may be considered using the concept of VLSI technology. So
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as a digital to analog converter. here, CMOS based logic gates are coupled
together by this technique that consumes low
10. What is the step angle of a permanent- power.
magnet stepper motor having 8 stator poles
and 4 rotor poles? 3. What is the order decided by a processor or
the CPU of a controller to execute an
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a) 60º
b) 45º instruction?
c) 30º a) decode,fetch,execute
d) 15º b) execute,fetch,decode
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c) fetch,execute,decode
Answer: b d) fetch,decode,execute
Explanation: Step angle is defined as =(Ns-
Answer: d
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b) ALU transfer and memory accesses instructions.
c) Control Bus RISC means Reduced Instruction Set
d) Address Bus Computer because here a microcontroller has
an instruction set that supports fewer
Answer: b addressing modes for the arithmetic and
Explanation: If we say a microcontroller is logical instructions and for data transfer
8-bit it means that it is capable of processing instructions.
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8-bit data at a time. Data processing is the
task of ALU and if ALU is able to process 8- 7. Give the names of the buses present in a
bit data then the data bus should be 8-bit controller for transferring data from one place
wide. In most books it tells that size of data to another?
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bus but to be precise it is the size of ALU a) data bus, address bus
because in Harvard Architecture there are two b) data bus
sets of data bus which can be of same size but
pa c) data bus, address bus, control bus
it is not mandatory. d) address bus
operation).
Answer: a
Explanation: As the bus width increases, the 8. What is the file extension that is loaded in
number of bits carried by bus at a time a microcontroller for executing any
increases as a result of which the total instruction?
performance and computer capability a) .doc
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increases. b) .c
c) .txt
6. Abbreviate CISC and RISC. d) .hex
a) Complete Instruction Set Computer,
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Explanation: For choosing the right d) because they consume low power
microcontroller for our product we must
consider its speed so that the instructions may Answer: b
be executed in the least possible time. It also Explanation: Microcontrollers are designed
depends on the availability so that the to perform dedicated tasks. While designing
particular product may be available in our general purpose computers end use is not
neighboring regions or market in our need. It known to designers.
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also depends on the compatibility with the
product so that the best results may be
obtained.
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