Data Sheet: Device Specification

INTEGRATED CIRCUITS
DATASPECIFICATION
DEVICE SHEET
UOCIII series
Versatile signal processor for low-
and mid-range TV applications
Preliminary specification 2003 Nov 11
File under18Integrated Circuits, <Handbook>
Version: Previous date: 2003 Oct 09
CONFIDENTIAL
Philips Semiconductors Preliminary specification
Versatile signal processor for low- and

UOCIII series
mid-range TV applications
GENERAL DESCRIPTION
The UOCIII series combines the functions of a Video
Signal Processor (VSP) together with a FLASH embedded
TEXT/Control/Graphics µ-Controller (TCG µ-Controller)
and US Closed Caption decoder. In addition the following
functions can be added:
• Adaptive digital (4H/2H) PAL/NTSC combfilter
• Teletext decoder with 10 page text memory
• Multi-standard stereo decoder FEATURES
• BTSC stereo decoder Analogue Video Processing (all versions)
• Digital sound processing circuit • Multi-standard vision IF circuit with alignment-free PLL
• Digital video processing circuit demodulator
The UOCIII series consists of the following 3 basic • Internal (switchable) time-constant for the IF-AGC circuit
concepts: • Switchable group delay correction and sound trap (with
• Stereo versions. These versions contain the TV switchable centre frequency) for the demodulated CVBS
processor with a stereo audio selector, the TCG signal
µ-Controller, the multi-standard stereo or BTSC • DVB/VSB IF circuit for preprocessing of digital TV
decoder, the digital sound processing circuit and the signals.
digital video processing circuit. Options are the adaptive
• Video switch with 3 external CVBS inputs and a CVBS
digital PAL/NTSC comb filter and a teletext decoder with
output. All CVBS inputs can be used as Y-input for Y/C
10 page text memory.
signals. However, only 2 Y/C sources can be selected
• AV stereo versions. These versions contain the TV because the circuit has 2 chroma inputs. It is possible to
processor with stereo audio selector and the TCG add an additional CVBS(Y)/C input (CVBS/YX and CX)
µ-Controller. Options are the digital sound processing when the YUV interface and the RGB/YPRPB input are
circuit, the digital video processing circuit, the adaptive not needed.
digital PAL/NTSC comb filter and a teletext decoder with
• Automatic Y/C signal detector
a 10 page text memory.
• Adaptive digital (4H/2H) PAL/NTSC comb filter for
• Mono sound versions. These versions contain the TV
optimum separation of the luminance and the
processor with a selector for mono audio signals and the
chrominance signal.
TCG µ-Controller. Options are the adaptive digital
PAL/NTSC combfilter and a teletext decoder with 10 • Integrated luminance delay line with adjustable delay
page text memory. time
• Picture improvement features with peaking (with
The most important features of the complete IC series are
switchable centre frequency, depeaking, variable
given in the following feature lists. The exact feature
positive/negative peak ratio, variable pre-/overshoot
content of the various ICs is given in Table 1 on page 7.
ratio and video dependent coring), dynamic skin tone
The ICs are mounted in a QFP-128 envelope(1) and can be control, gamma control and blue- and black stretching.
used in economy television receivers with 90° and 110° All features are available for CVBS, Y/C and
picture tubes. They have supply voltages of 5V, 3.3V. Also RGB/YPBPR signals.
an 1.8V supply is needed, but this can be simply derived • Switchable DC transfer ratio for the luminance signal
by adding an emitter follower at a reference voltage from
the device. • Only one reference (24.576 MHz) crystal required for
the TCG µ-Controller, digital sound processor, Teletext-
UOCIII is supported by a comprehensive Global TV and the colour decoder
Software Development kit to enable easy programming
• Multi-standard colour decoder with automatic search
and fast time-to-market (see also Chapter “LICENSE
system and various “forced mode” possibilities
INFORMATION” on page 6.
• Internal base-band delay line
(1) Both standard and “face down” versions of the QFP128
0.8mm pitch package are available.
2003 Nov 11 2
CONFIDENTIAL

UOCIII series
• Indication of the Signal-to-Noise ratio of the incoming Sound Demodulation (all versions)
CVBS signal
• Separate SIF (Sound IF) input for single reference QSS
• Linear RGB/YPBPR input with fast insertion. (Quasi Split Sound) demodulation.
• YUV interface. When this feature is not required some • AM demodulator without extra reference circuit
pins can be used as additional RGB/YPBPR input. It is
• The mono intercarrier sound circuit has a selective
also possible to use these pins for additional CVBS (or
FM-PLL demodulator which can be switched to the
Y/C) input (CVBS/YX and CX).
different FM sound frequencies (4.5/5.5/6.0/6.5 MHz).
• Tint control for external RGB/YPBPR signals The quality of this system is such that the external
• Scan Velocity Modulation output. The SVM circuit is band-pass filters can be omitted. In the stereo versions
active for all the incoming CVBS, Y/C and RGB/YPBPR of UOCIII the use of this demodulator is optional for
signals. The SVM function can also be used during the special applications. Normally the FM demodulators of
display of teletext pages. the stereo demodulator/decoder part are used (see
below).
• RGB control circuit with ‘Continuous Cathode
Calibration’, white point and black level off-set • The FM-PLL demodulator can be set to centre
adjustment so that the colour temperature of the dark frequencies of 4.72/5.74 MHz so that a second sound
and the light parts of the screen can be chosen channel can be demodulated. In such an application it is
independently. necessary that an external bandpass filter is inserted.
• Contrast reduction possibility during mixed-mode of • The vision IF and mono intercarrier sound circuit can be
OSD and Text signals used for the demodulation of FM radio signals. With an
external FM tuner also signals with an IF frequency of
• Adjustable ‘wide blanking’ of the RGB outputs
10.7 MHz can be demodulated.
• Horizontal synchronization with two control loops and
alignment-free horizontal oscillator • Switch to select between 2nd SIF from QSS
demodulation or external FM (SSIF)
• Vertical count-down circuit
• Vertical driver optimized for DC-coupled vertical output Audio Interfaces and switching (stereo versions with
stages Audio DSP)
• Horizontal and vertical geometry processing with • Audio switch circuit with 4 stereo inputs, a stereo output
horizontal parallelogram and bow correction and for SCART/CINCH, 1 stereo output for HEADPHONE.
horizontal and vertical zoom The headphone channel has an analogue volume
• Low-power start-up of the horizontal drive circuit control circuit for the L and R channel. Finally 1 stereo
SPEAKER output with digital controls.
Analogue video processing (stereo versions) • AVL (Automatic Volume Levelling) circuit for the
• The low-pass filtered ‘mixed down’ I signal is available headphone channel.
via a single ended or balanced output stage. • Digital input crossbar switch for all digital signal sources
and destinations
Analogue video processing (mono versions) • Digital output crossbar for exchange of channel
• The low-pass filtered ‘mixed down’ I signal is available processing functionality
via a single ended output stage • Digital audio input interface (stereo I2S input interface)
• Digital audio output interface (stereo I2S output
Digital Video Processing (some versions)
interface)
• Double Window mode applications. It is possible to
display a video and a text window or 2 text windows in Audio interfaces and switching (AV stereo versions
parallel. without Audio DSP)
• Linear and non-linear horizontal scaling of the video • Audio switch circuit with 4 stereo inputs, a stereo output
signal to be displayed. for SCART/CINCH and a stereo SPEAKER output with
analogue volume control.
• Analogue mono AVL circuit at left audio channel
2003 Nov 11 3
CONFIDENTIAL

UOCIII series
Audio interfaces and switching (mono versions) Volume and tone control for loudspeakers (stereo
versions with Audio DSP)
• Audio switch circuit with 4 external audio (mono) inputs
and a volume controlled output • Automatic Volume Level (AVL) control
• AVL circuit • Smooth volume control
• Master volume control
Stereo Demodulator and Decoder (full stereo
• Soft-mute
versions)
• Loudness
• Demodulator and Decoder Easy Programming (DDEP)
• Bass, Treble
• Auto standard detection (ASD)
• Dynamic Bass Boost (DBB) (2)
• Static Standard Selection (SSS)
• Dynamic Virtual Bass (DVB) (3)
• DQPSK demodulation for different standards,
simultaneously with 1-channel FM demodulation • BBE® Sound processing (4)
• NICAM decoding (B/G, I, D/K and L standard) • Graphic equaliser
• Two-carrier multistandard FM demodulation (B/G, D/K • Processed or non processed subwoofer

and M standard) • Programmable beeper
• Decoding for three analog multi-channel systems (A2,
A2+ and A2*) and satellite sound Reflection and delay for loudspeaker channels
(stereo versions with Audio DSP)
• Adaptive de-emphasis for satellite FM
• Dolby® Pro Logic® Delay (1)
• Optional AM demodulation for system L, simultaneously
with NICAM • Pseudo hall/matrix function
• Identification A2 systems (B/G, D/K and M standard)
Psycho acoustic spatial algorithms, downmix and
with different identification time constants
split in loudspeaker channels (stereo versions with
• FM pilot carrier present detector Audio DSP)
• Monitor selection for FM/AM DC values and signals,
• Extended Pseudo Stereo (EPS) (5)
with peak and quasi peak detection option
• Extended Spatial Stereo (ESS) (6)
• BTSC MPX decoder
• Virtual Dolby® Surround (VDS 422,423) (1)
• SAP decoder
• SRS 3D and SRS TruSurround® (4)
• dbx® noise reduction (4)
• Japan (EIAJ) decoder RDS/RBDS
• FM radio decoder
• Demodulation of the European Radio Data system
• Soft-mute for DEMDEC outputs DEC, MONO and SAP (RDS) or the USA Radio Broadcast Data System
• FM overmodulation adaptation option to avoid clipping (RBDS) signal
and distortion • RDS and RBDS block detection
• Error detection and correction
Audio Multi Channel Decoder (stereo versions with
Audio DSP) • Fast block synchronisation
• Synchronisation control (flywheel)
• Dolby® Pro Logic® (DPL) (1)
• Mode control for RDS/RBDS processing
• Five channel processing for Main Left and Right,
Subwoofer, Centre and Surround. To exploit this feature • Different RDS/RBDS block information output modes
an external DAC is required. (2) Also referred to as “Dynamic UltraBass”
(3) Also referred to as “Dynamic Bass Enhancement”
(4) For the use of these products a licence is required. More
details are given in the chapter “LICENSE INFORMATION” on
page 6
(5) Also referred to as “I-Mono” or “Incredible Mono”
(1) Dolby is a trademark of Dolby Laboratories (6) Also referred to as “I-Stereo” or “Incredible Stereo”
2003 Nov 11 4
CONFIDENTIAL

UOCIII series
µ-Controller Display
• 80C51 µ-controller core standard instruction set and • Teletext and Enhanced OSD modes
timing • Features of level 1.5 WST and US Close Caption
• 0.4883 µs machine cycle • 50Hz/60Hz display timing modes
• maximum of 256k x 8-bit flash programmable ROM • Two page operation for 16:9 screens
• maximum of 8k x 8-bit Auxiliary RAM • Serial and Parallel Display Attributes
• 12-level Interrupt controller for individual enable/disable • Single/Double/Quadruple Width and Height for
with two level priority characters
• Two 16-bit Timer/Counter registers • Smoothing capability of both Double Size, Double Width
• One 24-bit Timer (16-bit timer with 8-bit Pre-scaler) & Double Height characters
• WatchDog timer • Scrolling of display region
• Auxiliary RAM page pointer • Variable flash rate controlled by software
• 16-bit Data pointer • Soft colours using CLUT with 4096 colour palette
• Stand-by, Idle and Power Down modes • Globally selectable scan lines per row (9/10/13/16/) and
• 24 general-purpose I/O pins character matrix [12x9, 12x13, 12x16, 16x18, (VxH)]
• 14 bits PWM for Voltage Synthesis Tuning • Fringing (Shadow) selectable from N-S-E-W direction
• 8-bit A/D converter with 4 multiplexed inputs • Fringe colour selectable
• 5 PWM (6-bits) outputs for analogue control functions • Contrast reduction of defined area
• Remote Control Pre-processor (RCP) • Cursor
• Universal Asynchronous Receiver Transmitter (UART) • Special Graphics Characters with two planes, allowing
four colours per character
Data Capture • 64 software redefinable On-Screen display characters
• Text memory up to 10 pages • 4 WST Character sets (G0/G2) in single device (e.g.
Latin, Cyrillic, Greek, Arabic)
• Inventory of transmitted Teletext pages stored in the
Transmitted Page Table (TPT) and Subtitle Page Table • G1 Mosaic graphics, Limited G3 Line drawing
(SPT) characters
• Data Capture for US Closed Caption • WST Character sets and Closed Caption Character set
in single device
• Data Capture for 525/625 line WST, VPS (PDC system
A) and 625 line Wide Screen Signalling (WSS) bit • SVM for Text
decoding
• Automatic selection between 525 WST/625 WST
• Automatic selection between 625 WST/VPS on line 16
of VBI
• Real-time capture and decoding for WST Teletext in
Hardware, to enable optimized µ-processor throughput
• Automatic detection of FASTEXT transmission
• Real-time packet 26 engine in Hardware for processing
accented, G2 and G3 characters
• Signal quality detector for video and WST/VPS data
types
• Comprehensive teletext language coverage
• Vertical Blanking Interval (VBI) data capture of WST
data
2003 Nov 11 5
CONFIDENTIAL

UOCIII series
LICENSE INFORMATION
dbx
dbx is a registered trademark of Carillon Electronics Corp. A license is required for the use of this product. For further
information, please contact THAT Corporation, 45 Summer street, Milford, Massachusetts 01757-1656, USA.
Tel: 1-508-478-9200, FAX: 1-508-478-0990
Dolby
“Dolby”, “Pro Logic” and the double-D symbol are trademarks of Dolby Laboratories, San Francisco, USA, products are
available to licensees of Dolby Laboratories Licensing Corporation, 100 Potrero Avenue, San Francisco, CA, 94103,
USA,
Tel: 1-415-558-0200, Fax: 1-415-863-1373
Supply of this Implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any
other Industrial or Intellectual Property Right of Dolby Laboratories, to use this Implementation in any finished end-user
or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.
BBE
BBE is a registered trademark of BBE Sound, Inc., 5381 Production Drive, Huntington Beach, California 92649, USA.
The use of BBE needs licensing from BBE Sound, Inc.
Tel: 1-714-897-6766, Fax: 1-714-895-6728
The SRS TruSurround technology rights incorporated in the TDA120xxH are owned by SRS Labs, a U.S. Corporation
and licensed to Philips Semiconductors B.V. Purchaser of TDA120xxH must sign a license for use of the chip and display
of the SRS Labs trademarks. Any products incorporating the TDA120xxH must be sent to SRS Labs for review. SRS
and TruSurround are protected under US and foreign patents issued and/or pending. TruSurround, SRS and (O) symbol
are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the chip
TDA120xxH, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized
recordings made with any SRS technology. SRS Labs requires all set makers to comply with all rules and regulations as
outlined in the SRS Trademark Usage Manual separately provided.
Philips
“Dynamic Ultra BassTM”, “Dynamic Bass Enhancement”, “I-Mono” and “I-Stereo” are denominators for Philips patented
technologies. The use of the IC does not imply any copyrights nor the right to use the same denominators but instead
generic ones such as listed below.
Generic name/ Philips name
• Dynamic Virtual Bass (DVB)/Dynamic UltraBass
• Dynamic Bass Boost (DBB)/Dynamic Bass Enhancement
• Extended Pseudo Stereo (EPS)/I-Mono
• Extended Spatial Stereo (ESSI)/I-Stereo
GTV
Delivery and use of the GTV Software Development Kit requires a separate License sold by Philips Semiconductors B.V.
Please contact your nearest Philips Semiconductors sales office for further details.
2003 Nov 11 6
CONFIDENTIAL
2003 Nov 11 OVERVIEW OF THE VARIOUS VERSIONS
Philips Semiconductors
Table 1 Overview of types
COMB FILTER
COLOUR DECODER
STEREO FM RADIO
MONO FM RADIO
RDS/RBDS
dbx®
Dolby® ProLogic®
Virtual Dolby® (VDS)
SRS® 3D Stereo
SRS® TruSurround
BBETM
DW / PANORAMA
ROM SIZE (k)
AUX RAM SIZE (k)
DISPLAY RAM (k)
DRCS RAM (k)

NUMBER OF
SOUND SYSTEM TELETEXT
PAGES
TYPE NUMBER(1)
STEREO
AUDIO
DECO- MONO 0 10
DSP
DER
TDA11000H/H1 √ √ NTSC √ 128 4 1.25 2.25

TDA11001H/H1 √ √ √ NTSC √ 128 4 1.25 2.25
TDA11010H/H1 √ √ MULTI √ 128 4 1.25 2.25
CONFIDENTIAL
TDA11011H/H1 √ √ √ MULTI √ 128 4 1.25 2.25

TDA11020H/H1 √ √ MULTI √ 128 4 10 2.25
TDA11021H/H1 √ √ √ MULTI √ 128 4 10 2.25
TDA12000H/H1(2) BTSC(3) √ √ NTSC √ √ 128/256 8 1.25 2.25
TDA12001H/H1(2) BTSC(3) √ √ √ NTSC √ √ 128/256 8 1.25 2.25
√ √ √ √ √ √ √
7
TDA12006H/H1 BTSC(3) NTSC 128/256 8 1.25 2.25

TDA12007H/H1 BTSC(3) √ √ √ NTSC √ √ √ √ √ 128/256 8 1.25 2.25
TDA12008H/H1 BTSC(3) √ √ NTSC √ √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25
TDA12009H/H1 BTSC(3) √ √ √ NTSC √ √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25
TDA12010H/H1(2) MULTI √ √ MULTI √ √ 128/256 8 1.25 2.25
TDA12011H/H1(2) MULTI √ √ √ MULTI √ √ 128/256 8 1.25 2.25
TDA12016H/H1 MULTI √ √ MULTI √ √ √ √ √ 128/256 8 1.25 2.25
TDA12017H/H1 MULTI √ √ √ MULTI √ √ √ √ √ 128/256 8 1.25 2.25
TDA12018H/H1 MULTI √ √ MULTI √ √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25
TDA12019H/H1 MULTI √ √ √ MULTI √ √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25
√ √ √ √
Preliminary specification
TDA12020H/H1(2) MULTI MULTI 128/256 8 10 2.25
UOCIII series
TDA12021H/H1(2) MULTI √ √ √ MULTI √ √ 128/256 8 10 2.25
TDA12026H/H1 MULTI √ √ MULTI √ √ √ √ √ 128/256 8 10 2.25
TDA12027H/H1 MULTI √ √ √ MULTI √ √ √ √ √ 128/256 8 10 2.25
TDA12028H/H1 MULTI √ √ MULTI √ √ √ √ √ √ √ √ √ 128/256 8 10 2.25
TDA12029H/H1 MULTI √ √ √ MULTI √ √ √ √ √ √ √ √ √ 128/256 8 10 2.25
2003 Nov 11
COMB FILTER
COLOUR DECODER
STEREO FM RADIO
MONO FM RADIO
RDS/RBDS
dbx®
Dolby® ProLogic®
SRS® 3D Stereo
SRS® TruSurround
BBETM
DW / PANORAMA
ROM SIZE (k)
AUX RAM SIZE (k)
DISPLAY RAM (k)
DRCS RAM (k)

NUMBER OF
SOUND SYSTEM TELETEXT
PAGES
TYPE NUMBER(1)
STEREO
AUDIO
DECO- MONO 0 10
DSP
DER
TDA12060H/H1 √ MULTI √ 128/256 8 1.25 2.25

TDA12061H/H1 √ √ MULTI √ 128/256 8 1.25 2.25
TDA12062H/H1(2) √ MULTI √ 128/256 8 1.25 2.25
TDA12063H/H1(2) √ √ MULTI √ 128/256 8 1.25 2.25
TDA12066H/H1 √ √ MULTI √ √ √ √ √ 128/256 8 1.25 2.25
CONFIDENTIAL
TDA12067H/H1 √ √ √ MULTI √ √ √ √ √ 128/256 8 1.25 2.25

TDA12068H/H1 √ √ MULTI √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25
TDA12069H/H1 √ √ √ MULTI √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25
TDA12070H/H1 √ MULTI √ 128/256 8 10 2.25
TDA12071H/H1 √ √ MULTI √ 128/256 8 10 2.25
√ √
8
TDA12072H/H1(2) MULTI 128/256 8 10 2.25

TDA12073H/H1(2) √ √ MULTI √ 128/256 8 10 2.25
TDA12076H/H1 √ √ MULTI √ √ √ √ √ 128/256 8 10 2.25
TDA12077H/H1 √ √ √ MULTI √ √ √ √ √ 128/256 8 10 2.25
TDA12078H/H1 √ √ MULTI √ √ √ √ √ √ √ √ 128/256 8 10 2.25
TDA12079H/H1 √ √ √ MULTI √ √ √ √ √ √ √ √ 128/256 8 10 2.25
Note
1. The “standard” version is indicated with “H” and the “facedown” version with “H1”
2. For these versions the feature content can be found from the type number. More details are given in the next Section.
3. When the BTSC demodulation is active the EIAJ demodulation is also activated.
UOCIII series

UOCIII series
Type Number Definition and Feature Indication

The complete type number of these versions is given below.
TDA12000H1/N1VXY0AA
The explanation of the various parts of the type number is given below:
• The first 8 characters indicate the type number, the last 2 characters vary depending on the version.
• The next 1 or 2 characters indicate the envelope. The normal QFP128 version is indicated with “H” and the “face-down
version” with “H1”.
• The first 3 characters after the slash (/) indicate the IC version.
• The characters “X” and “Y” give an indication of the Feature Content. More information is given in the Tables 2 and 3.
• The last 3 characters give an indication of the ROM code.
Table 2 Feature Indication, first character (X) Table 3 Feature Indication, second character (Y)
SECOND INDICATION (Y)
FIRST INDICATION (X)

ROM size / 0 = 128K
Dolby® ProLogic®
SRS® TruSurround
DW / PANORAMA
SRS® 3D Stereo
dbx®
BBETM
0 0 0 0 0
1 0 0 0 1 0 0 0 0 0
2 0 0 1 0 1 0 0 0 1
3 0 0 1 1 2 0 0 1 0
4 0 1 0 0 3 0 0 1 1
5 0 1 0 1 4 0 1 0 0
6 0 1 1 0 5 0 1 0 1
7 0 1 1 1 6 0 1 1 0
8 1 0 0 0 7 0 1 1 1
9 1 0 0 1 8 1 0 0 0
A 1 0 1 0 9 1 0 0 1
B 1 0 1 1 A 1 0 1 0
C 1 1 0 0 B 1 0 1 1
D 1 1 0 1 C 1 1 0 0
E 1 1 1 0 D 1 1 0 1
F 1 1 1 1 E 1 1 1 0
F 1 1 1 1
2003 Nov 11 9
CONFIDENTIAL

UOCIII series
QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Supply
VP analogue supply voltage TV processor 4.7 5.0 5.3 V
IP supply current (5.0 V) − 190 − mA
VDDA digital supply TV processor / analogue supply periphery 3.0 3.3 3.6 V
IDDA supply current (3.3 V) − 36 − mA
VDDC/P digital supply to core/periphery 1.65 1.8 1.95 V
IDDC/P supply current (1.8 V) − 440 − mA
VPAudio (1) audio supply voltage 4.7 8.0 8.4 V
IPAudio (1) supply current (5.0/8.0 V) − 0.5 − mA
Ptot total power dissipation − 1.87 − W
Input voltages
ViVIFrms) video IF amplifier sensitivity (RMS value) − 75 150 µV
ViSIF(rms) QSS sound IF amplifier sensitivity (RMS value) − 45 tbf dBµV
ViSSIF(rms) sound IF amplifier sensitivity (RMS value) − 1.0 − mV
ViAUDIO(rms) external audio input (RMS value) − 1.0 1.3 V
ViCVBS(p-p) external CVBS/Y input (peak-to-peak value) − 1.0 1.4 V
ViCHROMA(p-p) external chroma input voltage (burst amplitude) − 0.3 1.0 V
(peak-to-peak value)
ViRGB(p-p) RGB inputs (peak-to-peak value) − 0.7 0.8 V
ViY(p-p) luminance input signal (peak-to-peak value) − 1.4 / 1.0 − V
ViU(p-p) / U / PB input signal (peak-to-peak value); note 2 − −1.33 / − V
ViPB(p-p) +0.7
ViV(p-p) / V / PR input signal (peak-to-peak value); note 2 − −1.05 / − V
ViPR(p-p) +0.7
Output signals
Vo(IFVO)(p-p) demodulated CVBS output (peak-to-peak value) − 2.0 − V
Vo(QSSO)(rms) sound IF intercarrier output (RMS value) − 100 − mV
Vo(AMOUT)(rms) demodulated AM sound output (RMS value) − 250 − mV
Vo(AUDIO)(rms) (1) non-controlled audio output signals (RMS value) 1.0 − − V
Vo(CVBSO)(p-p) selected CVBS output (peak-to-peak value) − 2.0 − V
Io(AGCOUT) tuner AGC output current range 0 − 1 mA
VoRGB(p-p) RGB output signal amplitudes (peak-to-peak value) − 1.2 − V
IoHOUT horizontal output current 10 − − mA
IoVERT vertical output current (peak-to-peak value) − 1 − mA
IoEWD EW drive output current − − 1.2 mA
Note
1. The supply voltage for the analogue audio part of the IC can be 5V or 8V. For a supply voltage of 5V the maximum
signal amplitudes at in and outputs are 1Vrms. For a supply voltage of 8V the maximum output signal amplitude is
2 Vrms.
2. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation.
2003 Nov 11 10
CONFIDENTIAL
SSIF
QSSO/AMOUT
SCART/CINCH IN/OUT LS-OUT HP-OUT
I2S
2003 Nov 11
REFO L R L R
SWITCH AUDIO CONTROL BLOCK DIAGRAMS

A/D CONVERTER
AUDIO SELECT
SIFIN/DVBIN QSS SOUND IF SOUND PLL ALL-STANDARD VOLUME
AGC STEREO ADC/DAC TREBBLE/BASS
QSS MIXER DEEMPHASIS AM FEATURES
DVBO/IFVO/ DECODER
AM DEMODULATOR DACs I/Os
FMRO
DVBO/FMRO RDS
AGCOUT
VISION IF/AGC/AFC
PLL DEMOD. PAL/SECAM/NTSC BASE-BAND µ-PROCESSOR AND TELETEXT DECODER

VIFIN
SOUND TRAP
DECODER DELAY LINE DIGITAL SIGNAL PROCESSING FEATURES
GROUP DELAY
VIDEO AMP.
IFVO/SVO/ REF
CVBSI SCAVEM
YSYNC ON TEXT BL R G B CR
CVBS2/Y2 C RO
CON.
DIGITAL PEAKING RGB CONTROL
11
CVBS3/Y3 GO
YUV IN/OUT
VIDEO SWITCH 2H/4H SCAN VELOCITY OSD/TEXT INSERT
C2/C3 VIDEO IDENT. CONTR/BRIGHTN BO
CVBS4/Y4 COMB FILTER MODULATION
VIDEO FILTERS BRI CCC
C4 Y DELAY ADJ. U/V DELAY BCLIN
WHITE-P. ADJ.
CVBSO/ Y
BLKIN
CONFIDENTIAL
PIP YUV
SVM
H/V SYNC SEP. H/V SKIN TONE RGB MATRIX
H-OSC. + PLL VERTICAL
RGB/YPRPB INSERT BLUE STRETCH
2nd LOOP & EAST-WEST U/V TINT
BLACK STRETCH
H-SHIFT YUV INTERFACE SATURATION
H-DRIVE GEOMETRY GAMMA CONTROL
SAT
Vo Uo Yo Yi Ui Vi
V-DRIVE EHTO BL G/Y
EWD R/PR B/PB

HOUT
B/PB
SWO1 BL G/Y R/PR
(CVBSx/Yx) (Cx)
UOCIII series
Fig.1 Block diagram of the “Stereo” TV processor

SSIF
QSSO/AMOUT
SCART/CINCH IN/OUT LS-OUT HP-OUT
I2S
2003 Nov 11
REFO L R L R
SWITCH AUDIO CONTROL

SOUND PLL AUDIO SELECT
SIFIN/DVBIN QSS SOUND IF VOLUME
AGC ADC/DAC TREBBLE/BASS
DEEMPHASIS
QSS MIXER AM FEATURES
DVBO/IFVO/ AM DEMODULATOR DACs I/Os
FMRO
DVBO/FMRO RDS
AGCOUT
VISION IF/AGC/AFC
VIFIN
SOUND TRAP
GROUP DELAY
VIDEO AMP.
IFVO/SVO/ REF
CVBSI SCAVEM
YSYNC ON TEXT
BL R G B CR
CVBS2/Y2 C RO
CON.
12
DIGITAL RGB CONTROL
CVBS3/Y3 PEAKING GO
VIDEO SWITCH OSD/TEXT INSERT
YUV IN/OUT
C2/C3 2H/4H SCAN VELOCITY
VIDEO IDENT. CONTR/BRIGHTN BO
COMB FILTER
CVBS4/Y4 VIDEO FILTERS MODULATION BRI CCC
Y DELAY ADJ.
CONFIDENTIAL
C4 U/V DELAY WHITE-P. ADJ. BCLIN
Y
CVBSO/ BLKIN
PIP
SVM
H/V SYNC SEP. H/V
RGB/YPRPB INSERT SKIN TONE RGB MATRIX
U/V TINT BLUE STRETCH
2nd LOOP & EAST-WEST YUV INTERFACE
BLACK STRETCH
H-SHIFT SATURATION
SAT
Vo Uo Yo Yi Vi Ui
V-DRIVE EHTO BL
G/Y
R/PR B/PB
HOUT EWD B/PB
SWO1 BL G/Y R/PR
(CVBSx/Yx) (Cx)
Fig.2 Block diagram of the “AV-stereo” TV processor with audio DSP

UOCIII series
SSIF
QSSO/AMOUT
SCART/CINCH IN/OUT LS-OUT
2003 Nov 11
REFO R
L
SWITCH
SIFIN/DVBIN QSS SOUND IF SOUND PLL
AGC AUDIO SELECT VOLUME CONTROL
DEEMPHASIS
QSS MIXER AM
DVBO/IFVO/ AM DEMODULATOR I/Os
FMRO
DVBO/FMRO RDS
AGCOUT
VISION IF/AGC/AFC
VIFIN
SOUND TRAP
GROUP DELAY
VIDEO AMP.
IFVO/SVO/ REF
CVBSI SCAVEM
YSYNC ON TEXT
BL R G B CR
CVBS2/Y2 C RO
CON.
13
DIGITAL RGB CONTROL
CVBS3/Y3 PEAKING GO
YUV IN/OUT
VIDEO IDENT. CONTR/BRIGHTN BO
CVBS4/Y4 COMB FILTER MODULATION BRI CCC
VIDEO FILTERS
Y DELAY ADJ.
CONFIDENTIAL
C4 U/V DELAY WHITE-P. ADJ. BCLIN
Y
CVBSO/ BLKIN
PIP
SVM
H/V SYNC SEP. H/V
RGB/YPRPB INSERT SKIN TONE RGB MATRIX
U/V TINT BLUE STRETCH
2nd LOOP & EAST-WEST YUV INTERFACE
BLACK STRETCH
H-SHIFT SATURATION
SAT
Vo Uo Yo Yi Vi Ui
V-DRIVE EHTO BL
G/Y
R/PR B/PB
HOUT EWD B/PB
SWO1 BL G/Y R/PR
(CVBSx/Yx) (Cx)
Fig.3 Block diagram of the “AV-stereo” TV processor without audio DSP

UOCIII series
(SSIF)
2003 Nov 11
I/Os
AUDEEM
AUDIO2
AUDIO3
AUDIO4
AUDIO5
(AVL)
AUDOUT/AMOUT
QSSO/AMOUT
SWITCH SOUND PLL

µ-PROCESSOR AND TELETEXT DECODER
QSS SOUND IF DEEMPHASIS
SIFIN/DVBIN AGC AUDIO SWITCH
QSS MIXER AVL DIGITAL SIGNAL PROCESSING FEATURES
AM DEMODULATOR VOLUME CONTROL
DVBO/IFVO
FMRO
SCAVEM
AGCOUT RDS ON TEXT
VISION IF/AGC/AFC
REF
PLL DEMOD. PAL/SECAM/NTSC
DVB MIXER REF
VIFIN
GROUP DELAY
DECODER SVM
SOUND TRAP
IFVO/SVO/
YUV IN/OUT
CVBSI
COR R G B BL
14
CVBS2/Y2 RO
DIGITAL CONTR/BRIGHTN
CVBS3/Y3 BASE-BAND PEAKING GO
CVBS4/Y4 VIDEO IDENT. DELAY LINE BLUE STRETCH BO
COMB FILTER
CONFIDENTIAL
MODULATION
CCC
C4 VIDEO FILTERS Y DELAY ADJ. U/V DELAY WHITE-P. ADJ. BCLIN
YSYNC BLKIN
YUV
CVBSO/PIP H/V SYNC SEP. Y
VERTICAL + EW SKIN TONE
H-OSC. + PLL U/V TINT
U/V RGB/YUV/YPRPB INSERT
2nd LOOP GEOMETRY SATURATION
H-SHIFT YUV INTERFACE BLACK STRETCH
AND DRIVE
H-DRIVE V
GAMMA CONTROL
VO UO YO YI UI VI
V-DRIVE (EWD) EHTO

(REFO)
HOUT BL G/Y
R/PR B/PB
SWO1 BL G/Y B/PB R/PR
(CVBS/Yx) (Cx)
UOCIII series
Fig. 4 Block diagram of the “Mono” TV processor

2003 Nov 11 PINNING OF THE VARIOUS VERSIONS
“STANDARD” “FACE DOWN”
VERSION VERSION
NO AUDIO DSP
NO AUDIO DSP
AV STEREO
AV STEREO
AV STEREO
AV STEREO
STEREO +
STEREO +
SYMBOL DESCRIPTION
MONO
MONO
VSSP2 1 1 1 128 128 128 ground
VSSC4 2 2 2 127 127 127 ground
VDDC4 3 3 3 126 126 126 digital supply to SDACs (1.8V)
CONFIDENTIAL
VDDA3(3.3V) 4 4 4 125 125 125 supply (3.3 V)

VREF_POS_LSL 5 − − 124 − − positive reference voltage SDAC (3.3 V)
VREF_NEG_LSL+HPL 6 − − 123 − − negative reference voltage SDAC (0 V)
VREF_POS_LSR+HPR 7 − − 122 − − positive reference voltage SDAC (3.3 V)
VREF_NEG_HPL+HPR 8 − − 121 − − negative reference voltage SDAC (0 V)
15
VREF_POS_HPR 9 − − 120 − − positive reference voltage SDAC (3.3 V)

XTALIN 10 10 10 119 119 119 crystal oscillator input
XTALOUT 11 11 11 118 118 118 crystal oscillator output
VSSA1 12 12 12 117 117 117 ground
VGUARD/SWIO 13 13 13 116 116 116 V-guard input / I/O switch (e.g. 4 mA current sinking capability for
direct drive of LEDs)
DECDIG 14 14 14 115 115 115 decoupling digital supply
VP1 15 15 15 114 114 114 1st supply voltage TV-processor (+5 V)
PH2LF 16 16 16 113 113 113 phase-2 filter
UOCIII series
PH1LF 17 17 17 112 112 112 phase-1 filter
GND1 18 18 18 111 111 111 ground 1 for TV-processor
SECPLL 19 19 19 110 110 110 SECAM PLL decoupling
DECBG 20 20 20 109 109 109 bandgap decoupling
EWD/AVL (1) 21 21 21 108 108 108 East-West drive output or AVL capacitor
2003 Nov 11
VERSION VERSION
NO AUDIO DSP
NO AUDIO DSP
AV STEREO
AV STEREO
AV STEREO
AV STEREO
STEREO +
STEREO +
SYMBOL DESCRIPTION
MONO
MONO
VDRB 22 22 22 107 107 107 vertical drive B output
VDRA 23 23 23 106 106 106 vertical drive A output
VIFIN1 24 24 24 105 105 105 IF input 1
VIFIN2 25 25 25 104 104 104 IF input 2
CONFIDENTIAL
VSC 26 26 26 103 103 103 vertical sawtooth capacitor

IREF 27 27 27 102 102 102 reference current input
GNDIF 28 28 28 101 101 101 ground connection for IF amplifier
SIFIN1/DVBIN1 (2) 29 29 29 100 100 100 SIF input 1 / DVB input 1
SIFIN2/DVBIN2 (2)
16
30 30 30 99 99 99 SIF input 2 / DVB input 2

AGCOUT 31 31 31 98 98 98 tuner AGC output
EHTO 32 32 32 97 97 97 EHT/overvoltage protection input
AVL/SWO/SSIF/ 33 33 33 96 96 96 Automatic Volume Levelling / switch output / sound IF input /
REFO/REFIN (2)(3) subcarrier reference output / external reference signal input for I
signal mixer for DVB operation
AUDIOIN5 − − 34 − − 95 audio 5 input
AUDIOIN5L 34 34 − 95 95 − audio-5 input (left signal)
AUDIOIN5R 35 35 − 94 94 − audio-5 input (right signal)
AUDOUTSL 36 36 − 93 93 − audio output for SCART/CINCH (left signal)
− −
UOCIII series
AUDOUTSR 37 37 92 92 audio output for SCART/CINCH (right signal)
DECSDEM 38 38 38 91 91 91 decoupling sound demodulator
QSSO/AMOUT/AUDEEM (2) 39 39 39 90 90 90 QSS intercarrier output / AM output / deemphasis (front-end audio
out)
GND2 40 40 40 89 89 89 ground 2 for TV processor
2003 Nov 11
VERSION VERSION
NO AUDIO DSP
NO AUDIO DSP
AV STEREO
AV STEREO
AV STEREO
AV STEREO
STEREO +
STEREO +
SYMBOL DESCRIPTION
MONO
MONO
PLLIF 41 41 41 88 88 88 IF-PLL loop filter
SIFAGC/DVBAGC (2) 42 42 42 87 87 87 AGC sound IF / internal-external AGC for DVB applications
DVBO/IFVO/FMRO (2) 43 43 43 86 86 86 Digital Video Broadcast output / IF video output / FM radio output
DVBO/FMRO (2) 44 44 − 85 85 − Digital Video Broadcast output / FM radio output
CONFIDENTIAL
VCC8V 45 45 45 84 84 84 8 Volt supply for audio switches

AGC2SIF 46 − − 83 − − AGC capacitor second sound IF
VP2 47 47 47 82 82 82 2nd supply voltage TV processor (+5 V)
IFVO/SVO/CVBSI (2) 48 48 48 81 81 81 IF video output / selected CVBS output / CVBS input
− − − −
17
AUDIOIN4 49 80 audio 4 input

AUDIOIN4L 49 49 − 80 80 − audio-4 input (left signal)
AUDIOIN4R 50 50 − 79 79 − audio-4 input (right signal)
CVBS4/Y4 51 51 51 78 78 78 CVBS4/Y4 input
C4 52 52 52 77 77 77 chroma-4 input
AUDIOIN2L/SSIF (3) 53 53 − 76 76 − audio 2 input (left signal) / sound IF input
AUDIOIN2R 54 54 − 75 75 − audio 2 input (right signal)
UOCIII series
AUDIOIN3L 56 56 − 73 73 − audio 3 input (left signal)
AUDIOIN3R 57 57 − 72 72 − audio 3 input (right signal)
C2/C3 59 59 59 70 70 70 chroma-2/3 input
2003 Nov 11
VERSION VERSION
NO AUDIO DSP
NO AUDIO DSP
AV STEREO
AV STEREO
AV STEREO
AV STEREO
STEREO +
STEREO +
SYMBOL DESCRIPTION
MONO
MONO
AUDOUTLSL 60 62 − 69 67 − audio output for audio power amplifier (left signal)
AUDOUTLSR 61 63 − 68 66 − audio output for audio power amplifier (right signal)
AUDOUT/AMOUT/FMOUT − − 62 − − 67 audio output / AM output / FM output, volume controlled
AUDOUTHPL 62 − − 67 − − audio output for headphone channel (left signal)
CONFIDENTIAL
AUDOUTHPR 63 − − 66 − − audio output for headphone channel (right signal)

CVBSO/PIP 64 64 64 65 65 65 CVBS / PIP output
SVM 65 65 65 64 64 64 scan velocity modulation output
FBISO/CSY 66 66 66 63 63 63 flyback input/sandcastle output or composite H/V timing output
18
HOUT 67 67 67 62 62 62 horizontal output

VSScomb 68 68 68 61 61 61 ground connection for comb filter
VDDcomb 69 69 69 60 60 60 supply voltage for comb filter (5 V)
VIN (R/PRIN2/CX) 70 70 70 59 59 59 V-input for YUV interface (2nd R input / PR input or CX input)
UIN (B/PBIN2) 71 71 71 58 58 58 U-input for YUV interface (2nd B input / PB input)
YIN (G/YIN2/CVBS-YX) 72 72 72 57 57 57 Y-input for YUV interface (2nd G input / Y input or CVBS/YX input))
YSYNC 73 73 73 56 56 56 Y-input for sync separator
YOUT 74 74 74 55 55 55 Y-output (for YUV interface)
UOUT (INSSW2) 75 75 75 54 54 54 U-output for YUV interface (2nd RGB / YPBPR insertion input)
VOUT (SWO1) 76 76 76 53 53 53 V-output for YUV interface (general purpose switch output)
UOCIII series
INSSW3 77 77 77 52 52 52 3rd RGB / YPBPR insertion input
R/PRIN3 78 78 78 51 51 51 3rd R input / PR input
G/YIN3 79 79 79 50 50 50 3rd G input / Y input
B/PBIN3 80 80 80 49 49 49 3rd B input / PB input
2003 Nov 11
VERSION VERSION
NO AUDIO DSP
NO AUDIO DSP
AV STEREO
AV STEREO
AV STEREO
AV STEREO
STEREO +
STEREO +
SYMBOL DESCRIPTION
MONO
MONO
GND3 81 81 81 48 48 48 ground 3 for TV-processor
VP3 82 82 82 47 47 47 3rd supply for TV processor
BCLIN 83 83 83 46 46 46 beam current limiter input
BLKIN 84 84 84 45 45 45 black current input
CONFIDENTIAL
RO 85 85 85 44 44 44 Red output
GO 86 86 86 43 43 43 Green output
BO 87 87 87 42 42 42 Blue output
VDDA1 88 88 88 41 41 41 analog supply for TCG µ-Controller and digital supply for
TV-processor (+3.3 V)
19
VREFAD_NEG 89 89 89 40 40 40 negative reference voltage (0 V)

VREFAD_POS 90 90 90 39 39 39 positive reference voltage (3.3 V)
VREFAD 91 − − 38 − − reference voltage for audio ADCs (3.3/2 V)
GNDA 92 92 92 37 37 37 ground
VDDA(1.8V) 93 93 93 36 36 36 analogue supply for audio ADCs (1.8 V)
VDDA2(3.3) 94 94 94 35 35 35 supply voltage SDAC (3.3 V)
VSSadc 95 95 95 34 34 34 ground for video ADC and PLL
VDDadc(1.8) 96 96 96 33 33 33 supply voltage video ADC and PLL
INT0/P0.5 97 97 97 32 32 32 external interrupt 0 or port 0.5 (4 mA current sinking capability for
UOCIII series
direct drive of LEDs)
P1.0/INT1 98 98 98 31 31 31 port 1.0 or external interrupt 1
P1.1/T0 99 99 99 30 30 30 port 1.1 or Counter/Timer 0 input
VDDC2 100 100 100 29 29 29 digital supply to core (1.8 V)
VSSC2 101 101 101 28 28 28 ground
2003 Nov 11
VERSION VERSION
NO AUDIO DSP
NO AUDIO DSP
AV STEREO
AV STEREO
AV STEREO
AV STEREO
STEREO +
STEREO +
SYMBOL DESCRIPTION
MONO
MONO
P0.4/I2SWS 102 − − 27 − − port 0.4 or I2S word select
P0.4 − 102 102 − 27 27 port 0.4
P0.3/I2SCLK 103 − − 26 − − port 0.3 or I2S clock
P0.3 − 103 103 − 26 26 port 0.3
CONFIDENTIAL
P0.2/I2SDO2 104 − − 25 − − port 0.2 or I2S digital output 2

P0.2 − 104 104 − 25 25 port 0.2
P0.1/I2SDO1 105 − − 24 − − port 0.1 or I2S digital output 1
P0.1 − 105 105 − 24 24 port 0.1
− − − − port 0.0 or I2S digital input 1 or I2S digital output
20
P0.0/I2SDI1/O 106 23
P0.0 − 106 106 − 23 23 port 0.0
P1.3/T1 107 107 107 22 22 22 port 1.3 or Counter/Timer 1 input
P1.6/SCL 108 108 108 21 21 21 port 1.6 or I2C-bus clock line
P1.7/SDA 109 109 109 20 20 20 port 1.7 or I2C-bus data line
VDDP(3.3V) 110 110 110 19 19 19 supply to periphery and on-chip voltage regulator (3.3 V)
P2.0/TPWM 111 111 111 18 18 18 port 2.0 or Tuning PWM output
P2.1/PWM0 112 112 112 17 17 17 port 2.1 or PWM0 output
UOCIII series
P3.0/ADC0 115 115 115 14 14 14 port 3.0 or ADC0 input
VDDC1 117 117 117 12 12 12 digital supply to core (+1.8 V)
DECV1V8 118 118 118 11 11 11 decoupling 1.8 V supply
2003 Nov 11
VERSION VERSION
NO AUDIO DSP
NO AUDIO DSP
AV STEREO
AV STEREO
AV STEREO
AV STEREO
STEREO +
STEREO +
SYMBOL DESCRIPTION
MONO
MONO
VSSC/P 121 121 121 8 8 8 digital ground for µ-Controller core and periphery
CONFIDENTIAL

VDDC3 124 124 124 5 5 5 digital supply to core (1.8V)
VSSC3 125 125 125 4 4 4 ground
P1.2/INT2 126 126 126 3 3 3 port 1.2 or external interrupt 2
21
P1.4/RX 127 127 127 2 2 2 port 1.4 or UART bus

P1.5/TX 128 128 128 1 1 1 port 1.5 or UART bus
Note
1. The function of this pin can be chosen by means of the AVLE bit.
2. The functional content of these pins is dependent on the mode of operation and on some I2C-bus control bits. More details are given in table 4.
3. With the ESSIF bit the SSIF input can be selected either on pin 33 or pin 53. For the “face down” versions these pin numbers are 96 and 76
respectively.
UOCIII series
2003 Nov 11 Table 4 Pin functions for various modes of operation
ANALOGUE TV MODE
IC MODE FM-PLL MODE
QSS MODE (QSS = 1)
DVB MODE (QSS = 0) FM RADIO MODE
FM QSS-FM
FUNCTION QSS/AM DEMODULATION
DEMODULATION DEMODULATION
IFA/IFB/IFC bits 101/111 000/001/010/011/100/110 101/111
FMR bit 0 0 0 1
FMI bit − − 0 1 −
AVLE bit 1 0 1 0 1 0 1 0 1 0
CMB2/CMB1/CMB0 bits 010/011 100 000/001/010/011/101/110
− − − −
CONFIDENTIAL
AM bit 0 1 0 1
Standard Face-down
pin 21 pin 108 AVL EWD AVL EWD AVL EWD AVL EWD AVL EWD
pin 29 pin 100 DVBIN1 − SIFIN1 SIFIN1
pin 30 pin 99 DVBIN2 − SIFIN2 SIFIN2
pin 33 (1) pin 96 (1) SWO REFIN SWO/ AVL/ SWO/SSIF/REFO AVL/SWO/SSIF/ SWO/ AVL/ SWO/ AVL/
22
SSIF/ SWO/ REFO SSIF/ SWO/ SSIF/ SWO/

REFO SSIF/ REFO SSIF/ REFO SSIF/
REFO REFO REFO
pin 39 pin 90 − AUDEEM QSSO AMOUT QSSO AMOUT AUDEEM AUDEEM
pin 42 pin 87 DVBAGC − SIFAGC SIFAGC
pin 43 (2) pin 86 (2) DVBO IFVO IFVO FMRO
pin 44 (2) pin 85 (2) DVBO − − FMRO
pin 48 (3) pin 81 (3) SVO/CVBSI IFVO/SVO/CVBSI IFVO/SVO/CVBSI IFVO/SVO/CVBSI
pin 62 (4) pin 67 (4) AUDOUT AUDOUT AUDOUT AMOUT AUDOUT AMOUT AUDOUT AUDOUT
Note
1. The function of this pin is controlled by the bits CMB2-CMB0 in subaddress 4AH.
UOCIII series
2. The functions of the pins 43/44 (standard pinning) or 85/86 (face-down pinning) are controlled by the IFO2-IFO0 bits in subaddress 31H.
3. The function of this pin is determined by the SVO1/SVO0 bits in subaddress 39H.
4. This functionality is only valid for the mono versions. In the “stereo” and “AV-stereo” versions this pin has the function of audio output for the
headphone channel (left signal).

UOCIII series
103 P0.3/I2SCLK
P0.1/I2SDO1
104 P0.2/I2SDO2
VDDP(3.3V)
P2.2/PWM1
114 P2.3/PWM2
P2.1/PWM0
117 VDDC1(1.8)
102 P0.4/I2SWS
106 P0.0/I2SDI1
123 P2.5/PWM4
122 P2.4/PWM3
116 P3.1/ADC1
P3.0/ADC0
119 P3.2/ADC2
120 P3.3/ADC3
P2.0/PMW
98 P1.O/INT1
118 DECV1V8
126 P1.2/INT2
P1.7/SDA
P1.6/SCL
97 INT0/P0.5
121 VSSC1/P
127 P1.4/RX
128 P1.5/TX
P1.3/T1
99 P1.1/T0
100 VDDC2
124 VDDC3
101 VSSC2
125 VSSC3
111
107
113
112
105
115
110
109
108
VSSP2 1 96 VDDadc(1.8)
VSSC4 2 95 VSSadc
VDDC4 3 94 VDDA2(3.3V)
VDDA3(3.3V) 4 93 VDDA(1.8V)
VREF_POS_LSL 5 92 GNDA
VREF_NEG_LSL+LSR 6 91 VREFAD
VREF_POS_LSR+HPL 7 90 VREFAD_POS
VREF_NEG_HPL+HPR 8 89 VREFAD_NEG
VREF_POS_HPR 9 88 VDDA1(3.3V.)
XTALIN 10 87 BO
XTALOUT 11 86 GO
VSSA1 12 85 RO
VGUARD/SWIO 13 84 BLKIN
DECDIG 14 83 BCLIN
VP1 15 82 VP3
PH2LF 16 81 GND3
PH1LF 17 80 B/PB-3
GND1 18 79 G/Y-3
SECPLL 19 78 R/PR-3
DECBG 20 77 INSSW3
AVL/EWD 21 76 VOUT(SWO1)
VDRB 22 75 UOUT(INSW-2)
VDRA 23 74 YOUT
VIFIN1 24 73 YSYNC
VIFIN2 25 72 YIN(G/Y-2/CVBS/Y-X)
VSC 26 71 UIN (B/PB-2)
IREF 27 70 VIN(R/PR-2/C-X)
GNDIF 28 69 VDDcomb
DVBIN1/SIFIN1 29 68 VSScomb
DVBIN2/SIFIN2 30 67 HOUT
AGCOUT 31 66 FBISO/CSY
32
EHTO QFP-128 0.8mm pitch “standard version” 65 SVM
39
47
61
AUDIOIN2L 53
CVBS3/Y3 58
34
42
50
62
40
48
37
45
60
CVBSO/PIP 64
AUDIOIN3R 57
59
AUDIOIN2R/SSIF 54
35
43
63
38
46
52
AUDIOIN3L 56
36
44
49
51
CVBS2/Y2 55
33
41
AUDOUTHPL
REFIN/REFOUT
AUDOUTHPR
AUDOUTLSL
AUDIOIN5L
AUDOUTSL
AUDOUTLSR
AUDOUTSR
AUDIOIN5R
C2/C3
SIFAGC/DVBAGC
DVBO//IFVO/FMRO
AUDIOIN4R
VCC8V
VP2
AUDIOIN4L
C4
AGC2SIF
GND2
DVBO/FMRO
AVL/SWO/SSIF/
CVBS4/Y4
DECSDEM
PLLIF
AMOUT/QSSO/AUDEEM
SVO/IFOUT/CVBSI
Fig.5 Pin configuration “stereo” and “AV-stereo” versions with Audio DSP
2003 Nov 11 23
CONFIDENTIAL

UOCIII series
VDDP(3.3V)
P2.2/PWM1
114 P2.3/PWM2
P2.1/PWM0
117 VDDC1(1.8)
P2.5/PWM4
P2.4/PWM3
116 P3.1/ADC1
P3.0/ADC0
119 P3.2/ADC2
P3.3/ADC3
P2.0/PMW
98 P1.O/INT1
118 DECV1V8
126 P1.2/INT2
97 INT0/P0.5
VSSC1/P
127 P1.4/RX
P1.7/SDA
P1.6/SCL
128 P1.5/TX
VDDC3
125 VSSC3
99 P1.1/T0
107 P1.3/T1
VDDC2
VSSC2
106 P0.0
105 P0.1
P0.2
P0.3
P0.4
103
122
121
120
111
123
104
124
113
112
102
101
100
115
110
109
108
VSSC4 2 95 VSSadc
VDDA3(3.3V) 4 93 VDDA(1.8V)
- 5 92 GNDA
- 6 91 -
- 7 90 VREFAD_POS
- 8 89 VREFAD_NEG
- 9 88 VDDA1(3.3V.)
XTALIN 10 87 BO
XTALOUT 11 86 GO
VSSA1 12 85 RO
DECDIG 14 83 BCLIN
VP1 15 82 VP3
PH2LF 16 81 GND3
PH1LF 17 80 B/PB-3
GND1 18 79 G/Y-3
SECPLL 19 78 R/PR-3
DECBG 20 77 INSSW3
VDRA 23 74 YOUT
VIFIN1 24 73 YSYNC
GNDIF 28 69 VDDcomb
EHTO 32 QFP-128 0.8mm pitch “standard version” 65 SVM
39
47
- 61
53
58
34
SIFAGC/DVBAGC 42
50
AUDOUTLSL 62
40
48
37
VCC8V 45
- 60
CVBSO/PIP 64
57
C2/C3 59
54
35
DVBO//IFVO/FMRO 43
AUDOUTLSR 63
38
- 46
52
56
36
- 44
49
51
55
33
41
REFIN/REFOUT
AUDIOIN3L
AUDIOIN5L
AUDOUTSL
AUDIOIN3R
AUDOUTSR
AUDIOIN5R
AUDIOIN2R
AUDIOIN2L/SSIF
CVBS3/Y3
AUDIOIN4R
CVBS2/Y2
VP2
AUDIOIN4L
C4
GND2
AVL/SWO/SSIF/
CVBS4/Y4
DECSDEM
PLLIF
AMOUT/QSSO/AUDEEM
SVO/IFOUT/CVBSI
Fig.6 Pin configuration of “AV stereo” versions without Audio DSP
2003 Nov 11 24
CONFIDENTIAL

UOCIII series
VDDP(3.3V)
P2.2/PWM1
P2.3/PWM2
P2.1/PWM0
117 VDDC1(1.8)
123 P2.5/PWM4
122 P2.4/PWM3
116 P3.1/ADC1
P3.0/ADC0
119 P3.2/ADC2
120 P3.3/ADC3
P2.0/PMW
98 P1.O/INT1
118 DECV1V8
126 P1.2/INT2
97 INT0/P0.5
121 VSSC1/P
127 P1.4/RX
P1.7/SDA
P1.6/SCL
128 P1.5/TX
124 VDDC3
99 P1.1/T0
125 VSSC3
107 P1.3/T1
VDDC2
VSSC2
106 P0.0
105 P0.1
P0.2
P0.3
P0.4
103
111
104
114
113
112
102
101
100
115
110
109
108
VSSC4 2 95 VSSadc
VDDA3(3.3V) 4 93 VDDA(1.8V)
- 5 92 GNDA
- 6 91 -
- 7 90 VREFAD_POS
- 8 89 VREFAD_NEG
- 9 88 VDDA1(3.3V.)
XTALIN 10 87 BO
XTALOUT 11 86 GO
VSSA1 12 85 RO
DECDIG 14 83 BCLIN
VP1 15 82 VP3
PH2LF 16 81 GND3
PH1LF 17 80 B/PB-3
GND1 18 79 G/Y-3
SECPLL 19 78 R/PR-3
DECBG 20 77 INSSW3
VDRA 23 74 YOUT
VIFIN1 24 73 YSYNC
GNDIF 28 69 VDDcomb
32
EHTO QFP-128 0.8mm pitch “standard version” 65 SVM
39
47
61
AUDIOIN2 53
CVBS3/Y3 58
34
42
50
AUDOUT/AMOUT 62
40
48
37
45
60
CVBSO/PIP 64
- 57
C2/C3 59
- 54
35
43
- 63
38
46
52
AUDIOIN3 56
36
44
49
51
CVBS2/Y2 55
33
41
REFIN/REFOUT
SIFAGC/DVBAGC
DVBO//IFVO/FMRO
-
AUDIOIN5
VCC8V
VP2
AUDIOIN4
-
-
-
-
CVBS4/Y4
C4
-
-
GND2
AVL/SWO/SSIF/
DECSDEM
-
PLLIF
AMOUT/QSSO/AUDEEM
SVO/IFOUT/CVBSI
Fig.7 Pin configuration “mono” versions
2003 Nov 11 25
CONFIDENTIAL

UOCIII series
121 VREF_NEG_HPL+HPR
122 VREF_POS_LSR+HPL
123 VREF_NEG_LSL+LSR
120 VREF_POS_HPR
124 VREF_POS_LSL
99 DVBIN2/SIFIN2
116 VGUARD/SWIO
DVBIN1/SIFIN1
125 VDDA3(3.3V)
AVL/EWD
118 XTALOUT
98 AGCOUT
DECDIG
SECPLL
DECBG
119 XTALIN
127 VSSC4
117 VSSA1
126 VDDC4
128 VSSP2
PH1LF
PH2LF
GNDIF
VIFIN1
VIFIN2
107 VDRB
GND1
106 VDRA
97 EHTO
IREF
VSC
VP1
103
111
104
114
113
112
105
102
101
100
115
110
109
108
AVL/SWO/SSIF/
P1.5/TX 1 96 REFIN/REFOUT
P1.4/RX 2 95 AUDIOIN5L
P1.2/INT2 3 94 AUDIOIN5R
VSSC3 4 93 AUDOUTSL
VDDC3 5 92 AUDOUTSR
P2.5/PWM4 6 91 DECSDEM
P2.4/PWM3 7 90 AMOUT/QSSO/AUDEEM
VSSC1/P 8 89 GND2
P3.3/ADC3 9 88 PLLIF
P3.2/ADC2 10 87 SIFAGC/DVBAGC
DECV1V8 11 86 DVBO//IFVO/FMRO
VDDC1(1.8) 12 85 DVBO/FMRO
P3.1/ADC1 13 84 VCC8V
P3.0/ADC0 14 83 AGC2SIF
P2.3/PWM2 15 82 VP2
P2.2/PWM1 16 81 SVO/IFOUT/CVBSI
P2.1/PWM0 17 80 AUDIOIN4L
P2.0/PMW 18 79 AUDIOIN4R
VDDP(3.3V) 19 78 CVBS4/Y4
P1.7/SDA 20 77 C4
P1.6/SCL 21 76 AUDIOIN2L/SSIF
P1.3/T1 22 75 AUDIOIN2R
P0.0/I2SDI1 23 74 CVBS2/Y2
P0.1/I2SDO1 24 73 AUDIOIN3L
P0.2/I2SDO2 25 72 AUDIOIN3R
P0.3/I2SCLK 26 71 CVBS3/Y3
P0.4/I2SWS 27 70 C2/C3
VSSC2 28 69 AUDOUTLSL
VDDC2 29 68 AUDOUTLSR
P1.1/T0 30 67 AUDOUTHPL
P1.O/INT1 31 66 AUDOUTHPR
INT0/P0.5 32
QFP-128 0.8 mm pitch “face down version” 65 CVBSO/PIP
VREFAD_POS 39
VP3 47
VSScomb 61
VOUT(SWO1) 53
UIN (B/PB-2) 58
VSSadc 34
BO 42
G/Y-3 50
HOUT 62
VREFAD_NEG 40
GND3 48
GNDA 37
BLKIN 45
VDDcomb 60
SVM 64
YIN(G/Y-2/CVBS/Y-X) 57
VIN(R/PR-2/C-X) 59
UOUT(INSW-2) 54
VDDA2(3.3V) 35
GO 43
FBISO/CSY 63
VREFAD 38
BCLIN 46
INSSW3 52
YSYNC 56
VDDA(1.8V) 36
RO 44
B/PB-3 49
R/PR-3 51
YOUT 55
VDDadc(1.8) 33
VDDA1(3.3V.) 41
Fig.8 Pin configuration “stereo” and “AV-stereo” versions with Audio DSP
2003 Nov 11 26
CONFIDENTIAL

UOCIII series
99 DVBIN2/SIFIN2
116 VGUARD/SWIO
DVBIN1/SIFIN1
125 VDDA3(3.3V)
AVL/EWD
118 XTALOUT
98 AGCOUT
DECDIG
SECPLL
DECBG
VSSC4
XTALIN
126 VDDC4
VSSP2
117 VSSA1
PH1LF
PH2LF
GNDIF
VIFIN1
VIFIN2
107 VDRB
GND1
106 VDRA
97 EHTO
IREF
VSC
VP1
124 -
123 -
122 -
121 -
120 -
103
127
111
104
128
119
114
113
112
105
102
101
100
115
110
109
108
AVL/SWO/SSIF/
P1.4/RX 2 95 AUDIOIN5L
P1.2/INT2 3 94 AUDIOIN5R
VSSC3 4 93 AUDOUTSL
VDDC3 5 92 AUDOUTSR
VSSC1/P 8 89 GND2
VDDC1(1.8) 12 85 -
P3.1/ADC1 13 84 VCC8V
P3.0/ADC0 14 83 -
P2.3/PWM2 15 82 VP2
P2.1/PWM0 17 80 AUDIOIN4L
P2.0/PMW 18 79 AUDIOIN4R
P1.7/SDA 20 77 C4
P1.6/SCL 21 76 AUDIOIN2L/SSIF
P1.3/T1 22 75 AUDIOIN2R
P0.0 23 74 CVBS2/Y2
P0.1 24 73 AUDIOIN3L
P0.2 25 72 AUDIOIN3R
P0.3 26 71 CVBS3/Y3
P0.4 27 70 C2/C3
VSSC2 28 69 -
VDDC2 29 68 -
P1.1/T0 30 67 AUDOUTLSL
P1.O/INT1 31 66 AUDOUTLSR
INT0/P0.5 32
QFP-128 0.8mm pitch “face down version” 65 CVBSO/PIP
VREFAD_POS 39
VP3 47
VSScomb 61
VOUT(SWO1) 53
UIN (B/PB-2) 58
VSSadc 34
BO 42
G/Y-3 50
HOUT 62
VREFAD_NEG 40
GND3 48
GNDA 37
BLKIN 45
VDDcomb 60
SVM 64
VIN(R/PR-2/C-X) 59
UOUT(INSW-2) 54
VDDA2(3.3V) 35
GO 43
FBISO/CSY 63
- 38
BCLIN 46
INSSW3 52
YSYNC 56
VDDA(1.8V) 36
RO 44
B/PB-3 49
R/PR-3 51
YOUT 55
VDDadc(1.8) 33
VDDA1(3.3V.) 41
Fig.9 Pin configuration of “AV stereo” versions without Audio DSP
2003 Nov 11 27

UOCIII series
99 DVBIN2/SIFIN2
116 VGUARD/SWIO
DVBIN1/SIFIN1
125 VDDA3(3.3V)
AVL/EWD
118 XTALOUT
98 AGCOUT
DECDIG
SECPLL
DECBG
XTALIN
127 VSSC4
117 VSSA1
126 VDDC4
128 VSSP2
PH1LF
PH2LF
GNDIF
VIFIN1
VIFIN2
107 VDRB
GND1
106 VDRA
97 EHTO
IREF
VSC
VP1
124 -
123 -
122 -
121 -
120 -
103
111
104
114
113
112
119
105
102
101
100
115
110
109
108
AVL/SWO/SSIF/
P1.4/RX 2 95 AUDIOIN5
P1.2/INT2 3 94 -
VSSC3 4 93 -
VDDC3 5 92 -
VSSC1/P 8 89 GND2
VDDC1(1.8) 12 85 -
P3.1/ADC1 13 84 VCC8V
P3.0/ADC0 14 83 -
P2.3/PWM2 15 82 VP2
P2.1/PWM0 17 80 AUDIOIN4
P2.0/PMW 18 79 -
P1.7/SDA 20 77 C4
P1.6/SCL 21 76 AUDIOIN2
P1.3/T1 22 75 -
P0.0 23 74 CVBS2/Y2
P0.1 24 73 AUDIOIN3
P0.2 25 72 -
P0.3 26 71 CVBS3/Y3
P0.4 27 70 C2/C3
VSSC2 28 69 -
VDDC2 29 68 -
P1.1/T0 30 67 AUDOUT/AMOUT
P1.O/INT1 31 66 -
INT0/P0.5 32
QFP-128 0.8mm pitch “face down version” 65 CVBSO/PIP
39
VP3 47
VSScomb 61
VOUT(SWO1) 53
UIN (B/PB-2) 58
VSSadc 34
BO 42
G/Y-3 50
HOUT 62
40
GND3 48
37
BLKIN 45
VDDcomb 60
SVM 64
VIN(R/PR-2/C-X) 59
UOUT(INSW-2) 54
VDDA2(3.3V) 35
GO 43
FBISO/CSY 63
38
BCLIN 46
INSSW3 52
YSYNC 56
VDDA(1.8V) 36
RO 44
B/PB-3 49
R/PR-3 51
YOUT 55
VDDadc(1.8) 33
VDDA1(3.3V.) 41
VREFAD_NEG
VREFAD_POS
-
GNDA
Fig.10 Pin configuration “mono” versions
2003 Nov 11 28
CONFIDENTIAL

UOCIII series
FUNCTIONAL DESCRIPTION OF THE 80C51

The functionality of the micro-controller used on this
device is described here with reference to the industry
standard 80C51 micro-controller. A full description of its
functionality can be found in the 80C51 based 8-bit
micro-controllers - Philips Semiconductors (ref. IC20).
Features of the 80c51

• 80C51 micro-controller core standard instruction set and
timing
• 0.4883µs machine cycle (Xtal frequency 24.576MHz)
• Maximum 256Kx8bit Flash Program ROM
• Maximum of 8Kx8bit Auxiliary RAM
• 12-Level Interrupt Controller for individual
enable/disable with two level priority
• Two 16-bit Timer/Counter registers Fig.11 ROM Bank switching memory map
• Additional 24-bit Timer (16-bit timer with 8-bit pre-scaler)

• WatchDog Timer RAM Organisation
• Auxiliary RAM Page Pointer The Internal Data RAM is organised into two areas, Data
Memory and Special Function Registers (SFRs) as shown
• 16-bit Data pointer
in Fig.12.
• Stand-by, IDLE and Power Down (PD) modes
• 24 General I/O via individual addressable controls
• Five 6-bit Pulse Width Modulator (PWM) outputs for Internal RAM : “I-Data”
control of TV analogue signals
FF H Special Function Registers
• One 14-bit PWM for Voltage Synthesis tuning control 128B RAM 128B SFR
= extension method for 80c51
only Indirect only Direct
• 8-bit ADC with 4 multiplexed inputs addressing

80 H
addressing
30..7F H RAM R7
R6
• High-speed I 2C for ISP (up to 1.2 Mb/s) 7F H 20..2F H Bit-addressable
space
Register-Bank
select bits
R5
R4
Lower 128 Byte RAM in PSW
R3
• Remote Control Pre-processor (RCP) Direct & Indirect
addressing
18..1F H Register-Bank3
10..17 H Register-Bank2 R-Bank
R2
R1
• Universal Asynchronous Receiver Transmitter (UART) 00 H 08..0F H Register-Bank1 R0

00..07 H Register-Bank0
Memory Organisation • Different addressing method for upper 128 Bytes

accesses RAM or SFR
The device has the capability of a maximum of 256K Bytes
of PROGRAM ROM and 8K Bytes of AUX DATA RAM for
internally.
Fig.12 Internal Data Memory
ROM Organisation
The 256K is arranged in eight banks of 32K. One of the
32K banks is common and is always addressable. The DATA MEMORY
other banks (Bank0 to Bank6) can be accessed by The Data memory is 256 x 8-bits and occupies the address
selecting the right bank via the SFR ROMBK bits 2/1/0. range 00 to FF Hex when using Indirect addressing and 00
to 7F Hex when using direct addressing. The SFRs occupy
the address range 80 Hex to FF Hex and are accessible
using Direct addressing only. The lower 128 Bytes of Data
memory are mapped as shown in Fig.12. The lowest 32
bytes are grouped into 4 banks of 8 registers, the next 16
bytes above the register banks form a block of bit
addressable memory space. The upper 128 bytes are not
allocated for any special area or functions.
2003 Nov 11 29
CONFIDENTIAL

UOCIII series
SFR MEMORY Sixteen of the addresses in the SFR space are both bit and
The Special Function Register (SFR) space is used for byte addressable. The bit addressable SFRs are those
port latches, counters/timers, peripheral control, data whose address ends in 0H or 8H. A summary of the SFR
capture and display control, etc. These registers can only map in address order is shown in Table 5.
be accessed by direct addressing.
ADD R/W Names BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
80H R/W P0 Reserved Reserved P0<5> P0<4> P0<3> P0<2> P0<1> P0<0>
81H R/W SP SP<7> SP<6> SP<5> SP<4> SP<3> SP<2> SP<1> SP<0>
82H R/W DPL DPL<7> DPL<6> DPL<5> DPL<4> DPL<3> DPL<2> DPL<1> DPL<0>
83H R/W DPH DPH<7> DPH<6> DPH<5> DPH<4> DPH<3> DPH<2> DPH<1> DPH<0>
84H R/W IEN1 - - - EX2 ERDS EUART ET2PR EBUSY
85H R/W IP1 - - - PX2 PRDS PUART PT2PR PBUSY
86H R/W RCP1 DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0>
87H R/W PCON SMOD ARD RFI WLE GF1 GF0 PD IDL
88H R/W TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
89H R/W TMOD GATE C/T M1 M0 GATE C/T M1 M0
8AH R/W TL0 TL0<7> TL0<6> TL0<5> TL0<4> TL0<3> TL0<2> TL0<1> TL0<0>
8BH R/W TL1 TL1<7> TL1<6> TL1<5> TL1<4> TL1<3> TL1<2> TL1<1> TL1<0>
8CH R/W TH0 TH0<7> TH0<6> TH0<5> TH0<4> TH0<3> TH0<2> TH0<1> TH0<0>
8DH R/W TH1 TH1<7> TH1<6> TH1<5> TH1<4> TH1<3> TH1<2> TH1<1> TH1<0>
8EH R RCP3 RA<7> RA<6> RA<5> RA<4> RA<3> RA<2> RA<1> RA<0>
8FH R RCP4 RB<11> RB<10> RB<9> RB<8> RA<11> RA<10> RA<9> RA<8>
90H R/W P1 P1<7> P1<6> P1<5> P1<4> P1<3> P1<2> P1<1> P1<0>
91H R/W TP2L TP2L<7> TP2L<6> TP2L<5> TP2L<4> TP2L<3> TP2L<2> TP2L<1> TP2L<0>
92H R/W TP2H TP2H<7> TP2H<6> TP2H<5> TP2H<4> TP2H<3> TP2H<2> TP2H<1> TP2H<0>
93H R/W TP2PR TP2PR<7> TP2PR<6> TP2PR<5> TP2PR<4> TP2PR<3> TP2PR<2> TP2PR<1> TP2PR<0>
94H R/W TP2CRL - - - - - - TP2CRL<1> TP2CRL<0>
95H R/W RCP2 - - - - DAT<11> DAT<10> DAT<9> DAT<8>
96H R/W P0CFGA Reserved Reserved P0CFGA<5> P0CFGA<4> P0CFGA<3> P0CFGA<2> P0CFGA<1> P0CFGA<0>
97H R/W P0CFGB Reserved Reserved P0CFGB<5> P0CFGB<4> P0CFGB<3> P0CFGB<2> P0CFGB<1> P0CFGB<0>
98H R/W SADB SSD_ON - - DC_COMP SAD<3> SAD<2> SAD<1> SAD<0>
99H R/W S0CON SM<0> SM<1> SM<2> REN TB8 RB8 TI RI
9AH R/W S0BUF S0BUF<7> S0BUF<6> S0BUF<5> S0BUF<4> S0BUF<3> S0BUF<2> S0BUF<1> S0BUF<0>
9BH R RCP5 RB<7> RB<6> RB<5> RB<4> RB<3> RB<2> RB<1> RB<0>
9CH R TP2CL TP2CL<7> TP2CL<6> TP2CL<5> TP2CL<4> TP2CL<3> TP2CL<2> TP2CL<1> TP2CL<0>
9DH R TP2CH TP2CH<7> TP2CH<6> TP2CH<5> TP2CH<4> TP2CH<3> TP2CH<2> TP2CH<1> TP2CH<0>
9EH R/W P1CFGA P1CFGA<7> P1CFGA<6> P1CFGA<5> P1CFGA<4> P1CFGA<3> P1CFGA<2> P1CFGA<1> P1CFGA<0>
9FH R/W P1CFGB P1CFGB<7> P1CFGB<6> P1CFGB<5> P1CFGB<4> P1CFGB<3> P1CFGB<2> P1CFGB<1> P1CFGB<0>
2003 Nov 11 30
CONFIDENTIAL

UOCIII series
A0H R/W P2 Reserved Reserved P2<5> P2<4> P2<3> P2<2> P2<1> P2<0>
A1H R/W TXT31 0 CC_TXT ACTIVE PAGE 1V8GUARD GPF<11> GPF<10> GPF<9> GPF<8>
B
A2H R TXT32 GPF<11> 9FF<11> 9FF<10> 9FF<9> 9FF<8> 9FF<7> 9FF<6> 9FF<5>
A3H R TXT33 BFE<7> BFE<6> BFE<5> BFE<4> BFE<3> BFE<2> BFE<1> BFE<0>
A4H R TXT34 BFE<15> BFE<14> BFE<13> BFE<12> BFE<11> BFE<10> BFE<9> BFE<8>
A5H R/W Video_process - - - - - - DW_PA<1> DW_PA<0>
A6H R/W P2CFGA Reserved Reserved P2CFGA<5> P2CFGA<4> P2CFGA<3> P2CFGA<2> P2CFGA<1> P2CFGA<0>
A7H R/W P2CFGB Reserved Reserved P2CFGB<5> P2CFGB<4> P2CFGB<3> P2CFGB<2> P2CFGB<1> P2CFGB<0>
A8H R/W IE EA ES2 ECC EDET ET1 EX1 ET0 EX0
A9H R/W TXT23 NOT B <3> NOT B <2> NOT B <1> NOT B <0> East/West B DRCS B BS B<1> BS B<0>
ENABLE
AAH R/W TXT24 BKGND OUT BKGND IN B CORB OUT B CORB IN TEXT OUT B TEXT IN PICTURE ON PICTURE ON
B B B OUT IN
B B
ABH R/W TXT25 BKGND OUT BKGND IN B CORB OUT B CORB IN TEXT OUT B TEXT IN PICTURE ON PICTURE ON
B B B OUT IN
B B
ACH R/W TXT26 EXTENDED TRANS B 0 0 SHADOW BOX ON BOX ON BOX ON

DRCS ENABLE B 24 B 1-23 B 0B
ADH R/W TXT28 DISPLAY DISPLAY DISPLAY DISPLAY PAGE B<3> PAGE B<2> PAGE B<1> PAGE B<0>
BANK B<3> BANK B<2> BANK B<1> BANK B<0>
AEH R ADJUST_E0 ADJUST ADJUST ADJUST ADJUST ADJUST E0<3> ADJUST ADJUST ADJUST
E0<7> E0<6> E0<5> E0<4> E0<2> E0<1> E0<0>
AFH R ADJUST_E1 ADJUST ADJUST ADJUST ADJUST ADJUST E1<3> ADJUST ADJUST ADJUST
E1<7> E1<6> E1<5> E1<4> E1<2> E1<1> E1<0>
B0H R/W P3 Reserved Reserved Reserved Reserved P3<3> P3<2> P3<1> P3<0>
B1H R/W TXT27 - - - - RDS ON SCR B<2> SCR B<1> SCR B<0>
B2H R/W TXT18 NOT<3> NOT<2> NOT<1> NOT<0> 0 0 BS<1> BS<0>
B3H R/W TXT19 TEN TC<2> TC<1> TC<0> 0 0 TS<1> TS<0>
B4H R/W TXT20 DRCS OSD PLANES EXTENDED CHAR OSD LANG OSD LAN<2> OSD LAN<1> OSD LAN<0>
ENABLE SPECIAL SELECT ENABLE
GRAPHICS ENABLE
B5H R/W TXT21 DISP LINE<1> DISP CHAR CHAR Reserved (0) CC ON I2C PORT EN CC/TXT
LINES<0> SIZE<1> SIZE<0>
B6H R TXT22 GPF<7> GPF<6> GPF<5> GPF<4> GPF<3> GPF<2> GPF<1> GPF<0>
B7H R/W CCLIN 0 0 0 CS<4> CS<3> CS<2> CS<1> CS<0>
B8H R/W IP 0 PES2 PCC PDET PT1 PX1 PT0 PX0
B9H R/W TXT17 0 FORCE FORCE FORCE FORCE SCREEN SCREEN SCREEN
ACQ<1> ACQ<0> DISP<1> DISP<0> COL<2> COL<1> COL<0>
BAH R WSS1 0 0 0 WSS<3:0> WSS<3> WSS<2> WSS<1> WSS<0>

ERROR
BBH R WSS2 0 0 0 WSS<7:4> WSS<7> WSS<6> WSS<5> WSS<4>

ERROR
2003 Nov 11 31
CONFIDENTIAL

UOCIII series
BCH R WSS3 WSS<13:11> WSS<13> WSS<12> WSS<11> WSS<10:8> WSS<10> WSS<9> WSS<8>
ERROR ERROR
BDH R ADJUST_E2 ADJUST ADJUST ADJUST ADJUST ADJUST E2<3> ADJUST ADJUST ADJUST
E2<7> E2<6> E2<5> E2<4> E2<2> E2<1> E2<0>
BEH R/W P3CFGA Reserved Reserved Reserved Reserved P3CFGA<3> P3CFGA<2> P3CFGA<1> P3CFGA<0>
BFH R/W P3CFGB Reserved Reserved Reserved Reserved P3CFGB<3> P3CFGB<2> P3CFGB<1> P3CFGB<0>
C0H R/W TXT0 X24 POSN DISPLAY X24 AUTO FRAME DISABLE DISPLAY DISABLE VPS ON INV ON
HEADER STATUS ROW FRAME
ROLL ONLY
C1H R/W TXT1 EXT PKT OFF 8 BIT ACQ OFF X26 OFF Reserved FIELD H POLARITY V POLARITY
POLARITY
C2H R/W TXT2 ACQ REQ<3> REQ<2> REQ<1> REQ<0> SC<2> SC<1> SC<0>
BANK<0>
C3H R/W TXT3 ACQ ACQ ACQ PRD<4> PRD<3> PRD<2> PRD<1> PRD<0>
BANK<3> BANK<2> BANK<1>
C4H R/W TXT4 OSD BANK QUAD EAST/WEST DISABLE 0 0 TRANS SHADOW
ENABLE WIDTH DOUBLE ENABLE ENABLE
ENABLE HEIGHT
C5H R/W TXT5 BKGND OUT BKGND IN CORB OUT CORB IN TEXT OUT TEXT IN PICTURE ON PICTURE ON
OUT IN
C6H R/W TXT6 BKGND OUT BKGND IN CORB OUT CORB IN TEXT OUT TEXT IN PICTURE ON PICTURE ON
OUT IN
C7H R/W TXT7 STATUS ROW CURSOR ON REVEAL BOTTOM/TOP DOUBLE BOX ON 24 BOX ON 1-23 BOX ON 0
TOP HEIGHT
C8H R/W TXT8 (Reserved) FLICKER HUNT DISABLE PKT 26 WSS WSS ON (Reserved)
0 STOP ON SPANISH RECEIVED RECEIVED 0
C9H R/W TXT9 CURSOR CLEAR A0 R<4> R<3> R<2> R<1> R<0>
FREEZE MEMORY
CAH R/W TXT10 CHAR - C<5> C<4> C<3> C<2> C<1> C<0>
16/12
CBH R/W TXT11 D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0>
CCH R TXT12 525/625 SYNC ROM VER<4> ROM VER<3> ROM VER<2> ROM VER<1> ROM VER<0> 1 VIDEO
SIGNAL
QUALITY
CDH R/W TXT14 DISPLAY DISPLAY DISPLAY DISPLAY PAGE<3> PAGE<2> PAGE<1> PAGE<0>
BANK<3> BANK<2> BANK<1> BANK<0>
CEH R/W TXT15 MICRO MICRO MICRO MICRO BLOCK<3> BLOCK<2> BLOCK<1> BLOCK<0>
CFH R ADJUST_E3 ADJUST ADJUST ADJUST ADJUST ADJUST E3<3> ADJUST ADJUST E31> ADJUST
E3<7> E3<6> E3<5> E3<4> E3<2> E3<0>
D0H R/W PSW C AC F0 RS1 RS0 OV - P
D1H R ADJUST_E4 ADJUST ADJUST ADJUST ADJUST ADJUST E4<3> ADJUST ADJUST ADJUST
E4<7> E4<6> E4<5> E4<4> E4<2> E4<1> E4<0>
D2H R/W TDACL TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0>
D3H R/W TDACH TPWE 0 TD<13> TD<12> TD<11> TD<10> TD<9> TD<8>
D4H R/W P3DCXOCTR P3DCXOMUX P3DCXOCAP P3DCXOCAP P3DCXOCAPS P3DCXOCAPS P3DCXOCAP P3DCXOCAPS P3DCXOCAPS
L S<6> S<5> <4> <3> S<2> <1> <0>
D5H R/W PWM0 PW0E Reserved (0) PW0V<5> PW0V<4> PW0V<3> PW0V<2> PW0V<1> PW0V<0>
D6H R/W PWM1 PW1E 0 PW1V<5> PW1V<4> PW1V<3> PW1V<2> PW1V<1> PW1V<0>
2003 Nov 11 32
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UOCIII series
D7H R CCDAT1 CCD1<7> CCD1<6> CCD1<5> CCD1<4> CCD1<3> CCD1<2> CCD1<1> CCD1<0>
D8H R/W S1CON EN_I2CINT ENSI STA STO SI AA 0 0
D9H R S1STA STAT<4> STAT<3> STAT<2> STAT<1> STAT<0> 0 0 0
DAH R/W S1DAT DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0>
DBH R/W S1ADR ADR<6> ADR<5> ADR<4> ADR<3> ADR<2> ADR<1> ADR<0> GC
DCH R/W PWM3 PW3E 0 PW3V<5> PW3V<4> PW3V<3> PW3V<2> PW3V<1> PW3V<0>
DDH R/W PWM4 PW4E 0 PW4V<5> PW4V<4> PW4V<3> PW4V<2> PW4V<1> PW4V<0>
DEH R/W HSBIR 0 0 0 HSB<4> HSB<3> HSB<2> HSB<1> HSB<0>
DFH R/W FSBIR F/S FSB<6> FSB<5> FSB<4> FSB<3> FSB<2> FSB<1> FSB<0>
E0H R/W ACC ACC<7> ACC<6> ACC<5> ACC<4> ACC<3> ACC<2> ACC<1> ACC<0>
E1H R/W TXT29 TEN B TS B <1> TS B <0> OSD OSD LANG OSD LAN B OSD LAN B OSD LAN B
PLANES B ENABLE B <2> <1> <0>
E2H R/W TXT30 TC B <2> TC B <1> TC B <0> BOTTOM/TOP DOUBLE STATUS ROW DISPLAY X24 DISPLAY
B HEIGHT TOP B B STATUS ROW
B ONLY B
E3H R/W RDS_F0_F1 F0<3> F0<2> F0<1> F0<0> F1<3> F1<2> F1<1> F1<0>
E4H R/W PWM2 PW2E 0 PW2V<5> PW2V<4> PW2V<3> PW2V<2> PW2V<1> PW2V<0>
E5H R/W RDS_COEF_ COEF<15> COEF<14> COEF<13> COEF<12> COEF<11> COEF<10> COEF<9> COEF<8>
H
E6H R/W RDS_COEF_ COEF<7> COEF<6> COEF<5> COEF<4> COEF<3> COEF<2> COEF<1> COEF<0>
L
E7H R CCDAT2 CCD2<7> CCD2<6> CCD2<5> CCD2<4> CCD2<3> CCD2<2> CCD2<1> CCD2<0>
E8H R/W SAD VHI CH<1> CH<0> ST SAD<7> SAD<6> SAD<5> SAD<4>
E9H R RDS_STAT SYNC DOFL RSTD LBIN<2> LBIN<1> LBIN<0> ELB<1> ELB<0>
EAH R RDS_LDATH LDAT<15> LDAT<14> LDAT<13> LDAT<12> LDAT<11> LDAT<10> LDAT<9> LDAT<8>
EBH R RDS_LDATL LDAT<7> LDAT<6> LDAT<5> LDAT<4> LDAT<3> LDAT<2> LDAT<1> LDAT<0>
ECH R RDS_PDATH PDAT<15> PDAT<14> PDAT<13> PDAT<12> PDAT<11> PDAT<10> PDAT<9> PDAT<8>
EDH R RDS_PDATL PDAT<7> PDAT<6> PDAT<5> PDAT<4> PDAT<3> PDAT<2> PDAT<1> PDAT<0>
EFH R/W RCP6 RCP ON NFP NGP 0 0 RCPSET<2> RCPSET<1> RCPSET<0>
F0H R/W B B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0>
F1H R RDS_CNT1 BBC<5> BBC<4> BBC<3> BBC<2> BBC<1> BBC<0> EPB<1> EPB<0>
F2H R RDS_CNT2 GBC<5> GBC<4> GBC<3> GBC<2> GBC<1> PBIN<2> PBIN<1> PBIN<0>
F3H R/W RDS_CTRL1 - RBDS MBBL<5> MBBL<4> MBBL<3> MBBL<2> MBBL<1> MBBL<0>
F4H R/W RDS_CTRL2 SYM<1> SYM<0> MGBL<5> MGBL<4> MGBL<3> MGBL<2> MGBL<1> MGBL<0>
F5H R/W RDS_CTRL3 DAC<1> DAC<0> NWSY MBBG<4> MBBG<3> MBBG<2> MBBG<1> MBBG<0>
F6H R/W I2S I2S_CLK<1> I2S_CLK<0> EN_I2S_DI1 EN_I2SDO1 EN_I2SDO2 EN_I2SCLK EN_I2SWS rds_clkin
F7H R TXT35 9FF<15> 9FF<14> 9FF<13> 9FF<12> GPF<15> GPF<14> GPF<13> GPF<12>
F8H R/W TXT13 VPS PAGE 525 DISPLAY 525 TEXT 625 TEXT PKT 8/30 FASTEXT 0
RECEIVED CLEARING
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UOCIII series
F9H R/W SCAVTXT SCAVEM_EN 0 0 PULSE_ PULSE_ EARLY<2> EARLY<1> EARLY<0>

WIDTH<1> WIDTH<0>
FAH R/W XRAMP XRAMP<7> XRAMP<6> XRAMP<5> XRAMP<4> XRAMP<3> XRAMP<2> XRAMP<1> XRAMP<0>
FBH R/W ROMBK STANDBY SW_RST TEMP_140 TEMP_130 0 ROMBK<2> ROMBK<1> ROMBK<0>
FCH R TXT36 - - - BFF<4> BFF<3> BFF<2> BFF<1> BFF<0>
FDH R TEST TEST<7> TEST<6> TEST<5> TEST<4> TEST<3> TEST<2> TEST<1> TEST<0>
FEH W WDTKEY WKEY<7> WKEY<6> WKEY<5> WKEY<4> WKEY<3> WKEY<2> WKEY<1> WKEY<0>
FFH R/W WDT WDV<7> WDV<6> WDV<5> WDV<4> WDV<3> WDV<2> WDV<1> WDV<0>
Table 5 SFR Map
A description of each the SFR bits is shown in Table 6. The SFRs are in alphabetical order.
Table 6 SFR Bit description
Names Add BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RESET
ACC E0H ACC<7> ACC<6> ACC<5> ACC<4> ACC<3> ACC<2> ACC<1> ACC<0> 00H
ACC<7:0> Accumulator value
ADJUST_E0 AEH ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST XXH
E0<7> E0<6> E0<5> E0<4> E0<3> E0<2> E0<1> E0<0>
ADJUST E0<7:0> For internal testing purpose.
ADJUST_E1 AFH ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST XXH
E1<7> E1<6> E1<5> E1<4> E1<3> E1<2> E1<1> E1<0>
ADJUST_E2 BDH ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST XXH
E2<7> E2<6> E2<5> E2<4> E2<3> E2<2> E2<1> E2<0>
ADJUST_E3 CFH ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST XXH
E3<7> E3<6> E3<5> E3<4> E3<3> E3<2> E3<1> E3<0>
ADJUST_E4 D1H ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST ADJUST XXH
E4<7> E4<6> E4<5> E4<4> E4<3> E4<2> E4<1> E4<0>
P3DCXOCTRL D4H P3DCXOMUX P3DCXOCAP P3DCXOCAP P3DCXOCAP P3DCXOCAPS P3DCXOCAP P3DCXOCAP P3DCXOCAP XXH
S<6> S<5> S<4> <3> S<2> S<1> S<0>
P3DCXOMUX DCXO Cap. Bank Selection:-

0 - P3DCXOCAPS
1 - SSD Nicam
P3DCXOCAPS<6:0> DCXO Cap. Bank tuning for NICAM.
B F0H B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0> 00H
B<7:0> B Register value
CCDAT1 D7H CCD1<7> CCD1<6> CCD1<5> CCD1<4> CCD1<3> CCD1<2> CCD1<1> CCD1<0> 00H
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UOCIII series
CCD1<7:0> Closed Caption first data byte
CCDAT2 E7H CCD2<7> CCD2<6> CCD2<5> CCD2<4> CCD2<3> CCD2<2> CCD2<1> CCD2<0> 00H
CCD2<7:0> Closed Caption second data byte
CCLIN B7H 0 0 0 CS<4> CS<3> CS<2> CS<1> CS<0> 15H
CS<4:0> Closed caption Slice line using 525 line number.
DPH 83H DPH<7> DPH<6> DPH<5> DPH<4> DPH<3> DPH<2> DPH<1> DPH<0> 00H
DPH<7:0> Data Pointer High byte, used with DPL to address auxiliary memory
DPL 82H DPL<7> DPL<6> DPL<5> DPL<4> DPL<3> DPL<2> DPL<1> DPL<0> 00H
DPL<7:0> Data pointer low byte, used with DPH to address auxiliary memory
FSBIR DFH F/S FSB<6> FSB<5> FSB<4> FSB<3> FSB<2> FSB<1> FSB<0> 00H
F/S 0 - the duty cycle of SCLH-out is according the Standard mode requirement.
1 - the duty cycle of SCLH-out is according the Fast mode requirement.
FSB<6:0> Determine the SCLH-out frequency in F/S-mode
HSBIR DEH 0 0 0 HSB<4> HSB<3> HSB<2> HSB<1> HSB<0> 00H
HSBIR<4:0> Determine the SCLH-out frequency in Hs-mode
I2S F6H I2S_CLK<1> I2S_CLK<0> EN_I2SDI1 EN_I2SDO1 EN_I2SDO2 EN_I2SCLK EN_I2SWS rds_clkin 00H
I2S_CLK<1:0> I2S Clock Output Selection:-

00 - 256fs
01 - 128fs
10 - 64fs
11 - invalid
fs = 32kHz
EN_I2SDI1 Enable I2S Data Input 1 alternative function to port pin:-

0 - GPIO function
1 - I2S Data Input 1
EN_I2SDO1 Enable I2S Data Output 1 alternative function to port pin:-

0 - GPIO function
1 - I2S Data Output 1
EN_I2SDO2 Enable I2S Data Output 2 alternative function to port pin:-

0 - GPIO function
1 - I2S Data Output 2
EN_I2SCLK Enable I2S Clock Output alternative function to port pin:-

0 - GPIO function
1 - I2S Clock Output
EN_I2SWS Enable I2S Word Select alternative function to port pin:-

0 - GPIO function
1 - I2S Word Select
rds_clkin For RDS debugging / evaluation only.
IE A8H EA ES2 ECC EDET ET1 EX1 ET0 EX0 00H
EA Disable all interrupts (0), or use individual interrupt enable bits (1)
ES2 Enable I2C interrupt.
ECC Enable Closed Caption interrupt
EDET Enable Supply Dip Monitor Interrupt.
ET1 Enable Timer 1 interrupt
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UOCIII series
EX1 Enable External interrupt 1
ET0 Enable Timer 0 interrupt
EX0 Enable External interrupt 0
IEN1 84H - - - EX2 ERDS EUART ET2PR EBUSY 00H
EX2 Enable External Interrupt 2.
ERDS Enable RDS/RBDS Interrupt.
EUART Enable UART Interrupt.
ET2PR Enable Timer 2 interrupt
EBUSY Enable BUSY interrupt
IP B8H 0 PES2 PCC PDET PT1 PX1 PT0 PX0 00H
PES2 Priority I2C interrupt
PCC Priority Closed Caption Interrupt
PDET Priority Supply Dip Monitor Interrupt.
PT1 Priority Timer 1 interrupt
PX1 Priority External Interrupt 1
PT0 Priority Timer 0 interrupt
PX0 Priority External Interrupt 0
IP1 85H - - - PX2 PRDS PUART PT2PR PBUSY 00H
PX2 Priority External Interrupt 2.
PRDS Priority RDS/RBDS Interrupt.
PUART Priority UART Interrupt.
PT2PR Priority Timer 2 interrupt
PBUSY Priority BUSY Interrupt
P0 80H Reserved Reserved P0<5> P0<4> P0<3> P0<2> P0<1> P0<0> 00H
P0<5:0> Port 0 I/O register connected to external pins
P1 90H P1<7> P1<6> P1<5> P1<4> P1<3> P1<2> P1<1> P1<0> C3H
P2 A0H Reserved Reserved P2<5> P2<4> P2<3> P2<2> P2<1> P2<0> 00H
P3 B0H Reserved Reserved Reserved Reserved P3<3> P3<2> P3<1> P3<0> C0H
P0CFGA 96H Reserved Reserved P0CFGA<5> P0CFGA<4> P0CFGA<3> P0CFGA<2> P0CFGA<1> P0CFGA<0> 00H
P0CFGB 97H Reserved Reserved P0CFGB<5> P0CFGB<4> P0CFGB<3> P0CFGB<2> P0CFGB<1> P0CFGB<0> 00H
P0CFGB<x>/P0CFGA<x> = 00 MODE 0 Open Drain
P0CFGB<x>/P0CFGA<x> = 01 MODE 1 Quasi Bi-Directional
P0CFGB<x>/P0CFGA<x> = 10 MODE2 High Impedance
2003 Nov 11 36
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UOCIII series
P0CFGB<x>/P0CFGA<x> = 11 MODE3 Push Pull
P1CFGA 9EH P1CFGA<7> P1CFGA<6> P1CFGA<5> P1CFGA<4> P1CFGA<3> P1CFGA<2> P1CFGA<1> P1CFGA<0> 00H
P1CFGB 9FH P1CFGB<7> P1CFGB<6> P1CFGB<5> P1CFGB<4> P1CFGB<3> P1CFGB<2> P1CFGB<1> P1CFGB<0> 00H
P2CFGA A6H Reserved Reserved P2CFGA<5> P2CFGA<4> P2CFGA<3> P2CFGA<2> P2CFGA<1> P2CFGA<0> 00H
P2CFGB A7H Reserved Reserved P2CFGB<5> P2CFGB<4> P2CFGB<3> P2CFGB<2> P2CFGB<1> P2CFGB<0> 00H
P3CFGA BEH Reserved Reserved Reserved Reserved P3CFGA<3> P3CFGA<2> P3CFGA<1> P3CFGA<0> 00H
P3CFGB BFH Reserved Reserved Reserved Reserved P3CFGB<3> P3CFGB<2> P3CFGB<1> P3CFGB<0> 00H
P3CFGB<x>/P3CFGA<x> = 01 MODE 1 Quasi Bi-directional
PCON 87H SMOD ARD RFI WLE GF1 GF0 PD IDL 00H
SMOD UART Baud Rate Double Control
ARD Auxiliary RAM Disable, All MOVX instructions access the off-chip data memory.
‘0’: Enable
‘1’: Disable
In application mode, this bit should keep ‘0’.
RFI Disable ALE during internal access to reduce Radio Frequency Interference
’0’: Enable
’1’: Disable
WLE Watch Dog Timer enable

’0’: Disable
’1’: Enable
GF1 General purpose flag
GF0 General purpose flag
PD Power-down activation bit
IDL Idle mode activation bit
PSW D0H C AC F0 RS<1> RS<0> OV - P 00H
C Carry Bit
AC Auxiliary Carry bit
F0 Flag 0, General purpose flag
2003 Nov 11 37
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UOCIII series
RS<1:0> Register Bank selector bits

RS<1:0> = 00, Bank0 (00H - 07H)
RS<1:0> = 01, Bank1 (08H - 0FH)
RS<1:0> = 10, Bank2 (10H - 17H)
RS<1:0> = 11, Bank3 (18H - 1FH)
OV Overflow flag
P Parity bit
PWM0 D5H PW0E Reserved (0) PW0V<5> PW0V<4> PW0V<3> PW0V<2> PW0V<1> PW0V<0> 00H
PW0E 0 - Disable Pulse Width Modulator 0

1 - Enable Pulse Width Modulator 0
PW0V<5:0> Pulse Width Modulator high time
PWM1 D6H PW1E 0 PW1V<5> PW1V<4> PW1V<3> PW1V<2> PW1V<1> PW1V<0> 00H

PWM2 E4H PW2E 0 PW2V<5> PW2V<4> PW2V<3> PW2V<2> PW2V<1> PW2V<0> 00H

PWM3 DCH PW3E 0 PW3V<5> PW3V<4> PW3V<3> PW3V<2> PW3V<1> PW3V<0> 00H

PWM4 DDH PW4E 0 PW4V<5> PW4V<4> PW4V<3> PW4V<2> PW4V<1> PW4V<0> 00H

RCP1 86H DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0> 00H
DAT<7:0> Data location shared by CDIV<7:0>, AL<7:0>, AH<7:0>, BL<7:0>, BH<7:0>

Reset value of CDIV<7:0>, AL<7:0>, and BL<7:0> are 00H; reset value of AH<7:0> and BH<7:0> are FFH.
RCP2 95H - - - - DAT<11> DAT<10> DAT<9> DAT<8> X0H
DAT<11:8> Data location shared by CDIV<11:8>, AL<11:8>, AH<11:8>, BL<11:8> and BH<11:8>
Reset value of CDIV<11:8>, AL<11:8>, and BL<11:8> are 0H; reset value of AH<11:8> and BH<11:8> are FH.
RCP3 8EH RA<7> RA<6> RA<5> RA<4> RA<3> RA<2> RA<1> RA<0> 00H
RA<7:0> LOW time Result (bit 7:0) minus AL
RCP4 8FH RB<11> RB<10> RB<9> RB<8> RA<11> RA<10> RA<9> RA<8> 00H
RB<11:8> High time Result (bit 11:8)
RA<11:8> LOW time Result (bit 11:8)
RCP5 9BH RB<7> RB<6> RB<5> RB<4> RB<3> RB<2> RB<1> RB<0> 00H
RB<7:0> High time Result (bit 7:0) minus BL
RCP6 EFH RCP ON NFP NGP 0 0 RCPSET<2> RCPSET<1> RCPSET<0> 00H
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UOCIII series
RCP ON 0 - Remote Control Pre-processor disable

1 - Remote Control Pre-processor enable
NFP 0 - First Pulse

1 - Not First Pulse
NGP 0 - Good Pulse

1 - Not Good Pulse
RCPSET<2:0> Define DAT<11:0> value:-

000 - CDIV<11:0> is accessed via DAT<11:0>, default = 000H
001 - AL<11:0> is accessed via DAT<11:0>, default = 000H
010 - AH<11:0> is accessed via DAT<11:0>, default = FFFH
011 - BL<11:0> is accessed via DAT<11:0>, default = 000H
100 - BH<11:0> is accessed via DAT<11:0>, default = FFFH
101 - SPF<11:0> is accessed via DAT<11:0>, default = 003H
RDS_STAT E9H SYNC DOFL RSTD LBIN<2> LBIN<1> LBIN<0> ELB<1> ELB<0> 1CH
SYNC Synchronization found
DOFL Data overflow flag
RSTD Reset detected
LBIN<2:0> Last block identification

LBIN<2:0>=000, block A
LBIN<2:0>=001, block B
LBIN<2:0>=010, block C
LBIN<2:0>=011, block D
LBIN<2:0>=100, block C’
LBIN<2:0>=101, block E (RBDS mode)
LBIN<2:0>=110, invalid block E (RDS mode)
LBIN<2:0>=111, invalid block
ELB<1:0> Error status last block

ELB<1:0>=00, no errors detect
ELB<1:0>=01, max. 2 bits
ELB<1:0>=10, max. 5 bits
ELB<1:0>=11, uncorrectable block
RDS_LDATH EAH LDAT<15> LDAT<14> LDAT<13> LDAT<12> LDAT<11> LDAT<10> LDAT<9> LDAT<8> 00H
LDAT<15:8> Last processed block data high byte
RDS_LDATL EBH LDAT<7> LDAT<6> LDAT<5> LDAT<4> LDAT<3> LDAT<2> LDAT<1> LDAT<0> 00H
LDAT<7:0> Last processed block data low byte
RDS_PDATH ECH PDAT<15> PDAT<14> PDAT<13> PDAT<12> PDAT<11> PDAT<10> PDAT<9> PDAT<8> 00H
PDAT<15:8> Previous processed block data high byte
RDS_PDATL EDH PDAT<7> PDAT<6> PDAT<5> PDAT<4> PDAT<3> PDAT<2> PDAT<1> PDAT<0> 00H
PDAT<7:0> Previous processed block data low byte
RDS_CNT1 F1H BBC<5> BBC<4> BBC<3> BBC<2> BBC<1> BBC<0> EPB<1> EPB<0> 00H
BBC<5:0> Bad Blocks Counter
EPB<1:0> Error Status Previous Block

EPB<1:0>=00 - no errors detected
EPB<1:0>=01 - burst error of maximum 2 bits corrected
EPB<1:0>=10 - burst error of maximum 5 bits corrected
EPB<1:0>=11 - uncorrectable block
RDS_CNT2 F2H GBC<5> GBC<4> GBC<3> GBC<2> GBC<1> PBIN<2> PBIN<1> PBIN<0> 07H
GBC<5:1> Good Blocks Counter (Only 5 MSBs are available)
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UOCIII series
PBIN<2:0> Previous Block Identification

PBIN<2:0>=000 - block A
PBIN<2:0>=001 - block B
PBIN<2:0>=010 - block C
PBIN<2:0>=011 - block D
PBIN<2:0>=100 - block C’
PBIN<2:0>=101 - block E (RBDS mode)
PBIN<2:0>=110 - invalid block E (RDS mode)
PBIN<2:0>=111 - invalid block
RDS_CTRL1 F3H - RBDS MBBL<5> MBBL<4> MBBL<3> MBBL<2> MBBL<1> MBBL<0> 20H
RBDS Allow RBDS ‘E’ Block

‘0’ - RDS mode
‘1’ - RBDS mode
MBBL<5:0> Max Bad Block Lose
RDS_CTRL2 F4H SYM<1> SYM<0> MGBL<5> MGBL<4> MGBL<3> MGBL<2> MGBL<1> MGBL<0> 20H
SYM<1:0> Synchronization Mode

SYM<1:0>=00 - no error correction
SYM<1:0>=01 - error correction of a burst error maximum 2 bits
SYM<1:0>=10 - error correction of a burst error maximum 5 bits
SYM<1:0>=11 - no error correction
MGBL<5:0> Max Good Block Lose
RDS_CTRL3 F5H DAC<1> DAC<0> NWSY MBBG<4> MBBG<3> MBBG<2> MBBG<1> MBBG<0> 00H
DAC<1:0> Data output control

DAC<1:0>=00, standard mode
DAC<1:0>=01, fast PI search mode
DAC<1:0>=10, reduced data request
DAC<1:0>=11, decoder bypass
NWSY Start new synchronization
MBBG<4:0> Max bad blocks gain
RDS_F0_F1 E3H F0<3> F0<2> F0<1> F0<0> F1<3> F1<2> F1<1> F1<0> 32H
F0<3:0> Coarse Division Factor F0
F1<3:0> Coarse Division Factor F1
RDS_COEF_H E5H COEF<15> COEF<14> COEF<13> COEF<12> COEF<11> COEF<10> COEF<9> COEF<8> 4BH
COEF<15:8> DCS Coefficient High Byte
RDS_COEF_L E6H COEF<7> COEF<6> COEF<5> COEF<4> COEF<3> COEF<2> COEF<1> COEF<0> CAH
COEF<7:0> DCS Coefficient Low Byte
ROMBK FBH STANDBY SW_RST TEMP_140 TEMP_130 0 ROMBK<2> ROMBK<1> ROMBK<0> 00H
STANDBY 0 - Disable Stand-by Mode

1 - Enable Stand-by Mode
SW_RST 0 - Disable Software Reset

1 - Enable Software Reset
TEMP_140 0 - Temperature of the device below 140C

1 - Temperature of the device above 140C
TEMP_130 0 - Temperature of the device below 130C

1 - Temperature of the device above 130C
2003 Nov 11 40
CONFIDENTIAL

UOCIII series
ROMBK<2:0> ROM Bank selection

ROMBK<2:0> = 000, Bank0
ROMBK<2:0> = 001, Bank1
ROMBK<2:0> = 010, Bank2
ROMBK<2:0> = 011, Bank3
ROMBK<2:0> = 100, Bank4
ROMBK<2:0> = 101, Bank5
ROMBK<2:0> = 110, Bank6
ROMBK<2:0> = 111, Reserved
S0BUF 9AH S0BUF<7> S0BUF<6> S0BUF<5> S0BUF<4> S0BUF<3> S0BUF<2> S0BUF<1> S0BUF<0> 00H
S0BUF<7:0> UART data buffer
S0CON 99H SM<0> SM<1> SM<2> REN TB8 RB8 TI RI 00H
SM<0:1> UART Mode selection bits

SM<0:1> = 00, Shift Register
SM<0:1> = 01, 8-bit UART (variable baud rate)
SM<0:1> = 10, 9-bit UART
SM<0:1> = 11, 9-bit UART (variable baud rate)
SM<2> Enables the multi processor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if the
received 9th data bit is ’0’. In mode 1, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if no valid stop bit was received. In mode 0, SM2 has no
influence.
REN Enables serial reception. Set by software to enable reception. Cleared by software to disable reception.
TB8 Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired.
RB8 In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 is ’0’, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Loading of RB8 in modes
1, 2 and 3 depends on SM2.
TI Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software.
RI Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see
SM2). Must be cleared by software.
S1ADR DBH ADR<6> ADR<5> ADR<4> ADR<3> ADR<2> ADR<1> ADR<0> GC 00H
ADR<6:0> I2C Slave Address
GC 0 - Disable I2C general call address

1 - Enable I2C general call address
S1CON D8H EN_I2CINT ENSI STA STO SI AA 0 0 00H
EN_I2CINT Setting by software

0- the I2C interrupt signal is always non-active
1- the I2C interrupt signal is activated when if the SI is set
ENSI 0 - Disable I2C interface

1 - Enable I2C interface
STA START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus becomes free. If the device
operates in master mode it will generate a repeated START condition.
STO STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also be set in slave mode in
order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases the SDA and SCL lines and switches to the not
selected receiver mode. The STOP flag is cleared by the hardware
SI Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur:
-A START condition is generated in master mode.
-The own slave address has been received during AA=1
-The general call address has been received while S1ADR.GC and AA=1
-A data byte has been received or transmitted in master mode (even if arbitration is lost)
-A data byte has been received or transmitted as selected slave
A STOP or START condition is received as selected slave receiver or transmitter
While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software.
2003 Nov 11 41
CONFIDENTIAL

UOCIII series
AA Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions
-Own slave address is received.
-General call address is received(S1ADR.GC=1)
-A data byte is received, while the device is programmed to be a master receiver
-A data byte is received, while the device is selected slave receiver
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received.
S1DAT DAH DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0> 00H
DAT<7:0> I2C Data
S1STA D9H STAT<4> STAT<3> STAT<2> STAT<1> STAT<0> 0 0 0 F8H
STAT<4:0> I2C Interface Status
SAD E8H VHI CH<1> CH<0> ST SAD<7> SAD<6> SAD<5> SAD<4> 00H
VHI 0 - Analogue input voltage less than or equal to DAC voltage

1 - Analogue input voltage greater then DAC voltage
CH<1:0> ADC Input channel select

CH<1:0> = 00,ADC3
CH<1:0> = 01,ADC0
CH<1:0> = 10,ADC1
CH<1:0> = 11,ADC2
ST Initiate voltage comparison between ADC input Channel and SAD<7:0> value
Note: Set by Software and reset by Hardware
SAD<7:4> Most Significant nibble of DAC input word
SADB 98H SSD_ON - - DC_COMP SAD<3> SAD<2> SAD<1> SAD<0> 80H
SSD_ON 0 - Disable SSD Function

1 - Enable SSD Function
DC_COMP 0 - Disable DC Comparator mode

1 - Enable DC Comparator mode
SAD<3:0> Least Significant nibble of 8 bit SAD value
SCAVTXT F9H SCAVEM_ 0 0 PULSE_ PULSE_ EARLY<2> EARLY<1> EARLY<0> 00H

EN WIDTH<1> WIDTH<0>
SCAVEM_EN 0 - Disable scavem text output for R, G, and B signals

1 - Enable scavem text output for R, G, and B signals
PULSE_WIDTH<1:0> SCAVEM Text signal pulse width

PULSE_WIDTH<1:0>=00, 37ns
EARLY<2:0> SCAVEM Text output to Video Signal Processor earlier than R,G, and B signals
EARLY<2:0>=000, 0 ns
EARLY<2:0>=001, 74 ns
EARLY<2:0>=010, 111 ns
EARLY<2:0>=011, 148 ns
EARLY<2:0>=100, 185 ns
EARLY<2:0>=101, 212 ns
EARLY<2:0>=110, 259 ns
EARLY<2:0>=111, 296 ns
SP 81H SP<7> SP<6> SP<5> SP<4> SP<3> SP<2> SP<1> SP<0> 07H
SP<7> Stack Pointer
TCON 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
TF1 Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine
TR1 Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off
TF0 Timer 0 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine
2003 Nov 11 42
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UOCIII series
TR0 Timer 0 Run control bit. Set/Cleared by software to turn Timer/Counter on/off
IE1 Interrupt 1 Edge flag (both edges generate flag). Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.
IT1 Interrupt 1 Type control bit. Set/Cleared by Software to specify edge/low level triggered external interrupts.
IE0 Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.
IT0 Interrupt 0 Type flag.Set/Cleared by Software to specify falling edge/low level triggered external interrupts
TDACH D3H TPWE 0 TD<13> TD<12> TD<11> TD<10> TD<9> TD<8> 00H
TPWE 0 - Disable Tuning Pulse Width Modulator

1 - Enable Tuning Pulse Width Modulator
TD<13:8> Tuning Pulse Width Modulator High Byte
TDACL D2H TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0> 00H
TD<7:0> Tuning Pulse Width Modulator Low Byte
TH0 8CH TH0<7> TH0<6> TH0<5> TH0<4> TH0<3> TH0<2> TH0<1> TH0<0> 00H
TH0<7:0> Timer 0 high byte
TH1 8DH TH1<7> TH1<6> TH1<5> TH1<4> TH1<3> TH1<2> TH1<1> TH1<0> 00H
TH1<7:0> Timer 1 high byte
TL0 8AH TL0<7> TL0<6> TL0<5> TL0<4> TL0<3> TL0<2> TL0<1> TL0<0> 00H
TL0<7:0> Timer 0 low byte
TL1 8BH TL1<7> TL1<6> TL1<5> TL1<4> TL1<3> TL1<2> TL1<1> TL1<0> 00H
TL1<7:0> Timer 1 low byte
TMOD 89H GATE C/T M1 M0 GATE C/T M1 M0 00H
Timer / Counter 1 Timer / Counter 0
GATE Gating Control Timer /Counter 1
C/T Counter/Timer 1 selector
M1,M0 Mode control bits Timer/Counter 1

M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler
M1,M0 = 01, 16 bit time interval or event counter
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH1
M1,M0 = 11, stopped
GATE Gating control Timer/Counter 0
C/T Counter/Timer 0 selector
M1,M0 Mode Control bits Timer/Counter 0

M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler
M1,M0 = 01, 16 bit time interval or event counter
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0
M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter
TP2CL 9CH TP2CL<7> TP2CL<6> TP2CL<5> TP2CL<4> TP2CL<3> TP2CL<2> TP2CL<1> TP2CL<0> 00H
TP2CL<7:0> Indicate the low byte of the Time 2 current value.
TP2CH 9DH TP2CH<7> TP2CH<6> TP2CH<5> TP2CH<4> TP2CH<3> TP2CH<2> TP2CH<1> TP2CH<0> 00H
TP2CH<7:0> Indicate the high byte of the Time 2 current value.
2003 Nov 11 43
CONFIDENTIAL

UOCIII series
TP2H 92H TP2H<7> TP2H<6> TP2H<5> TP2H<4> TP2H<3> TP2H<2> TP2H<1> TP2H<0> 00H
TP2H<7:0> Timer 2 high byte, never change unless updated by the software.
TP2L 91H TP2L<7> TP2L<6> TP2L<5> TP2L<4> TP2L<3> TP2L<2> TP2L<1> TP2L<0> 00H
TP2L<7:0> Timer 2 low byte, never change unless updated by the software.
TP2PR 93H TP2PR<7> TP2PR<6> TP2PR<5> TP2PR<4> TP2PR<3> TP2PR<2> TP2PR<1> TP2PR<0> 00H
TP2PR<7:0> Timer 2 Pre-scaler, never change unless updated by the software
TP2CRL 94H - - - - - - TP2CRL<1> TP2CRL<0> 00H
TP2CRL<0> Timer 2 Control.

0 - Timer 2 disabled.
1 - Timer 2 enabled.
TP2CRL<1> Timer 2 Status.

0 - No Overflow.
1 - Overflow.
TEST FDH TEST<7> TEST<6> TEST<5> TEST<4> TEST<3> TEST<2> TEST<1> TEST<0> A0H
TEST<7:0> For internal testing use.
TXT0 C0H X24 POSN DISPLAY X24 AUTO DISABLE DISPLAY DISABLE VPS ON INV ON 00H
FRAME HEADER STATUS ROW FRAME
ROLL ONLY
X24 POSN 0 - Store X/24 in extension memory

1 - Store X/24 in basic page memory with packets 0 to 23
DISLAY X24 0 - Display row 24 from basic page memory

1 - Display row 24 from appropriate location in extension memory
AUTO FRAME 0 - Normal Frame output

1 - Frame output is switched off automatically if any video displayed
DISABLE HEADER ROLL 0 - Write rolling headers and time to current display page
1 - Disable writing of rolling headers and time to into memory
DISPLAY STATUS ROW 0 - Display normal page rows 0 to 24

ONLY 1- Display only row 24
DISABLE FRAME 0 - Normal Frame output

1 - Force Frame output to be low (0)
VPS ON 0 - VPS acquisition off

1 - VPS acquisition on
INV ON 0 - Inventory page off

1 - Inventory page on
TXT1 C1H EXT PKT OFF 8 BIT ACQ OFF X26 OFF full-field FIELD H POLARITY V POLARITY 00H
POLARITY
EXT PKT OFF 0 - Acquire extension packets X/24,X/27,8/30/X

1 - Disable acquisition of extension packets
8 BIT 0 - Error check and/or correct packets 0 to 24

1 - Disable checking of packets 0 to 24 written into memory
ACQ OFF 0 - Write requested data into display memory

1 - Disable writing of data into Display memory
X26 OFF 0 - Enable automatic processing of X/26 data

1 - Disable automatic processing of X/26 data
full-field unused, must keep reset value -> ‘0’
2003 Nov 11 44
CONFIDENTIAL

UOCIII series
FIELD POLARIY 0 - Vsync pulse in first half of line during even field
1 - Vsync pulse in second half of line during even field
For MCM package, this bit should be set to ‘1’
H POLARITY 0 - Hsync reference edge is positive going

1 - Hsync reference edge is negative going
V POLARITY 0 - Vsync reference edge is positive going

1 - Vsync reference edge is negative going
TXT2 C2H ACQ REQ<3> REQ<2> REQ<1> REQ<0> SC<2> SC<1> SC<0> 00H
BANK<0>
ACQ_BANK<0> Should combine TXT3 ACQ_BANK<3:1>
REQ<3:0> Page request
SC<2:0> Start column of page request
TXT3 C3H ACQ ACQ ACQ PRD<4> PRD<3> PRD<2> PRD<1> PRD<0> 00H
BANK<3> BANK<2> BANK<1>
ACQ_BANK Combine with TXT2 ACQ_BANK<0>

<3:1> 0000 - Select BLOCK 0 ~ 9 for acquisition storage
0001 - Reserved
0010 - Reserved
0011 - Reserved
0100 - Reserved
0101 - Reserved
0110 - Reserved
0111 - Reserved
1000 - Reserved
1001 - Reserved
1010 - Reserved
1011 - Reserved
1100 - Reserved
1101 - Reserved
1110 - Reserved
1111 - Reserved
PRD<4:0> Page Request data
TXT4 C4H OSD BANK QUAD EAST/WEST DISABLE 0 0 TRANS SHADOW 00H
ENABLE WIDTH DBL HEIGHT ENABLE ENABLE
ENABLE
OSD BANK ENABLE 0 - Only alpha numeric OSD characters available, 32 locations
1 - Alternate OSD location available via graphic attribute, additional 32 location
QUAD WIDTH ENABLE 0 - Disable display of Quadruple width characters

1 - Enable display of Quadruple width characters
EAST/WEST 0 - Western language selection of character codes A0 to FF

1 - Eastern character selection of character codes A0 to FF
DISABLE DOUBLE 0 - Allow normal decoding of double height characters

HEIGHT 1 - Disable normal decoding of double height characters
TRANS ENABLE 0 - Display black background as normal

1 - Display black background as video
SHADOW ENABLE 0 - Disable display of shadow/fringing

1 - Display shadow/ fringe (default SE black)
TXT5 C5H BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON PICTURE ON 03H
OUT IN
BKGND OUT 0 - Background colour not displayed outside teletext boxes(teletext page)
1 - Background colour displayed outside teletext boxes(teletext page)
BKGND IN 0 - Background colour not displayed inside teletext boxes(teletext page)

1 - Background colour displayed inside teletext boxes(teletext page)
2003 Nov 11 45
CONFIDENTIAL

UOCIII series
COR OUT 0 - COR not active outside teletext and OSD boxes(teletext page)
1 - COR active outside teletext and OSD boxes(teletext page)
COR IN 0 - COR not active inside teletext and OSD boxes(teletext page)
1 - COR active inside teletext and OSD boxes(teletext page)
TEXT OUT 0 - TEXT not displayed outside teletext boxes(teletext page)

1 - TEXT displayed outside teletext boxes(teletext page)
TEXT IN 0 - TEXT not displayed inside teletext boxes(teletext page)

1 - TEXT displayed inside teletext boxes(teletext page)
PICTURE ON OUT 0 - VIDEO not displayed outside teletext boxes(teletext page)

1 - VIDEO displayed outside teletext boxes(teletext page)
PICTURE ON IN 0 - VIDEO not displayed inside teletext boxes(teletext page)

1 - VIDEO displayed inside teletext boxes(teletext page)
TXT6 C6H BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON PICTURE ON 03H
OUT IN
BKGND OUT 0 - Background colour not displayed outside teletext boxes(newsflash/subtitle)

1 - Background colour displayed outside teletext boxes(newsflash/subtitle)
BKGND IN 0 - Background colour not displayed inside teletext boxes(newsflash/subtitle)

1 - Background colour displayed inside teletext boxes(newsflash/subtitle)
COR OUT 0 - COR not active outside teletext and OSD boxes(newsflash/subtitle)
1 - COR active outside teletext and OSD boxes(newsflash/subtitle)
COR IN 0 - COR not active inside teletext and OSD boxes(newsflash/subtitle)

1 - COR active inside teletext and OSD boxes(newsflash/subtitle)
TEXT OUT 0 - TEXT not displayed outside teletext boxes(newsflash/subtitle)

1 - TEXT displayed outside teletext boxes(newsflash/subtitle)
TEXT IN 0 - TEXT not displayed inside teletext boxes(newsflash/subtitle)

1 - TEXT displayed inside teletext boxes(newsflash/subtitle)
PICTURE ON OUT 0 - VIDEO not displayed outside teletext boxes(newsflash/subtitle)

1 - VIDEO displayed outside teletext boxes(newsflash/subtitle)
PICTURE ON IN 0 - VIDEO not displayed inside teletext boxes(newsflash/subtitle)

1 - VIDEO displayed inside teletext boxes(newsflash/subtitle)
TXT7 C7H STATUS ROW CURSOR ON REVEAL BOTTOM/ DOUBLE BOX ON 24 BOX ON 1-23 BOX ON 0 00H
TOP TOP HEIGHT
STATUS ROW TOP 0 - Display memory row 24 information below teletext page (on display row 24)
1 - Display memory row 24 information above teletext page (on display row 0)
CURSOR ON 0 - Disable display of cursor

1 - Display cursor at position given by TXT9 and TXT10
REVEAL 0 - Display as spaces characters in area with conceal attribute set

1 - Display characters in area with conceal attribute set
BOTTOM/TOP 0 - Display memory rows 0 to 11 when double height bit is set

1 - Display memory rows 12 to 23 when double height bit is set
DOUBLE HEIGHT 0 - Display each characters with normal height

1 - Display each character as twice normal height.
BOX ON 24 0 - Disable display of teletext boxes in memory row 24

1 - Enable display of teletext boxes in memory row 24
BOX ON 1-23 0 - Disable display of teletext boxes in memory row 1 to 23

1 - Enable display of teletext boxes in memory row 1 to 23
BOX ON 0 0 - Disable display of teletext boxes in memory row 0

1 - Enable display of teletext boxes in memory row 0
2003 Nov 11 46
CONFIDENTIAL

UOCIII series
TXT8 C8H (Reserved) FLICKER HUNT DISABLE PKT 26 WSS WSS ON (Reserved) 00H
0 STOP ON SPANISH RECEIVED RECEIVED 0
FLICKER STOP ON 0 - Enable ‘Flicker Stopper’ circuitry

1 - Disable ‘Flicker Stopper’ circuitry
HUNT 0 - Allow automatic hunting for amplitude of data to be acquired

1 - Disable automatic hunting for amplitude
DISABLE SPANISH 0 - Enable special treatment of Spanish packet 26 characters

1 - Disable special treatment of Spanish packet 26 characters
PKT 26 RECEIVED 0 - No packet 26 data has been processed

1 - Packet 26 data has been processed.
Note: This flag is set by Hardware and must be reset by Software
WSS RECEIVED 0 - No Wide Screen Signalling data has been processed

1 - Wide Screen signalling data has been processed
Note: This flag is set by Hardware and must be reset by Software.
WSS ON 0 - Disable acquisition of WSS data.

1 - Enable acquisition of WSS data.
TXT9 C9H CURSOR CLEAR A0 R<4> R<3> R<2> R<1> R<0> 00H
FREEZE MEMORY
CURSOR FREEZE 0 - Use current TXT9 and TXT10 values for cursor position.
1 - Lock cursor at current position
CLEAR MEMORY 0 - Clear memory action is finished

1 - Clear memory block pointed to by TXT15
Note: This flag is set by Software and reset by Hardware
A0 0 - Access memory block pointed to by TXT15

1 - Access extension packet memory
R<4:0> Current memory ROW value.

Note: Valid range TXT mode 0 to 24, CC mode 0 to 15
TXT10 CAH CHAR - C<5> C<4> C<3> C<2> C<1> C<0> 00H
16/12
CHAR A 16/12 Character Matrix width on Display Page A and B

0 - 12 pixel width
1 - 16 pixel width
C<5:0> Current memory COLUMN value.

Note: Valid range TXT mode 0 to 39, CC mode 0 to 47
TXT11 CBH D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> 00H
D<7:0> Data value written or read from memory location defined by TXT9, TXT10 and TXT15
TXT12 CCH 625/525 SYNC ROM VER<4> ROM VER<3> ROM VER<2> ROM VER<1> ROM VER<0> 1 VIDEO xxxxxx1xB
SIGNAL
QUALITY
625/525 SYNC 0 - 625 line CVBS signal is being received

1 - 525 line CVBS signal is being received
ROM VER<4> Mask programmable identification for character set

ROM Version <4>:
0 - Spanish Flicker Stopper Disabled.
1 - Spanish Flicker Stopper Enabled (Controlled by TXT8 Bit-6).
ROM VER<3:0> General purpose register, bits defined by mask programmable bits
1 Reserved
VIDEO SIGNAL 0 - Acquisition can not be synchronised to CVBS input.

QUALITY 1 - Acquisition can be synchronised to CVBS
2003 Nov 11 47
CONFIDENTIAL

UOCIII series
TXT13 F8H VPS PAGE 525 DISPLAY 525 TEXT 625 TEXT PKT 8/30 FASTEXT 0 xxxxxxx0B
RECEIVED CLEARING
VPS RECEIVED 0 - VPS data not being received

1 - VPS data being received
PAGE CLEARING 0 - No page clearing active

1 - Software or Power On page clear in progress
525 DISPLAY 0 - 625 Line synchronisation for Display

1 - 525 Line synchronisation for Display
525 TEXT 0 - 525 Line WST not being received

1 - 525 line WST being received
625 TEXT 0 - 625 Line WST not being received

1 - 625 line WST being received
PKT 8/30 0 - No Packet 8/30/x(625) or Packet 4/30/x(525) data detected

1 - Packet 8/30/x(625) or Packet 4/30/x(525) data detected
FASTEXT 0 - No Packet x/27 data detected

1 - Packet x/27 data detected
0 Reserved
TXT14 CDH DISPLAY DISPLAY DISPLAY DISPLAY PAGE<3> PAGE<2> PAGE<1> PAGE<0> 00H
DISPLAY 0000 - Select Page 0 ~ 9 for Display

BANK <3:0> 0001 - Reserved
0010 - Reserved
0011 - Reserved
0100 - Reserved
0101 - Reserved
0110 - Reserved
0111 - Reserved
1000 - Reserved
1001 - Reserved
1010 - Reserved
1011 - Reserved
1100 - Reserved
1101 - Reserved
1110 - Reserved
1111 - Reserved
PAGE<3:0> Current Display page
TXT15 CEH MICRO MICRO MICRO MICRO BLOCK<3> BLOCK<2> BLOCK<1> BLOCK<0> 00H
MICRO 0000 - Select BLOCK 0 ~ 9 for Micro

BANK<3:0> 0001 - Reserved
0010 - Reserved
0011 - Reserved
0100 - Reserved
0101 - Reserved
0110 - Reserved
0111 - Reserved
1000 - Reserved
1001 - Reserved
1010 - Reserved
1011 - Reserved
1100 - Reserved
1101 - Reserved
1110 - Reserved
1111 - Reserved
BLOCK<3:0> Current Micro block to be accessed by TXT9, TXT10 and TXT11
TXT17 B9H 0 FORCE FORCE FORCE FORCE SCREEN SCREEN SCREEN 00H
ACQ<1> ACQ<0> DISP<1> DISP<0> COL2 COL1 COL0
2003 Nov 11 48
CONFIDENTIAL

UOCIII series
FORCE ACQ<1:0> 00 - Automatic Selection

01 - Force 525 timing, Force 525 Teletext Standard
FORCE DISP<1:0> 00 - Automatic Selection

01 - Force Display to 525 mode (9 lines per row)
10 - Force Display to 625 mode (10 lines per row)
11 - Not Valid (default to 625)
SCREEN COL<2:0> Defines colour to be displayed instead of TV picture and black background. The bits <2:0> are equivalent to the RGB components
000 - Transparent
001 - CLUT entry 9
010 - CLUT entry 10
011- CLUT entry 11
100 - CLUT entry 12
101 - CLUT entry 13
110- CLUT entry 14
111 - CLUT entry 15
TXT18 B2H NOT<3> NOT<2> NOT<1> NOT<0> 0 field_indent BS<1> BS<0> 00H
NOT<3:0> National Option table selection, maximum of 32 when used with East/West bit
field_indent unused, must keep reset value -> ‘0’
BS<1:0> Basic Character set selection
TXT19 B3H TEN TC<2> TC<1> TC<0> 0 0 TS<1> TS<0> 00H
TEN 0 - Disable Twist function

1- Enable Twist character set
TC<2:0> Language control bits (C12/C13/C14) that has Twisted character set
TS<1:0> Twist Character set selection
TXT20 B4H DRCS OSD PLANES EXTENDED CHAR OSD LANG OSD LAN<2> OSD LAN<1> OSD LAN<0> 00H
ENABLE SPECIAL SELECT ENABLE
GRAPHICS ENABLE
DRCS ENABLE 0 - Normal OSD characters used

1 - Re-map column 9 to DRCS (TXT and CC modes),
OSD PLANES 0 - Character code columns 8 and 9 defined as single plane characters
1- Character code columns 8 and 9 defined as double plane characters
EXTENDED SPECIAL 0 - Extended Special Graphics disabled (columns 8 & 9 only used for special graphics characters)
GRAPHICS 1 - Extended Special Graphics enabled (user definable range for special graphics characters)
CHAR SELECT ENABLE 0 - Disables character set selection in CC display mode

1 - Enables character set selection in CC display mode
OSD LANG ENABLE Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14
OSD LAN<2:0> Alternative C12/C13/C14 bits for use with OSD menus
TXT21 B5H DISP DISP CHAR CHAR Reserved 0) CC ON I2C PORT EN CC/TXT 02H
LINES<1> LINES<0> SIZE<1> SIZE<0>
DISP LINES<1:0> The number of display lines per character row.

00 - 10 lines per character (defaults to 9 lines in 525 mode)
01 - 13 lines per character
CHAR SIZE<1:0> Character matrix size.
01 - 13 lines per character (matrix 12x13)

2003 Nov 11 49
CONFIDENTIAL

UOCIII series
CCON 0 - Closed Caption acquisition off

1 - Closed Caption acquisition on
I2C PORT EN 0 - Disable I2C PORT EN

1 - Enable I2C PORT EN selection (P1.7/SDA0, P1.6/SCL0)
CC/TXT 0 - Display configured for TXT mode

1 - Display configured for CC mode
TXT22 B6H GPF<7> GPF<6> GPF<5> GPF<4> GPF<3> GPF<2> GPF<1> GPF<0> XXH
GPF<7:0> General purpose register, bits defined by mask programmable bits
TXT23 A9H NOT B<3> NOT B<2> NOT B<1> NOT B<0> EAST/WEST DRCS B BS B<1> BS B<0> 00H
B ENABLE
NOT B<3:0> National Option table selection for Page B, maximum of 32 when used with East/West bit
EAST/WEST B 0 - Western language selection of character codes A0 to FF on Page B

1 - Eastern language selection of character codes A0 to FF on Page B
DRCS B ENABLE 0 - Normal OSD characters used on Page B

1 - Re-map column 8/9 to DRCS (TXT and CC modes) on Page B
BS B<1:0> Basic Character set selection for Page B
TXT24 AAH BKGND OUT BKGND IN B COR OUT B COR IN B TEXT OUT B TEXT IN B PICTURE ON PICTURE ON 03H
B OUT B IN B
BKGND OUT B 0 - Background colour not displayed outside teletext boxes (Teletext page)
1 - Background colour displayed outside teletext boxes (Teletext page)
BKGND IN B 0 - Background colour not displayed inside teletext boxes (Teletext page)
1 - Background colour displayed inside teletext boxes (Teletext page)
COR OUT B 0 - COR not active outside teletext and OSD boxes (Teletext page)
1 - COR active outside teletext and OSD boxes (Teletext page)
COR IN B 0 - COR not active inside teletext and OSD boxes (Teletext page)
1 - COR active inside teletext and OSD boxes (Teletext page)
TEXT OUT B 0 - TEXT not displayed outside teletext boxes (Teletext page)
1 - TEXT displayed outside teletext boxes (Teletext page)
TEXT IN B 0 - TEXT not displayed inside teletext boxes (Teletext page)

1 - TEXT displayed inside teletext boxes (Teletext page)
PICTURE ON OUT B 0 - VIDEO not displayed outside teletext boxes (Teletext page)
1 - VIDEO displayed outside teletext boxes (Teletext page)
PICTURE ON 0 - VIDEO not displayed inside teletext boxes (Teletext page)

IN B 1 - VIDEO displayed inside teletext boxes (Teletext page)
TXT25 ABH BKGND OUT BKGND IN B COR OUT B COR IN B TEXT OUT B TEXT IN B PICTURE ON PICTURE ON 03H
B OUT B IN B
BKGND OUT B 0 - Background colour not displayed outside teletext boxes (Sub-Title / Newsflash page)
1 - Background colour displayed outside teletext boxes (Sub-Title / Newsflash page)
BKGND IN B 0 - Background colour not displayed inside teletext boxes (Sub-Title / Newsflash page)
1 - Background colour displayed inside teletext boxes (Sub-Title / Newsflash page)
COR OUT B 0 - COR not active outside teletext and OSD boxes (Sub-Title / Newsflash page)
1 - COR active outside teletext and OSD boxes (Sub-Title / Newsflash page)
COR IN B 0 - COR not active inside teletext and OSD boxes (Sub-Title / Newsflash page)
1 - COR active inside teletext and OSD boxes (Sub-Title / Newsflash page)
TEXT OUT B 0 - TEXT not displayed outside teletext boxes (Sub-Title / Newsflash page)
1 - TEXT displayed outside teletext boxes (Sub-Title / Newsflash page)
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UOCIII series
TEXT IN B 0 - TEXT not displayed inside teletext boxes (Sub-Title / Newsflash page)
1 - TEXT displayed inside teletext boxes (Sub-Title / Newsflash page)
PICTURE ON OUT B 0 - VIDEO not displayed outside teletext boxes (Sub-Title / Newsflash page)
1 - VIDEO displayed outside teletext boxes (Sub-Title / Newsflash page)
PICTURE ON IN B 0 - VIDEO not displayed inside teletext boxes (Sub-Title / Newsflash page)
1 - VIDEO displayed inside teletext boxes (Sub-Title / Newsflash page)
TXT26 ACH EXTENDED TRANS B 0 0 SHADOW BOX ON 24 B BOX ON 1-23 BOX ON 0 B 03H
DRCS ENABLE B B
EXTENDED DRCS 0 - Columns 8/9 mapped to DRCS when DRCS characters enabled (32 DRCS characters)
1 - Columns 8/9/A/C mapped to DRCS when DRCS characters enabled (64 DRCS characters)
TRANS ENABLE B 0 - Display black background as normal on Page B

1 - Display black background as video on Page B
SHADOW ENABLE B 0 - Disable display of shadow/fringing on Page B

1 - Display shadow/ fringe (default SE black) on Page B
BOX ON 24 B 0 - Disable display of teletext boxes in memory row 24 of Page B

1 - Enable display of teletext boxes in memory row 24 of Page B
BOX ON 1-23 B 0 - Disable display of teletext boxes in memory row 1 to 23 of Page B

1 - Enable display of teletext boxes in memory row 1 to 23 of Page B
BOX ON 0 B 0 - Disable display of teletext boxes in memory row 0 of Page B

1 - Enable display of teletext boxes in memory row 0 of Page B
TXT27 B1H - - - - RDS ON SCR B<2> SCR B<1> SCR B<0> 00H
RDS ON 0 - RDS/RBDS disable

1 - RDS/RBDS enable
SCR B<2:0> Defines colour to be displayed instead of TV picture and black background for Page B. The bits <2:0> are equivalent to the RGB components
000 - Transparent
001 - CLUT entry 9
010 - CLUT entry 10
011 - CLUT entry 11
100 - CLUT entry 12
101 - CLUT entry 13
110 - CLUT entry 14
111 - CLUT entry 15
TXT28 ADH DISPLAY DISPLAY DISPLAY DISPLAY PAGE B<3> PAGE B<2> PAGE B<1> PAGE B<0> 00H
BANK B<3> BANK B<2> BANK B<1> BANK B<0>
DISPLAY BANK 0000 - Select Page 0 ~ 9 for Display Page B

B<3:0> 0001 - Reserved
0010 - Reserved
0011 - Reserved
0100 - Reserved
0101 - Reserved
0110 - Reserved
0111 - Reserved
1000 - Reserved
1001 - Reserved
1010 - Reserved
1011 - Reserved
1100 - Reserved
1101 - Reserved
1110 - Reserved
1111 - Reserved
PAGE B<3:0> Current Display page for Page B
TXT29 E1H TEN B TS B <1> TS B <0> OSD PLANES OSD LANG OSD LAN B OSD LAN B OSD LAN B 00H
B ENABLE B <2> <1> <0>
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TEN B 0 - Disable Twist function for Page B

1 - Enable Twist character set for Page B
TS B<1:0> Twist Character set selection for Page B
OSD PLANES B 0 - Character code columns 8 and 9 defined as single plane characters for Display Page B
1 - Character code columns 8 and 9 defined as double plane characters (special graphics characters) for Display Page B
OSD LANG ENABLE B Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14 for Display Page B
OSD LAN B <2:0> Alternative C12/C13/C14 bits for use with OSD menus for Display Page B
TXT30 E2H TC B <2> TC B <1> TC B <0> BOTTOM/ DOUBLE STATUS ROW DISPLAY X24 DISPLAY 00H
TOP B HEIGHT TOP B B STATUS ROW
B ONLY B
TC B<2:0> Language control bits (C12/C13/C14) that has Twisted character set for Page B
BOTTOM/TOP 0 - Display memory rows 0 to 11 when double height bit is set on Display Page B
B 1 - Display memory rows 12 to 23 when double height bit is set on Display Page B
DOUBLE HEIGHT B 0 - Display each characters with normal height on Display Page B
1 - Display each character as twice normal height on Display Page B
STATUS ROW TOP B 0 - Display memory row 24 information below teletext page (on display row 24) on Display Page B
1 - Display memory row 24 information above teletext page (on display row 0) on Display Page B
DISLAY X24 B 0 - Display row 24 from basic page memory on Display Page B
1 - Display row 24 from appropriate location in extension memory on Display Page B
DISPLAY STATUS ROW 0 - Display normal page rows 0 to 24 on Display Page B

ONLY B 1 - Display only row 24 on Display Page B
TXT31 A1H 0 CC_TXT B ACTIVE 1V8GUARD GPF<11> GPF<10> GPF<9> GPF<8> 0XH
PAGE
CC/TXT B 0 - Display Page B configured for TXT mode

1 - Display Page B configured for CC mode
ACTIVE PAGE 0 - Display Page A active during two page mode

1 - Display Page B active during two page mode
1V8GUARD 0 - 1.8V supply is normal

1 - 1.8Vsupply is abnormal (1.44V)
GPF<11:8> General purpose register, bits defined by mask programmable bits
TXT32 A2H GPF<11> 9FF<11> 9FF<10> 9FF<9> 9FF<8> 9FF<7> 9FF<6> 9FF<5> XXH
GPF<11>,9FF<11:5> General purpose register, bits defined by mask programmable bits
TXT33 A3H BFE<7> BFE<6> BFE<5> BFE<4> BFE<3> BFE<2> BFE<1> BFE<0> XXH
BFE<7:0> General purpose register, bits defined by mask programmable bits
TXT34 A4H BFE<15> BFE<14> BFE<13> BFE<12> BFE<11> BFE<10> BFE<9> BFE<8> XXH
BFE<15:8> General purpose register, bits defined by mask programmable bits
TXT35 F7H 9FF<15> 9FF<14> 9FF<13> 9FF<12> GPF<15> GPF<14> GPF<13> GPF<12> XXH
9FF<15:12>, GPF<15:12> General purpose register, bits defined by mask programmable bits
TXT36 FCH - - - BFF<4> BFF<3> BFF<2> BFF<1> BFF<0> XXH
BFF<4:0> General purpose register, bits defined by mask programmable bits
Video_process A5H - - - - - - DW_PA<1> DW_PA<0> 00H
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DW_PA<1:0> Double Window and Panorama feature selection:-

00- normal mode (both Double Window and Panorama are disable)
01 - Double Window mode enable; the others are disable
10 - Linear scaling mode enable, the others are disable
11 - non-Linear scaling mode enable, the others are disable
WDT FFH WDV<7> WDV<6> WDV<5> WDV<4> WDV<3> WDV<2> WDV<1> WDV<0> 00H
WDV<7:0> Watch Dog Timer period
WDTKEY FEH WKEY<7> WKEY<6> WKEY<5> WKEY<4> WKEY<3> WKEY<2> WKEY<1> WKEY<0> 00H
WKEY<7:0> Watch Dog Timer Key

Note: Must be set to 55H to disable Watch dog timer when active
WSS1 BAH 0 0 0 WSS<3:0> WSS<3> WSS<2> WSS<1> WSS<0> 00H

ERROR
WSS<3:0> ERROR 0 - No error in WSS<3:0>

1 - Error in WSS<3:0>
WSS<3:0> Signalling bits to define aspect ratio (group 1)
WSS2 BBH 0 0 0 WSS<7:4> WSS<7> WSS<6> WSS<5> WSS<4> 00H

ERROR
WSS<7:4> ERROR 0 - No errors in WSS<7:4>

WSS<7:4> Signalling bits to define enhanced services (group 2)
WSS3 BCH WSS<13:11> WSS<13> WSS<12> WSS<11> WSS<10:8> WSS<10> WSS<9> WSS<8> 00H
ERROR ERROR

WSS<13:11> Signalling bits to define reserved elements (group 4)

1 - Error in WS<10:8>
WSS<10:8> Signalling bits to define subtitles (group 3)
XRAMP FAH XRAMP<7> XRAMP<6> XRAMP<5> XRAMP<4> XRAMP<3> XRAMP<2> XRAMP<1> XRAMP<0> 00H
XRAMP<7:0> Internal RAM access upper byte address
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UOCIII series
External (MOVX) Memory

The normal 80C51 external memory area has been
mapped internally to the device, this means that the MOVX
FFH FFFFH
instruction accesses data memory internal to the device. (XRAMP)=FFH
The movx memory map is shown in Fig.13.
00H FF00H
FFH FEFFH
(XRAMP)=FEH
7FFFH FFFFH
MOVX @Ri, A 00H FE00H
MOVX A, @Ri MOVX @DPTR,A
7500H MOVX A,@DPTR
74FFH
FFH 01FFH
RDS/RBDS Display Data (XRAMP)=01H
7000H 00H 0100H

FFH 00FFH
6FFFH
(XRAMP)=00H
9100H
90FFH 00H 0000H
Dynamically
Re-definable Fig.14 Indirect addressing
Characters
Display RAM
for (Movx address space)
TEXT PAGES 8800H
87FFH
Display Registers
87E0H
Power-on Reset
871FH Power on reset is generated internally to the UOCIII
CLUT
2000H device, hence no external reset circuitry is required.
8700H
84FFH Software Reset

0FFFH Display RAM
for
The UOCIII features a software reset (ROMBK SFR, bit 6),
Data RAM Closed Caption(1) which can be used by the micro-controller to reset the
0000H 8000H
following functions/blocks: stereo sound decoder, RDS,
Lower 32K bytes Upper 32K bytes
ISP, acquisition, display, display RAM and double
window/panorama. The software reset is executed by
initially setting the corresponding bit to ‘1’ followed by
(1) Display RAM for Closed Caption, Text, RDS/RBDS is shared clearing the bit to ‘0’. It takes approximately 200 µs to
complete the internal reset sequence.Please note the
micro-controller, its peripherals (e.g. timers) and program
Fig.13 Movx Address Map flash are not reset.
Power Saving modes of Operation

Auxiliary RAM Page Selection There are three Power Saving modes, Stand-by, Idle and
The Auxiliary RAM page pointer is used to select one of Power Down, incorporated into the TCG micro-controller
the 256 pages within the auxiliary RAM, not all pages are (Text/Control/Graphic micro-controller) die. When utilizing
allocated, refer to Fig. 14. A page consists of 256 either mode, the 3.3V power to the device (Vddp & Vdda)
consecutive bytes. XRAMP only works on internal MOVX should be maintained. The analogue blocks are
memory. powered-down and the clocks to various digital blocks are
disabled to minimize the power consumption. The +1.8 V
analogue supplies can be switched off.The internally
generated 1.8V will be maintained to supply the power of
80c51 and pads.
Stand-by Mode
During Stand-by mode, the Acquisition, Display, RDS, and
SSD sections of the device are disabled. This includes
analog modules, such A/D and D/A converter. Before
2003 Nov 11 54
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UOCIII series
entering standby-mode, the SSD will be allowed to • A second method of exiting Idle is via an Interrupt
soft-mute the audio outputs. After the required 32 ms, the generated by the SAD DC Compare circuit. When TCG
video processor is powered-down and the following micro-controller is configured in this mode, detection of
functions remain active:- an analogue threshold at the input to the SAD may be
used to trigger wake-up of the device i.e. TV Front Panel
• 80c51 CPU Core Key-press. As above, the interrupt is serviced, and
• I2C following the instruction RETI, the next instruction to be
executed will be the one following the instruction that put
• RCP (Remote Control Pre-processor) the device into Idle.
• Timer/Counters
• The third method of terminating Idle mode is with a
• WatchDog Timer Power On reset. Reset defines all SFRs and Display
• UART, SAD and PWMs memory to a pre-defined state, but maintains all other
RAM values. Code execution commences with the
Program Counter set to ’0000’.
To enter Stand-by mode, the STANDBY bit in the
ROMBANK register must be set. The contents of the
Display memory are lost. Since the output values on RGB Power Down Mode
and VDS are maintained the display output must be In Power Down mode the XTAL oscillator is still running.
disabled before entering this mode. The contents of all SFRs and Data memory are
This mode should be used in conjunction with both Idle maintained. The port pins maintain the values defined by
and Power-Down modes. Hence, prior to entering either their associated SFRs.
Idle or Power-Down, the STANDBY bit should be set. The power down mode is activated by setting the PD bit in
the PCON register. It is advised to disable the WatchDog
Idle Mode timer prior to entering Power down. Recovery from
During Idle mode, Acquisition, Display, RDS, SSD and the Power-Down takes several milli-seconds as the oscillator
CPU sections of the device are disabled. The following must be given time to stabilize.
functions remain active:-
There are three methods of exiting power down:-
• I2C
• An External interrupt provides the first mechanism for
• RCP
waking from Power-Down. Since the clock is stopped,
• Timer/Counters external interrupts needs to be set level sensitive prior to
• WatchDog Timer entering Power-Down. The interrupt is serviced, and
following the instruction RETI, the next instruction to be
• UART, SAD and PWMs
executed will be the one after the instruction that put the
device into Power-Down mode.
To enter Idle mode the IDL bit in the PCON register must
• A second method of exiting Power-Down is via an
be set. The WatchDog timer must be disabled prior to
Interrupt generated by the SAD DC Compare circuit.
entering Idle to prevent the device being reset. It is advice
When TCG micro-controller is configured in this mode,
to use the RCP (Remote Control Pre-processor) during the
detection of a certain analogue threshold at the input to
Idle mode to reduce the false interrupt wake-up of 80c51 in
the SAD may be used to trigger wake-up of the device
order to achieve the low power saving mode. The CPU
i.e. TV Front Panel Key-press. As above, the interrupt is
state is frozen along with the status of all SFRs, internal
serviced, and following the instruction RETI, the next
RAM contents are maintained, as are the device output pin
instruction to be executed will be the one following the
values.
instruction that put the device into Power-Down.
There are three methods available to recover from Idle:- • The third method of terminating the Power-Down mode
• Assertion of an enabled interrupt will cause the IDL bit to is with a Power On reset. Reset defines all SFRs and
be cleared by hardware, thus terminating Idle mode. Display memory, but maintains all other RAM values.
The interrupt is serviced, and following the instruction Code execution commences with the Program Counter
RETI, the next instruction to be executed will be the one set to ’0000’.
after the instruction that put the device into Idle mode.
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I/O Facility To accommodate this, another interrupt ET2PR has been

added to indicate timer overflow.
I/O PORTS In addition to the conventional 80c51, four application
The IC has 24 I/O lines, each is individually addressable, specific interrupts are incorporated internally to the device
or form part of 4 parallel addressable ports which are which have the following functionality:-
port0, port1, port2 and port3. RDS (Radio Data System Interrupt) - This interrupt is
The I/O cells are designed to transfer 3.3V external (Pad generated when the RDS/RBDS is decoded and available.
side) signals to 1.8V internal (core side) signals, vice The interrupt is activated when DAVN (data available) is
versa. And the I/O pads for the bond-out as well as GPIO active which is generated by RDS/RBDS subblock.
have 5V tolerant except the I2C clock pad in High-speed DET (Supply Dip Monitor Interrupt) - This interrupt is
mode. generated when the supply dip monitor detects at dip of
1.44V on one of the 1.8V supply pins.
PORT TYPE CC (Closed Caption Data Ready Interrupt) - This
All individual ports can be programmed to function in one interrupt is generated when the device is configured for
of four modes, the mode is defined by two Port Closed Caption acquisition. The interrupt is activated at
Configuration SFRs. The modes available are Open Drain, the end of the currently selected Slice Line as defined in
Quasi-bidirectional, High Impedance and Push-Pull. the CCLIN SFR.
BUSY (Display Busy Interrupt) - An interrupt is
Open Drain generated when the Display enters either a Horizontal or
The Open drain mode can be used for bi-directional Vertical Blanking Period. i.e. Indicates when the
operation of a port. It requires an external pull-up resistor, micro-controller can update the Display RAM without
the pull-up voltage has a maximum value of 5.5V, to allow causing undesired effects on the screen. This interrupt can
connection of the device into a 5V environment. be configured in one of two modes using the MMR
Configuration Register (Address 87FF, Bit-3 [TXT/V]):-
Quasi bi-directional • TeXT Display Busy: An interrupt is generated on each
The quasi-bidirectional mode is a combination of open active horizontal display line when the Horizontal
drain and push pull. It requires an external pull-up resistor Blanking Period is entered.
to VDDp (nominally 3.3V). When a signal transition from • Vertical Display Busy: An interrupt is generated on each
0->1 is output from the device, the pad is put into push-pull vertical display field when the Vertical Blanking Period is
mode for one clock cycle (81.38ns) after which the pad entered.
goes into open drain mode. This mode is used to speed up
the edges of signal transitions. This is the default mode of
operation of the pads after reset. There are two interrupts connected to the 80c51
micro-controller peripherals as follows: -
High Impedance
The high impedance mode can be used for Input only ES2 - I2C Transmit/Receive interrupt.
operation of the port. When using this configuration the two EUART - UART Receive/Transmit interrupt.
output transistors are turned off.
One additional general purpose external interrupt (EX2) is
incorporated into TCG micro-controller and is only
Push-Pull
The push pull mode can be used for output only. In this available in QFP128 package.
mode the signal is driven to either 0V or VDDp, which is
nominally 3.3V. INTERRUPT ENABLE STRUCTURE
Each of the individual interrupts can be enabled or
Interrupt System disabled by setting or clearing the relevant bit in the
The device has 12 interrupt sources, each of which can be interrupt enable SFRs (IE and IEN1). All interrupt sources
enabled or disabled. When enabled, each interrupt can be can also be globally disabled by clearing the EA bit (IE.7).
assigned one of two priority levels. There are four The EDET interrupt can only be cleared by setting the
corresponding status bits in bit 4 and 7 of TXT31 or bit4
interrupts that are common to the 80C51, two of these are
external interrupts (EX0 and EX1) and the other two are and 5 of ROMBK to ’0’.
timer interrupts (ET0 and ET1).
The TCG micro-controller family of devices have an
additional 24-bit Timer (16-bit timer with 8-bit pre-scaler).
2003 Nov 11 56
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Source Priority within level Trigger Condition Interrupt Vector
H1 Highest Priority Level1 EBUSY falling-edge 003BH

EX0
L1 Highest Priority Level0
H2 ET2PR Timer2 0043H
ET0
L2
H3 EUART UART 004BH
EX1
L3
H4 ERDS falling-edge 0053H
ET1
L4
H5 EX2 Lowest low-level 005BH
EDET
L5
H6 Table 7 Interrupt Priority (within same level)
ECC
L6
H7
ES2
L7
INTERRUPT VECTOR ADDRESS
EBUSY
H8 The processor acknowledges an interrupt request by
L8
H9
executing a hardware generated LCALL to the appropriate
ET2PR
L9 servicing routine. The interrupt vector addresses are
H10
EUART shown in Table 7.
L10
H11
ERDS
L11 LEVEL/EDGE INTERRUPT
H12 Lowest Priority Level1
EX2
L12 Lowest Priority Level0
The external interrupt (EX0 and EX1) can be programmed
Interrupt Source Global Priority to be either level-activated or transition activated by setting
Source Enable Enable Control
IE.0:6 IE.7 IP.0:6 or clearing the IT0/1 bits in the Timer Control SFR(TCON).
IEN1.0:4 IP1.0:4
ITx Interrupt Type
Fig.15 Interrupt Structure 0 Level, Active Low
1 Edge, Negative Edge
INTERRUPT ENABLE PRIORITY Table 8 External Interrupt Activation

Each interrupt source can be assigned one of two priority
levels (High/Low). The interrupt priorities are defined by Timer/Counter
the interrupt priority SFRs (IP and IP1). A low priority Two 16 bit timers/counters are incorporated Timer0 and
interrupt can be interrupted by a high priority interrupt, but Timer1. Both can be configured to operate as either timers
not by another low priority interrupt. A high priority interrupt or event counters.
can not be interrupted by any other interrupt source. If two In Timer mode, the register is incremented on every
requests of different priority level are received machine cycle. It is therefore counting machine cycles.
simultaneously, the request with the highest priority level is Since the machine cycle consists of 6 oscillator periods,
serviced. If requests of the same priority level are received the count rate is 1/6 micro-controller clock(12.288MHz) =
simultaneously, an internal polling sequence determines 2.048MHz.
which request is serviced. Thus, within each priority level In Counter mode, the register is incremented in response
there is a second priority structure determined by the to a negative transition at its corresponding external pin
polling sequence as defined in Table 7. T0/1. Since the pins T0/1 are sampled once per machine
cycle it takes two machine cycles to recognise a transition,
Source Priority within level Trigger Condition Interrupt Vector
this gives a maximum count rate of 1/12 micro-controller
EX0 Highest low-level or falling-edge 0003H clock(12.288MHz)= 1.024MHz.
There are six special function registers used to control the
ET0 Timer0 000BH
timers/counters as defined in Table 9.
EX1 low-level or falling-edge 0013H
SFR Address
ET1 Timer1 001BH
TCON 88H
EDET 1v8guard 0023H
TMOD 89H
ECC high-level 002BH
TL0 8AH
ES2 low-level 0033H
TH0 8BH
Table 7 Interrupt Priority (within same level)
Table 9 Timer/Counter Registers
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UOCIII series
SFR Address
80C51 based 8-bit micro-controllers - Philips
Semiconductors (ref. IC20) for detail of the modes and
TL1 8CH
operation.
TH1 8DH TL0/TL1 and TH0/TH1 are the actual timer/counter
registers for timer0 / timer1. TL0/TL1 is the low byte and
Table 9 Timer/Counter Registers
TH0/TH1 is the high byte.
TIMER2 WITH PRE-SCALER

TF1 TR TF0 TR IE1 IT1 IE0 IT0 An additional 24-bit Timer (16-bit timer with 8-bit
Symbol Position Name and Significance pre-scaler) is provided to allow timer periods up to 8.192
TF1 TCON.7 Timer 1 overflow flag. Set by hard- seconds. This timer remains active during IDLE mode.
ware on timer/counter overflow.
Cleared by hardware when processor TP2L sets the lower value of the period for timer 2 and
vectors to interrupt routine.
TR1 TCON.6 Timer 1 Run control bit. Set/cleared TP2H is the upper timer value. TP2PR provides an 8-bit
by software to turn timer.counter
on/off. pre-scaler for timer 2. The value on TP2PR, TP2H and
TF0 TCON.5 Timer 0 overflow flag. Set by hard-
ware on timer/counter overflow.
TP2L shall never change unless updated by the software.
Cleared by hardware when processor
vectors to interrupt routine.
If the micro reads TP2R, TP2H orTP2L at any stage, this
TR0 TCON.4 Timer 0 Run control bit. Set/cleared should return the value written and not the current timer 2
by software to turn timer.counter
on/off. value. The timer 2 should continue after overflow by
Symbol Position Name and Significance re-loading (hardware) the timer with the values of SFRs
IE1 TCON.3 Interrupt 1 Edge flag. Set by hardware TP2PR, TP2H and TP2L.
when external interrupt edge
detected. Cleared when interrupt TP2CL and TP2CH indicate the current timer 2 value.
processed.
IT1 TCON.2 Interrupt 1 Type control bit. These should be readable both when the timer 2 is active
Set/cleared by software to specify fall-
ing edge/low level triggered external and inactive. Once the timer 2 is disable, the timer 2 value
interrupts.
IE0 TCON.1 Interrupt 0 Edge flag. Set by hardware
at the time of disabling should be maintained on the SFRs
when external interrupt edge
detected. Cleared when interrupt
TP2CL and TP2CH. At a count of zero (on TP2CL and
IT0 TCON.0
processed.
Interrupt 0 Type control bit.
TP2CH), the overflow flag should be set:- TP2CRL<1> - ’0’
Set/cleared by software to specify fall-
ing edge/low level triggered external
= no timer 2 overflow, ’1’= timer 2 overflow.
interrupts. TP2CRL is the control and status for timer 2. TP2CRL.0 is
the timer enable and TP2CRL.1 is the timer overflow
Fig.16 Timer/Counter Control (TCON) register
status. The overflow flag will need to be reset by software.
Hence, if required, software may poll flag rather than use
interrupt. Upon overflow an interrupt should also be
generated.
Gat C/T M1 M0 Gat C/T M1 M0 Reset values of all registers should be 00 hex.
Timer2 interval = (TP2H * 256 + TP2L) * (TP2PR + 1) * 0.4883us
Timer 1 Timer 0
Gate Gating control when set. Timer/counter is enabled only
while external interrupt 0/1 is high and TR control bit is WatchDog Timer
set. When cleared timer/counter is enabled whenever TR
control bit is set. The WatchDog timer is a counter that once in an overflow
C/T Timer or Counter selector. Cleared for timer operation
(input from system clock). Set for counter operation (input state forces the micro-controller in to a reset condition. The
from T input pin.
purpose of the WatchDog timer is to reset the
M1 M0 Operating
micro-controller if it enters an erroneous processor state
0 0 8048 Timer, TL serves as 5-bit prescaler.
0 1 16-bit Timer/Counter, TL and TH are cascaded. (possibly caused by electrical noise or RFI) within a
1 0 8-bit auto-reload Timer/Counter, TH holds a value
which is to be loaded into TL. reasonable period of time. When enabled, the WatchDog
1 1 timer 0: two 8-bit Timers/Counters. TL0 is controlled by circuitry will generate a system reset if the user program
timer 0 control bits. TH0 is controlled by timer 1 control
bits. timer 1: stopped. fails to reload the WatchDog timer within a specified length
Fig.17 Timer/Counter Mode control (TMOD) of time known as the WatchDog interval.
The WatchDog timer consists of an 8-bit counter with an
16-bit pre-scaler. The pre-scaler is fed with a signal whose
The Timer/Counter function is selected by control bits C/T frequency is 1/6 * 12.288MHz = 2.048MHz. The 8 bit timer
in the Timer Mode SFR (TMOD). These two is incremented every ‘t’ seconds where:
Timer/Counter have four operating modes, which are t=6x65536x1/12.288x106 = 32ms
selected by bit-pairs (M1.M0) in the TMOD. Refer to the
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WATCHDOG TIMER OPERATION 0.1628us. e.g. if TD<6:0> = 01H then 1 in 128 periods will
The WatchDog operation is activated when the WLE bit in be extended by 0.1628us, if TD<6:0>=02H then 2 in 128
the Power Control SFR (PCON) is set. The WatchDog can periods will be extended.
be disabled by Software by loading the value 55H into the The TPWM will not start to output a new value until TDACH
WatchDog Key SFR (WDTKEY). This must be performed has been written to. Therefore, if the value is to be
before entering Idle/Power Down mode to prevent exiting changed, TDACL should be written before TDACH.
the mode prematurely.
Once activated the WatchDog timer SFR (WDT) must be SAD SOFTWARE A/D
reloaded before the timer overflows. The WLE bit must be Four successive approximation Analogue to Digital
set to enable loading of the WDT SFR, once loaded the Converters can be implemented in software by making use
WLE bit is reset by hardware, this is to prevent erroneous of the on board 8-bit Digital to Analogue Converter and
Software from loading the WDT SFR. Analogue Comparator.
The value loaded into the WDT defines the WatchDog
interval. SAD Control
WatchDog interval = (256 - WDT) * t = (256 -WDT) * 32ms. The control of the required analogue input is done using
the channel select bits CH<1:0> in the SAD SFR, this
The range of intervals is from WDT=00H which gives selects the required analogue input to be passed to one of
8.192s to WDT=FFH which gives 32ms. the inputs of the comparator. The second comparator input
is generated by the DAC whose value is set by the bits
PORT Alternate Functions SAD<7:0> in the SAD and SADB SFRs. A comparison
The Ports 0, 1,2 and 3 are shared with alternate functions between the two inputs is made when the start compare bit
to enable control of external devices and circuitry. The ST in the SAD SFR is set, this must be at least one
alternate functions are enabled by setting the appropriate instruction cycle after the SAD<7:0> value has been set.
SFR and also writing a ‘1’ to the Port bit that the function The result of the comparison is given on VHI one
occupies. instruction cycle after the setting of ST.
PWM PULSE WIDTH MODULATORS

The device has five 6-bit Pulse Width Modulated (PWM)
outputs for analogue control. The PWM outputs generate VDDP
pulse patterns with a repetition rate of 10.4166us, with the ADC0
high time equal to the PWM SFR value multiplied by ADC1
0.1628us. The analogue value is determined by the ratio MUX
ADC2
of the high time to the repetition time, a D.C. voltage 4-1
ADC3 VHI
proportional to the PWM setting is obtained by means of +
an external integration network (low pass filter). CH<1:0> -
PWM Control
The relevant PWM is enabled by setting the PWM enable SAD<7:0> 8-bit
DAC
bit PWxE in the PWMx Control register. The high time is
defined by the value PWxV<5:0>
Fig.18 SAD Block Diagram
TPWM TUNING PULSE WIDTH MODULATOR
The device has a single 14-bit PWM that can be used for
SAD Input Voltage
Voltage Synthesis Tuning. The method of operation is
The external analogue voltage that is used for comparison
similar to the normal PWM except the repetition period is
with the internally generated DAC voltage does not have
20.833us.
the same voltage range. The DAC has a lower reference
level of VSSA and an upper reference level of VDDA. The
TPWM Control resolution of the DAC voltage with a nominal value is
Two SFRs are used to control the TPWM, they are TDACL 3.3/256 ~= 13mV. The external analogue voltage has a
and TDACH. The TPWM is enabled by setting the TPWE
lower value equivalent to VSSA and an upper value
bit in the TDACH SFR. The most significant bits TD<13:7>
equivalent to VDDP - Vtn, were Vtn is the threshold voltage
alter the high period between 0 and 20.833us. The 7 least
for an NMOS transistor. The reason for this is that the input
significant bits TD<6:0> extend certain pulses by a further
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pins for the analogue signals (P3.0 to P3.3) are 5V tolerant • F/S-mode (Fast/Standard: 12kHz~384kHz)
for normal port operations, i.e. when not used as analogue Hs-mode can operate up to 2.048 Mbit/s.
input. To protect the analogue multiplexer and comparator Fast-mode can operate up to 384kbit/s, which also covers
circuitry from the 5V, a series transistor is used to limit the Standard-mode (up to 100kHz).
voltage. This limiting introduces a voltage drop equivalent The SCLH-out (Serial CLock line/signal in Hs-mode
to Vtn (~0.6V) on the input voltage. Therefore, for an input system) frequency in Hs-mode is specified in SFR,
voltage in the range VDDp to VDDp-Vtn the SAD returns the HSBIR<4:0>, and in F/S-mode is specified in SFR,
same comparison value. FSBIR<6:0>.
The micro-controller peripheral is controlled by the Serial
SAD DC Comparator Mode Control SFR (S1CON) and its Status is indicated by the
The SAD module incorporates a DC Comparator mode status SFR (S1STA). Information is transmitted/received
which is selected using the ’DC_COMP’ control bit in the to/from the I2C bus using the Data SFR (S1DAT) and the
SADB SFR. This mode enables the micro-controller to Slave Address SFR (S1ADR) is used to configure the
detect a threshold crossing at the input to the selected slave address of the peripheral.
analogue input pin (P3.0, P3.1, P3.2 or P3.3) of the
Software A/D Converter. A level sensitive interrupt is Hs-mode
generated when the analogue input voltage level at the pin The various serial rates are shown below: -
falls below the analogue output level of the SAD D/A
converter.
This mode is intended to provide the device with a Reload-value in
MOD_CLK divided by MOD_CLK=12.288MHz
wake-up mechanism from Power-Down or Idle when a HSBIR<4:0>
key-press on the front panel of the TV is detected. 0 3 not allowed
The following software sequence should be used when 1 6 2.048MHz
utilizing this mode for Power-Down or Idle:- 2 9 1.365MHz

1. Disable INT1 using the IE SFR. 3 12 1.024MHz
2. Set INT1 to level sensitive using the TCON SFR. 4 15 0.819MHz
3. Set the D/A Converter digital input level to the desired 5 18 0.6875MHz
threshold level using the SAD/SADB SFRs and select 6 21 0.585MHz
the required input pin (P3.0, P3.1, P3.2 or P3,3) using 7 24 0.512MHz
CH1, CH0 in the SAD SFR. | | |
4. Enter DC Compare mode by setting the ’DC_COMP’ | | |
enable bit in the SADB SFR. 31 96 0.128MHz
5. Enable INT1 using the IE SFR.

6. Enter Power-Down/Idle. Upon wake-up the SAD Table 10 I2C Serial Rates ‘Hs-mode’
should be restored to its conventional operating mode
by disabling the ’DC_COMP’ control bit.
I2C Serial I/O Bus

The I2C bus consists of a serial data line (SDA) and a serial
clock line (SCL). The definition of the I2C protocol can be
found in The I2C-bus Specification v2.1, January 2000,
Philips Semiconductor.
The device operates in four modes: -
• Master Transmitter
• Master Receiver
• Slave Transmitter
• Slave Receiver
Each of the 4 modes above can operate at the next speed
modes:
• Hs-mode (High speed: 128kHz~2.048MHz) or
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F/S mode The 80c51 Micro-controller incorporates a full duplex

UART with a single byte receive buffer, meaning that it
Reload-value in
MOD_CLK divided by MOD_CLK=12.288MHz commence reception of a second byte before the first is
FSBIR<6:0>
read form the receive buffer. The UART’s RX and TX pins
0 8 not allowed
connect to P1.4 & P1.5 respectively.
1 16 not allowed
Two registers (S0CON, S0BUF) control the UART along
2 24 not allowed with SMOD bit of PCON register: -
3 32 384kHz
4 40 307kHz
5 48 256kHz SFR Address

6 56 219kHz
PCON 87H
7 64 192kHz
8 72 170.65kHz S0CON 99H

9 80 168.75kHz
| | |
S0BUF 9AH
12 104 118.15kHz Table 12 UART Special Function Registers
| |
14 120 102.4kHz
S0CON
15 128 96kHz
The serial port control and status register is the Special
| | |
Function Register S0CON. This register contains not only
24 200 61.45kHz the mode selection bits, but also the 9th data bit for
| | | transmit and receive (TB8 and RB8), and the serial port
33 272 45.2kHz interrupt bits (TI and RI).
| | |
37 304 40.4kHz
| | |
49 400 30.7kHz
| | |
127 1024 12kHz
Table 11 I2C Serial Rates ‘F/S mode’1

1. F/S-SCL frequencies between 0 and 100 kHz are allowed if the F/S bit in FSBIR is
’0’ (Standard mode); F/S-SCL frequencies between 0 and 400kHz are allowed if the
F/S-bit in FSBIR is ’1’ (Fast mode).
I2C Port Enable

One external I2C port is available. This port is enabled
using TXT21.I2C PORT EN. Any information transmitted to
the device can only be acted upon if the port is enabled.
Internal communication between the 80c51
micro-controller and the TV Signal Processor will continue
regardless of the value written to TXT21.I2C PORT EN.
I2S Port Enable

Five external I2S port are available. Each port is enabled
using I2S.EN_I2SDI1, I2S.EN_I2SDO1, I2S.EN_I2SDO2,
I2S.EN_I2SCLK, and I2S.EN_I2SWS. Any information
transmitted/received to/from the device can only be
activated upon if the port is enabled.
UART Peripheral
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Mode 0: Serial data enters and exits through RxD. TxD

outputs the shift clock. 8 bits are transmitted/received
(LSB first). The baud rate is fixed at 1/6 the frequency of
SM0 SM1 SM2 REN TB8 RB8 TI RI
clk.
Mode 1: 10 bits are transmitted (through TxD) or received
Symbol Position Name and Significance (through RxD): a start bit (’0’), 8 data bits (LSB first), and a
SM0 S0CON.7 Mode selection bit 0. stop bit (’1’). On receive, the stop bit goes into RB8 in
SM1 S0CON.6 Mode selection bit 1.
Special Function Register S0CON. The baud rate is
SM2 S0CON.5 Enables the multi processor
communication feature in modes determined by the Timer 1 overflow rate.
2 and 3. In mode 2 or 3, if SM2 is Mode 2: 11 bits are transmitted (through TxD) or received
set, then RI will not be activated,
RB8 and S0BUF will not be (through RxD): start bit (’0’), 8 data bits (LSB first), a 9th
loaded if the received 9th data data bit, and a stop bit (’1’). On Transmit, the 9th data bit,
bit is ’0’. In mode 1, if SM2 is set, TB8 in S0CON, can be assigned the value of ’0’ or ’1’. For
then RI will not be activated,
RB8 and S0BUF will not be example, the parity bit could be moved into TB8. On
loaded if no valid stop bit was receive, the 9th data bit goes into RB8 in S0CON, while the
received. In mode 0, SM2 has no
influence. stop bit is ignored. The baud rate is programmable to
REN S0CON.4 Enables serial reception. Set by either 1/32 or 1/64 the frequency of the micro-controller
software to enable reception. clock.
Cleared by software to disable
reception. Mode 3: 11 bits are transmitted (through TxD) or received
(through RxD): a start bit (’0’), 8 data bits (LSB first), a 9th
Symbol Position Name and Significance data bit, and a stop bit (’1’). In fact, mode 3 is the same as
TB8 S0CON.3 Is the 9th data bit that will be mode 2 in all respects except baud rate. The baud rate is
transmitted in modes 2 and 3.
Set or cleared by software as determined by the Timer 1 overflow rate.
desired.
RB8 S0CON.2 In modes 2 and 3, RB8 is the 9th In all four modes, transmission is initiated by any
data bit that was received. In
mode 1, if SM2 is ’0’, RB8 is the instruction that uses S0BUF as a destination register.
stopbit that was received. In Reception is initiated in mode 0 by the condition RI = ’0’
mode 0, RB8 is not used. Load- and REN = ’1’. In the other modes reception is initiated by
ing of RB8 in modes 1, 2 and 3
depends on SM2. the incoming start bit if REN = 1.
TI S0CON.1 Is the transmit interrupt flag. Set
by hardware at the end of the 8th UART Multi-Processor Communications
bit time in mode 0, or at the
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received.
Fig.19 S0CON Special Function Registers The 9th bit goes into RB8, followed by a stop bit. The port
can be programmed such that when the stop bit is
received, the serial port interrupt will be activated only if
RB8 = ’1’. This feature is enabled by setting bit SM2 in
S0CON. A way to use this feature in multi-processor
S0BUF systems is as follows:
This register is implemented twice. Writing to S0BUF When the master processor wants to transmit a block of
writes to the transmit buffer. Reading from S0BUF reads data to one of several slaves, it first sends out an address
from the receive buffer. Only hardware can read from the byte which identifies the target slave. An address byte
transmit buffer and write to the receive buffer. differs from a data byte. The 9th bit is ’1’ in an address byte
and ’0’ in a data byte. With SM2 = ’1’, no slave will be
SMOD bit of PCON interrupted by a data byte reception. An address byte,
SMOD is the double baud rate bit. If SMOD=’1’ the baud however, will interrupt all slaves, so that each slave can
rate in mode 1, 2 and 3 is doubled. In mode 0 SMOD is not examine the received byte and see if it is being addressed.
used. The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will follow. The slaves that
UART Modes weren’t being addressed leave their SM2s set and go on
The serial port can operate in 4 modes: - about their business, ignoring the incoming data bytes.
SM2 has no effect in mode 0, and in mode 1 it can be used
to check the validity of the stop bit. When receiving in
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mode 1, if SM2 = ’1’, the receive interrupt will not be Remote Control Pre-processor
activated unless a valid stop bit is received. The remote control pre-processor is used to reduce the
number of wake-up’s for the 80c51 core (from IDLE
S0BUF Registers mode).
This register is implemented twice. Writing to S0BUF To Start the remote control pre-processor, bit 7 of RCP6
writes to the transmit buffer. Reading from S0BUF reads register (SFR address EEH), must be programmed to ‘1’.
from the receive buffer. Only hardware can read from the Afterward, SW has to program the RCP-SFRs:-
transmit buffer and write to the receive buffer.
• Clock divider rate CDIV (= divider between Xtal
UART Baud Rates and RCP counter)
NOTE: fclk used in the following calculations refers to the • AL = 75% of the nominal, shortest allowable
micro-controller clock frequency (12.288MHz). LOW pulse
The serial port can operate with different baud rates • AH = 125% of the nominal, longest allowable
depending on its mode. The baud rate in mode 0 is derived pulse MINUS AL (saves timer span & is easier
from state 2 and state 5 and thus fixed: for SW)
Mode 0 baud rate = fclk/ 6 • BL, BH = same as AL, AH, but then for the
The baud rate in mode 2 depends on the value of bit HIGH time of the pulse
SMOD.
Because RC5 does not have a real start-pulse (long, with
If SMOD = 0, the baud rate is fclk/32 other timing) the registers AL, AH, BL, BH don’t have to
If SMOD = 1, the baud rate is fclk/16 be written every pulse transition.
Further the SW (re-)programs:
SMOD
2
Mode 2 baud rate = ------------------ × f clk • NGP = 0 -> the flag that tells the RCP-HW has
32
found a timing-error (not in the first pulse) and
The baud rates in mode 1 and 3 are determined by the so the RC5 message string decoding must be
Timer 1 overflow rate and the value of SMOD as follows: terminated.
• NFP = 0 -> means the RCP-HW is “hunting” for
SMOD the first pulse. If there occurs a timing-error dur-
2
Mode 1, 3 baud rate = ------------------ × ( Timer1OverflowRate ) ing the first pulse, the micro gets NO wake-up
32
interrupt. The RCP keeps hunting for a pulse
that matches the “start-pulse-timing”. (= ideal
The Timer 1 interrupt should be disabled in this for protocols with a ling start-pulse). The
application. The Timer itself can be configured for either RCP-HW sets NFP=1, to signal that the first
’timer’ or ’counter’ operation, and in any of its 3 running (start-) pulse was found. Further NFP=1 takes
modes. In the most typical applications, it is configured for care that any following-pulse-with-error
’timer’ operation, in the auto-reload mode (high nibble of ALWAYS generates a wake-up interrupt (termi-
TMOD = 0010B). In that case the baud rate is given by the nate decoding).
formula:
2
SMOD f clk Now the SW goes to sleep in IDLE mode. The Xtal clock
Mode 1, 3 Baud Rate = ------------------ × ------------------------------------------
32 6 × ( 256 – T1H ) continues, watchdog timer, timer & RCP keep working
(with same Xtal frequency).
One can achieve very low baud rates with Timer 1 by When an RC-INT arrives, the micro-core wake-up in
leaving the Timer 1 interrupt enabled, and configuring the STANDBY mode. Now the SW must read the RCP results
Timer to run as a 16-bit timer (high nibble of TMOD = from RA, RB (two 12-bits, folded into 3 SFRS:- RCP3,
0001B), and using the Timer 1 interrupt to do a 16-bit RCP4, and RCP5) plus the error flags NFP and NGP.
software reload. (note that after the FIRST pulse, the RCP-HW will always
come back with NGP=0).
For further details on the UART operation refer to “80C51 When there is an error (NGP=1), then the RC-string
Based 8-Bit Micro-controllers - Philips Semiconductors decoding must be terminated (i.e. further, trailing bits will
(ref. IC20). make an the following string an invalid one).
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With NO-ERROR the SW only has to check if RA and RB At the END of an RC5 string there is a special condition: a
are longer than 1x tp (minus 75% of the shortest allowable LOW-pulse, followed by a HIGH data-clean time (>2.5tp),
pulse=AL) which show whether the pulse had a width of WITHOUT subsequent interrupt. A simple solution is to
1x tp or 2x tp. load the BH register BEFORE the last pulse with 3xtp
This simplifies the decoding SW considerably (timing (minus AL). As a consequence you will get an INT after
3tp data clean time: in this special case NGP=1 shows
errors are already checked by RCP-HW), for RC5 the
during 3tp nothing has happened, to the message has
bi-phase decoding-method is similar to the older SW.
ended OK.
If an error NGP=1 is received, then break-off the decoding
The following table shows the timing characteristics of
and let SW set NFP=0, so that the HW starts hunting
some existing Remote Control Protocols:-
again for the FIRST pulse.
Name RC5 Sony NEC Motorola Japan Daewoo Samsung Denon

Startbit 889us 2.4ms 9ms 3ms 3.38ms 8ms 4.5ms -
Shortest 889us 600us 560us 512us 420us 450us 560us 275us
Longest 1178us 1.2ms 1.69ms 1024us 1.27ms 1.45ms 1.69ms 1.9ms
Repeat 113.8ms 45ms 67.5ms 34ms 90ms 60ms 60ms 65ms
Table 13 Remote Control Protocols
I2S Clock Output Selection

The I2S Clock output can be selected via information that has been requested. The Display reads
I2S.I2S_CLK<1:0> SFRs. The output clock is shown in the SRAM information and converts it to RGB output
below:- values.
fs=32kHz The display RAM is initialized on power-on to a value of
20H throughout. The contents of the display RAM is not
maintained when entering power saving modes (stand-by,
I2S.I2S_CLK<1:0> I2S Clock Output idle, and power-down). Upon leaving standby mode and
resuming normal operation, the display RAM is initialized
00 256fs to a value of 20H throughout again (by hardware). The
same applies when a software reset is issued. In this case,
01 128fs
the display RAM is initialized to 20H throughout as well.
10 64fs The Display RAM occupies a maximum of 20K with an
address range from 2000H to 6FFFH; the TXT14.
11 not allowed DISPLAY BANK<3:0> and TXT15.MICRO BANK<3:0>
must keep default value “0000”. The RDS/RBDS Display
Table 14 I2S Clock Output Selection Data occupies 1.25K with an address range from 7000H to
74FF H. The three modes although having different
address ranges occupy physical the same SRAM area.
LED Support
When TXT27.RDS ON = 1, the RDS/RBDS Display
All port pins have a 4mA current sinking capability to
memory would map to the physical SRAM area. When
enable LEDs in series with current limiting resistors to be
TXT27.RDS ON=0, TXT21.CC/TXT=1 / 0, then the CC /
driven directly, without the need for additional buffering
TXT memory would map to the physical SRAM area.
circuitry.
Data Capture
SRAM MEMORY INTERFACE The Data Capture section takes in the analogue
The SRAM memory interface controls the access to the Composite Video and Blanking Signal (CVBS) from Video
embedded SRAM and page clearing. The SRAM is shared Signal Processor, and from this extracts the required data,
between Data Capture and Display sections. The Data which is then decoded and stored in SFR or memory.
Capture section uses the SRAM to store acquired
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The extraction of the data is performed in the digital Data Standards

domain. The first stage is to convert the analogue CVBS The data and clock standards that can be recovered are
signal into a digital form. This is done using an ADC shown in Table 15 below:-
sampling at 12.288MHz. The data and clock recovery is
then performed by a Multi-Rate Video Input Processor Data Standard Clock Rate
(MulVIP). From the recovered data and clock the following 625WST 6.9375 MHz
data types are extracted WST Teletext (625/525),Closed
Caption, VPS, WSS(625). The extracted data is stored in 525WST 5.7272 MHz
either memory (SRAM) via the SRAM Memory Interface or
VPS 5.0 MHz
in SFR locations.
625WSS 5.0 MHz
Data Capture Features
• Video Signal Quality detector. Closed Caption 500 KHz
• Data Capture for 625 line WST Table 15 Data Slicing Standards
• Data Capture for 525 line WST
Data Capture Timing
• Data Capture for US Closed Caption
The Data Capture timing section uses the Synchronisation
• Data Capture for VPS data (PDC system A) information extracted from the CSI signal to generate the
• Data Capture for 625 line Wide Screen Signalling (WSS) required Horizontal and Vertical reference timings.
bit decoding The timing section automatically recognises and selects
the appropriate timings for either 625 (50Hz)
• Automatic selection between 525 WST/625WST
synchronisation or 525 (60Hz) synchronisation. A flag
• Automatic selection between 625WST/VPS on line 16 of TXT12.Video Signal Quality is set when the timing section
VBI is locked correctly to the incoming CVBS signal. When
• Real-time capture and decoding for WST Teletext in TXT12.Video Signal Quality is set another flag
Hardware, to enable optimized microprocessor TXT12.625/525 SYNC can be used to identify the
throughput standard.
• Up to 10 pages stored On-Chip
Acquisition
• Inventory of transmitted Teletext pages stored in the The acquisition sections extracts the relevant information
Transmitted Page Table (TPT) and Subtitle Page Table from the serial stream of data from the MulVIP and stores
(SPT) it in memory.
• Automatic detection of FASTEXT transmission
• Real-time packet 26 engine in Hardware for processing 625 WST ACQUISITION
accented, G2 and G3 characters The family is capable of acquiring 625-line and 525-line
World System Teletext. Teletext pages are identified by
• Signal quality detector for WST/VPS data types seven numbers: magazine (page hundreds), page tens,
• Comprehensive Teletext language coverage page units, hours tens, hours units, minutes tens and
• Vertical Blanking Interval (VBI) data capture of WST minutes units. The last four digits, hours and minutes, are
data known as the subcode, and were originally intended to be
time related, hence their names.
Analogue to Digital Converter
The CVBS input is passed through a differential to single Making a page request
ended converter (S/D-Conv+Level-shift). The analogue A page is requested by writing a series of bytes into the
output of S/D-Conv+Level-shift is converted into a digital TXT3.PRD<4:0> SFR which correspond to the number of
representation by a Video ADC with a sampling rate of the page required. The bytes written into TXT3 are stored
12.288MHz. in a RAM with an auto-incrementing address. The start
address for the RAM is set using the TXT2.SC<2:0> to
Multi Rate Video Input Processor define which part of the page request is being written,
The multi rate video input processor is a Digital Signal TXT2.ACQ_BANK<0> and TXT3.ACQ_BANK<3:1> are
Processor designed to extract the data and recover the used to define which bank and TXT2.REQ<3:0> is used to
clock from the digital CVBS signal. define which of the 10 page requests in the selected bank
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is being modified. If TXT2.REQ<3:0> is greater than 09h, and to display each page header as it arrives until the
then data being written to TXT3 is ignored. Table 16 shows correct page has been found.
the contents of the page request RAM. When a page request is changed (i.e.: when the TXT3
Up to 10 pages of teletext can be acquired on the 10 page SFR is written to) a flag (PBLF) is written into bit 5, column
device when TXT1.EXT PKT OFF is set to logic 1; and up 9, row 25 of the corresponding block of the page memory.
to 9 pages can be acquired when this bit is set to logic 0. The state of the flag for each block is updated every TV
If the 'Do Care' bit for part of the page number is set to 0 line, if it is set for the current display block, the acquisition
then that part of the page number is ignored when the section writes all valid page headers which arrive into the
teletext decoder is deciding whether a page being display block and automatically writes an alpha-numerics
received off air should be stored or not. For example, if the green character into column 7 of row 0 of the display block
Do Care bits for the 4 subcode digits are all set to 0 then every TV line.
every subcode version of the page will be captured. When a requested page header is acquired for the first
Start Byte
PRD<4> PRD<3> PRD<2> PRD<1> PRD<0> time, rows 1 to 23 of the relevant memory block are
Column Identification
cleared to space, i.e.: have 20h written into every column,
0 Magazine DO CARE HOLD MAG2 MAG1 MAG0
1 Page Tens DO CARE PT3 PT2 PT1 PT0
before the rest of the page arrives. Row 24 is also cleared
2 Page Units DO CARE PU3 PU2 PU1 PU0
if the TXT0.X24 POSN bit is set. If the TXT1.EXT PKT OFF
3 Hours Tens DO CARE x x HT1 HT0 bit is set the extension packets corresponding to the page
4 Hours Units DO CARE HU3 HU2 HU1 HU0 are also cleared.
5 Minutes Tens DO CARE x MT2 MT1 MT0 The last 8 characters of the page header are used to
6 Minutes Units DO CARE MU3 MU2 MU1 MU0 provide a time display and are always extracted from every
7 Error Mode x x x E1 E0 valid page header as it arrives and written into the display
block
Table 16 The contents of the Page request RAM The TXT0. DISABLE HEADER ROLL bit prevents any
Note: MAG = Magazine PT = Page Tens PU = Page Units data being written into row 0 of the page memory except
HT = Hours Tens HU = Hours Units when a page is acquired off air i.e.: rolling headers and
MT = Minutes Tens MU = Minutes Units E = Error check time are not written into the memory. The TXT1.ACQ OFF
mode bit prevents any data being written into the memory by the
When the Hold bit is set to 0 the teletext decoder will not teletext acquisition section.
recognise any page as having the correct page number When a parallel magazine mode transmission is being
and no pages will be captured. In addition to providing the received only headers in the magazine of the page
user requested hold function this bit should be used to requested are considered valid for the purposes of rolling
prevent the inadvertent capture of an unwanted page headers and time. Only one magazine is used even if don't
when a new page request is being made. For example, if care magazine is requested. When a serial magazine
the previous page request was for page 100 and this was mode transmission is being received all page headers are
being changed to page 234, it would be possible to capture considered to be valid.
page 200 if this arrived after only the requested magazine
number had been changed. Error Checking
The E1 and E0 bits control the error checking which should Before teletext packets are written into the page memory
be carried out on packets 1 to 23 when the page being they are error checked. The error checking carried out
requested is captured. This is described in more detail in a depends on the packet number, the byte number, the error
later section (‘Error Checking’). check mode bits in the page request data and the TXT1.8
For a multi page device, each packet can only be written BIT bit.
into one place in the teletext RAM so if a page matches If an uncorrectable error occurs in one of the Hamming
more than one of the page requests the data is written into checked addressing and control bytes in the page header
the area of memory corresponding to the lowest numbered or in the Hamming checked bytes in packet 8/30, bit 4 of
matching page request. the byte written into the memory is set, to act as an error
At power-up each page request defaults to any page, hold flag to the software. If uncorrectable errors are detected in
on and error check mode 0. any other Hamming checked data the byte is not written
into the memory.
Rolling Headers and Time
When a new page has been requested it is conventional Teletext Memory Organisation
for the decoder to turn the header row of the display green The teletext memory is divided into 10 banks of 10 blocks.
Normally, when the TXT1.EXT PKT OFF bit is logic 0,
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each of blocks 0 to 8 contains a teletext page arranged in when a page header is received for that page. The bit in
the same way as the basic page memory of the page the SPT is set when a page header for the page is received
device and block 9 contains extension packets. When the which has the ‘subtitle’ page header control bit (C6)
TXT1.EXT PKT OFF bit is logic 1, no extension packets set.The bit for a particular page in the TPT is set when a
are captured and block 9 of the memory is used to store page header is received for that page. The bit in the SPT
another page. The number of the memory block into which is set when a page header for the page is received which
a page is written corresponds to the page request number has the ‘subtitle’ page header control bit (C6) set.
which resulted in the capture of the page.
Packet 0, the page header, is split into 2 parts when it is Packet 26 Processing
written into the text memory. The first 8 bytes of the header One of the uses of packet 26 is to transmit characters
contain control and addressing information. They are which are not in the basic teletext character set. The family
Hamming decoded and written into columns 0 to 7 of row automatically decodes packet 26 data and, if a character
25. Row 25 also contains the magazine number of the corresponding to that being transmitted is available in the
acquired page and the PBLF flag but the last 14 bytes are character set, automatically writes the appropriate
unused and may be used by the software, if necessary. character code into the correct location in the teletext
memory. This is not a full implementation of the packet 26
Row 25 Data Contents specification allowed for in level 2 teletext, and so is often
The Hamming error flags are set if the on-board 8/4 referred to as level 1.5.
Hamming checker detects that there has been an By convention, the packets 26 for a page are transmitted
uncorrectable (2 bit) error in the associated byte. It is before the normal packets. To prevent the default
possible for the page to still be acquired if some of the character data over writing the packet 26 data the device
page address information contains uncorrectable errors if incorporates a mechanism which prevents packet 26 data
that part of the page request was a 'don't care'. There is no from being overwritten. This mechanism is disabled when
error flag for the magazine number as an uncorrectable the Spanish national option is detected as the Spanish
error in this information prevents the page being acquired. transmission system sends even parity (i.e. incorrect)
The interrupted sequence (C9) bit is automatically dealt characters in the basic page locations corresponding to
with by the acquisition section so that rolling headers do the characters sent via packet 26 and these will not over
not contain a discontinuity in the page number sequence. write the packet 26 characters anyway. The special
The magazine serial (C11) bit indicates whether the treatment of Spanish national option is prevented if
transmission is a serial or a parallel magazine TXT12. ROM VER R4 is logic 0 or if the TXT8.DISABLE
transmission. This affects the way the acquisition section SPANISH is set.
operates and is dealt with automatically. Packet 26 data is processed regardless of the TXT1. EXT
The newsflash (C5), subtitle (C6), suppress header (C7), PKT OFF bit, but setting theTXT1.X26 OFF disables
inhibit display (C10) and language control (C12 to 14) bits packet 26 processing.
are dealt with automatically by the display section, The TXT8. Packet 26 received bit is set by the hardware
described below. whenever a character is written into the page memory by
The update (C8) bit has no effect on the hardware. The the packet 26 decoding hardware. The flag can be reset by
remaining 32 bytes of the page header are parity checked writing a 0 into the SFR bit.
and written into columns 8 to 39 of row 0. Bytes which pass
the parity check have the MSB set to 0 and are written into In the first edition of ETS 300 706, the “@” symbol is
the page memory. Bytes with parity errors are not written available for display at level 1 only when:
into the memory. 1). the page uses the Latin G0 set and selects the English
national option set,
Inventory Page or
If the TXT0.INV on bit is 1, memory block 8 is used as an 2). when the Hebrew G0 character set is selected.
inventory page. The inventory page consists of two tables, The device will also display @ in response to the packet 26
- the Transmitted Page Table (TPT) and the subtitle page triplet containing NULL accent (mode value 10000) and
table (SPT). character 4/0 providing the Latin G0 set is currently
In each table, every possible combination of the page tens selected.
and units digit, 00 to FFh, is represented by a byte. Each The * character is available as a level 1 character in all of
bit of these bytes corresponds to a magazine number so the defined G0 character sets and it is very unlikely that a
each page number, from 100 to 8FF, is represented by a * character would be invoked at level 1.5 via the triplet
bit in the table.The bit for a particular page in the TPT is set NULL accent, character 2/A. Therefore, the second edition
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of ETS 300 706 defines that the @ symbol should be version of the packet are the same so they are stored
displayed in response to the NULL accent, character 2/A whenever either version of the packet is acquired.
triplet for all G0 character set. In 525 line text each packet 26 only contains ten 24/18
The IC will display the * character while providing * is sent Hamming encoded data triplets, rather than the 13 found
as the fallback character on the level 1 page, and depend in 625 line text. The tabulation bit is used as an extra bit
on the software (DDS) to implement the first edition of ETS (the MSB) of the designation code, allowing 32 packet 26s
300 706 which should also display *, or the second edition to be transmitted for each page. The last byte of each
of ETS 300 706 which should display the @ symbol. packet 26 is ignored.
FASTEXT DETECTION
525 WST When a packet 27, designation code 0 is detected,
The 525 line format is similar to the 625 line format but the whether or not it is acquired, the TXT13. FASTEXT bit is
data rate is lower and there are less data bytes per packet set. If the device is receiving 525 line teletext, a packet
(32 rather than 40). There are still 40 characters per X/0/27/0 is required to set the flag. The flag can be reset
display row so extra packets are sent each of which by writing a 0 into the SFR bit.
contains the last 8 characters for four rows. These packets
can be identified by looking at the ‘tabulation bit’ (T), which BROADCAST SERVICE DATA DETECTION
replaces one of the magazine bits in 525 line teletext. When a packet 8/30 is detected, or a packet 4/30 when the
When an ordinary packet with T = 1 is received, the device is receiving a 525 line transmission, the TXT13.
decoder puts the data into the four rows starting with that Packet 8/30. The flag can be reset by writing a 0 into the
corresponding to the packet number, but with the 2 LSBs SFR bit. The data of packet 8/30 is written to the block 9.
set to 0. For example, a packet 9 with T = 1 (packet X/1/9)
contains data for rows 8, 9, 10 and 11. The error checking VPS ACQUISITION
carried out on data from packets with T = 1 depends on the When the TXT0. VPS ON bit is set, any VPS data present
setting of the TXT1. 8 BIT bit and the error checking control on line 16, field 0 of the CVBS signal at the input of the
bits in the page request data and is the same as that teletext decoder is error checked and stored in row 25,
applied to the data written into the same memory location block 9 of the basic page memory. The device
in the 625 line format. automatically detects whether teletext or VPS is being
The rolling time display (the last 8 characters in row 0) is transmitted on this line and decodes the data
taken from any packets X/1/1, 2 or 3 received. In parallel appropriately.
magazine mode only packets in the correct magazine are
used for rolling time. Packet number X/1/0 is ignored.
column
The tabulation bit is also used with extension packets. The 0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
first 8 data bytes of packet X/1/24 are used to extend the Teletext page VPS VPS VPS VPS VPS VPS VPS
row 25 header data byte 11 byte 12 byte 13 byte 14 byte 15 byte 4 byte 5
Fastext prompt row to 40 characters. These characters are
written into whichever part of the memory the packet 24 is
Fig.20 VPS Data Storage
being written into (determined by the ‘X24 Posn’ bit).
Packets X/0/27/0 contain 5 Fastext page links and the link
control byte and are captured, Hamming checked and Each VPS byte in the memory consists of 4 bi-phase
stored by in the same way as are packets X/27/0 in 625 decoded data bits (bits 0-3), a bi-phase error flag (bit 4)
line text. Packets X/1/27/0 are not captured. and three 0s (bits 5-7). The TXT13. VPS Received bit is
Because there are only 2 magazine bits in 525 line text, set by the hardware whenever VPS data is acquired. The
packets with the magazine bits all set to 0 are referred to flag can be reset by writing a 0 into the SFR bit.
as being in magazine 4. Therefore, the broadcast service
data packet is packet 4/30, rather than packet 8/30. As in
625 line text, the first 20 bytes of packet 4/30 contain 625 WSS ACQUISITION
encoded data which is decoded in the same way as that in The Wide Screen Signalling data transmitted on line 23
packet 8/30. The last 12 bytes of the packet contains half gives information on the aspect ratio and display position
of the parity encoded status message. Packet 4/0/30 of the transmitted picture, the position of subtitles and on
contains the first half of the message and packet 4/1/30 the camera/film mode. Some additional bits are reserved
contains the second half. The last 4 bytes of the message for future use. A total of 14 data bits are transmitted. All of
are not written into memory. The first 20 bytes of the each the available data bits transmitted by the Wide Screen
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Signalling signal are captured and stored in SFRs WSS1, RDS_Subsystem

WSS2 and WSS3. The bits are stored as groups of related The RDS_SUBSYSTEM contains Serialiser, RDS
bits and an error flag is provided for each group to indicate demodulator, and RDS/RBDS decoder.
when a transmission error has been detected in one or
more of the bits in the group. Wide screen signalling data Serialiser
is only acquired when the TXT8.WSS ON bit is set. The The RDS Serialiser converts the 304kHz 10-bits parallel
TXT8.WSS RECEIVED bit is set by the hardware data to 9.728MHz 32-bits serial data (10-bits data, 22-bits
whenever wide screen signalling data is acquired. The flag dummy). The output bitstream data of the Serialiser will
can be reset by writing a 0 into the SFR bit. then feed to Demodulator.
CLOSED CAPTION ACQUISITION DEMODULATOR

The US Closed Caption data is transmitted on line 21 (525 The RDS demodulator regenerates the raw RDS bit
line timings) and is used for Captioning information, Text stream (bit rate=1187.5 Hz) from the modulated RDS
information and Extended Data Services. Closed Caption signal in two steps. The first step is the demodulation of the
data is only acquired when TXT21.CC ON bit is set. Double-Side-Band Suppressed-Carrier signal around 57
Two bytes of data are stored per field in SFRs, the first bye kHz into a baseband signal, by carrier extraction and
is stored in CCDAT1 and the second byte is stored in down-mixing. The second step is the BPSK demodulation
CCDAT2. The value in the CCDAT registers are reset to of the biphase coded baseband signal, by clock extraction
00h at the start of the Closed Caption line defined by and correlation. The raw RDS bit stream data is provided
CCLIN.CS<4:0>. At the end of the Closed Caption line an for further processing by the RDS/RBDS decoder block.
interrupt is generated if IE.ECC is active.
The processing of the Closed Caption data to convert into DECODER
a displayable format is performed by Software. The RDS/RBDS decoder handles the complete data
processing and decoding of the continuously received
serial RDS/RBDS demodulator output data stream.
RDS/RBDS
Different data processing modes are software controllable
The Radio Data System (RDS)/ Radio Broadcast Data
via SFRs.
System (RBDS) informations are carried in FM radio
The RDS/RBDS decoder provides the RDS/RBDS block
channels. The FM radio channels are located in the range
detection, error detection, error correction,
from 87.5MHz to 108MHz. Once a radio channel is tuned,
synchronization, flywheel for synchronization hold, and
the MPX signal is processed by this block.
programmable block data output. New processed
RDS/RBDS block information is signalled (interrupt) to the
RDS/RBDS Features
micro-controller as “new data available” by use of the
• Demodulation of the European Radio Data System
DAVN output. The block data and the corresponding
(RDS) or the USA Radio Broadcast Data System
status information will be output to the RDS SFRs and can
(RBDS) signal
be read out by micro-controller via SFR Interface.
• RDS and RBDS block detection The processing of the RDS/RBDS data to convert into a
• Error detection and correction displayable format is performed by Software.
• Fast block synchronization
RDS/RBDS Block Detection
• Synchronization control (flywheel) The RDS/RBDS block detection is always active.
• Mode control for RDS/RBDS processing For a received sequence of 26 data bits a valid block and
• Different RDS/RBDS block information output modes corresponding offset are identified via syndrome
calculation.
During synchronization search, the syndrome is calculated
Analogue to Digital Converter with every new received data bit (bit-by-bit) for a received
The RDS input is passed to a single ended to differential 26-bit sequence. If the decoder is synchronized, syndrome
converter (S/D-conv+L-shift). The analogue output of calculation is activated only after 26 data bits for each new
S/D-conv+L-shift is converted into a digital representation block received.
by a Video ADC with a sampling rate of 304kHz. Under RBDS reception situation, besides the RDS block
sequences with (A, B, C/C’, D) offset also block sequences
of 4 blocks with offset E may be received. If the decoder
detects an ‘E-block’, the block is marked in the block
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identification number (BlNr<2:0>) and is stored in the SFR carried out until the first valid and error free block has been
LBIN<2:0>. In RBDS processing mode the block is received. Then the next expected block calculated and
signalled as valid ‘E-block’ and in RDS processing mode, syndrome calculation is done after the next 26 bits have
where only RDS blocks are expected, signalled as invalid been received. The block-span in which the second valid
‘E-block’. and expected block can be received is selectable via
This information can be used by the micro-controller to previously setting of the Max_Bad_Blocks_Gain
detect ‘E-block’ sequences and identify RDS or RBDS (MBBG<4:0>). If the second received block is an invalid
transmitter stations. block, then the bad_blocks_counter is incremented and
again the new next expected block is calculated. If the
Error Detection and Correction bad_blocks_counter value reaches the pre-selected
The RDS/RBDS error detection and correction recognizes Max_Bad_Blocks_Gain, then the bit-by-bit search for the
and corrects potential transmission errors within a first block is started again.
received block via parity-check in consideration of the If synchronization is found, the synchronization status flag
offset word of the expected block. Burst errors with a (SYNC) is set and available via SFR read. The
maximum length of 5 bits are corrected with this method. synchronization is held until the bad_blocks_counter value
After synchronization has been found the error correction reaches the pre-selected Max_Bad_Blocks_Lose value
is always active depending on the pre-selected ‘error (used for synchronization hold) or an external restart of
correction mode of synchronization’ (mode SYNCA ... synchronization is performed (NWSY=1; or power-on
SYNCD), but cannot be carried out in every reception reset).
situation.
During synchronization search, the error correction is FLYWHEEL FOR SYNCHRONIZATION HOLD
disable for detection of the first block and is enable for For a fast detection of loss of synchronization an internal
processing of the second block depending on the flywheel shall be implemented. Therefore one counter
pre-selected ‘error correction mode for synchronization’ (bad_blocks_counter) checks the number of uncorrectable
(mode SYNCA ... SYNCD). blocks and a second counter (good_blocks_counter)
The processed block data and the status of error checks the number of error free or correctable blocks.
correction are stored in the SFRs (Status Registers). Error blocks increment the bad_blocks_counter and valid
blocks increment the good_blocks_counter. If the counter
EXB1 EXB0 Description
value of the good_blocks_counter reaches the
0 0 no errors detected pre-selected Max_Good_Blocks_Lose value (MGBL<5:0>
the good_blocks_counter and bad_blocks_counter are
0 1 burst error of max. 2 bits corrected
reset to zero. But if the bad_blocks_counter reaches the
1 0 burst error of max. 5 bits corrected pre-selected Max_Bad_Blocks_Lose value (MBBL<5:0>)
1 1 uncorrectable block
then new synchronization search (bit-by-bit) is started
(SYNC=0) and both counters are reset to zero.
The flywheel function is only activated if the decoder is
Table 17 RDS processed error correction synchronized. The synchronization is held until the
Processed blocks are characterized as uncorrectable bad_blocks_counter reaches the pre-selected
under the following conditions: Max_Bad_Blocks_Lose value (loss of synchronization) or
• During synchronization search, if the burst error (for the an external forced start of new synchronization search
second block) is higher than allowed by the pre-selected (NWSY=1) is performed. The maximum values for the
correction mode SYNCA ... SYNCD. flywheel counters are both adjustable via SFR in a range
• After synchronization has been found, if the burst error of 0 to 63.
exceeds the correctable max. 5 bit burst error or if errors
are detected but error correction is not possible. Bit Slip Correction
During poor reception situation phase shifts of one bit to
Synchronization the left or right (+/- 1 bit slip) between the RDS/RBDS clock
The decoder is synchronized if two valid blocks in a valid and data may occur, depending on the lock conditions of
sequence are detected by the block detection. the demodulator clock regeneration.
The search for the first block is done by a bit-by-bit If the decoder is synchronized and detects a bit slip
syndrome calculation, starting after the first 26 bits have (BSLP=1), the synchronization is corrected +1, 0 or -1 bit
been received. This bit-by-bit syndrome calculation is via block detection on the respectively shifted expected
new block.
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Data Processing Control RBDS Processing Mode

The decoder should provide different operating modes The decoder should be suitable for receivers intended for
selectable by NWSY, SYM0, SYM1, DAC0 and DAC1 the European (RDS) as well as for the USA (RBDS)
inputs via the SFRs. The data processing control performs standard. If RBDS mode is selected (RBDS=1) via the
the pre-selected operating modes and controls the SFR, the block detection and the error detection and
requested output of the RDS/RBDS information. correction are adjusted to RBDS data processing. That is,
also E blocks are treated as valid blocks. If RBDS is reset
Restart of Synchronization Mode to zero (RDS_CTRL.RBDS=0), RDS mode is selected.
The ‘restart synchronization’ (NWSY) control mode
immediately terminates the actual synchronization and Data Available Control Modes
restarts a new synchronization search procedure The decoder provides three different RDS/RBDS data
(NWSY=1). The NWSY flag is automatically reset after the output processing modes plus one decoder bypass mode
restart of synchronization by decoder (NWSYRe pulse). selectable via the ’data available’ control mode inputs
This mode is required for a fast new synchronization on the DAC0 and DAC1.
RDS/RBDS data from a new transmitter station if the
tuning frequency is changed by the radio set. mode DAVA: Standard output mode: If the decoder is
(DAC1=0, synchronized and a new block is received (every
Restart of synchronization search is furthermore DAC0=0) 26 bits), the actual RDS/RBDS information of the
last two blocks is available with every new
automatically carried out if the internal flywheel signals a received block (approx. every 21.9ms).
loss of synchronization.
mode DAVB: Fast PI search mode: During synchronization
(DAC1=0, search and if a new A or C’ block is received, the
Error Correction Control Mode For Synchronization DAC0=1) actual RDS/RBDS information of this or the last
two A or C’ blocks respectively is available with
For error correction and identification of valid blocks during every new received A or C’ block. If the decoder
is synchronized, the "standard output mode" is
synchronization search as well as synchronization hold, active.
four different modes are selectable (SYM<1>, SYM<0>).
• mode SYNCA (SYM<1>=0, SYM<0>=0): no error mode DAVC:
(DAC1=1,
Reduced data request output mode: If the
decoder is synchronized and two new blocks are
correction; blocks detected as correctable are treated as DAC0=0) received (every 52 bits), the actual RDS/RBDS
information of the last two blocks is available with
invalid blocks internal bad_blocks_counter still every two new received blocks (approx. every
incremented even if correctable errors detected. If 43.8ms).
synchronized only error free blocks increment the mode DAVD: Decoder bypassed mode: If this mode is selected
good_blocks_counter. All blocks except error free (DAC1=1, then the OutMux output of the decoder is reset to
DAC0=1) low (OutMux=0). Then the internal row buffer
blocks increment the bad_blocks_counter. output is active and the decoder is bypassed.
This mode is not available in normal application
• mode SYNCB (SYM<1>=0, SYM<0>=1): error mode.
correction of burst error max. 2 bits; blocks corrected are
treated as valid blocks, all other errors detected are
Table 18 DAV Modes
treated as invalid blocks. If synchronized error free and
correctable max. 2 bit error increment the The decoder provides:- data output of the
good_blocks_counter. block-identification of the last and previously processed
blocks, the RDS/RBDS information words and error
• mode SYNCC (SYM<1>=1, SYM<0>=0): error
detection/correction status of the last two blocks as well as
correction of burst error max. 5 bits; blocks corrected are
general decoder status information.
treated as valid blocks, all other errors detected are
In addition the decoder output is controlled indirectly by the
treated as invalid blocks. If synchronized error free and
data request (SFR read) by micro-controller. The decoder
correctable max. 5 bit error increment the
receives a ‘data overflow’ (DOFL) signal controlled by the
good_blocks_counter.
SRF. This DOFL signal has to be set to high (DOFL=1) if
• mode SYNCD (SYM<1>=1, SYM<0>=1): no error the decoder is synchronized and a new RDS/RBDS block
correction; blocks detected as correctable are treated as is received before the previously processed block was
invalid always incremented even if correctable errors completely transmitted via SFRs. After detection of data
detected. If synchronized error free blocks are overflow the SFRs are not updated (no DecWrE) until reset
correctable max. 5 bit errors increment the of the data overflow flag (DOFL=0) by reading via the
good_blocks_counter. Only uncorrectable blocks SFRs or if NWSY=1 which results in start of new
increment the bad_blocks_counter. synchronization search (SYNC=0).
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Data Output of RDS/RBDS Information • If the decoder is synchronized and in DAVC mode two
The decoded RDS/RBDS block information and the new blocks have been processed.
current decoder status should be available via the SFRs. • If the decoder is synchronized and in any DAV mode
For synchronization of data request between except DAVD mode loss of synchronization is detected
micro-controller and decoder the additional data available (flywheel loss of synchronization, resulting in restart of
output (DAVN) is used for the interrupt. For DAVN timing synchronization search).
information see next section.
If the decoder has processed new information for the • In any DAV mode except DAVD mode, if a reset caused
by power-on or voltage-drop is detected (PresN=0).
micro-controller the data available signal (DAVN) is
activated (low) under the following condition:- • Remark: If the decoder is synchronized, the DAVN
• During synchronization search in DAVB mode if a valid signal is always activated after 21.9ms in DAVA or
A or C’ block has been detected. This mode can be used DAVB mode and after 43.8ms in DAVC mode
for fast search tuning (detection and comparison of the independent of valid or invalid blocks are detected.
PI code contained in the A and C’ blocks.
• During synchronization search in any DAV mode except
DAVN Timing
The processed RDS/RBDS data are available for
DAVD mode, if two blocks in the correct sequence have
been detected (synchronization criterion fulfilled). micro-controller request for at least 20ms after the DAVN
signal was activated. The DAVN signal is always
• If the decoder is synchronized and in mode DAVA and automatically de-activated (high) after ~ 10ms.
DAVB a new block has been processed. This mode is
the standard output mode, if the decoder is
synchronized. The decoder ignores new processed RDS/RBDS blocks if
the DAVN signal is active (low).
Fig.21 DAVN LOW-time (decoder is synchronized)
RDS SFRs
SYMBOL PARAMETER Typical UNIT
tDVL data valid to DAVN LOW 2.0 us CONTROL REGISTER

tTDAV data valid period 21.9 ms The RDS has 4 input control registers to which can be
tDV data valid 21.9 ms written by the micro-controller via the MOVX.
tDAVL data available signal is LOW 10.1 ms The RDS provides 3 different RDS/RBDS data output
processing modes plus one decoder module bypass mode
Table 19 Data Available Signal (DAVN) selectable via the control registers DAC<1:0>.
The NWSY control signal is to start new synchronization
process, if set to high. This bit of the control register is
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reset to low with a positive NWSYRe output pulse demodulator module) clock pulses and has to be used
generated automatically by the decoder module. directly as RSTD register-flag set signal.
The maximum invalid blocks allowed during Last block identification number, LBIN<2:0> hold the block
synchronization search (SYNC=0). If the first block needed number of the last processed RDS/RBDS data block. The
for synchronization has been found and the expected LBIN<2:0> are controlled by the output signals, BlNr<2:0>,
second block (after 26 bits) is an invalid block, then the of decoder module. The LBIN<2:0> registers has to be
decoder module internal_bad_blocks_counter is connected to the inputs of the register(PBlN<2:0>) which
incremented and the next expected block is calculated; holds the previously processed block number. So if
exception: if RBDS mode is selected and the first block is RCopyE is set to high while DecWrE is active a copy from
block E, then the next expected block is always block A, the last to the previously block number will be done.
until synchronization is found or the maximum Error status of last block, ELB<1:0>, these registers are
bad_blocks_counter value is reached. If the decoder controlled by the output signals, EXB1 & EXB0. The
module internal bad_blocks_counter reaches the value of ELB<1:0> holds the error status of the last processed
the MBBG<4:0>, then immediately start of new RDS/RBDS data block. The output of these registers has
synchronization search (bit-by-bit) is started to find a new to be connected to the input of the register (EPB<1:0>)
first block. The function of Max_Bad_Blocks_Gain is which holds the previously processed error status. So, if
disable if MAX_Bad_Blocks_Gain is set to zero. Only in RCopyE is set to high while DecWrE is active a copy from
this case the 2 path synchronization search function is the last to the previously error status will be done.
activated. Bad block counter registers, BBC<5:0>, represent the
For error correction and identification of valid blocks during actual bad_blocks_counter value.
synchronization search as well as synchronization hold, 4 Good block counter registers, GBC<5:1>, represent the
different modes are selectable (SYM<1>, SYM<0>). actual good_blocks_counter value.
MBBL<5:0> - Max_Bad_Blocks_Lose: maximum invalid
blocks allowed while synchronized (SYNC=1). If the RDS/RBDS DECODED DATA REGISTER
decoder module internal bad_blocks_counter reaches this The decoder module has 4 output registers to put the
value, then immediately start of “new synchronization processed/decoded RDS/RBDS block data. These
search” (bit-by-bit) is started (SYNC=0) and the internal registers can be read by the micro-controller after
bad_blocks_counter as well as the good_blocks_counter detection of the RDS interrupt (DAVN=low).
itself are reset to zero. Last processed data, LDAT<15:0>, hold the parallel output
MGBL<5:0> - Max_Good_Blocks_Lose: maximum valid of the 16 bit from Data<15:0> decoder module output bus,
blocks required to clear the decoder module internal which represents the information word of the last
bad_blocks_counter. Only activated while synchronized processed RDS/RBDS data block. The output of this
(SYNC=1). If the decoder module internal registers has to be connected to the input of the register
good_blocks_counter reaches this value, then PDAT<15:0> which holds the previously processed block
immediately the bad_blocks_counter and the data. So if RCopyE is set to high while DecWrE is active a
good_blocks_counter itself are reset to zero. copy from the last to the previously block will be done.
RBDS - If this bit set to high, then allow processing of
RBDS ‘E’ block. Otherwise, if set to low, it will enter RDS
DISPLAY
mode.
The display section is based on the requirements for a
Level 1.5 WST Teletext and US Closed Caption. There are
STATUS REGISTER
some enhancements for use with locally generated
The RDS module has one status register.
On-Screen Displays.
The output signal, SYNC, from decoder module indicates
The display section reads the contents of the Display
the synchronization found. It is set high, if synchronization
memory and interprets the control/character codes. Using
is found; otherwise reset to zero. The SYNC output signal
this information and other global settings, the display
directly effects the status register.
produces the required RGB signals and Video/Data (Fast
RSTD is set to high, if a reset occurred, caused by
Blanking) signal for the TV signal processing.
power-on reset or voltage drop. RSTD register is set by
The display is synchronised to the TV signal processing by
SRSTD signal output from decoder module. The RSTD
way of Horizontal and Vertical sync signals generated
status flag has to be cleared automatically after the status
within UOCIII. From these signals all display timings are
register was read by micro-controller. SRSTD is set to high
derived.
(after power-on reset) for the first received 26 RDCL(from
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Display Features device.The display is configured as a fixed 25 rows

• Teletext and Enhanced OSD modes with 40 characters per row.
• Level 1.5 WST features • CC:- This is the display configured as the US Closed
• US Closed Caption Features Caption mode with the same functionality as the
PC83C771 device. The display is configured as a
• 50Hz/60Hz display timing modes maximum of 16 rows with a maximum of 48
• Two page operation for 16:9 screens characters per row.
• Serial and Parallel Display Attributes • OSD:-This is the display configured as either TXT or CC
• Single/Double/Quadruple Width and Height for mode but without the restriction of display size or
characters character matrix.
• Smoothing capability of both Double Size, Double Width There is an option of 10/13/16/18 lines per display row for
& Double Height characters CC style OSD mode, the characters used in these rows
can be either 12x13, 12x16, 12X18, 16X16, 16x18.
• Scrolling of display region
In CC style OSD mode the number of rows and columns
• Variable flash rate controlled by software available in limited by the maximum row value of 16, the
• Globally selectable scan lines per row 9/10/13/16/18. maximum column value of 48 and the maximum number of
character location of 624. This gives a full occupied display
• Globally selectable character matrix (HxV) 12x9/10,
of 16 rows by 39 columns for maximum rows, or 13 rows
12x13, 12x16, 16x16 and 16x18
by 48 columns for maximum columns.
• Italics, Underline and Overline In TXT style OSD mode the maximum number of rows is
• Soft Colours using CLUT with 4096 colour palette. 25 and the maximum number of columns is 40, both of
• Fringing (Shadow) selectable from N-S-E-W direction. these limits can be achieved simultaneously.
Note: Not all combinations of lines per row and maximum
• Fringe colour selectable display rows give a sensible OSD display, since there is
• Contrast reduction of defined area is available in both limited number of TV scan lines available.
TXT and CC mode Special Function Register, TXT21 and memory mapped
• Double window register are used to control the mode selection.
• Cursor
The following is a list of features available in each mode.
• Special Graphics characters with two planes, allowing Each setting can either be a serial or parallel attribute, and
four colours per character some have a global effect on the display.
• 64 Software re-definable DRCs (Dynamically
Re-definable Characters), when it’s used as 4 colour
Feature TXT CC
mode for each pixel, the number of DRCs will be 32
• 4 WST Character sets(G0/G2) in single device (e.g. Flash serial serial
Latin, Cyrillic, Greek, Arabic)
Boxes TXT/OSD (Serial) serial
• G1 Mosaic graphics, Limited G3 Line drawing
characters Horizontal Size x1/x2/x4 (serial) x1/x2 (serial)
• WST Character sets and Closed Caption Character set Vertical Size x1/x2 (serial) x1/x2 (serial)
in single device x4 (global)
• Panorama Mode, display 4:3 signals on 16:9 screen Italic N/A serial
• SCAVEM for Text
Foreground 8 (serial) 8+8 (parallel)
colours
Display Modes
The display section has three distinct modes with different Background 8 (serial) 16 (serial)
colours
features available in each. The two modes are:
• TXT:- This is the display configured as the WST mode Soft Colours 16 from 4096 16 from 4096
with additional serial and global attributes to enable (CLUT)
the same functionality as the SAA5497 (ETT)
Table 20 Display Features
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mode the background colour is displayed. Character

Feature TXT CC
locations where boxes are not set show video/screen
Underline N/A serial colour (depending on the setting in the display control
register. REG0: Display Control) in stead of the
Overline N/A serial
background colour.
Fringe N+S+E+W N+S+E+W TXT: Two types of boxes exist the Teletext box and the
OSD box. The Teletext box is activated by the ‘start box’
Fringe Colour 16 (Global) 16 (Serial) control character (0Bh), Two start box characters are
required begin a Teletext box, with box starting between
Smoothing YES (Global) YES (Global)
the 2 characters. The box ends at the end of the line or
Fast Blanking YES YES after a ‘end box’ control character.
Polarity TXT mode can also use OSD boxes, they are started using
Screen Colour 16 (Global) 16 (Global) size implying OSD control characters
(BCh/BDh/BEh/BFh). The box starts after the control
DRCS 64 (Global) 64 (Global) character (‘set after’) and ends either at the end of the row
or at the next size implying OSD character (‘set at’). The
Character Matrix 12x9/10/13/16 12x9/10/13/16,
(HxV) 16x16/18 attributes flash, teletext box, conceal, separate graphics,
twist and hold graphics are all reset at the start of an OSD
No. of Rows 25 16 box, as they are at the start of the row. OSD Boxes are only
valid in TV mode which is defined by TXT5=03h and
No. of Columns 40 48
TXT6=03h.
No of Characters 1000 624
displayable SIZE
Cursor YES YES The size of the characters can be modified in both the
horizontal and vertical directions.
Special Graphics 32 32 CC: Two sizes are available in both the horizontal and
(2 planes per vertical directions. The sizes available are normal (x1),
character)
double (x2) height/width and any combination of these.
Scroll NO YES The attribute setting is always valid for the whole row.
Mixing of sizes within a row is not possible.
Table 20 Display Features TXT: Three horizontal sizes are available
normal(x1),double(x2),quadruple(x4). The control
Display Feature Descriptions
characters ‘normal size’ (0Ch/BCh) enables normal size,
the ‘double width’ or double size (0Eh/BEh/0Fh/BFh)
FLASH
enables double width characters. Any two consecutive
Flashing causes the foreground colour pixel to be
combination of ‘double width’ or ‘double size’
displayed as the background pixels.The flash frequency is
(0Eh/BEh/0Fh/BFh) activates quadruple width characters,
controlled by software setting and resetting display
provided quadruple width characters are enabled by
register REG0: Status at the appropriate interval.
TXT4.Quad Width Enable.
CC: This attribute is valid from the time set (see Table 27)
Three vertical sizes are available normal(x1), double(x2),
until the end of the row or until otherwise modified.
quadruple(x4). The control characters ‘normal size’
TXT: This attribute is set by the control character ‘flash’
(0Ch/BCh) enable normal size, the ‘double height’ or
(08h) and remains valid until the end of the row or until
‘double size’ (0Dh/BDh/0Fh/BFh) enable double height
reset by the control character ‘steady’ (09h).
characters. Quadruple height character are achieved by
using double height characters and setting the global
BOXES
attributes TXT7.Double Height (expand) and
CC: This attribute is valid from the time set until end of row
TXT7.Bottom/Top.
or otherwise modified if set with Serial Mode 0. If set with
If double height characters are used in teletext mode,
Serial Mode 1, then it is set from the next character
single height characters in the lower row of the double
onwards.
height character are automatically disabled.
In CC text mode the background colour is displayed
regardless of the setting of the box attribute bit. Boxes take
affect only during mixed mode, where boxes are set in this
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ITALIC writing data to a RAM that resides in the MOVX address

CC: This attribute is valid from the time set until the end of space of the 80C51.
the row or otherwise modified. The attribute causes the
RED3-0 GRN3-0 BLU3-0 Colour
character foreground pixels to be offset horizontally by 1
b11. . .b4 b7. . .b4 b3. . .b0 entry
pixel per 4 scan lines (interlaced mode). The base is the
bottom left character matrix pixel. The pattern of the 0000 0000 0000 0
character is indented as shown in Fig.22
0000 0000 1111 1
... ... ... ...

0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10
0
1 12x16 character matrix 12x13 character matrix 12x10 character matrix
Indented by 7/6/4 1111 1111 0000 14
2
3 Indented by 6/5/3
4 1111 1111 1111 15
Indented by 5/4/2
5
6 Indented by 4/3/1
7
8 Indented by 3/2/0 Table 21 CLUT Colour values
9
10 Indented by 2/1
11
12 Indented by 1/0
13
14 Indented by 0
15
Field 1
Field 2
Italy Shift Scan Line

Indented -2
by 10 -1
Indented 0
by 9 1
Indented 2
by 8 3
Indented 4
by 7 5
Indented 6
by 6 7
Indented 8
by 5 9
Indented 10
by 4 11
Indented 12
by 3 13
Indented 14
by 2 15
Indented 16
by 1 17
Indented 18
by 0 19
Pixels 0
4 8 0 2 4 6
2 6 10 12 14
Character Size 16 Wide x 18 High
Fig.22 Italic Characters

TXT: The Italic attribute is not available.
COLOURS
CLUT (Colour Look Up Table)

A CLUT (Colour Look Up Table) with 16 colour entries is
provided. The colours are programmable out of a palette
of 4096(4 bits per R, G and B). The CLUT is defined by
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The default value of the CLUT when entering TXT mode is Serial Mode 1, then the colour is set from the next
given in the table below, this gives the required full character onwards.
intensity teletext colours. The background colour can be chosen from all 16 CLUT
entries.
TXT: The control character “New background” (“1Dh”) is
Full Intensity Full Intensity used to change the background colour to the current
CLUT Equivalent CLUT Equivalent
Address Default<11:0> (Foreground) Address Default<11:0> (Background) foreground colour. The selection is immediate (“Set at”)
0 000000000000 Black 8 000000000000 Black and remains valid until the end of the row or until otherwise
modified.
1 111100000000 Red 9 111100000000 Red
The TEXT background control characters map to the
2 000011110000 Green A 000011110000 Green CLUT entries as shown below:
3 111111110000 Yellow B 111111110000 Yellow Control Code Defined Colour CLUT Entry
4 000000001111 Blue C 000000001111 Blue 00h+1Dh Black 8
5 111100001111 Magenta D 111100001111 Magenta 01h+1Dh Red 9
6 000011111111 Cyan E 000011111111 Cyan 02h+1Dh Green 10
7 111111111111 White F 111111111111 White 03h+1Dh Yellow 11
Table 22TXT Default CLUT map 04h+1Dh Blue 12
05h+1Dh Magenta 13
Foreground Colour 06h+1Dh Cyan 14
CC: The foreground colour can be chosen from 8 colours
on a character by character basis. Two sets of 8 colours 07h+1Dh White 15
are provided. A serial attribute switches between the Table 24 Background CLUT mapping
banks (see Table 27 Serial Mode 1, bit 7). The colours are
the CLUT entries 0 to 7 or 8 to 15. BACKGROUND DURATION
TXT: The foreground colour is selected via a control The attribute when set takes effect from the current
character. The colour control characters takes effect at the position until to the end of the text display defined in
start of the next character (“Set-After”) and remain valid REG4:Text Area End.
until the end of the row, or until modified by a control CC: The background duration attribute (see Table 27,
character. Only 8 foreground colours are available. Serial Mode 1, bit 8) in combination with the End Of Row
The TEXT foreground control characters map to the CLUT attribute (see Table 27, Serial Mode 1, bit 9) forces the
entries as shown below: background colour to be display on the row until the end of
Control Code Defined Colour CLUT Entry
the text area is reached.
TXT: This attribute is not available.
00h Black 0
01h Red 1 UNDERLINE

The underline attribute causes the characters to have the
02h Green 2
bottom scan line of the character cell forced to foreground
03h Yellow 3 colour, including spaces. If background duration is set,
04h Blue 4
then underline is set until the end of the text area.
CC: The underline attribute (see Table 27, Serial Mode
05h Magenta 5
0/1, bit 4) is valid from the time set until end of row or
06h Cyan 6 otherwise modified.
TXT: This attribute is not available.
07h White 7
Table 23 Foreground CLUT mapping OVERLINE

The overline attribute causes the characters to have the
Background Colour top scan line of the character cell forced to foreground
CC: This attribute is valid from the time set until end of row colour, including spaces. If background duration is set,
or otherwise modified if set with Serial Mode 0. If set with then overline is set until the end of the text area.
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CC: The overline attribute (see Table 27, Serial Mode 0/1, defined by TXT10.C<5:0>. The position of the cursor can
bit 5) is valid from the time set until end of row or otherwise be fixed using TXT9.CURSOR FREEZE.
modified. Overlining of Italic characters is not possible. CC: The valid range for row is 0 to 15. The valid range for
TXT: This attribute is not available. column is 0 to 47. The cursor remains rectangular at all
times, it’s shape is not affected by italic attribute, therefore
END OF ROW it is not advised to use the cursor with italic characters.
CC: The number of characters in a row is flexible and can TXT: The valid range for row positioning is 0 to 24.The
determined by the end of row attribute (see Table 27, valid range for column is 0 to 39.
Serial Mode 1, bit 9). However the maximum number of
character positions displayed is determined by the setting
of the REG2:Text Position Horizontal and REG4:Text Area
End.
NOTE: When using the end of row attribute the next
ABCDEF
character location after the attribute should always be
occupied by a ’space’. Fig.24 Cursor Display
TXT: This attribute is not available, Row length is fixed at
40 characters. SPECIAL GRAPHICS CHARACTERS
-Normal Special Graphics character
FRINGING Mode(TXT20.Extended special graphics = 0)
A fringe (shadow) can be defined around characters. The CC/TXT: Several special characters are provided for
fringe direction is individually selectable in any of the improved OSD special effects. These characters provide a
North, South, East and West direction using choice of 4 colours within a character cell. Addressing is
REG3:Fringing Control. The colour of the fringe can also therefore done using only the even character addresses.
be defined as one of the entries in the CLUT, again using The total number of special graphics characters is limited
REG3:Fringing Control. to max. 32 when Extended Special Graphics is not
CC: The fringe attribute (see Table 27, Serial Mode 0, bit enabled. They are stored in the character codes 8Xh, 9Xh
9) is valid from the time set until the end of the row or of the character table (32 ROM characters), or in the DRCs
otherwise modified. which overlay character codes 8Xh, 9Xh, AXh and CXh (if
TXT: The display of fringing in TXT mode is controlled by Extended DRC is enabled). Each special graphics
the TXT4.SHADOW bit. When set all the alphanumeric character uses two consecutive normal characters. The
characters being displayed are shadowed, graphics pixel planes are stored in adjacent characters, always
characters are not shadowed. starting with an even character. Special graphics
characters are activated when
TXT20/TXT29.OSD_PLANE = 1.
-Extended Special Graphics character

Mode(TXT20.Extended special graphics = 1)
CC:- When "TXT20.Extended special graphics" is
enabled, all characters from the ROM can be used as
special graphics characters in this mode. Each special
graphics character uses two consecutive characters from
the normal Character Set. Closed Caption character code
bit-14 enables display of special graphics on a character
by character basis.
Fig.23 South and Southwest Fringing note: Special Graphics capability extended to any
character only in Closed_Caption Mode
CURSOR
The cursor operates by reversing the background and Four-colour on-screen display characters can be created
foreground colours in the character position pointed to by in closed caption and teletext style sets, provided they are
the active cursor position. The cursor is enabled using either 12x13 or 16x16 or16x18 characters. Four-colour
TXT7.CURSOR ON. When active, the row the cursor characters are generated by overlaying two consecutive
appears on is defined by TXT9.R<4:0> and the column is
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two-colour characters. For example see following figure. Height, Double Width and Double Size Characters are all
The two characters on the left could overlap to produce the improved when smoothing is enabled.
four-colour character on the right. For the character
definition the black would represent a 1 and the white Character and Attribute Coding
would represent a 0. Four-colour characters can easily be
defined using the DDS tool. The character is defined on a CC MODE
pixel-by-pixel basis, after checking four colours option. Character coding is split into character oriented attributes
(parallel) and character group coding (serial). The serial
The colours here have been used for the example. Four attributes take effect either at the position of the attribute
colours are achieved by using the foreground and the (Set At), or at the following location (Set After) and remain
background colours, for example CLUT entries 0 and 1, effective until either modified by a new serial attribute or
and the default (for four-colour characters) CLUT entries 6 until the end of the row. A serial attribute is represented as
and 7. In your application software you will need to define a space (the space character itself however is not used for
the CLUT Table entries to obtain the colours that you this purpose), the attributes that are still active, e.g.
require and the foreground and the background colours. overline and underline will be visible during the display of
the space. The default setting at the start of a row is:
• 1x size, flash and italics OFF
Plane 1 Plane 0 Colour Colour Allocation
• overline and underline OFF
0 0 Blue Background Colour
• Display mode = superimpose
0 1 White Foreground Colour • fringing OFF
1 0 Red CLUT Entry 6 or 14 depending on • background colour duration = 0
the set bank
• end of row = 0
1 1 Green CLUT Entry 7 or 15 depending on The coding is done in 15 bit words. The codes are stored
the set bank
sequentially in the display memory. A maximum of 768
character positions can be defined for a single display.
Table 25 Special Character Colour allocation
PARALLEL CHARACTER CODING
.
Bits Description
Background Colour Serial Attribute Background Colour
“set at” (Mode 0) “set after” (Mode 1) 0-7 8 bit character code
8-10 3 bits for 8 foreground colours
11 Mode bit:
VOLUME 0 = Parallel code
12-13 Character Select Selection:

00 = Character Set 0
Foreground Colour 01 = Character Set 1
Background Colour Normal Character 10 = Character Set 2
Foreground Colour 7 Foreground Colour 6
11 = Character Set 3
Special Character
14 Character Definition:
0 = Single Plane Character
Fig.25 Special Character Example 1 = Two Plane Character (four colour)
Table 26 Parallel Character Coding

The example in Fig.25 can be done with 8 special graphics
characters.
Smoothing
Smoothing is available in both TXT and CC modes and is
activated using MMR 87E4<5:4>. The clarity of Double
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SERIAL CHARACTER CODING
Bits Description
Serial Mode 0 Serial Mode 1
(“set at”) Char.Pos. 1 (“set at”) Char.Pos. >1 (“set after”)
0-3 4 bits for 16 Background 4 bits for 16 Background colours 4 bits for 16 Background colours
colours
4 0 = Underline OFF Horizontal Size: 0 = Underline OFF

1 = Underline ON 0 = normal 1 = Underline ON
1 = x2
5 0 = Overline OFF Vertical Size: 0 = Overline OFF

1 = Overline ON 0 = normal 1 = Overline ON
1 = x2
6 Display mode: Display mode: Display mode:

0 = Superimpose 0 = Superimpose 0 = Superimpose
1 = Boxing 1 = Boxing 1 = Boxing
7 0 = Flash OFF Foreground colour switch Foreground colour switch

1 = Flash ON 0 = Bank 0 (colours 0-7) 0 = Bank 0 (colours 0-7)
1 = Bank 1 (colours 8-15) 1 = Bank 1 (colours 8-15)
8 0 = Italics OFF Background colour duration: Background colour duration

1 = Italics ON 0 = stop BGC (set at):
1 = set BGC to end of row 0 = stop BGC
1 = set BGC to end of row
9 0 = Fringing OFF End of Row End of Row (set at):

1 = Fringing ON 0 = Continue Row 0 = Continue Row
1 = End Row 1 = End Row
10 Switch for Serial coding Switch for Serial coding mode 0 Switch for Serial coding mode 0
mode 0 and 1: and 1: and 1:
0 = mode 0 1 = mode 1 1 = mode 1
11 Mode bit: Mode bit: Mode bit:
1 = Serial code 1 = Serial code 1 = Serial code
12 0 = Cont. Red. OFF 0 = Cont. Red. OFF 0 = Cont. Red. OFF

1 = Cont. Red. ON 1 = Cont. Red. ON 1 = Cont. Red. ON
Table 27 Serial Character Coding Bits 12/13 of the parallel character coding are used to
Character ROM Selection in CC Mode select the character set on character by character basis. In
CC Mode only, bits 13 and 12 of character code can
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control the character set selection when TXT20<4> is set. attribute will behave in exactly the same fashion as the
When TXT20<4> is reset to ’0’ the normal BS<1:0> background colour attribute.
bits(TXT18<1:0>) control character set selection as for The actual contrast reduction is carried out in the Video
Text mode. Signal Processor die and is simply switched in and out by
the cont_red signal from TCG micro-controller. The effect
In table 28 shows the character set selection. Although the of contrast reduction is to reduce the brightness and
hardware allow to select from 4 character sets, due to the contrast of the video image behind the OSD. For this
DDS tool limitation the Set 0 is only for teletext. reason, contrast reduction is only visible in mixed screen
mode with superimposed text.
TXT MODE
CC Mode character Example
Char code<13:12> Set Language Character coding is in a serial format, with only one
attributes being changed at any single location. The serial
00 Set 0 Latin attributes take effect either at the position of the attribute
(Set At), or at the following location (Set After). The
01 Set 1 Greek attribute remains effective until either modified by new
serial attributes or until the end of the row.The default
10 Set 2 Cyrillic
settings at the start of a row is:
11 Set 3 Arabic • foreground colour white (CLUT Address 7)
• background colour black (CLUT Address 8)
Table 28 Character Set Selection • Horizontal size x1, Vertical size x1 (normal size)
• Alphanumeric ON
Serial mode 0
• Contiguous Mosaic Graphics
Serial mode 0 means that these attributes are valid from
the time set until the end of the row or until otherwise • Release Mosaics
modified. This differs from serial mode 1, where they are • Flash, Box, Conceal and Twist OFF
valid from the next character onwards. The attributes have individual codes which are defined in
the basic character table below:
Serial mode 1
Serial mode 1 means that these attributes are valid from
the character following the character code until the end of
the row or until otherwise modified. This differs from serial
mode 0 where they are also valid for the character code
itself. However, for the first character of each line, serial
mode 1 behaves differently.
When a serial mode 1 character code is set in position 1 of
a line, attributes are valid from the time set as in mode 0.
There is also a different set of attributes. All but two of
these attributes are the same as for the rest of the line. The
two different attributes are horizontal and vertical size, bits
4 and 5 respectively. These replace Underline and
Overline.
Contrast Reduction in CC Mode

When bit 12 of the serial character coding is set, this
generates a contrast reduction box. By setting TXT5 bits 5
and 4, contrast reduction can be enabled inside, or
outside, these boxes. When contrast reduction is active,
the cont_red output signal is set low. The cont_red signal
is always synchronized with VDS. With regard to
interaction with other features, the contrast reduction
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E/W = 0 E/W = 1
b7
0 0 0 0 0 0 0 0 10 1 1 1 0 1 11 11 11 11 11 11
b6 0 0 0 0 1 1 1 1 0 1
bits b5 0
0
0
1
1
0
1 0 0
1 0 1
1
0
1
1 0 0 01 1
1
0 0 1 1 0 1 1
b4
0 1 0 0 1 0 1 1 0 1
b3 b2 b1 b0
column
0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 8a 9 9a A B C D E F D E F
row
alpha graphics Nat Nat O O O O bkgnd

0000 0 black black Opt Opt S S
D D
S S
D D black
alpha graphics O O O O bkgnd
0001 1 red red
S S
D D
S S
D D red
0010 2 green green
S S
D D
S S
D D green
alpha graphics Nat O O O O bkgnd
0011 3 yellow yellow Opt
S S
D D
S S
D D yellow
alpha graphics Nat O O O O bkgnd
0100 4 blue blue Opt
S S
D D
S S
D D blue
0101 5 magenta magenta
S S
D D
S S
D D magenta
0110 6 cyan cyan
S S
D D
S S
D D cyan
0111 7 white white
S S
D D
S S
D D white
conceal O O O O
1000 8 flash
display S S
D D
S S
D D
contiguous O O O O
1001 9 steady
graphics
S S
D D
S S
D D
end separated O O O O
1010 A box graphics
S S
D D
S S
D D
start Nat Nat O O O O
1011 B box
twist
Opt Opt
S S
D D
S S
D D
normal black Nat Nat O O O O norm sz
1100 C height bkgnd Opt Opt
S S
D D
S S
D D OSD
double new Nat Nat O O O O dbl ht
1101 D height bkgnd Opt Opt
S
D
S
D
S S
D D OSD
double hold Nat Nat O O O O dbl wd
1110 E width graphics Opt Opt
S S
D D
S S
D D OSD
double release Nat O O O O dbl sz
1111 F size graphics Opt
S S
D D
S S
D D OSD
Fig.26 TXT Basic Character Set (Pan-European)
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Screen and Global Controls

A number of attributes are available that affect the whole
display region, and cannot be applied selectively to
Display Mode MOD Description
regions of the display. <1 0>
TV SCAN LINES PER ROW Video 0 0 Video mode disables all display
The number of TV scan lines per field used for each activities and sets the RGB to true
black and VDS to video.
display row can be defined, the value is independent of the
character size being used. The number of lines can be Full Text 0 1 Full Text mode displays screen
either 10/13/16 per display row. The number of TV scan colour at all locations not covered by
lines per row is defined TXT21.DISP_LINES<1:0>. character foreground or background
A value of 9 lines per row can be achieved if the display is colour. The box attribute has no
effect.
forced into 525 line display mode by
TXT17.DISP_FORCE<1:0>, or if the device is in 10 line Mixed Screen 1 0 Mixed Screen mode displays screen
mode and the automatic detection circuitry within display Colour colour at all locations not covered by
finds 525 line display syncs. character foreground, within boxed
areas or, background colour.
CHARACTER MATRIX (HXV) Mixed Video 1 1 Mixed Video mode displays video at
There are five different character matrices available, these all locations not covered by
are 12x13, 12x16, 16x16 and 16x18. The selection is character foreground, within boxed
made using TXT21.CHAR_SIZE<1:0> and is independent areas or, background colour.
of the number of display lines per row.
If the character matrix is less than the number of TV scan Table 29 Display Modes
lines per row then the matrix is padded with blank lines. If
the character matrix is greater than the number of TV scan
lines then the character is truncated. TXT: The display mode is controlled by the bits in the TXT5
and TXT6. There are 3 control functions - Text on,
Background on and Picture on. Separate sets of bits are
Display Modes used inside and outside Teletext boxes so that different
CC: When attributes superimpose or when boxing (see display modes can be invoked. TXT6 is used if the
Table 27, Serial Mode 0/1, bit 6) is set, the resulting display newsflash (C5) or subtitle (C6) bits in row 25 of the basic
depends on the setting of the following screen control page memory are set otherwise TXT5 is used. This allows
mode bits in REG0:Display Control. the software to set up the type of display required on
newsflash and subtitle pages (e.g. text inside boxes, TV
picture outside) this will be invoked without any further
software intervention when such a page is acquired.
Background
Picture On Text On Effect
On
0 0 x Text mode, black screen
0 1 0 Text mode, background always black
0 1 1 Text mode
1 0 x Video mode
1 1 0 Mixed text and TV mode
1 1 1 Text mode, TV picture outside text area
Table 30 TXT Display Control Bits
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Screen Colour
Screen colour is displayed from 10.5 us to 62.5 us after the
active edge of the HSync input and on TV lines 23 to 310 Display Memory Text Area
ROW
inclusive, for a 625 line display, and lines 17 to 260 0 Display 0
inclusive for a 525 line display. 1 possible 1
2 2
The screen colour is defined by REG0:Display Control and 3 3
Display Map Entries

points to a location in the CLUT table. The screen colour 4 4
Enable bit = 0
5 5
covers the full video width. It is visible when the Full Text 6 Soft Scrolling 6
7 display possible 7
or Mixed Screen Colour mode is set and no foreground or 8 8
background pixels are being displayed. 9 9
10 10
11 11
Text Display Controls 12 12
13 Display 13
14 possible 14
TEXT DISPLAY CONFIGURATION 15 15
Two types of area are possible. The one area is static and
the other is dynamic. The dynamic area allows scrolling of
Display Data
a region to take place. The areas cannot cross each other.
Only one scroll region is possible.
Display Map
The display map allows a flexible allocation of data in the
memory to individual rows.
Sixteen words are provided in the display memory for this
purpose. The lower 10 bits address the first word in the
memory where the row data starts. This value is an offset
in terms of 16-bit words from the start of Display Memory Fig.27 Display Map and Data Pointers
(8000 Hex). The most significant bit enables the display
when not within the scroll (dynamic) area. SOFT SCROLL ACTION
The display map memory is fixed at the first 16 words in The dynamic scroll region is defined by the REG5:Scroll
the closed caption display memory. Area, REG6:Scroll Range, REG14:Top Scroll line and the
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 REG8:Status Register. The scroll area is enabled when
Pointer to Row Data the SCON bit is set in REG8: Status.
Reserved, should be set to 0 The position of the soft scroll area window is defined using
the Soft Scroll Position (SSP<3:0), and the height of the
Text Display Enable, valid outside Soft Scroll Area
window is defined using the Soft Scroll Height (SSH<3:0>)
0 = Disable
both are in REG6:Scroll Range. The rows that are scrolled
1 = Enable
through the window are defined using the Start Scroll Row
Table 31 Display map Bit Allocation (STS<3:0>) and the Stop Scroll Row (SPS<3:0>) both are
in REG5:Scroll Area.
The soft scrolling function is done by modifying the Scroll
Line (SCL<3:0>) in REG14: Top Scroll Line. and the first
scroll row value SCR<3:0> in REG8:Status. If the number
of rows allocated to the scroll counter is larger than the
defined visible scroll area, this allows parts of rows at the
top and bottom to be displayed during the scroll function.
The registers can be written throughout the field and the
values are updated for display with the next field sync.
Care should be taken that the register pairs are written to
by the software in the same field.
Only a region that contains only single height rows or only
double height rows can be scrolled.
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ROW
0
1 Usable for OSD Display Start Scroll Row
2 STS<3:0> e.g. 3
3 Should not be used for
Soft Scroll Position 4 OSD Display
Pointer SSP<3:0> e.g. 6
5
6
Soft Scroll Height 7
SSH<3:0> e.g.4 Soft Scrolling Area
8
9
10 Should not be used for
11 OSD Display
12 Stop Scroll Row
13 SPS<3:0> e.g. 11
14 Usable for OSD Display
15
Fig.28 Soft Scroll Area
ROW 0-63 lines

0 row0
1
2
row1 P01 NBC
3 row2 Scroll Area
4 row3 Offset
5 row4
6 row5
7 row6
8 row7
9 row8
ClosedCaptioning data row n
10 Closed Captioning data row n+1
11 Closed Captioning data row n+2 Visible area
12 for scrolling
Closed Captioning data row n+3
13 Closed Captioning data row n+4
14 row13
15 row14
Fig.29 CC Text Areas
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Two Page Display 0 of Display Configuration register 87FF. Two character

This mode enables two different pages to be displayed spaces are required between the pages to allow the
side by side for use with 16:9 TV Screens. Fig.30 shows display logic to switch correctly.
the possible combinations for two page display. The facility
is restricted to 1H/1V. Two page mode is selected using Bit
Screen Colour Area Screen Colour Area
Text Text
Text Text
OSD Subtitle
Text Video Text Text
CC
Video CC Video OSD
CC CC
Text Text
OSD OSD
Fig.30 Two Page TXT/CC/Video Combination
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Two CC_TXT mode control bits exist in two page mode, Screen Colour: Only the Screen colour definition for Text
TXT21<0> controls Text Area A and TXT31<6> (CC_TXT is required to be duplicated since only 1 CC page is
B) controls Text Area B. possible on a side with video on the other. The Text
TXT:- Screen Colour register Txt17<2:0> applies to Text area A
When displaying two teletext pages side by side, Text Area and Txt27<2:0> shall determine Screen Colour in Text
A display is selected using the Page A<3:0> register Area B.
TXT14<3:0> and Text Area B is selected using the Page
B<3:0> register TXT28<3:0>. The rolling header and time Double Window
information written by Acquisition will only apply to the In this mode, the video picture will display in the left half of
active page. the screen, the other half is for Text. The control bit is
Active Page Operation: enabled in SFR Video_process.DW_PA<1:0>=”01”
i) When reset to logic ’0’ (default value), acquisition writes enables double window functionality.
the header and time information to Text Area A. When set
to logic ’1’, acquisition writes the header and time
information to Text Area B.
ii) The display uses the Active Page bit to direct which
page (’0’ = Text Area A, ’1’ = Text Area B) to allow
operation of the Reveal bit, TXT7<5>, and Cursor,
TXT7<6>. The Expand mode is controlled individually on
each page.
CC:- When CC display mode is selected in two page mode
only one screen half may be used for CC/OSD and the
other either Text or Video. Two page CC display side by
side is not possible due to CC display RAM limitation (only
1 block RAM for CC).
To allow some flexibility in 2 page mode the DRCS Enable
bit is duplicated for the second page into TXT23<2>. This
allows two Text OSD pages, displayed in 2 page mode, to
use Character Rom OSD in one page and DRCS in the
other.
Character Set Selection

Individual control of the Basic Character Set / Twist
Character Set and National Option Table are possible
using TXT18, TXT19, TXT23 and TXT29. The East/West
bit TXT4<5> will apply to both pages.
Boxes
The teletext mode control registers (TXT5 & TXT6) are
duplicated (TXT24 & TXT25) so that, for example, a text
page can be displayed on one side and a subtitled page.
Display Attributes
Separate control of Fringing, Screen colour and
Transparent mode is required for each Text Area.
Fringing: Control of which page has fringing is controlled
by TXT4<0> for Text Area A and TXT26<3> for Text Area
B. The fringe colour and direction applies to both pages i.e.
Fringing Control MMR 87F3.
Trans: The facility to display Black background as
transparent is controlled by TXT4<1> for Text Area A and
TXT26<6> for Text Area B.
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Panorama
Linear and non-linear horizontal scaling circuit for aspect
DW=0, without Text, two-page=0 ratio conversion 4:3 video signal to 16:9 screen are
controlled by SFR Video_process.DW_PA<1:0>.
DW_PA<1:0> Modes
00 Normal mode, both DW and Panorama mode

are disable.
01 Double Window Mode Enable
DW=0, with Text, two-page=0 10 Enable linear scaling for 4:3 video signal
displaying on 16:9 screen.
11 Enable non-linear scaling for 4:3 video signal

displaying on 16:9 screen
Text
Table 32 DW and Panorama Scaling Modes
DW=0, two-page=1
4:3 video signal
Text
DW=1, two-page=1 linear scaling
Text
non-linear scaling
Fig.31 Double Window Feature
Fig.32 4:3 Video Signal Scaling to 16:9 Screen
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Display Positioning (Single Page) large vertical and horizontal range so that no offset is
The display consists of the Screen Colour covering the needed. The text area is offset in both directions relative to
whole screen and the Text Area that is placed within the the vertical and horizontal sync pulses.
visible screen area. The screen colour extends over a
Horizontal Sync.
Screen Colour Offset = 7.11µs Vertical
Sync.
6 Lines
Offset
Screen Colour Area
Text
H-Sync delay Vertical
Text Area Offset
0.25 char. offset Text Area Start

Text Area End
49.78µs
Fig.33 Display Area Positioning (Single Page)
Display Positioning (Two Page)

The display consists of the two Screen Colours covering
each half of the screen and two Text Areas that are placed
within the visible screen area. The screen colour extends
over a large vertical and horizontal range so that no offset
is needed. The both text areas are offset in both directions
relative to the vertical and horizontal sync pulses. The
second page may be positioned relative to HSYNC delay
using the Page B Position MMR, active to the vertical and
horizontal sync pulses. The second page may be
positioned relative to HSYNC delay using the Page B
Position MMR.
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Horizontal Sync.
Screen Colour Offset = 7.11µs Vertical
Sync.
6 Lines
Offset
Screen Colour Area
Text
H-Sync delay Vertical
Text Text
Offset
AreaA AreaB
0.25 char. offset Text Area

Start A
Text Area End A Text Area

Start B
Page B Start
0.25 char. offset Text Area

End B
Min.
2 Char.
Spaces
49.78µs
Fig.34 Display Area Positioning (Two Page)
The visible text area for Page A is controlled using the

TEXT AREA START and TEXT AREA END MMRs. Page
B visible text area is controlled using the TEXT AREA
START B and TEXT AREA END B MMRs.
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SCREEN COLOUR DISPLAY AREA Three extra memory mapped registers control the position
This area is covered by the screen colour. The screen of the second page: REG17: Text Area Start B, REG18:
colour display area starts with a fixed offset of 8 us from Text Area End B and REG19: Page B Position.
the leading edge of the horizontal sync pulse in the Page B positioning register controls the positioning of Text
horizontal direction. A vertical offset is not necessary. Area B relative to HSYNC delay. A minimum two character
gap should be allowed between each page to allow the
Horizontal starts 7.11us after the leading edge of H-Sync for reset of attributes.
49.78 us. Control of the vertical offset is as per single page operation
using REG1: Text Position Vertical Register.
Vertical line 9, field 1 (321, field 2) with respect to leading
The text area can be defined to start with an offset in the
edge of vertical sync (line numbering using 625
Standard). horizontal direction as follows:
Table 33 Screen Colour Display Area

Horizontal Up to 48 full sized characters per row.
Start position setting from 3 to 128 characters from
TEXT DISPLAY AREA (SINGLE PAGE) the leading edge of H-Sync. Fine adjustment in
The text area can be defined to start with an offset in both quarter characters.
the horizontal and vertical direction.
Table 35 Text Display Area B
Horizontal Up to 48 full sized characters per row. The horizontal offset is set in REG17: Text Area Start. The
Start position setting from 3 to 64 characters from offset is done in full width characters using TAS B<5:0>
the leading edge of H-Sync. Fine adjustment in
quarter characters. and quarter characters using HOP B<1:0> for fine setting.
The values 00h to 03h for TAS<5:0> will result in a
Vertical 256 lines (nominal 41- 297). corrupted display.
Start position setting from leading edge of vertical The width of the text area is defined in REG18: Text Area
sync legal values are 4 to 64 lines. End by setting the end character value TAE B<5:0>. This
(line numbering using 625 Standard)
number determines where the background colour of the
Text Area B will end if set to extend to the end of the row.
Table 34 Text Display Area It will also terminate the character fetch process thus
eliminating the necessity of a row end attribute. This
The horizontal offset is set in REG2: Text Area Start. The entails however writing to all positions.
offset is done in full width characters using TAS<5:0> and
quarter characters using HOP<1:0> for fine setting. The Character Set
values 00h to 03h for TAS<5:0> will result in a corrupted To facilitate the global nature of the device the character
display. set has the ability to accommodate a large number of
The width of the text area is defined in REG4:Text Area characters, which can be stored in different matrices.
End by setting the end character value TAE<5:0>. This
number determines where the background colour of the CHARACTER MATRICES
Text Area will end if set to extend to the end of the row. It The character matrices that can be accommodated are: -
will also terminate the character fetch process thus (HxVxPlanes) 12x9x1, 12x13x1, 12x16x1, 16x16x1 and
eliminating the necessity of a row end attribute. This 16x18x1. These modes allow two colours per character
entails however writing to all positions. position.
The vertical offset is set in REG1:Text Position Vertical In CC mode four additional character matrices are
Register. The offset value VOL<5:0> is done in number of available to allow four colours per character: -
TV scan lines. (HxVxPlanes) 12x13x2, 12x16x2, 16x16x2 and 16x18x2.
NOTE: REG1:Text Position Vertical Register should not The characters are stored physically in ROM in a matrix of
be set to 00 Hex as the Display Busy interrupt is not size either 12x16, 16x18.
generated in these circumstances.
CHARACTER SET SELECTION
TEXT DISPLAY AREA (TWO PAGE) Four character sets are available in the device. A set can
Control of Page A in two page mode is as per the control consist of alphanumeric characters as required by the
in single page mode. WST Teletext or FCC Closed Captioning, Customer
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definable On-Screen Display characters, and Special

Graphic characters.
4000H
CC:- Two control mechanism are available controlled
using TXT20<4>. CHAR PIXEL
DATA
When Char Select Enable is set inactive (TXT20<4>): 0800
14 x 16 bits
Only a single character set can be used for display and this
is selected using the Basic Set selection TXT18.BS<1:0>. Look-Up Set3
When selecting a character set in CC mode the Twist Set 0600
selection TXT19.TS<1:0> should be set to the same value Look-Up Set2

as TXT18.BS<1:0> for correct operation. 0400
When Char Select Enable is set active (TXT20<4>):
The Character Set is selected using the Display Character 0800H Look-Up Set1
code (Bit-12 & Bit-13) on a character by character basis. LOOK-UP

Basic + Nat Opt
0200
Selection is as per the basic character set selection 2048 location

Look-Up Set 0
(TXT18.BS<1:0>). 0000H 0000
TXT:- Two character sets can be displayed at once. These
are the basic G0 set or the alternative G0 set (Twist Set).
The basic set is selected using TXT18.BS<1:0>, The
alternative/twist character set is defined by Fig.35 ROM Organization
TXT19.TS<1:0>. Since the alternative character set is an
option it can be enabled or disabled using TXT19.TEN, Although the hardware implement of character set
and the language code that is defined for the alternative selection of Closed Caption can select one of the four sets,
set is defined by TXT19.TC<2:0>. but due to the DDS tool restrictive, the Look-Up Set 0 is for
The National option table is selected using Teletext only; the Look-Up Set1, Set2 and Set3 are for
TXT18.NOT<3:0>. A maximum of 32 National Option Closed Caption and Teletext depend on S/W setting.
tables can be defined when combined with the E/W control
bit (TXT4 Bit-5).
An example of the character set selection and definitions
is shown in Table 36
S<1:0>/TS<1:0> Character Example Language

Set
00 Set 0 Latin
01 Set 1 Greek
10 Set 2 Cyrillic
11 Set 3 Closed Caption
Table 36 Character Set Selection
ROM ADDRESSING
Three ROM’s are used to generate the correct pixel
information. The first contains the National Option look-up
table, the second contains the Basic Character look-up
table and the third contains the Character Pixel
information. Although these are individual ROM, since
they do not need to be accessed simultaneously they are
all combined into a single ROM unit.
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CHARACTER TABLE
The character table is shown in Table 37:-
Character code columns (Bits 4-7)
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 ® SP 0 @ P ú p
1 ˚ ! 1 A Q a q
2 1/2 " 2 B R b r
3 ¿ # 3 C S c s
Character code rows (Bits 0-3)
4 ™ $ 4 D T d t
5 ¢ % 5 E U e u
6 £ & 6 F V f v
7 ´ 7 G W g w
8 à ( 8 H X h x
9 _ ) 9 I Y i y
A è á : J Z j z
B â + ; K [ k ç
C ê , < L é l
D î - = M ] m Ñ
E ô . > N í n ñ
F û / ? O ó o n
Table 37 Closed Caption Character Table
Special Characters are in column 8 & 9.
Additional table locations for normal characters
Table locations for normal characters
Re-definable Characters
A number of Dynamically Redefinable Characters (DRC) -Extended DRC Mode(TXT26.EXTENDED DRCS = 1):
are available. These are mapped onto the normal Extra character codes (column A/C) will be used as DRC
character codes, and replace the predefined ROM value. characters, thus there are max. 64 DRC’s.
Each character is stored in a matrix of 16x18x1 (H x Vx
-Normal DRC Mode(TXT26.EXTENDED DRCS = 0): planes), this allows for all possible character matrices.
There are 32 DRC’s, the first 16 occupy the character
codes 80Hto 8FH, the second 16 occupy the locations 90H
to 9FH. This allows for 32 DRC’s in TXT mode, 32 DRC’s
in CC mode and 32 Normal or 16 Special DRC’s in OSD
mode.The remapping of the standard OSD to the DRC’s is
activated when the TXT20.DRCS ENABLE<7> for Page A,
or TXT23.DRCS ENABLE<2> for Page B bit is set. The
selection of Normal or Special OSD symbols is defined by
the TXT20.OSD PLANES<6> for Page A, TXT29.OSD
PLANES<4> for Page B.
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Micro Address
8800h 8C80h Top Left Line 13 from
CHAR 0 CHAR 32 Line Pixel character above
CHAR XX Address No. Hex MSB LSB
8823h 8CA3h
8824h 8CA4h 00 0 440 Fringing
A
CHAR 1 CHAR 33 01
02 1 003 Top Line
8847h 8CC7h 03 00C
8848h 04 2
8CC8h
CHAR 2 CHAR 34 05 3 030
8CEBh 06 4 0C0
886Bh 07
08 5 300
09
0A 6 C00
0B 7 C00
0C
0D 8 300
0E 9 C00
0F
8C38h 90B8h 10 10 030
CHAR 30 CHAR 62 11 11 00C
8C5Bh 90DBh 12 003
8C5Ch 90DCh 16 bits
13 000 Bottom Line
CHAR 31 CHAR 63
90FFh 14 1A8 Fringing
8C7Fh
15 000 Line not used
Fig.36 Organisation of DRC RAM Bottom Right
Line 1 from Pixel
character below
DEFINING CHARACTERS
The DRC RAM is mapped into the 80C51 RAM address Fig.37 13 Line High DRC’s Character Format
space and starts at location 8800H. The character matrix
is 16 bits wide and therefore requires two bytes to be Display Synchronization
written for each word, the first byte (even addresses) The horizontal and vertical synchronizing signals from the
addresses the lower 8 bits and the second byte (odd TV deflection are used as inputs. Both signals can be
addresses) addresses the upper 8 bits. inverted before being delivered to the Display section for
For characters of 9, 10, 16 or 18 lines high the pixel timing reference.
information starts in the first address and continues CC: The polarity is controlled using either VPOL or HPOL
sequentially for the required number of address. in REG2:Text position Vertical.
Characters of 13 lines high are slightly different to the TXT: SFRs bits TXT1.HPOL & TXT1.VPOL control the
others as they have the added feature of fringing across polarity.
row boundaries. This is not normally possible, but can be
achieved by programming a copy of the bottom line of the Video/Data Switch (Fast Blanking) Polarity
character above and the top line of the character below The polarity of the Video/Data (Fast Blanking) signal can
within the DRCS character definition. This technique is be inverted. The polarity is set with the VDSPOL in REG7:
especially useful for clustered characters. RGB Brightness register.
With the addition of the larger 18 line high characters, this

VDSPOL VDS Condition
feature of fringing across clustered characters is no longer
essential. For DRCS, however, this feature has been 0 1 RGB display
retained for backward compatibility. It should be noted that
13 line ROM characters are no longer coded in this way. 0 0 Video Display
The required character is defined with an initial offset of 1
1 0 RGB display
address with the bottom line of the character above copied
into the very first address (line 0). The top line of the 1 1 Video Display
character below is copied below the character definition
(line 14), see Fig.37. Only lines 1 to 13 are actually
displayed. Lines 0 and 14 are only read by the fringing Table 38 Fast Blanking Signal Polarity
generator.
To allow some flexibility in 2 page mode the DRCS Enable Video/Data Switch Adjustment
bit is duplicated for the second page into TXT23<2>.This To take into account the delay between the RGB values
shall allow two Text OSD pages, displayed in 2 page and the VDS signal due to external buffering, the VDS
mode, to use Character ROM OSD in one page and DRCS signal can be moved in relation to the RGB signals. The
in the other. VDS signal can be set to be either a clock cycle before or
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after the RGB signal, or coincident with the RGB signal. Contrast Reduction
This is done using VDEL<2:0> in REG15:Configuration. TXT: The COR bits in SFRs TXT5 & TXT6 control when
the COR output of the device is activated (i.e. Pulled-low).
RGB Brightness Control This output is intended to act on the TV’s display circuits to
A brightness control is provided to allow the RGB upper reduce contrast of the video when it is active. The result of
output voltage level to be modified. The RGB amplitude contrast reduction is to improve the readability of the text
may be varied between 60% and 100%. in a mixed teletext and video display.
The brightness is set in the RGB Brightness register as The bits in the TXT5 & TXT6 SFRs allow the display to be
follows: - set up so that, for example, the areas inside teletext boxes
will be contrast reduced when a subtitle is being displayed
BRI3-0 RGB Brightness but that the rest of the screen will be displayed as normal
video.
0 0 0 0 Lowest value
In Teletext display mode the serial teletext box attribute
... ... and OSD box attribute define the region of the screen
where Contrast Reduction is active.
1 1 1 1 Highest value In CC display mode the serial character attribute ‘Boxing’
is used to define the region of the screen in which the
Table 39 RGB Brightness Contrast Reduction is active.
Memory Mapped Registers

The memory mapped registers are used to control the
display. The registers are mapped into the Micro-controller
MOVX address space, starting at address 87E0h and
extending to 87FF.
MMR MAP
ADD R/W Functions BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
87F0 R/W Display SRC<3> SRC<2> SRC<1> SRC<0> - msh MOD<1> MOD<0>
Control
87F1 R/W Text Position VPOL HPOL VOL<5> VOL<4> VOL<3> VOL<2> VOL<1> VOL<0>
Vertical
87F2 R/W Text Area Start HOP<1> HOP<0> TAS<5> TAS<4> TAS<3> TAS<2> TAS<1> TAS<0>
87F3 R/W Fringing FRC<3> FRC<2> FRC<1> FRC<0> FRDN FRDE FRDS FRDW
Control
87F4 R/W Text Area End - - TAE<5> TAE<4> TAE<3> TAE<2> TAE<1> TAE<0>
87F5 R/W Scroll Area SSH<3> SSH<2> SSH<1> SSH<0> SSP<3> SSP<2> SSP<1> SSP<0>
87F6 R/W Scroll Range SPS<3> SPS<2> SPS<1> SPS<0> STS<3> STS<2> STS<1> STS<0>
87F7 R/W RGB Brightness VDSPOL - - - BRI<3> BRI<2> BRI<1> BRI<0>
87F8 R Status read BUSY FIELD SCON FLR SCR<3> SCR<2> SCR<1> SCR<0>
87F8 W Status write - - SCON FLR SCR<3> SCR<2> SCR<1> SCR<0>
87FC R/W H-Sync. Delay - HSD<6> HSD<5> HSD<4> HSD<3> HSD<3> HSD<1> HSD<0>
87FD R/W V-Sync. Delay - VSD<6> VSD<5> VSD<4> VSD<3> VSD<2> VSD<1> VSD<0>
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87FE R/W Top Scroll Line - - - - SCL<3> SCL<2> SCL<1> SCL<0>
87FF R/W Configuration CC VDEL<2 VDEL<1> VDEL<0> TXT/V 0 - Two_Page

>
87E0 R/W Text Area Start HOPB<1> HOPB<0 TASB<5> TASB<4> TASB<3> TASB<2> TASB<1> TASB<0>
B >
87E1 R/W Text Area End B - - TAEB<5> TAEB<4> TAEB<3> TAEB<2> TAEB<1> TAEB<0>
87E2 R/W Page B Position 0 PGB<6> PGB<5> PGB<4> PGB<3> PGB<2> PGB<1> PGB<0>
87E3 R/W Text Position - - VOLB<5> VOLB<4> VOLB<3> VOLB<2> VOLB<1> VOLB<0>
Vertical B
87E4 R/W Text Position - - SMTHB SMTH RANGE RANGE RANGEB RANGEB
Vertical Range <1> <0> <1> <0>
Table 40 MMR Map
MMR BIT DEFINITION
Names BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RESET
Display Control. SRC<3> SRC<2> SRC<1> SRC<0> - msh MOD<1> MOD<0> 00H
SRC<3:0> Screen Colour definition
msh unused, must keep reset value -> ‘0’
MOD<1:0> 00 - Video
01 - Full Text
10 - Mixed Screen Colour
11 - Mixed Video
Text Position VPOL HPOL VOL<5> VOL<4> VOL<3> VOL<2> VOL<1> VOL<0> 00H
Vertical
VPOL 0 - Input polarity

1 - Inverted input polarity
HPOL 0 - Input Polarity

1 - Inverted input polarity
VOL<5:0> Display start Vertical Offset from V-Sync. (lines)
Text Area Start HOP<1> HOP<0> TAS<5> TAS<4> TAS<3> TAS<2> TAS<1> TAS<0> 00H
HOP<1:0> Fine Horizontal Offset in quarter of characters
TAS<5:0> Text area start
Fringing Control. FRC<3> FRC<2> FRC<1> FRC<0> FRDN FRDE FRDS FRDW 00H
FRC<3:0> Fringing colour, value address of CLUT
FRDN 0 - No fringe in North direction

1 - Fringe in North direction
FRDE 0 - No fringe in East direction

1 - Fringe in East direction
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FRDS 0 - No fringe in South direction

1 - Fringe in South direction
FRDW 0 - No fringe in West direction

1 - Fringe in West direction
Text Area End - - TAE<5> TAE<4> TAE<3> TAE<2> TAE<1> TAE<0> 00H
TAE<5:0> Text Area End, in full characters
Scroll Area SSH<3> SSH<2> SSH<1> SSH<0> SSP<3> SSP<2> SSP<1> SSP<0> 00H
SSH<3:0> Soft Scroll Height
SSP<3:0> Soft Scroll Position
Scroll Range SPS<3> SPS<2> SPS<1> SPS<0> STS<3> STS<2> STS<1> STS<0> 00H
SPS<3:0> Stop Scroll row
STS<3:0> Start Scroll row
RGB Brightness VDSPOL - - - BRI<3> BRI<2> BRI<1> BRI<0> 00H
VDSPOL VDS Polarity

0 - RGB (1), Video (0)
1 - RGB (0), Video (1)
BRI<3:0> RGB Brightness control
Status read BUSY FIELD SCON FLR SCR<3> SCR<2> SCR<1> SCR<0> 00H
BUSY 0 - Access to display memory will not cause display problems

1 - Access to display memory could cause display problems.
FIELD 0 - Odd Field

1 - Even Field
FLR 0 - Active flash region foreground and background displayed

1 - Active flash region background only displayed
SCR<3:0> First scroll row
Status write - - SCON FLR SCR<3> SCR<2> SCR<1> SCR<0> 00H
SCON 0 - Scroll area disabled

1 - Scroll area enabled
FLR 0 - Active flash region foreground and background colour displayed

1 - Active flash region background colour only displayed
SCR<3:0> First Scroll Row
H-Sync. delay - HSD<6> HSD<5> HSD<4> HSD<3> HSD<3> HSD<1> HSD<0> 00H
HSD<6:0> H-Sync delay, in full size characters
V-Sync Delay - VSD<6> VSD<5> VSD<4> VSD<3> VSD<2> VSD<1> VSD<0> 00H
VSD<6:0> V-Sync delay in number of TV lines
Top Scroll Line - - - - SCL<3> SCL<2> SCL<1> SCL<0> 00H
SCL<3:0> Top line for scroll
Configuration CC VDEL<2> VDEL<1> VDEL<0> TXT/V 0 - Two_Page 00H
CC 0 - OSD mode
1 - Closed Caption mode
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VDEL<2:0> Pixel delay between VDS and RGB output

000 - VDS switched to video, not active
001 - VDS active one pixel earlier then RGB
010 - VDS synchronous to RGB
100 - VDS active one pixel after RGB
TXT/V BUSY Signal switch

0 - Vertical
1 - Horizontal
Two_Page Two Page mode select

0 - Single page
1 - Dual page
Text Area Start B HOP<1> HOP<0> TAS<5> TAS<4> TAS<3> TAS<2> TAS<1> TAS<0> 00H
HOP<1:0> Fine Horizontal Offset in quarter of characters
TAS<5:0> Text area start
Text Area End B - - TAE<5> TAE<4> TAE<3> TAE<2> TAE<1> TAE<0> 00H
TAE<5:0> Text Area End, in full characters
Page B Position 0 PGB<6> PGB<5> PGB<4> PGB<3> PGB<2> PGB<1> PGB<0> 00H
PGB<6:0> Page B Position
Text Position - - VOLB<5> VOLB<4> VOLB<3> VOLB<2> VOLB<1> VOLB<0> 00H

Vertical B
VOLB<5:0> Page B start Vertical Offset from V-Sync. Value is in horizontal scan lines. Must be set to VOL<5:0> in double window mode.
Vertical Range - - SMTHB SMTH RANGE RANGE RANGEB RANGEB 00H

<1> <0> <1> <0>
SMTHB 0 - Smoothing inactive (page B)

1 - Smoothing active for Double Size, Double Height and Double Width (page B)
SMTH 0 - Smoothing inactive (single page or page A)

1 - Smoothing active for Double Size, Double Height and Double Width (single page or page B)
RANGE<1:0> Bits<7:6> of VOL (single page or page A vertical offset)
RANGEB<1:0> Bits<7:6> of VOLB (page B vertical offset). Must be set to RANGE<1:0> in double window and two page mode.
Table 41 MMR Descriptions
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SCAVEM TEXT OUTPUT FLASH MEMORY

These may be programmed/erased via the ISP Interface.
The Scavem (Scan Velocity Modulator) circuit is existed in
The flash memory can be erased/written over 100k times.
the Video Signal Processor die. The function is to enhance
edge details by varying the speed of the electric beam,
ISP Interface
providing a sharp and crisp picture. The generated
ISP is via Hs-mode I2C upto 1.2 Mb/s.
character would have this feature by providing a
SCAVTXT signal to video processing die. The SCAVTXT
signal is generated from R, G and B signals. The SFR, FLASH MEMORY ORGANIZATION
SCAVTXT.SCAVEM_EN is high active to enable the
signal output. The Scavem text processing needs about
200ns. The SCAVTXT signal should go to Video Signal Sector x-1
Processor earlier than R, G and B signals 200ns as well. page ss-1
For flexibility of adjusting the delay between SCAVTXT
and R, G, and B signals, an SFR, SCAVTXT. EARLY<2:0>
is for this purpose.
EARLY<2:0> SCAVTXT output earlier than R, G, and B signals page 1

000 0 ns page 0
001 74 ns Sector 1
010 111 ns 256 bytes
011 148 ns
100 185 ns Sector 0

101 212 ns
110 259 ns
Fig.38 Flash memory organization
111 296 ns
Table 42 Delay between SCAVTXT and R, G, B The sectors are used to put program and character codes.
The pulse width of SCAVEM text signal is defined in the

SFR, SCAVTXT.PULSE_WIDTH<1:0>.
PULSE_WIDTH<1:0> SCAVEM Text pulse width
00 37 ns
01 74 ns
10 111 ns
11 148 ns
Table 43 SCAVEM Text pulse width
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Programming procedures Enter ISP mode

Flash programming procedure is shown as below: There are mainly two cases using ISP mode when the
UOCIII is mounted on PCB or TV. One case is the content
of flash memory is empty. Another case is that the
Enter ISP mode customer code (program and character codes) were
programmed in flash memory and need to be upgraded.
Enter ISP mode when flash memory is empty

In this case, the I2C bus is not occupied by the
Erase flash micro-controller, therefore follow the flows:- send the
correct slave address, erase flash, write flash, and verify
flash sections can access to the flash memory via I2C.
write flash Enter ISP mode when code is existed in flash memory
and is running
In this case, embedded software should release the
I2C-bus first and then following the flows:- send the correct
slave address, erase flash, write flash, and verify flash
verify flash sections can access to the flash memory via I2C.
The complete programming flow is supported by the WISP

tool from Philips Semiconductors.
Power-on-reset
Fig.39 Flash programming procedure
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FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR QSS Sound circuit

Vision IF amplifier The sound IF amplifier is similar to the vision IF amplifier
and has an external AGC decoupling capacitor.
The vision IF amplifier can demodulate signals with
positive and negative modulation. The PLL demodulator is The single reference QSS mixer is realised by a multiplier.
completely alignment-free. In this multiplier the SIF signal is converted to the
intercarrier frequency by mixing it with the regenerated
The VCO of the PLL circuit is internal and the frequency is
picture carrier from the VCO. The mixer output signal is
fixed to the required value by using the clock frequency of
supplied to the output via a high-pass filter for attenuation
the TCG µ-Controller as a reference. The setting of the
of the residual video signals. With this system a high
various frequencies (e.g. 38, 38.9, 45.75 and 58.75 MHz)
performance hi-fi stereo sound processing can be
can be made via the control bits IFA-IFC in subaddress
achieved.
2FH. Because of the internal VCO the IF circuit has a high
immunity to EMC interferences. The AM sound demodulator is realised by a multiplier. The
modulated sound IF signal is multiplied in phase with the
The output of the AFC detector can be read from output
limited SIF signal. The demodulator output signal is
byte 04H and has a resolution of 7 bits (25 kHz per step).
supplied to the output via a low-pass filter for attenuation
By means of this information a fast tuning algorithm can be
of the carrier harmonics.
designed.
Switching between the QSS output and AM output is made
The IC contains a group delay correction circuit which can
by means of the AM bit in subaddress 33H.
be switched between the BG and a uncompensated group
delay response characteristic. This has the advantage that
FM demodulator
in multi-standard receivers no compromise has to be made
for the choice of the SAW filter. This group delay correction The FM demodulator is realised as narrow-band PLL with
is realised for the demodulated CVBS output signal. The internal loop filter, which provides the necessary selectivity
IC contains in addition a sound trap circuit with a without using an external band-pass filter. To obtain a
switchable centre frequency. good selectivity a linear phase detector and a constant
input signal amplitude are required. For this reason the
Digital Broadcast reception intercarrier signal is internally supplied to the demodulator
via a gain controlled amplifier and AGC circuit. To improve
Apart from processing analogue TV signals, the IF circuit
the selectivity an internal bandpass filter is connected in
can also preprocess digital TV signals before they are sent
front of the PLL circuit.
to a digital signal processor. These signals have to be
supplied to the sound IF inputs. In this mode the IF The nominal frequency of the demodulator is tuned to the
reference frequency is fixed at 43.008 or 49.152 MHz. It is required frequency (4.5/5.5/6.0/6.5 MHz) by means of a
also possible to supply an external reference signal to calibration circuit which uses the clock frequency of the
demodulator. The demodulator multiplies the incoming TCG(1) µ-Controller as a reference. It is also possible to
signal with the fixed oscillator frequency. The mixed down frequencies of 4.72 and 5.74 MHz so that a second sound
signal is low pass filtered to obtain a I-signal. The “Stereo” channel can be demodulated. In the latter application an
and “AV Stereo” versions have a differential output, external bandpass filter has to be applied to obtain
however, it is possible to use a single-ended output. The sufficient selectivity (the sound input can be activated by
various output signal conditions can be set by means of means of the setting of CMB2-CMB0 bits in subaddress
the IFO2-IFO0 bits in subaddress 31H (see also table 94). 4AH). The setting to the wanted frequency is realised by
The “Mono” versions have a single-ended output. means of the control bits FMA, FMB and FMC in the
control bit 33H.
The AGC has two modes of operation: the internal mode
in which the IC sets the gain with its own reference and an From the output status bytes it can be read whether the
external mode in which the gain can be controlled with an PLL frequency is inside or outside the window and whether
external circuit. In the second case the SIFAGC pin is used the PLL is in lock or not. With this information it is possible
as an input to control the IF gain with an external circuit. to make an automatic search system for the incoming
sound frequency. This can be realised by means of a
software loop which switches the demodulator to the
(1) TCG = Text/Control/Graphics
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various frequencies and then select the frequency on The gain from an external audio input to each of the
which a lock condition has been found. (non-controlled) analog output is 0 or +6 dB (controlled by
the DSG bit). A supply voltage of 5V allows input and
The amplitude deemphasis output signal changed with 6
output amplitude of 1VRMS full scale. The audio selector
dB by means of the AGN bit. In this way output signal
circuit has a separate supply voltage pin. For audio output
differences between the 4.5 MHz standard (frequency
signal amplitudes of 2VRMS full scale, as required to
deviation ±25 kHz) and the other standards (frequency
comply with the SCART specification, the audio supply
deviation ±50 kHz) can be compensated.
voltage must be 8V. In that case the gain of the audio
amplifier must be doubled. This can be realised with the
FM radio mode
DSG bit in subaddress 32H.
The FM demodulator can be used for the demodulation of
The circuit contains an analogue stereo volume control
FM radio signals. This mode is activated by means of the
circuit with a control range of about 70 dB. This volume
FMR-bit (subaddress 34H). The selectivity must be made
control circuit is used for the headphone channel (stereo
by means of a SAW filter at the sound input with a centre
versions with Audio DSP) or for the main channel (AV
frequency of 33.4 MHz for Europe and 41.25 MHz for the
stereo versions without Audio DSP). The analogue control
USA. For this application the IF demodulator must be set
circuit also contains an Automatic Volume Levelling (AVL)
to a fixed frequency (43.008 MHz for Europe and
function. When this function is activated it stabilises the
49.152 MHz for the USA). The resulting input frequency
audio output signal to a certain level so that big fluctuations
for the FM demodulator is then 9.6 MHz for Europe and
of the output power are prevented.
7.9 MHz for the USA. This frequency must be selected by
means of the bits FMA, FMB and FMC (see table 104). In
MONO VERSIONS
the FM radio mode the demodulated intercarrier sound
output signal can be supplied to the output pin(s) (FMRO) The audio input selector circuit has 4 inputs for mono
so that an external bandpass filter can be applied between signals. The selection is made with the HPO2/0 bits.
this pin and the SSIF pin.
The circuit contains an analogue volume control circuit
The SSIF input can be either pin 33 or pin 53 (pins 96 or with a control range of about 70 dB and an AVL circuit.
76 respectively for the “face down” version). The selection
is made by means of the ESSIF bit in subaddress 35H. CVBS and Y/C input signal selection
The mono intercarrier sound circuit can also be combined ALL VERSIONS
with an external FM tuner (IF frequency of 10.7 MHz). In
The ICs have 3 inputs for external CVBS signals. All CVBS
that case an external 10.7 MHz bandpass filter is required.
inputs can be used as Y input for the insertion of Y/C
The demodulator centre frequency is set with the FMD bit
signals. However, the CVBS(Y)2 input has to be combined
(subaddress 33H).
with the C3 input. It is possible to add and extra
FM stereo decoding is possible in versions that contain the CVBS(Y/C) input via the pins which are intended to be
digital multi-standard stereo decoder. This mode is used for YUV interface (or RGB/YPRPB input). The
selected by means of the IFO2-IFO0 bits in subaddress selection of this additional CVBS(Y/C) input is made via
31H. the YC bit. The CVBS selector has one independently
switchable output. The switch configuration is given in
Audio input selector and volume control Fig. 40. The choice of the various modes can be made via
the INA-IND bits in subaddress 38H.
STEREO AND AV STEREO VERSIONS
The function of the IFVO/SVO/CVBSI pin is determined by
The audio input selector circuit has 4 external stereo
the SVO1/SVO0 bits. When used as output a selection can
inputs, a stereo output for SCART/CINCH and stereo
be made between the IF video output signal or the
outputs for headphone and audio power amplifiers. The
selected CVBS signal (monitor out). This pin can also be
selection is made with the bits SAS2/0, SO2/0 and
used as additional CVBS input. This signal is inserted in
HPO2/0. AV stereo versions without Audio DSP have no
front of the group delay / sound trap circuit. It is also
headphone output. The input signal selection for the
possible to use the group delay and sound trap circuit for
volume controlled audio outputs is realised by the HPO2/0
the CVBS2 signal (via the CV2 bit).
bits.
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For the CVBS(Y/C) inputs the circuit can detect whether a The video ident circuit can be connected to all video input
CVBS or Y/C signal is present on the input. The result can signals. This ident circuit is independent of the
be read from the status register (YCD bit in subaddress synchronisation and can be used to switch the
03H) and this information can be used to put the input time-constant of the horizontal PLL depending on the
switch in the right position (by means of the INA-IND bits presence of a video signal (via the VID bit). In this way a
in subaddress 38H). The Y/C detector is only active for the very stable OSD can be realised. The result of the video
CVBS(Y)3/C3, CVBS(Y)4/C4 and CVBS(Y)x/Cx inputs. It ident circuit can be read from the output bit SID
is not active for the CVBS(Y)2/C3 input. (subaddress 00)
SYS
SYNC H/V
SID VIDEO
CFA0
IDENTIFICATION SEPARATOR
4H/2H PAL/NTSC
Y
GD
COMB FILTER
CV2 or SVO1 C
SVO1/SVO0
IFOUT SOUND TRAP

GROUP DELAY
CORRECTION +
IFOX CVBS1
SVO1
IFOUT SVO/IFOUT/CVBSI CVBS/Y-2 CVBS/Y-3 C3 CVBS/Y-4 C4 CVBS/Y-x Cx YSYNC CVBSO
Fig.40 CVBS switch G/Y-3
Synchronisation circuit The horizontal drive signal is obtained from an internal

VCO which is running at a frequency of 25 MHz. This
The IC contains separator circuits for the horizontal and
oscillator is stabilised to this frequency by using the clock
vertical sync pulses. To obtain an accurate timing of the
signal coming from the reference oscillator of the TCG
displayed picture the input signal of the sync separator is
µ-Controller.
not derived from the various CVBS/Y or RGB/YPRPB
inputs but from the YOUT pin. For this reason the YOUT To obtain a stable On-Screen-Display (OSD) under all
pin must be capacitively coupled to the YSYNC pin. The conditions it is important that the first control loop is
delay between the various inputs and the YOUT signal can switched off or set to low gain when no signal is available
have rather large differences (e.g. comb filter active or at the input. The input signal condition is detected by the
not). By choosing the YOUT signal as input signal for the video identification circuit. The video identification circuit
sync separator these delays have no effect on the picture can automatically switch first control loop to a low gain
position. Only for RGB signals without sync on green the when no input signal is available. This mode is obtained
input of the sync separator has to be connected to one of when the VID bit is set to “0”. When the VID bit is “1” the
the CVBS inputs. This selection is made by means of the mode of the first control loop can be switched by means of
SYS bit. the FOA/FOB or POC bits.
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For a good performance during normal TV reception When the vertical amplitude is compressed (zoom
(display of the front-end signal) various connections are factor <1) it is still possible to display the black current
active between the vision IF amplifier and the measuring lines in the overscan. This function is activated
synchronisation circuit (e.g. gating pulses for the AGC by means of the bit OSVE in subaddress 40H.
detector and noise gating of the sync separator). These
The vertical guard input is combined with an I/O function.
connections are not allowed when external video signals
The following functions can be realised with this pin:
are displayed. The switching of these connections can be
coupled to the input signal selection bits (INA-IND). This • Just vertical guard input.
mode is obtained when the VDXEN bit is “0”. Due to the • Combination of vertical guard and LED drive output. In
input signal selector configuration it is possible that the this condition the output is high-ohmic during the vertical
internal CVBS signal is available on one of the other CVBS retrace (1 ms) so that the vertical guard pulse can be
inputs. In this condition the connections between the vision detected.
IF amplifier and the synchronisation circuit can be
• Single ended output switch
switched on and off by means of the VDX bit. The VDXEN
bit must be set to “1” for this mode. • Input port
The vertical synchronisation is realised by means of a The functionality of this pin is controlled by the VGM1/0
divider circuit. and LED bits.
When the East-West geometry function is not required
Horizontal and vertical drive (e.g. for 90° picture tubes) the EW output pin can be used
The horizontal drive is switched on and off via the soft for the connection of the AVL capacitor. This function is
start/stop procedure. The soft start function is realised by chosen by means of the AVLE bit.
means of variation of the TON of the horizontal drive The UOCIII devices can also be used as input processor
pulses. During the soft-stop period the horizontal output for 100 Hz or LCD TV receivers. In that case the deflection
frequency is doubled resulting in a reduction of the EHT so drive signals are not required. For these applications an
that the picture tube capacitance can easily be discharged. H/V timing signal can be obtained from the flyback
In addition the horizontal drive circuit has a ‘low-power input/sandcastle output pin. This mode is activated by
start-up’ function. means of the CSY bit (subaddress 4AH). The horizontal
The vertical ramp generator needs an external resistor and output pin is switched to “high” in this condition. A change
capacitor. For the vertical drive a differential output current of the CSY bit is possible only in the stand-by mode
is available. The outputs must be DC coupled to the (STB = 0).
vertical output stage.
Chroma, luminance and feature processing
The IC has the following geometry control functions:
Some versions contain a 4H/2H (2D) adaptive PAL/NTSC
• Vertical amplitude comb filter. The comb filter is automatically activated when
• Vertical slope standard CVBS signals are received. A signal is
• S-correction considered as “standard signal” when a PAL or NTSC
signal is identified and when the vertical divider is in the
• Vertical shift
modes ‘standard narrow window’ or ‘standard TV
• Vertical zoom norm’.For non-standard signals and for SECAM signals
• Vertical scroll the comb filter is bypassed and the signal is filtered by
means of bandpass and trap filters.
• Vertical linearity correction. When required the linearity
setting for the upper and lower part of the screen can The chroma band-pass and trap circuits (including the
have a different setting. SECAM cloche filter) are realised by means of internal
• Horizontal shift filters and are tuned to the right frequency by comparing
the tuning frequency with the reference frequency of the
• EW width
colour decoder.
• EW parabola width
The circuit contains the following picture improvement
• EW upper and lower corner parabola correction features:
• EW trapezium correction
• Horizontal parallelogram and bow correction.
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• Peaking control circuit. The peaking function can be Colour decoder

activated for all incoming CVBS, Y/C and RGB/YPRPB
The ICs decode PAL, NTSC and SECAM signals. The
signals. Various parameters of the peaking circuit can
PAL/NTSC decoder does not need external reference
be adapted by means of the I2C-bus. The main
crystals but has an internal clock generator which is
parameters are:
stabilised to the required frequency by using the clock
– Peaking centre frequency (via the PF1/PF0 bits in signal from the reference oscillator of the TCG
subaddress 19H). µ-Controller.
– Ratio of positive and negative peaks (via the Under bad-signal conditions (e.g. VCR-playback in feature
RPO1/RPO0 bits in subaddress 47H). The peaks in mode), it may occur that the colour killer is activated
the direction “white” are the positive peaks. although the colour PLL is still in lock. When this killing
– Ratio of pre- and aftershoots (via the RPA1/RPA0 action is not wanted it is possible to overrule the colour
bits in subaddress 47H). killer by forcing the colour decoder to the required standard
• Video dependent coring in the peaking circuit. The and to activate the FCO-bit (Forced Colour On) in
coring can be activated only in the low-light parts of the subaddress 3CH. The sensitivity of the colour decoder for
screen. This effectively reduces noise while having PAL and NTSC can be increased by means of the setting
maximum peaking in the bright parts of the picture. of the CHSE1/CHSE0 bits in subaddress 3CH.
• Black stretch. This function corrects the black level for The Automatic Colour Limiting (ACL) circuit (switchable
incoming signals which have a difference between the via the ACL bit in subaddress 3BH) prevents that
black level and the blanking level. The amount of oversaturation occurs when signals with a high
stretching (A-A in Fig. 72) and the minimum required chroma-to-burst ratio are received. The ACL circuit is
back ground to activate the stretching can be set by designed such that it only reduces the chroma signal and
means of the I2C-bus (BSD/AAS in subaddress 45H). not the burst signal. This has the advantage that the colour
• Gamma control. When this function is active the transfer sensitivity is not affected by this function.
characteristic of the luminance amplifier is made The SECAM decoder contains an auto-calibrating PLL
non-linear. The control curve can be adapted by means demodulator which has two references, viz: the divided
of I2C-bus settings (see Fig. 74). It is possible to make reference frequency (obtained from the µ-Controller)
the gamma control function dependent on the picture which is used to tune the PLL to the desired free-running
content (Average Picture Level, APL). The effect is frequency and the bandgap reference to obtain the correct
illustrated in Fig. 75. Previously this function was absolute value of the output signal. The VCO of the PLL is
mentioned under the name “white stretch function”. calibrated during each vertical blanking period, when the
• Blue-stretch. This circuit is intended to shift colour near IC is in search or SECAM mode. The frequency offset of
‘white’ with sufficient contrast values towards more blue the B-Y demodulator can be reduced by means of the
to obtain a brighter impression of the picture. SBO1/SBO0 bits in subaddress 3CH.
• Dynamic skin tone (flesh) control. This function is The base-band delay line is integrated. In devices without
realised in the YUV domain by detecting the colours CVBS comb filter this delay line is also active during NTSC
near to the skin tone. to obtain a good suppression of cross colour effects. The
• Scan-Velocity modulation output. Also the SVM function demodulated colour difference signals are internally
can be activated for all incoming CVBS, Y/C and supplied to the delay line. The baseband comb filter can be
RGB/YPRPB signals. The delay between the RGB switched off by means of the BPS bit (subaddress 3CH).
output signals and the SVM output signal can be The subcarrier output is combined with a 3-level output
adjusted (by means of the SVM2-SVM0 bits in switch (0 V, 2.1 V and 4.5 V). The output level and the
subaddress 48H) so that an optimum picture availability of the subcarrier signal is controlled by the
performance can be obtained. Furthermore a coring CMB2-CMB0 bits.
function can be activated. It is possible to generate Scan
Velocity Modulation drive signals during the display of
‘full screen’ teletext (not in mixed mode). Another
feature is that the SVM output signal can be made
dependent on the horizontal position on the screen
(parabola on the SVM output).
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RGB output circuit Table 44 Addition of WP, CL and gain register settings
In the RGB control circuit the signal is controlled on WPR(GB) ‘0’ B5 B4 B3 B2 B1 B0 max 64
contrast, brightness and saturation. The IC has a YUV CL ‘0’ B3 B2 B1 B0 ‘0’ ‘0’ max 60
interface so that additional picture improvement ICs can
CCC-gain B6 B5 B4 B3 B2 B1 B0 max 126
be applied. To compensate signal delays in the external
YUV path the clamp pulse in the control circuit can be R(GB)-gain B6 B5 B4 B3 B2 B1 B0 max 126
shifted by means of the CLD bit in subaddress 44H. When
the YUV interface is not required some of the pins can be The setting of the gain registers of the 3 channels can be
used for the insertion of RGB/YPRPB signals or as stored during switch off and can be loaded again during
additional CVBS(Y)/C input. When the YUV interface is not switch-on so that the drive conditions are maintained.
used one of the pins (VOUT) is transferred to general
purpose output switch (SWO1). The IC has also a YUV When required the operation of the CCC system can be
interface to the digital die. Via this loop digital features like changed into a one-point black current system. The
“double window” are added. switching between the 2 possibilities is realised by means
of the EGL bit (EGL = 0) in subaddress 42H. When used
A tint control is available for the base-band U/V signals. as one-point control loop the system will control the black
For this reason this tint control can be activated for all level of the RGB output signals to the ‘low’ reference
colour standards. The signals for OSD and text are current and not on the cut off point of the cathode. In this
internally supplied to the control circuit. The output signal way spreads in the picture tube characteristics will not be
has an amplitude of about 1.2 V black-to-white at nominal taken into account. In this condition the settings of the
input signals and nominal settings of the various controls. “white point control registers” (subaddress 20H - 22H) and
To obtain an accurate biasing of the picture tube the the “cathode drive level bits” (CL3 - CL0 in subaddress
‘Continuous Cathode Calibration’ system has been 42H) are added to the settings of the RGB preset gain
included in these ICs. The system is slightly adapted registers (subaddress 23H - 25H).
compared with the previous circuits. In the new A black level off-set can be made with respect to the level
configuration the cut-off level of the picture tube is which is generated by the black current stabilization
controlled with a continuous loop whereas the correction of system. In this way different colour temperatures can be
the amplitude of the output signals is realised by means of obtained for the bright and the dark part of the picture. The
a digital loop. As a consequence the current measurement black level control is active on the Red and the Green
can be controlled from the µ-Processor. The value of the output signal. It is also possible to control the black level of
“high current” in the CCC loop can be chosen via the SLG0 the Blue and the Green output signal (OFB bit = 1).
and SLG1 bits (subaddresses 42H and 46H). The gain
control in the 3 RGB channels is realised by means of 7-bit In the Vg2 adjustment mode (AVG = 1) the black current
DACs. The total gain control range is ±6 dB. The change stabilization system checks the output level of the 3
in amplitude at the cathodes of the picture tube for one channels and indicates whether the black level of the
LSB is about 1.1 VP-P. The setting of the control DAC is highest output is in a certain window (WBC-bit) or below or
determined by the following registers: above this window (HBC-bit). This indication can be read
from the status byte 01 and can be used for automatic
• The white point setting of the R, G and B channel in
adjustment of the Vg2 voltage during the production of the
subaddress 20H to 22H. This register has a resolution of TV receiver. During this test the vertical scan remains
6 bits and the control range in output signal amplitude is
active so that the indication of the 2 bits can be made
±3 dB.
visible on the TV screen.
• The cathode drive setting (CL3-CL0 in subaddress
The control circuit contains a beam current limiting circuit
42H). This setting is valid for all channels, the resolution
and a peak white limiting circuit. The control is realised by
is 4 bits and the control range is ±3 dB.
means of a reduction of the contrast and brightness control
• The gain setting of the R, G and B channel. During settings. The way of control (first contrast and then
switch on this register is loaded with the preset gain brightness or contrast and brightness in parallel) can be
setting of subaddress 23H to 25H and when necessary chosen by means of the CBS bit (subaddress 44H). The
it will be adapted by the CCC control loop. These peak white level is adjustable via the I2C-bus.
registers have a resolution of 7 bits. The control of the
gain setting is illustrated in table 44.
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To prevent that the peak white limiting circuit reacts on the current ensures that the picture tube capacitance is
high frequency content of the video signal a low-pass filter discharged. During the switch-off period the vertical
is inserted in front of the peak detector. The circuit also deflection can be placed in an overscan position so that
contains a soft-clipper which prevents that the high the discharge is not visible on the screen.
frequency peaks in the output signal become too high. The
A wide blanking pulse can be activated in the RGB outputs
difference between the peak white limiting level and the
by means of the HBL bit in subaddress 43H. The timing of
soft clipping level is adjustable via the I2C-bus in a few
this blanking can be adjusted by means of the bits WBF/R
steps.
bits in subaddress 26H.
During switch-off of the TV receiver a fixed beam current
is generated by the black current control circuit. This
I2C-BUS USER INTERFACE DESCRIPTION OF THE VIDEO PROCESSOR

The UOCIII series is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers.
Status information can be read from a set of info registers to enable the controlling microcontroller determine whether
any action is required.The device has an I2C-bus slave transceiver, in accordance with the fast-mode specification, with
a maximum speed of 400 kbits/s. Information concerning the I2C-bus can be found in brochure “I2C-bus and how to use
it” (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar or
complementary functions, there are two possible slave addresses available which can be selected by the SVM pin (pin
65).
Possible slave address
SVM PIN SLAVE ADDRESS A6 TO A0

scavem application 1000101
tied to 5 volts 1000111
The device will not respond to a ‘general call’ on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master.
Write registers
Each address of the address space (see below) can only be written.
Correct operation is not guaranteed if registers in the range $FB to $FF will be addressed!
Overview address space
ADDRESS WORDS WORDLENGTH DESCRIPTION

$00 to $29 42 words 1 byte I2C addresses enabled and
usable
$2A to $2E - - Not used
$2F to $4A 28 words 1 byte I2C addresses enabled and
usable
$4B to $FA - - Not used
$FB to $FF 5 words 1 byte I2C addresses enabled not
usable
Read registers
The output registers of the TV processor are only available via auto-increment mode, no address can be used and all
registers must be read.
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DESCRIPTION OF THE I2C-BUS SUBADDRESSES

Table 45 Inputs TV processor
SUBADDR DATA BYTE POR

FUNCTION
(HEX) D7 D6 D5 D4 D3 D2 D1 D0 Value
Spare 00 0 0 0 0 0 0 0 0 00
Spare 01 0 0 0 0 0 0 0 0 00
Spare 02 0 0 0 0 0 0 0 0 00
Volume control (L) 03 0 A6 A5 A4 A3 A2 A1 A0 20
Volume control R (2) 04 0 A6 A5 A4 A3 A2 A1 A0 20
Horizontal shift (HS) 05 0 0 A5 A4 A3 A2 A1 A0 20
Horizontal parallelogram 06 0 0 A5 A4 A3 A2 A1 A0 20
Horizontal bow 07 0 0 A5 A4 A3 A2 A1 A0 20
Vertical linearity 08 VL1 VL0 A5 A4 A3 A2 A1 A0 20
Vertical scroll 09 0 0 A5 A4 A3 A2 A1 A0 20
EW width (EW) (1) 0A 0 0 A5 A4 A3 A2 A1 A0 20
EW parabola/width (PW) (1) 0B 0 0 A5 A4 A3 A2 A1 A0 20
EW upper corner parabola(1) 0C 0 0 A5 A4 A3 A2 A1 A0 20
EW lower corner parabola(1) 0D 0 0 A5 A4 A3 A2 A1 A0 20
EW trapezium (TC) (1) 0E 0 0 A5 A4 A3 A2 A1 A0 20
Vertical slope (VS) 0F 0 0 A5 A4 A3 A2 A1 A0 20
Vertical amplitude (VA) 10 0 0 A5 A4 A3 A2 A1 A0 20
S-correction (SC) 11 0 0 A5 A4 A3 A2 A1 A0 20
Vertical shift (VSH) 12 0 0 A5 A4 A3 A2 A1 A0 20
Vertical zoom (VX) 13 0 0 A5 A4 A3 A2 A1 A0 20
Off-set IF demodulator 14 0 0 A5 A4 A3 A2 A1 A0 20
AGC take-over 15 0 0 A5 A4 A3 A2 A1 A0 20
Spare 16 0 0 0 0 0 0 0 0 00
Black level offset R 17 0 0 A5 A4 A3 A2 A1 A0 20
Black level offset G 18 0 0 A5 A4 A3 A2 A1 A0 20
Peaking 19 PF1 PF0 A5 A4 A3 A2 A1 A0 20
White limiting 1A 0 0 SOC1 SOC0 A3 A2 A1 A0 08
Brightness 1B 0 0 A5 A4 A3 A2 A1 A0 20
Saturation 1C 0 0 A5 A4 A3 A2 A1 A0 20
Contrast 1D 0 0 A5 A4 A3 A2 A1 A0 20
Base-band tint control 1E 0 0 A5 A4 A3 A2 A1 A0 20
Spare 1F 0 0 0 0 0 0 0 0 00
White point R 20 0 0 A5 A4 A3 A2 A1 A0 00
White point G 21 0 0 A5 A4 A3 A2 A1 A0 00
White point B 22 0 0 A5 A4 A3 A2 A1 A0 00
PGR - Preset Gain Red 23 LPG A6 A5 A4 A3 A2 A1 A0 00
PGG - Preset Gain Green 24 0 A6 A5 A4 A3 A2 A1 A0 00
PGB - Preset Gain Blue 25 0 A6 A5 A4 A3 A2 A1 A0 00
Timing of ‘wide blanking’ (1) 26 WBF3 WBF2 WBF1 WBF0 WBR3 WBR2 WBR1 WBR0 88
Hue for NTSC 27 0 0 A5 A4 A3 A2 A1 A0 00
IF Preset Value 1 28 0 EPVI A5 A4 A3 A2 A1 A0 00
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SUBADDR DATA BYTE POR

FUNCTION
(HEX) D7 D6 D5 D4 D3 D2 D1 D0 Value
IF Preset Value 2 29 0 0 A5 A4 A3 A2 A1 A0 00
Spare 2A 0 0 0 0 0 0 0 0 00
Spare 2B 0 0 0 0 0 0 0 0 00
Spare 2C 0 0 0 0 0 0 0 0 00
Spare 2D 0 0 0 0 0 0 0 0 00
Spare 2E 0 0 0 0 0 0 0 0 00
Vision IF 0 2F 0 IFD IFA IFB IFC VSW MOD AFN 00
Vision IF 1 30 0 STM AGCM IFLF GD AGC1 AGC0 FFI 00
Vision IF 2 31 CMSS VA1 VA0 VAI IFS IFO2 IFO1 IFO0 00
Sound 0 32 0 NRR 0 DSG RDS MONO FMWS1 FMWS0 00
Sound 1 33 AGN AM SM1 SM0 FMD FMC FMB FMA 00
Sound 2 34 0 0 AVLE QSS BPB AVL(4) FMR FMI 00
Sound 3 35 0 FMS AVLM 0 ESSIF CMCA BPB2 AMLOW 00
Audio selection 0 36 0 HPVC SPT 0 SMLS SO2 SO1 SO0 00
Audio selection 1 37 0 E2D(3) SAS2 SAS1 SAS0 HPO2 HPO1 HPO0 00
Video selection 0 38 CS1A CS1B CS1C CS1D INA INB INC IND 00
Video selection 1 39 0 0 0 CFA0 CV2 SVO1 SVO0 SYS 00
Video selection 2 3A 0 0 VDXEN VDX YD3 YD2 YD1 YD0 00
Colour decoder 0 3B CM3 CM2 CM1 CM0 MAT MUS ACL CB 00
Colour decoder 1 3C SBO1 SBO0 CHSE1 CHSE0 CLO DTR BPS FCO 00
Synchronisation 0 3D SDC HP2 FOA FOB POC STB HTXT VID 00
Synchronisation 1 3E WBI RED FSL OSO FORF FORS DL NCIN 00
Synchronisation 2 3F 0 VGM1 VGM0 LED SSL SD2 SD1 SD0 00
Deflection 0 40 VSD OSVE DFL XDT SBL AVG EVG HCO(1) 00
Deflection 1 / Control 0 41 DEFL SVMA MVK 0 0 0 FBC EVB 00
Control 1 42 INTF EGL SLG0 AKB CL3 CL2 CL1 CL0 00
Control 2 43 IE3 IE2 DINT YC YUV2 YUV1 YUV0 HBL(1) 00
Control 3 44 GAM TFR CLD CBS OUV PWL RBL RGBL 00
Control 4 45 BKS BSD AAS DSK WS1 WS0 BLS TUV 00
Control 5 46 OFB HCT FINM FIN SLG1 BLBG LLB DSA 00
Peaking 47 0 0 RPA1 RPA0 RPO1 RPO0 COR1 COR0 00
SVM 0 48 0 CRA0 SPR2 SPR1 SPR0 SVM2 SVM1 SVM0 00
SVM 1 49 DSS 0 0 0 VMA1 VMA0 SMD1 SMD0 00
Miscellaneous 1 4A 0 DISG DDLE CSY SWO1 CMB2 CMB1 CMB0 00
Miscellaneous 2 4B 0 0 0 0 BPYD 0 0 0 00
Note
1. These functions are only available when the East-West drive output is active (AVLE = 0).
2. This function is available only in the “Stereo” and “AV Stereo” versions.
3. Only available in the “Mono” versions
4. The AVL function can only be activated when a capacitor is connected to the EW output pin (AVLE = 1) or to the
subcarrier output pin (via the bits CMB2-CMB0).
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Table 46 Outputs TV-processor
DATA BYTE
FUNCTION SUBADDR
D7 D6 D5 D4 D3 D2 D1 D0
Output status bytes 00 POR SID LOCK SL CD3 CD2 CD1 CD0
01 XPR NDF FSI IVW WBC HBC BCF COMB
02 SUP AGC IN3 IN2 SUPR X FMW FML
03 X X X IVWF SN2 SN1 SN0 YCD
04 AFC7 AFC6 AFC5 AFC4 AFC3 AFC2 AFC1 AFC0
05 GLOK RG6 RG5 RG4 RG3 RG2 RG1 RG0
06 PTW GG6 GG5 GG4 GG3 GG2 GG1 GG0
07 X BG6 BG5 BG4 BG3 BG2 BG1 BG0
08-09 X X X X X X X X
0A 0 0 0 DFL4 DFL3 DFL2 DFL1 DFL0
0B DISC9 DISC8 DISC7 DISC6 DISC5 DISC4 DISC3 DISC2
0C-0F X X X X X X X X
Explanation input control data TV-processor Table 50 Horizontal bow

Table 47 Volume control (L and R) DAC SETTING CONTROL
DAC SETTING CONTROL 0 screen top and bottom 1.0 µs delayed
with respect to centre
0 attenuation 70 dB
20 no correction
7F no attenuation
3F screen top and bottom 1.0 µs
Table 48 Horizontal shift advanced with respect to centre
DAC SETTING CONTROL Table 51 Upper/lower vertical linearity control

0 −2 µs VL1 VL0 SETTING
20 0
0 0 ‘full-screen’ vertical linearity (see
3F +2 µs Table 52)
0 1 only ‘lower’ vertical linearity
Table 49 Horizontal parallelogram
1 0 only ‘upper’ vertical linearity
DAC SETTING CONTROL
0 screen top 0.75 µs delayed and Table 52 Vertical linearity (VL1/VL0 setting 0/0)
screen bottom 0.75 µs advanced with DAC SETTING CONTROL
respect to centre
0 ratio bottom/top of screen: 117%
20 no correction
20 no correction
3F screen top 0.75 µs advanced and
screen bottom 0.75 µs delayed with 3F ratio bottom/top of screen: 85%
respect to centre
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Table 53 Vertical scroll (at zoom setting of 3FH, Table 59 Vertical amplitude
percentage of nominal visible amplitude); note 1
DAC SETTING CONTROL
DAC SETTING CONTROL 0 amplitude 80%
0 picture shift −18% 20 amplitude 100%
20 no picture shift 3F amplitude 120%
3F picture shift +18%
Table 60 S-correction
Note
1. The vertical scroll function is active only in the expand DAC SETTING CONTROL
mode of the vertical zoom, i.e at a DAC position which 0 correction −10%
is larger than 10H. 0E no correction
3F correction 25%
Table 54 EW width
DAC SETTING CONTROL Table 61 Vertical shift

0 output current 700 µA DAC SETTING CONTROL
3F output current 0 µA
0 shift −5%
20 no correction
Table 55 EW parabola/width
3F shift +5%
DAC SETTING CONTROL
0 output current 0 µA Table 62 Vertical zoom
3F output current 440 µA at top and DAC SETTING CONTROL
bottom of screen
0 amplitude 75%
Table 56 EW upper/lower corner parabola 19 amplitude 100%
3F amplitude 138%
DAC SETTING CONTROL
0 output current +262 µA (+55%) Table 63 Offset IF demodulator
11 output current 0 µA
DAC SETTING CONTROL
3F output current −262 µA (−55%)
0 negative correction
Table 57 EW trapezium 20 no correction
3F positive correction
DAC SETTING CONTROL
0 output current at top of screen 100 µA Note
lower that at bottom 1. This control is intended to correct for DC offset in the
20 no correction IF-PLL to improve the S/N ratio of the intercarrier
3F output current at top of screen 100 µA sound signal.
higher than at bottom
Table 64 AGC take-over
Table 58 Vertical slope DAC SETTING CONTROL
DAC SETTING CONTROL 0 tuner take-over at IF input signal of
0.4 mV
0 correction −20%
3F tuner take-over at IF input signal of
20 no correction
80 mV
3F correction +20%
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Table 65 Black level offset R/V - G/U; Table 70 Brightness control
DAC SETTING CONTROL DAC SETTING CONTROL

0 −100 mV (R/G), -50mV (U/V) 0 correction −0.4 V
20 no offset 20 no correction
3F +100 mV (R/G), +50mV (U/V) 3F correction +0.4 V
Note Table 71 Saturation control

1. Offset DAC can be used for offset correction on RG or
on UV. The range for both cases is different. DAC SETTING CONTROL
0 colour off (−52 dB)
Table 66 Peaking centre frequency and delay 17 saturation nominal
PF1 PF0 CENTRE FREQUENCY DELAY 3F saturation +300%
0 0 2.7 MHz 190 ns
Table 72 Contrast control
0 1 3.1 MHz 160 ns
1 0 3.5 MHz 143 ns DAC SETTING CONTROL
1 1 4.0 MHz 125 ns 0 RGB amplitude −14 dB
20 RGB amplitude nominal
Table 67 Peaking control (overshoot in direction ‘black’) 3F RGB amplitude +6 dB
DAC SETTING CONTROL
Table 73 Base-band tint control
0 depeaking (overshoot −18%)
0D no peaking DAC SETTING CONTROL
3F overshoot 75% 0 −30°
20 0°
Table 68 Soft clipping level 3F +30°
VOLTAGE DIFFERENCE BETWEEN
SOC1 SOC0 Table 74 White point R/G/B
SOFT CLIPPING AND PWL
0 0 0% above PWL level SETTING CONTROL
0 1 5% above PWL level 0 gain −3 dB
1 0 10% above PWL level 20 no correction
1 1 soft clipping off 3F gain +3 dB
Table 69 Peak White Limiting; note 1 Table 75 RGB gain preset; note 1
DAC SETTING CONTROL LPG CONDITION
00 0.40 VBL-WH 0 normal operation
0F 0.60 VBL-WH 1 preset gain setting is loaded
Note Note
1. CVBS/Y input signal at which the Peak White Limiting 1. The gain of the RGB amplifiers is controlled by means
is activated (max contrast setting). Nominal input of 7-bit DACs. The value of the gain is dependent on
signal: 0.7 VBL-WH. the setting of the “White Point RGB” registers
(subaddress 20H - 22H), the setting of the “Cathode
drive level” (CL3 - CL0 in subaddress 42H) and the
CCC loop control. During switch-on of the TV receiver
the preset value of the gain setting has to be loaded.
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Table 76 Preset gain setting for R, G and B, note 1 Table 80 PLL demodulator frequency setting
SETTING CRT DRIVE VOLTAGE IFD IFA IFB IFC IF FREQUENCY
0 45 VP-P 0 0 0 0 58.75 MHz
40 90 VP-P 0 0 0 1 45.75 MHz
7F 180 VP-P 0 0 1 0 38.90 MHz
0 0 1 1 38.00 MHz
Note
0 1 0 0 33.40 MHz
1. These values are valid in the following condition:
0 1 0 1 43.008 MHz
a) The white point setting for the R, G and B channel
is set to 0 0 1 1 0 33.90 MHz
b) The cathode drive setting (CL3-CL0) is set to 0 0 1 1 1 49.152 MHz

1 X X X external reference carrier
c) The contrast setting is −3 dB
d) The gain of the RGB output amplifiers is 80 Table 81 Video mute
Table 77 Timing of ‘wide blanking’ VSW STATE
WBF/R3-0 SETTING 0 normal operation
0 3.5 / 7.8 µs 1 IF-video signal switched off

0F 5.9 / 10.2 µs
Table 82 Modulation standard
Table 78 Hue control for NTSC MOD MODULATION

HUE CONTROL 0 negative
0 −40° 1 positive
20 0°
Table 83 AFC switch
3F +40°
AFN MODE
Table 79 IF PLL oscillator preset value; note 1 0 normal operation
EPVI CONDITION 1 AFC not active
0 normal operation
Table 84 Search tuning mode
1 preset value is loaded
STM MODE
Note
0 normal operation
1. During “mix-down” of DVB signals with an external
1 reduced sensitivity of video indent circuit
reference carrier (CMB2/CMB1/CMB0 = 1/0/0) the
frequency of the oscillator can be defined by means of
Table 85 Internal or external AGC mode
the settings of the “IF Preset Value” registers
(subaddress 28H and 29H). AGCM MODE
0 internal mode of DVB AGC
1 external mode for DVB AGC
Table 86 Calibration of IF PLL demodulator

IFLF MODE
0 calibration system active
1 calibration system not active
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Table 87 Group delay on CVBS1 signal Table 90 Selection of sync input signal for the video ident
circuit
GD CONDITION
0 no group delay correction CMSS CONDITION
1 group delay correction switched on 0 input from sync separator in IF ident circuit
1 input from main sync separator
Table 88 IF AGC speed
Table 91 Video output signal amplitude
AGC1 AGC0 AGC SPEED
0 0 0.7 × norm VA1 VA0 OUTPUT SIGNAL AMPLITUDE
0 1 norm 0 0 no correction
1 0 3 × norm 1 0 amplitude −5%
1 1 6 × norm 1 1 amplitude +5%
Table 89 Fast filter IF-PLL Table 92 System I output signal amplitude correction
FFI CONDITION VAI MODE
0 normal time constant 0 no correction

1 increased time constant 1 amplitude +12%
Table 93 IF sensitivity
IFS IF SENSITIVITY
0 normal
1 reduced
Table 94 IF output selection, note 1
STEREO and AV STEREO versions MONO versions

IFO2 IFO1 IFO0 DESCRIPTION
PIN 43 PIN 44 PIN 43
0 0 0 mute mute mute high ohmic output
0 0 1 IFOUT mute IFOUT IF output without sound trap / group delay
0 1 0 IFOUT + sndtrap mute IFOUT + sndtrap IF output with sound trap / group delay
0 1 1 DVBP / FMRO DVBN / FMRO DVBSE / FMRO DVB output or FM radio output
1 0 0 DVBSE / FMRO mute DVBSE / FMRO DVB output or FM radio output
1 1 0 mute DVBSE / FMRO DVBSE / FMRO DVB output or FM radio output
1 1 1 black DC black DC black DC black level DC output
Note
1. The result of this setting of the IFO2-IFO0 bits is also dependent on the setting of the IF-PLL frequency (IFA-IFC in
subaddress 2FH) and the FMR bit (subaddress 34H). The following conditions are possible:
a) Analogue TV mode (required settings: FMR = 0 and IFA/IFB/IFC = 000/001/010/011/100/110). In this mode the
valid IFO2-IFO0 settings are: 000, 001, 010 and 111.
b) DVB mode (required settings: FMR = 0 and IFA/IFB/IFC = 101 or 111). In this mode the valid IFO2-IFO0 settings
are: 000, 011, 100, 110 and 111. The mixed-down DVB signals are now available at the outputs (DVBP/N
indicates a balanced output, DVPSE a single ended output).
c) FM radio mode (required settings: FMR = 1 and IFA/IFB/IFC = 101 or 111). The valid IFO2-IFO0 settings are the
same as for the DVB mode.
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Table 95 No Red reduction during blue stretch Table 102 Sound mute
NRR CONDITION SM1 SM0 CONDITION
0 red reduction active 0 0 mute off
1 not active 0 1 sound enhancer; note 1
1 0 mute on
Table 96 Gain from audio inputs to audio outputs
Note
DSG GAIN
1. The sound enhancer is active only during FM sound. It
0 0 dB limits the noise which is generated by the digital
1 +6 dB acquisition circuit. For AM sound only the positions
“mute off” and “mute on” should be used.
Table 97 Radio Data System (RDS)
Table 103FM demodulator at 10.7 MHz
RDS CONDITION
FMD MODE
0 not active
0 frequency FM demodulator determined by the
1 demodulated audio signal supplied to RDS
bits FMA, FMB and FMC
decoder
1 frequency FM demodulator 10.7 MHz
Table 98 Activate mono-FM demodulator (in “stereo”
versions) Table 104Centre frequency FM demodulator/sound trap
MONO MODE FMC FMB FMA FM DEMOD. SOUND TRAP

0 mono-FM demodulator not active 0 0 0 5.5 MHz 5.5 MHz
1 mono-FM demodulator active 0 0 1 6.0 MHz 6.0 MHz
0 1 0 4.5 MHz 4.5 MHz
Table 99 Window select for FM demodulator 0 1 1 6.5 MHz 6.5 MHz
FMWS1 FMWS0 WINDOW 1 0 0 5.74 MHz 5.5 MHz
0 0 100 kHz 1 0 1 7.90 MHz −
0 1 225 kHz 1 1 0 4.72 MHz 4.5 MHz
1 0 450 kHz 1 1 1 9.60 MHz −
1 1 900 kHz
Table 105Enable AVL function on East-West output pin
Table 100 Gain FM demodulator AVLE CONDITION
AGN MODE 0 East-West functionality active
0 normal operation 1 AVL functionality active
1 gain +6 dB
Table 106 Mode of Quasi Split Sound amplifier
Table 101Selection QSS out or AM out
QSS MODE
AM MODE 0 QSS amplifier not active, input of sound PLL
0 QSS output selected connected to vision IF amplifier output
1 QSS amplifier active, output connected to
1 AM output selected
QSSO or to input sound PLL (via FMI bit)
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Table 107 Bypass of sound bandpass filter Table 115 Bypass sound bandpass filter section 2
BPB CONDITION BPB2 MODE
0 normal operation 0 bandpass filter active
1 sound bandpass filter bypassed 1 bandpass filter bypassed
Table 108 Auto Volume Levelling Table 116 Audio output signal for AM sound
AVL MODE AMLOW CONDITION
0 not active 0 normal output signal amplitude
1 active 1 output signal amplitude reduced with 6 dB
Table 109 FM radio function enabled Table 117 Head phone volume control
FMR MODE HPVC CONDITION
0 TV mode 0 volume control not active
1 FM radio mode 1 volume control active
Table 110 Connection of output of QSS amplifier Table 118 Sync Performance Trick mode
FMI MODE SPT MODE
0 output connected to QSSO output 0 influence S/N detector on phi1 loop disabled
1 output connected to sound PLL circuit
1 influence S/N detector on phi1 loop enabled
Table 111 FM mono demodulator sensitivity

Table 119 Sound mute loudspeaker output
FMS MODE
SMLS CONDITION
0 normal operation
0 normal operation
1 reduced sensitivity
1 output muted
Table 112 Maximum audio gain when AVL is active

Table 120 Audio select for SCART/CINCH output, note 1
AVLM MODE SO2 SO1 SO0 AUDOUTSL/R
0 normal gain 0 0 0 FM MONO / AM
1 maximum gain 0 0 1 AUDIOIN2
0 1 0 AUDIOIN3
Table 113 SSIF input pin selection 0 1 1 AUDIOIN4
1 0 0 AUDIOIN5
ESSIF MODE
1 0 1 fixed output of Audio DSP,
0 SSIF at pin 33 note 2
1 SSIF at pin 53 1 1 0 vol. contr. output Audio DSP,
note 2
Table 114 Activate complete mono channel (in “stereo” 1 1 1 mute
versions)
Note
CMCA MODE
1. These bits are only valid for stereo and AV stereo
0 stereo mode versions
1 mono LF path only HP left 2. Only valid in versions with Audio DSP
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Table 121 Selection of audio output signal on AUDEEM Table 124 CVBS/PIP output
pin, note 1 (Mono versions)
CS1A CS1B CS1C CS1D SELECTED SIGNALS
E2D MODE 0 0 0 0 mute
0 deemphasis (front-end audio available) 0 0 0 1 CVBS1 (internal from IF)
1 selected audio signal available 0 0 1 0 CVBS2
Note 1 0 1 0 Y2 + C3
1. This function can be activated only when the MOD bit 0 0 1 1 CVBS3
is 0. 1 0 1 1 Y3 + C3
0 1 0 0 CVBS4
Table 122 Audio select for Audio DSP input
1 1 0 0 Y4 + C4
SAS2 SAS1 SAS0 SELECTION 0 1 0 1 CVBSX; note 1
0 0 0 FM MONO / AM 1 1 0 1 YX + CX; note 1
0 0 1 AUDIOIN2
0 1 0 AUDIOIN3 Table 125 Video input selection
0 1 1 AUDIOIN4
1 0 0 AUDIOIN5 INA INB INC IND SELECTED SIGNALS
1 0 1 spare 0 0 0 1 CVBS1 (internal from IF)
1 1 0 spare 0 0 1 0 CVBS2
1 1 1 mute 1 0 1 0 Y2/C3
0 0 1 1 CVBS3
Table 123 Audio select; note 1
1 0 1 1 Y3/C3
HPO2 HPO1 HPO0 AUDOUTHPL/R 0 1 0 0 CVBS4
0 0 0 FM MONO / AM
1 1 0 0 Y/C4
0 0 1 AUDIOIN2
0 1 0 1 CVBSX; note 1
0 1 0 AUDIOIN3
0 1 1 AUDIOIN4 1 1 0 1 Y/CX; note 1
1 0 0 AUDIOIN5 Notes for table 124 and 125
1 0 1 fixed output of Audio DSP,
1. This command is valid only when the CVBSX (Y/CX)
note 2
function is activated via the YC-bit.
1 1 0 vol. contr. output Audio DSP,
note 2 Table 126 Comb filter mode
1 1 1 mute
CFA0 COMB FILTER
Note
0 adaptive 4H/2H comb filter for PAL/NTSC
1. The function of the HPO2/0 bits depends on the IC
1 comb filter off
version. For stereo versions with Audio DSP these bits
control the input signal selection for the Headphone
Table 127 CVBS2 input signal selection
channel. For stereo versions without Audio DSP and
for mono versions they control the input signal CV2 MODE
selection for the speaker output channel.
0 CVBS2 input directly selected
2. Only valid in versions with Audio DSP
1 CVBS2 input signal is supplied sound trap
and group delay correction circuit. The
selection of this signal is realised by means of
the CS1A-D and INA-D bits (setting 0001).
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Table 128 Function of IFVO/SVO/CVBSI pin Table 133 Colour decoder mode, note 1
SVO1 SVO0 PIN FUNCTION CM3 CM2 CM1 CM0 DECODER MODE FREQ
0 0 wrong function, do not use 0 0 0 0 PAL/NTSC/SECAM A
0 1 selected CVBS available at output 0 0 0 1 PAL/SECAM A
1 0 pin used as CVBS input; note 1 0 0 1 0 PAL A
1 1 wrong function, do not use 0 0 1 1 NTSC A
0 1 0 0 SECAM
Note
0 1 0 1 PAL/NTSC B
1. When this function is selected the setting of the CV2
bit is neglected. The signal is supplied to the sound 0 1 1 0 PAL B
trap and group delay correction circuit. The selection 0 1 1 1 NTSC B
of this signal is realised by means of the CS1A-D and 1 0 0 0 PAL/NTSC/SECAM(2) ABCD
INA-D bits (setting 0001).
1 0 0 1 PAL/NTSC C
Table 129 Active input for sync separator, note 1 1 0 1 0 PAL C
1 0 1 1 NTSC C
SYS MODE
1 1 0 0 PAL/NTSC (Tri-Norma) (2) BCD
0 sync coupled to YSYNC input
1 1 0 1 PAL/NTSC D
1 sync coupled to selected CVBS/Y input
1 1 1 0 PAL D
Note 1 1 1 1 NTSC D
1. Sync coupled to the selected CVBS input should only
Note
be used when the external RGB signal contains no
sync pulse. 1. The decoder frequencies for the various standards are
obtained from an internal clock generator which is
Table 130 Control of coupling between vision IF amplifier synchronised by a 24.576 MHz reference signal which
and synchronisation circuit is obtained from the µ-Controller clock generator.
a) The nominal standard frequencies are:
VDXEN MODE
b) A: 4.433619 MHz
0 coupling controlled by the input signal
selection bits (INA-IND) c) B: 3.582056 MHz (PAL-N)
1 coupling controlled by the VDX bit d) C: 3.575611 MHz (PAL-M)
e) D: 3.579545 MHz (NTSC-M)
Table 131 Coupling between vision IF amplifier and The nominal oscillator frequency may have a slightly
synchronisation circuit different value (see also Table 249)
VDX MODE 2. In the auto modes (CM3-CM0 setting 1000 and 1100)
PAL with frequency D and NTSC with frequencies B
0 the circuits are coupled
and C are not possible.
1 the circuits are not coupled
Table 134 PAL-SECAM/NTSC matrix
Table 132 Y-delay adjustment
MAT MATRIX POSITION
YD0 to YD3 FSC = 4.43 MHz FSC = 3.58 MHz
0 adapted to standard
YD3 YD3 × 220 ns + YD3 × 280 ns +
1 PAL matrix
YD2 YD2 × 110 ns + YD2 × 140 ns +
YD1 YD1 × 55 ns + YD1 × 70 ns + Table 135 NTSC matrix
YD0 YD0 × 30 ns YD0 × 30 ns
MUS MATRIX POSITION
0 Japanese matrix
1 USA matrix
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Table 136 Automatic colour limiting Table 143 Forced Colour-On

ACL COLOUR LIMITING FCO CONDITION
0 not active 0 off
1 active 1 on
Table 137 Chroma bandpass centre frequency Table 144 Setting duty cycle of horizontal drive signal,
note 1 on page 119
CB CENTRE FREQUENCY
0 FSC SDC CONDITION
1 1.1 × FSC 0 duty cycle 55:45

1 duty cycle 60:40
Table 138 SECAM B-Y black level offset adjustment
Note
SBO1 SBO0 OFFSET 1. The setting of the duty cycle of the horizontal drive
0 0 + 4 kHz signal can only be adapted when the IC is in the
0 1 + 1 kHz ‘stand-by’ mode (STB = 0)
1 0 − 1 kHz
Table 145 Synchronization of OSD/TEXT display
1 1 − 4 kHz
HP2 µ-CONTROLLER COUPLED TO
Table 139 PAL/NTSC ident sensitivity (burst amplitude at 0 ϕ1 loop
strong signal (typical value) 1 ϕ2 loop
CHSE1 CHSE0 SENSITIVITY
Table 146 Phase 1 (ϕ1) time constant
0 0 −34 dB
0 1 −37 dB FOA FOB MODE
1 0 −41 dB 0 0 normal
1 1 −46 dB 0 1 slow
1 0 OSD mode (very slow)
Table 140 Centre frequency of cloche filter 1 1 fast
CLO CENTRE FREQUENCY
Table 147 Synchronization mode
0 4.29 MHz
1 4.33 MHz POC MODE
0 active
Table 141 Chroma trap mode 1 not active
DTR MODE
Table 148 Stand-by
0 single chroma trap
1 dual chroma trap, more suppression but less STB MODE
bandwidth 0 stand-by
1 normal
Table 142 Bypass of chroma base-band delay line
BPS DELAY LINE MODE Table 149 Source of CSO signal for teletext decoder
0 active HTXT MODE
1 bypassed 0 CSO derived from dedicated sync separator
1 CSO derived from main sync separator
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Table 150 Mode of ϕ1 loop Table 157 Vertical divider mode

VID MODE NCIN VERTICAL DIVIDER MODE
0 ϕ1 loop dependent on the video ident system 0 normal operation
1 ϕ1 loop only dependent on FOA/FOB or POC 1 switched to search window
bits
Table 158 Function of VGUARD/SWIO pin
Table 151 Increased wide blanking
VGM1 VGM0 FUNCTION
WBI MODE 0 0 vertical guard
0 normal mode 0 1 vertical guard combined with LED
1 wide blanking range adapted to Double drive output
window mode 1 0 switch output (0 - 5 V)
1 1 input port, detector output via NDF
Table 152 Disable reference oscillator check in the SUP bit
output bit (see also Table 234)
RED CONDITION Table 159 Mode of LED driver / switch output
0 reference oscillator check enabled LED MODE
1 reference oscillator check disabled 0 LED drive off / switch output HIGH
1 LED drive on / switch output LOW
Table 153 Forced slicing level for vertical sync
FSL SLICING LEVEL Table 160 Slicing level sync separator
0 slicing level dependent on noise detector SSL SLICING LEVEL
1 fixed slicing level of 60% 0 50%
1 30%, direction top sync
Table 154 Switch-off in vertical overscan
OSO MODE Table 161 Source selection for video identification
0 Switch-off undefined SD2 SD1 SD0 VIDEO INPUT
1 Switch-off in vertical overscan 0 0 0 selected input signal (via
INA-IND bits)
Table 155 Forced field frequency 0 0 1 CVBS1 (internal from IF)
0 1 0 CVBS2
FORF FORS FIELD FREQUENCY
0 1 1 CVBS3/Y3
0 0 auto (60 Hz when line not in sync) 1 0 0 CVBS4/Y4
0 1 60 Hz 1 0 1 G/Y-2 (CVBS/Y-X)
1 0 keep last detected field frequency 1 1 0 G/Y-3
1 1 auto (50 Hz when line not in sync)
Table 162 Vertical scan disable
Table 156 Interlace VSD SETTING
DL STATUS 0 normal operation
0 interlace 1 vertical scan switched off
1 de-interlace
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Table 163 Black current measuring lines in overscan (for Table 170 Read-out deflection timer
vertical zoom setting < 1)
DEFL MODE
OSVE MODE 0 read-out disabled
0 normal operation 1 read-out enabled
1 measuring lines in overscan
Table 171 Scan Velocity Modulation output signal (1)
Table 164 Disable flash protection
SVMA OUTPUT SIGNAL AMPLITUDE
DFL MODE
0 600 mVP-P
0 flash protection active 1 1200 mVP-P
1 flash protection disabled
Note
Table 165 X-ray detection 1. Input signal: 1 MHz with an amplitude of 350 mVP-P
XDT MODE
Table 172 Macro Vision Keying
0 protection mode, when a too high EHT is
detected the receiver is switched to stand-by MVK MODE
and the XPR-bit is set to 1 0 Macro vision keying not active
1 detection mode, the receiver is not switched 1 Macro Vision keying active
to stand-by and only the XPR-bit is set to 1
Table 173 Fixed beam current switch-off
Table 166Service blanking
FBC MODE
SBL SERVICE BLANKING MODE 0 switch-off with blanked RGB outputs
0 off 1 switch-off with fixed beam current
1 on
Table 174 Extended vertical blanking
Table 167 Adjustment Vg2 voltage
EVB SETTING
AVG MODE 0 normal vertical blanking
0 normal operation 1 extended vertical blanking in the upper and
1 Vg2 adjustment (WBC and HBC bits in output lower part of the picture; see also Fig. 82
byte 01 can be read)
Table 175 Amplitude/polarity of YUV interface signal
Table 168 Enable vertical guard (RGB blanking)
INTF INTERFACE SIGNAL AMPLITUDE
EVG VERTICAL GUARD MODE 0 signal according to YPRPB standard; note 1
0 not active 1 signal according to YUV standard; note 2
1 active
Note
Table 169 EHT tracking mode 1. YPRPB input: (colour bar 100% saturation):
Y = +1.0 VP-P; PR = +0.7 VP-P; PB = +0.7 VP-P.
HCO TRACKING MODE
2. YUV input: (colour bar 75% saturation):
0 EHT tracking only on vertical
Y = 1.4 VP-P; U = −1.33 VP-P; V = −1.05 VP-P.
1 EHT tracking on vertical and EW
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Table 176 Enable gain loop in the CCC system Table 179 Cathode drive level
EGL MODE CL3 - CL0 CONTROL
0 control loop not active 0 gain −3 dB
1 control loop active 7 nominal value
F gain +3 dB
Table 177 Selection high current in CCC system
SLG1 SLG0 MODE Table 180 Enable fast blanking of RGB/YPRPB-3 input
0 0 current level 220 µA IE3 FAST BLANKING

0 1 current level 150 µA 0 not active
1 0 current level 280 µA 1 active
1 1 current level 190 µA
Table 181 Enable fast blanking of RGB/YPRPB-2 input
Table 178 Black current stabilization
IE2 FAST BLANKING
AKB MODE 0 not active
0 active 1 active
1 not active
Table 182 Enable digital interface
DINT MODE
0 not active
1 active
Table 183 RGB/YUV/YPRPB switching options
RGB/YUV/YPRPB-2 INPUT OR INPUT WITH

YC YUV2 YUV1 YUV0 RGB/YPRPB-3 INPUT YUV/YPRPB INTERFACE OR HIGHEST
CVBS (Y/C) INPUT PRIORITY (5)
0 0 0 0 RGB with fast insertion RGB with fast insertion; note 1 RGB-3
0 0 0 1 RGB with fast insertion interface; note 2
0 0 1 0 RGB with fast insertion YUV with fast insertion; notes 1 + 3 YUV-2
0 0 1 1 RGB with fast insertion YPRPB input; notes 1+ 4 RGB-3
0 1 0 0 YPRPB input; note 4 YPRPB input; notes 1 + 4 YPRPB-3
0 1 0 1 YPRPB input; note 4 RGB with fast insertion; note 1 RGB-2
0 1 1 0 YPRPB input; note 4 interface; note 2
0 1 1 1 YPRPB input; note 4 YUV with fast insertion; notes 1 + 3 YUV-2
1 0 0 0 RGB with fast insertion CVBS-X or Y/C-X input RGB-3
1 1 1 1 YPRPB input; note 4 CVBS-X or Y/C-X input YPRPB-3
Notes
1. In this position the V output is changed to general purpose switch output (SWO1). This output is controlled by the
SWO1 bit in subaddress 4AH.
2. The amplitude and polarity of the input and output signals are determined by the setting of the INTF bit
3. YUV input: (colour bar 75% saturation): Y = 1.4 VP-P; U = −1.33 VP-P; V = −1.05 VP-P.
4. YPRPB input: (colour bar 100% saturation): Y = +1.0 VP-P; PR = +0.7 VP-P; PB = +0.7 VP-P.
5. When both inputs are activated (by means of IE2/IE3 or fast blanking) the input with the highest priority is dependent
on the selected option.
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Table 184 RGB blanking mode Table 192 Blanking of RGB outputs
HBL MODE RGBL CONDITION
0 normal blanking (horizontal flyback) 0 normal operation
1 wide blanking 1 RGB outputs blanked continuously
Table 185 Gamma control Table 193 Black stretch

GAM CONDITION BKS BLACK STRETCH
0 not active 0 off
1 active 1 on
Table 186 DC transfer ratio of luminance signal Table 194 Black Stretch Depth (A-A in Fig. 72)
TFR TRANSFER RATIO BSD MODE
0 no black level shift due to video content 0 15 IRE
1 black level shift of 10 IRE for complete white 1 30 IRE
picture
Table 195 Black area to switch off the black stretch
Table 187 Delay of clamp pulse
AAS MODE
CLD DELAY 0 10% back ground needed
0 normal timing 1 20% back ground needed
1 extra delay of 400 ns
Table 196 Dynamic skin control on/off
Table 188 Control sequence of beam current limiting
DSK MODE
CBS MODE
0 off
0 normal operation (contrast → brightness)
1 on
1 control on contrast and brightness in parallel
Table 197 Gamma control and white stretch settings
Table 189 Off-set control on UV input signals
WS1 WS0 EXPANSION (1) APL (2)
OUV MODE
0 0 0% −
0 off-set control on R/G output signals
0 1 6% 17%
1 off-set control on U/V input signals
1 0 8% 25%
Table 190 Peak White limiting 1 1 12% 28%
PWL MODE Note

0 peak white limiting circuit not active 1. This figure indicates the maximum increase of the gain
1 peak white limiting circuit active in the lower part of the characteristic (slope of the
curve, see Fig. 74).
Table 191 RGB blanking 2. The APL (Average Picture Level) figure indicates the
average luminance level at which the white stretch
RBL RGB BLANKING characteristic starts shifting from maximum stretching
0 not active to the linear curve. At an increase of the APL of about
1 active 13% the curve is linear (see also Fig. 75).
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Table 198 Blue stretch Table 205 Low level of beam current limiter
BLS BLUE STRETCH MODE LLB CONDITION

0 off 0 internal bias current of BCL pin switched off
1 on 1 internal bias current of BCL pin of 0.5 mA
switched on
Table 199 Tint control on UV signals
Table 206 Dynamic skin tone angle
TUV MODE
0 not active DSA CONDITION
1 active 0 117
1 123
Table 200 Black level offset on Blue channel
Table 207 Ratio pre- and aftershoot
OFB MODE
0 offset control on Red channel RPA1 RPA0 RATIO
1 offset control on Blue channel 0 0 1:1

0 1 1.5 : 1
Table 201 High contrast in Text mode 1 0 2:1
HCT MODE
Table 208 Ratio of positive and negative peaks
0 normal operation
RPO1 RPO0 RATIO
1 RGB output signal increased with 3 dB
0 0 1:1
Table 202 Fast insertion mode 0 1 1 : 1.3
1 0 1 : 1.7
FINM MODE 1 1 1 : 0.7
0 normal operation
1 fast insertion active behind the digital Table 209 Video dependent coring (peaking)
interface COR1 COR0 SETTING
Table 203 Forced mode of RGB/YUV/YPRPB inputs 0 0 off

0 1 coring active between 0 and 20 IRE
FIN MODE
1 0 coring active between 0 and 40 IRE
0 normal mode 1 1 coring active between 0 and 100 IRE
1 selected input forced on
Table 210 Coring on SVM
Table 204 Blanking of blue and green output
CRA0 SETTING
BLBG CONDITION
0 8%
0 normal operation 1 15%
1 blanking of the blue and green channel
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Table 211 Parabola on SVM output; note 1 Table 214 Scan Velocity Modulation mode
SETTING AT POSITIONS A, B SMD1 SMD0 MODE
SPR2 SPR1 SPR0 AND C (dB)
0 0 off
A B C 0 1 SVM on video
0 0 0 0 0 0
1 0 SVM on teletext or OSD
0 0 1 0 −3 −3
1 1 SVM on video or OSD (fast
0 1 0 −3 0 0
switching)
0 1 1 0 0 −3
1 0 0 −3 −3 0 Table 215 Gain selection of DISCO
1 0 1 0 −3 −6
1 1 0 −6 −3 0 DISG MODE
0 normal gain
Note
1 gain increased with 6 dB
1. The Scan Velocity Modulation output can be made
depend on the horizontal position on the screen. The
Table 216 Stabilization of the 1.8 V supply voltage; note 1
positions A, B and C are indicated in Fig. 77 on page
231. DDLE MODE
0 control loop 2.5 V internally
Table 212 Delay of RGB output to SVM output
1 control loop 2.5 V externally
SVM0 to SVM2 DELAY SETTING
SVM2 SVM2 × 100 ns + Note
SVM1 SVM1 × 50 ns + 1. The 1.8 V supply voltage is derived from the internally
SVM0 SVM0 × 25 ns generated 2.5 V supply rail by means of an emitter
follower. The control loop of this 2.5 V supply can be
Table 213 Amplitude of SVM output, note 1 closed taking into account the spread of this emitter
follower (DDLE = 1). In this way a very stable 1.8 V
VMA1 VMA0 SETTING supply is guaranteed. It is also possible to stabilise the
0 0 off 2.5 V supply by means of an internal control loop
0 1 0.9 VP-P (DDLE = 0).
1 0 1.3 VP-P
1 1 1.8 VP-P Table 217 Soft start-up mode
Note DSS MODE
1. The output signal amplitudes are specified for an input 0 normal operation
signal amplitude that is 50% of the nominal value. 1 soft start-up disabled
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Table 218 Condition flyback input pin (FBISO) Table 221 Y-delay bypass mode (note 1)
CSY CONDITION BPYD CONDITION
0 normal flyback input 0 Y-delay bypassed
1 composite H/V timing output 1 Y-delay enabled
Note
Table 219 Output switch (SWO1)
1. This mode can only be activated in the YC-mode
SWO1 CONDITION (INA=1).
0 output is ‘LOW’
1 output is ‘HIGH’
Table 220 Condition AVL/SWO/SSIF/REFO/IFREFI

CMB2 CMB1 CMB0 CONDITION
0 0 0 AVL and
SIF to FM mono demodulator
SIF to stereo demodulator
0 0 1 output voltage 2.1 V + subcarrier
(REFO)
0 1 0 SWO output voltage low (<0.8 V)
0 1 1 SWO output voltage high (>4.5 V)
1 0 0 external reference carrier for DVB
mix-down (REFIN)
1 0 1 SSIF to digital stereo decoder.
SSIF to FM mono demodulator.
1 1 0 SSIF to digital stereo decoder.
SIF to FM mono demodulator.
1 1 1 SSIF to FM mono demodulator.
SIF to digital stereo decoder.
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Explanation output control data TV-processor Table 227 X-ray protection

Table 222 Power-on-reset XPR OVERVOLTAGE
POR MODE 0 no overvoltage detected
0 normal 1 overvoltage detected
1 power-down
Table 228 Output vertical guard
Table 223 Video input signal identification NDF VERTICAL OUTPUT STAGE
SID CONDITION 0 OK
0 no video signal identified 1 failure
1 video signal identified
Table 229 Field frequency indication
Table 224 IF-PLL lock indication FSI FREQUENCY
LOCK INDICATION 0 50 Hz
0 not locked 1 60 Hz
1 locked
Table 230 Condition vertical divider, note 1
Table 225 Phase 1 (ϕ1) lock indication
IVW VERTICAL WINDOW INDICATION
SL INDICATION 0 vertical sync pulse not in narrow window
0 not locked 1 15 succeeding sync pulses in narrow window
1 locked
Note
Table 226Colour decoder mode, note 1 1. More information is given in note 61 on page 214
CD3 CD2 CD1 CD0 STANDARD Table 231 Indication black current stabilization; note 1
0 0 0 0 no colour standard identified WBC HBC CONDITION
0 0 0 1 NTSC with freq. A
0 0 outside window; current too low
0 0 1 0 PAL with freq. A
0 1 outside window; current too high
0 0 1 1 NTSC with freq. B
1 X in window
0 1 0 0 PAL with freq. B
0 1 0 1 NTSC with freq. C Note
0 1 1 0 PAL with freq. C 1. This function is valid only during the adjustment of the
Vg2 voltage (AVG = 1)
0 1 1 1 NTSC with freq. D
1 0 0 0 PAL with freq. D Table 232 Condition black current loop
1 0 1 0 SECAM
BCF CONDITION
Note 0 black current loop is stabilised
1. The values for the various frequencies can be found in 1 black current loop is not stabilised
the note of table 133.
Table 233 Comb filter mode
COMB MODE
0 comb filter not active
1 comb filter active
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Table 234 Supply voltage and reference oscillator Table 240 Indication FM-PLL in/out lock
indication
FML CONDITION
SUP CONDITION 0 FM-PLL out of lock
0 supply voltage (5 Volt) not present or 1 FM-PLL locked
reference oscillator not OK
1 supply voltage (5 Volt) present and reference Table 241 Condition vertical divider, note 1
oscillator OK, note 1
IVWF VERTICAL WINDOW INDICATION
Note
0 vertical sync pulse not in narrow window
1. When RED = 1 only the supply voltage condition is
checked. 1 7 succeeding sync pulses in narrow window
Note
Table 235 Indication tuner AGC
1. More information is given in note 61 on page 214
AGC CONDITION
0 tuner gain control active Table 242 Signal-to-Noise ratio of the demodulated CVBS
signal (IFVO)
1 no gain control of tuner
SN2 SN1 SN0 CONDITION
Table 236 Indication RGB-3 input condition 0 0 0 S/N ≤ 18 dB
IN3 RGB INSERTION 0 0 1 S/N ≥ 18 dB and ≤ 25 dB
0 no 0 1 0 S/N ≥ 25 dB and ≤ 28 dB
1 yes 0 1 1 S/N ≥ 28 dB and ≤ 31 dB
1 0 0 S/N ≥ 31 dB and ≤ 37 dB
Table 237 Indication RGB-2 input condition 1 0 1 S/N ≥ 37 dB and ≤ 40 dB
IN2 RGB INSERTION 1 1 0 S/N ≥ 40 dB and ≤ 43 dB
0 no 1 1 1 S/N ≥ 43 dB
1 yes
Table 243 Output of Y/C detector; note 1
Table 238 Protection of 1.8 V supply voltage YCD CONDITION
SUPR SUPPLY VOLTAGE PROTECTION 0 CVBS signal at input
0 supply voltage OK 1 Y/C signal at input
1 supply voltage too high Note
1. The Y/C detector is only active for the CVBS(Y)3/C3,
Table 239 Indication FM-PLL in/out window
CVBS(Y)4/C4 and CVBS(Y)x/Cx inputs and not for the
FMW CONDITION CVBS(Y)2/C3 input.
0 FM-PLL in window
1 FM-PLL out of window
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Table 244 AFC output (two-complement notation); 25 kHz Table 246 Indication “picture tube warm”
per step
PTW CONDITION
OUTPUT FREQUENCY DEVIATION 0 cathode current below selected current
0 no frequency deviation 1 cathode current ≥ selected current
3C deviation: +1.5 MHz or more
C4 deviation: −1.5 MHz or more Table 247 Read-out CCC registers, see note on Table 76
RG6 - RG0
Table 245 Indication CCC gain loop GG6 - GG0 CRT DRIVE VOLTAGE
GLOK CONDITION BG6 - BG0
0 gain loop not yet stabilised 0 45 VP-P

1 gain loop stabilised 40 90 VP-P
7F 180 VP-P
Table 248 Deflection timer read-out

DFL4 DFL3 DFL2 DFL1 DFL0 STATE CONDITION
0 0 0 0 0 standby POR situation
0 0 0 0 1 standby Only standby supply is present
0 0 0 1 0 standby Standby supply is present and ‘SUP’ bit = ‘1’, note 1
0 0 1 1 0 slow start Slow start of horizontal output is active when ‘SUP’ bit = ‘1’
0 0 1 0 1 slow start Slow start of horizontal output is active when ‘SUP’ bit = ‘0’
0 1 0 0 0 soft stop Soft stop of horizontal output is active
0 1 1 1 1 operational Slow start of horizontal output is ended, device is operational
Note
1. IF and sound are operational
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Table 249 Subcarrier oscillator frequency, note 1.

DECODER FREQUENCY
DISC9-DISC2 A B C D
00000000 -750 -750 -750 -750
10000000 nom. nom. nom. nom.
11111111 +750 +750 +750 +750
Note
1. The nominal decoder frequencies are obtained from
an internal clock generator which is synchronised by a
24.576 MHz reference signal from the µ-controller
clock. These frequencies can have a small offset from
the standard subcarrier frequencies.
The nominal frequencies are:
a) A: 4.433625 MHz
b) B: 3.582000 MHz (PAL-N)
c) C: 3.575625 MHz (PAL-M)
d) D: 3.579563 MHz (NTSC-M)
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GENERAL DESCRIPTION OF THE TV SOUND Supported standards

PROCESSOR
The multistandard capability of the TV Sound Processor
The TV Sound Processor is a digital TV sound processor covers all terrestrial TV sound standards, FM Radio and
for analog multi-channel sound systems in TV sets. It is satellite FM.
based on a 24 bit DSP and designed to support several
The AM sound of L/L' standard is normally demodulated in
applications.
the 1st sound IF. The resulting AF signal has to be entered
A new easy-to-use control concept was implemented for into the mono audio input of the TV Sound Processor. A
easiest configuration programming of the very complex second possibility is to use the AM demodulator in the
functionality of the TV Sound Processor. Pre-defined DEMDEC part, however this may result in limited
setups are available for all implemented sound processing performance.
modes. A loudspeaker switching concept allows it to adapt
Korea has a stereo sound system similar to Europe. It is
the pre-defined setups to the specific loudspeaker
supported by the TV Sound Processor. Differences
application.The built-in intelligence for pre-defined
include deviation, modulation contents and identification. It
standards and Auto Standard Detection (ASD) allows an
is based on M standard.
easy setup of the demodulator and decoder part.
Other features of the DEMDEC are:
The control concept for the audio processor is based on
the following new features: • M/BTSC and N standards supported
• Pre-defined setups for the sound processing modes like • M/Japan (EIAJ) supported
Dolby® Pro Logic® and Virtual Dolby® Surround (422, • FM Radio stereo decoding
423) • Alignment-free, fully digital system
• Flexible configuration of audio outputs to the
• For BTSC full dbx® performance
loudspeaker configuration with an additional output
crossbar • SAP demodulation (without dbx®) simultaneously with
stereo decoding, or mono plus SAP with dbx®
• Master volume function
• Line/pilot frequency selectable from 15.734 kHz and
The control concept for the demodulator and decoder 15.625 kHz (or automatic detection / auto search)
(DEMDEC) is based on the following new features:
• High selectivity for pilot detection, high robustness
• Easy demodulator setup for all implemented standards against high-frequent audio components
with Demodulator and Decoder Easy Programming
• Pilot lock indicator
(DDEP) for a pre-selected standard or combined with
Auto Standard Detection (ASD) for automatic detection • SAP detector
of a transmitted standard • Separate noise detectors for stereo and SAP with
• Automatic decoder configuration and signal routing adjustable threshold levels, hysteresis, and automute
depending on the selected or detected standard function
• FM overmodulation adaptation option to avoid clipping An overview of the supported standards and sound
and distortion systems and their key parameters is given in the following
tables.
The analog multi-channel sound systems (A2, A2+ and
A2*) are sometimes also named 2CS (2 carrier systems).
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ANALOG 2-CARRIER SYSTEMS

Table 250 Frequency modulation
CARRIER FM DEVIATION MODULATION BANDWIDTH/
SOUND
STANDARD FREQUENCY (kHz) DE-EMPHASIS
SYSTEM SC1 SC2
(MHz) NOM./MAX./OVER (kHz/µs)
M mono 4.5 15/25/50 mono − 15/75
M A2+ 4.5/4.724 15/25/50 1⁄ (L + R) 1⁄ − R)
2 2(L 15/75 (Korea)
B/G A2 5.5/5.742 27/50/80 1⁄ (L + R) R 15/50
2
I mono 6.0 27/50/80 mono − 15/50
D/K (1) A2* 6.5/6.258 27/50/80 1⁄ (L + R) R 15/50
2
D/K (2) A2* 6.5/6.742 27/50/80 1⁄ (L + R) R 15/50
2
D/K (3) A2* 6.5/5.742 27/50/80 1⁄ (L + R) R 15/50
2
Table 251 Identification for A2 systems

PARAMETER A2/A2* A2+ (KOREA)
Pilot frequency 54.6875 kHz = 3.5 × line frequency 55.0699 kHz = 3.5 × line frequency
Stereo identification line frequency line frequency
frequency 117.5 Hz = ------------------------------------- 149.9 Hz = -------------------------------------
133 105
Dual identification frequency line frequency line frequency
274.1 Hz = ------------------------------------- 276.0 Hz = -------------------------------------
57 57
AM modulation depth 50% 50%
2-CARRIER SYSTEMS WITH NICAM

Table 252 NICAM standards
SC1
MODULATION
SC2
ROLL-OFF NICAM
STANDARD FREQUENCY DEVIATION (MHz) DE-EMPHASIS
TYPE INDEX (%) CODING
(MHz) (kHz) NICAM
(%)
NOM./MAX.
NOM./MAX.
/OVER
B/G 5.5 FM − 27/50/80 5.85 J17 40 note 1
I 6.0 FM − 27/50/80 6.552 J17 100 note 1
D/K 6.5 FM − 27/50/80 5.85 J17 40 note 1
L 6.5 AM 54/100 − 5.85 J17 40 note 1
Notes
1. See 'EBU specification' or equivalent specification.
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SATELLITE SYSTEMS
An important specification for satellite TV reception is the Astra specification. The TV Sound Processor is suited for the
reception of Astra and other satellite signals.
Table 253 FM satellite sound
CARRIER MAXIMUM BANDWIDTH/

MODULATION
CARRIER TYPE FREQUENCY FM DEVIATION MODULATION DE-EMPHASIS
INDEX
(MHz) (kHz) (kHz/µs)
Main 6.50(1) 0.26 85 mono 15/50(1)
Sub 7.02/7.20 0.15 50 m/st/d(2) 15/adaptive(3)
Notes
1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis
of 60 µs, or in accordance with J17, is available.
2. m/st/d = mono or stereo or dual language sound.
3. Adaptive de-emphasis = compatible to transmitter specification.
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BTSC/SAP, JAPAN (EIAJ) AND FM RADIO SYSTEMS

Table 254 Frequency modulation
CARRIER FM DEVIATION MODULATION BANDWIDTH/
SOUND
STANDARD FREQUENCY (kHz) DE-EMPHASIS
SYSTEM SC1
(MHz) NOM./MAX./OVER (kHz/µs)
M mono 4.5 15/25/50 mono 15/75
M BTSC 4.5 50 max MPX (FM/AM) 14/n.a.*
SAP 5fh=78,67kHz 15 max SAP (FM) 8/n.a.*
M Japan 4.5 15/25/50 MPX (FM/FM) 15/50
FM Radio stereo 4.5...10.7 40/75/150 MPX (FM/AM) 15/75 or 15/50
*: not applicable due to dbx® noise reduction
Table 255 Identification for BTSC/SAP, Japan (EIAJ) and FM Radio systems
PARAMETER PILOT TONE FREQUENCY
BTSC 1fh=15.734 kHz
Japan/(EIAJ) 3.5fh= 55,069 kHz
FM Radio 19kHz
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FUNCTIONAL DESCRIPTION SOUND PROCESSOR
The UOCIII TV Sound Concept

The UOCIII sound concept is implemented over the video processor and TCG-microcontroller.
Fig. 41 is showing this concept.
Only relevant blocks, functions and signal flows for sound are given. For details of the application see UOCIII application
notes.
analogue crossbar
AUDIO IN 5
-3dB
AUDIO IN 4 AUDOUT
-3dB S L,R
AUDIO IN 3 Audio DAC1 DAC1 3dB/
-3dB
ADC 9dB
AUDIO IN 2 PROC
-3dB
FMMONO/AM
Video- Dig.Controller AUX
3dB/
Dig. Output Crossbar

FM Digital audio
proc. part Input contr.
9dB
AUDOUT
part Cross- HP L,R
SIF bar
RF1 AM DEM
TUNER IN
DEC
SSIF SSIF SSIF
+ SAW LS DAC2 3dB/
QSS PROC 9dB
filters SW AGC ADC HW/
AUDOUT
or DSP
VIF VIF LS L,R
IN
I2S proc./interface
I2S I2S OUT

SSIF IN/out
I2SDI1/O I2SDO2 I2SDO1
(only relevant blocks, functions and signal flow for sound are shown)
Fig.41 UOCIII Sound Concept
The tuner receives a RF signal and converts it to IF. Via appropriate SAW filters the SIF signal is delivered to the QSS
stage of the video processor and if channels according to standard L/L’ are received also to the AM demodulator. The
Quasi Split Sound demodulation generates the SSIF or intercarrier signal. By the SSIF switch it is possible to choose
between the internally derived intercarrier and an external second SIF (2NDSIF EXT), e.g. an intercarrier coming from a
PIP frontend. In other applications a 10.7 MHz radio IF or satellite FM may be connected to this input. The selected SSIF
passes some anti alias filtering, is amplified in an AGC amplifier (SSIF AGC) and is then converted from analogue to
digital (SSIF ADC).
The audio signal out of the AM demodulator is connected to the analogue crossbar at the video processor. All other inputs
to this multiplexer/audio switch come from external, either from a PIP frontend or SCART/CINCH (AUD IN x) or the DAC
output signals from the digital controller. The audio AD converters are digitising the audio signals foreseen for further
digital processing. One stereo output (AUDOUT S) is available for connections to SCART/CINCH sockets.
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The sound part on the digital controller consists of the Functional Overview Of the digital controller sound
demodulator/decoder (DEMDEC), a digital input crossbar, part
the digital audio processing for the loudspeaker and DAC
The digital controller sound part consists of the SSIF ADC,
channels, the I2S processing and interfacing, a digital
audio ADCs, DEMDEC HW, the sound DSP core, audio
output crossbar as well as the DA conversion.
DACs and I2S interface hardware as shown in fig. 42. The
An auxiliary audio control (volume control, AUX audio DEMDEC part of the Sound DSP is used for the decoder
contr.) is available on the video processor. Here it is and partly demodulator tasks. The AUDIO part provides
applied to the headphone channel. the sound features, from the level adjust unit up to the
output crossbar. Audio DACs and I2S hardware are
The part of the concept located in the digital controller will
converting the processed signals to analogue or digital
be described in the next chapters.
audio.
Sound DSP
Dolby® Beeper
DAFO1
Audio Control
Pro Logic®
DEMDEC
Hardware
dig.
L/A BMT (L+R)/2
SSIF SSIF SSIF VDS DAC2
ADC OUTL
DAC2
DEMDEC
R/B Main Channel Processing

DAC2
MONO
SW Channel Processing OUTR
DAFO2
SAP
Centre Channel Processing
DAC1L
Surround Channel Processing
Digital Output Crossbar
Digital Input Crossbar
AUD A_ADC1 DAC1

ADC AUD OUTL
DAC1
IN ADC
A_ADC2 DAC1
OUTR
DAC1R
AUX1/I2S1 Channel Processing
Noise/
AUX2/I2S2 Channel Processing
Silence
Generator
AUX3/DAC1 Channel Processing

I2S I2S1L IN
I2S1 OUT
IN I2S
I2S
I2S2 OUT
proc
(*) Audio Monitor
I2S1R IN I2S3 OUT
(*)
(*) : connected to one pin that can be used alternatively as I2S IN or I2S3 OUT
Fig.42 Overview of the UOCIII Sound Functions on the digital controller
The SSIF signal is applied to the SSIF ADC for conversion The audio signals (AUD ADC IN) from the analogue
and is then fed to the DEMDEC hardware processing crossbar pass the audio ADC and are fed directly into the
mainly for demodulation but also some decoding tasks. AUDIO part of the Sound DSP like the I2S signals, which
Remaining decoding is done in the DEMDEC block of the is coming from I2S processing hardware. After level adjust
Sound DSP. The DEMDEC processing will be described in all signals from the DEMDEC and the I2S input are
the next chapter. available at the digital input crossbar. A special input is
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UOCIII series
provided for the Noise/Silence Generator needed for MIXER

Dolby® Pro Logic® processing.
The digitized 2nd SIF input signal is fed to the mixers,
The loudspeaker signal processing is performed in the which mix one or both input sound carriers down to zero IF.
main, SW (subwoofer), centre and surround channels The mixer frequency is derived by the standard setting
according to the signal type received. Channels AUX1 and (Easy Programming) or in the Demodulator and Decoder
AUX2 are provided for I2S signal processing and channel Expert Mode (DDXM) by a 24-bit control word for each
AUX3 is dedicated to DAC1 signal handling. carrier. For NICAM demodulation, a feedback signal is
added to the control word of the second carrier mixer to
All channel processing delivers signals to the digital output
establish a carrier-frequency loop.
crossbar, which offers the facility to connect each of the
channel signals to the appropriate DACs, or to the I2S
FM AND AM DEMODULATION
outputs.
An FM or AM input signal is fed via a band-limiting filter to
In standard TV applications the main channel signal (L, R)
a one of two demodulators that can be used for either FM
will be connected to the DAC2 for reproduction at the
or AM demodulation. Four filters with different bandwidth
speakers. With multichannel signals centre, surround or
are available. The output signal of the first demodulator
subwoofer channels may be passed to the I2S outputs
can be used for further demodulation of multiplex signals
where external DACs may be applied. By this it is possible
used in the BTSC, EIAJ and FM Radio standards.
to build Dolby Normal/Wide, Dolby Phantom Centre or
Dolby 3 Stereo set-ups and also a VDS423 application.
FM IDENTIFICATION
Details of the audio processing will be described in
The identification of the FM sound mode is performed by
following chapters.
AM synchronous demodulation of the pilot signal and
narrow-band detection of the identification frequencies.
Demodulator and decoder
The result is available via the control bus interface. A
INTRODUCTION selection can be made for three different modes that
represent different trade-offs between speed and reliability
The TV sound processor provides an easy-to-use
of identification. The mode is set by DDEP (for FM
programming interface and built-in intelligence for the
two-carrier standards) or via expert mode. DDEP also
demodulator and decoder part.
performs automatic FM de-matrix control in dependence
The sound demodulator is able to search for sound on the identification.
carriers and react to transmission mode changes
autonomously, without interaction of the micro controller FM/AM DECODING
software.
A high-pass filter suppresses DC offsets from the FM / AM
It is possible for a typical terrestrial TV application to set up demodulators due to carrier frequency offsets and
the entire demodulator with transmission of few control supplies the monitor/peak function with DC values and an
words. un-filtered signal, e.g. for the purpose of carrier detection.
The control interface still allows access to every detail, The audio bandwidth is approx. 15 kHz.
called demodulator expert mode, for special applications
The de-emphasis function offers fixed settings for the
such as satellite TV, more elaborated search algorithms
supported standards (50 µs, 60 µs, 75 µs and J17).
etc.
An adaptive de-emphasis is available for Wegener-Panda
The new TV Sound Processor Demodulator and
1 encoded programs.
Decoder Easy Programming (DDEP) interface provides
three possible approaches to setup the demodulator and A matrix performs the de-matrixing of the A2 stereo, dual
decoder parts: and mono signals to obtain the left (L) and right (R) or
• Auto Standard Detection (ASD) language A and B signals.
• Static Standard Selection (SSS)

FM PILOT CARRIER PRESENT DETECTOR
• Demodulator and Decoder Expert Mode (DDXM)
The TV Sound Processor provides FM A2 standard pilot
carrier detection.
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NICAM DEMODULATION or AM). When the error count is smaller than the lower
error limit the NICAM sound is restored.
The NICAM signal is transmitted via DQPSK modulation at
a bit rate of 728 kBit/s. The NICAM demodulator performs The auto-mute function can be disabled by setting bit
DQPSK demodulation and feeds the resulting bit stream NIC_AMUTE to 1. In this condition clicks become audible
and clock signal to the NICAM decoder. when the error count increases; the user will hear a signal
of degrading quality.
A timing loop controls the sample rate conversion circuitry
to lock the sampling rate to the symbol timing of the For NICAM L applications, it is recommended to
NICAM data. demodulate AM sound in the first sound IF. The
demodulated AM is provided by the internal IF processor.
NICAM DECODER For applications with external IF processing the external
demodulated AM signal can be connected to the
The NICAM decoder performs all decoding functions in
SCART/Mono input of the TV Sound Processor. By setting
accordance with the EBU NICAM 728 specification. After
the EXTAM bit, the auto-mute function will switch to the
locking to the frame alignment word, the data is de
audio ADC input signal named EXTAM instead of
scrambled by applying the defined pseudo-random binary
switching to the first sound carrier. The ADC source
sequence; the NICAM decoder will then synchronize to the
selector should be set to internal AM mono signal or to the
periodic frame flag bit C0.
external SCART/mono input, where the AM sound signal
The status of the NICAM decoder can be read out from the should be connected.
NICAM status register by the user (see the control-bus
register description). The OSB bit indicates that the BTSC STEREO DECODER
decoder has locked to the NICAM data. The VDSP bit
The FM demodulated composite signal is fed into the MPX
indicates that the decoder has locked to the NICAM data
demodulator for synchronous AM demodulation of the sub
and that the data is valid sound data. The C4 bit indicates
carrier. The demodulator includes a pilot detector and pilot
that the sound conveyed by the FM mono channel is
cancellation circuit. The main channel (baseband part,
identical to the sound conveyed by the NICAM channel.
encoded (L + R)/2) signal passes a 75 µs fixed
The error byte contains the number of sound sample
de-emphasis filter, while the compressed sub channel
errors, resulting from parity checking, that occurred in the
signal goes through the dbx decoder. Both signals are fed
past 128 ms period. The Bit Error Rate (BER) can be
to the stereo dematrix to obtain the L and R signals.
calculated using the following equation;
bit errors –5
BER = ----------------------- ≈ error byte × 1.74 × 10 SAP DEMODULATOR
total bits
During NICAM mode a switchable J17 de-emphasis is The composite signal is fed to the FM sub channel
supplied. demodulator and detector circuit. A noise detector can be
used to mute the SAP output in the event of insufficient
NICAM AUTO-MUTE signal conditions. The SAP identification signal can be
read by the control bus.
If the Auto Standard Detection (ASD) or the Static
Standard Detection (SSS) feature is activated the
dbx® DECODER
following auto mute function is in effect.
The circuit includes the noise reduction system in
If NICAM B/G, I, D/K is received, the auto-mute is enabled
accordance with the BTSC system specification and
and the signal quality becomes poor, the built-in control
conforms to the standard of quality defined by THAT
automatically switches the output signal (DEC output) to
Corporation
FM channel 1. The automatic switching depends on the
NICAM bit error rate. The auto-mute function can be
JAPAN (EIAJ) DECODER
disabled via the control bus.
The above mentioned FM sub channel demodulator,
This function is enabled by setting bit NIC_AMUTE to 0.
together with a matching low pass filter, is used to decode
Upper and lower error limits may be defined by writing
the EIAJ multiplex signal. The resulting main and sub
appropriate values to the corresponding control bits
channel signals then pass through the similar blocks as in
(NICLOERRLIM and NICUPERRLIM). When the number
FM A2 mode, that is DC notch filtering, fixed deemphasis
of errors in a 128 ms period exceeds the upper error limit
(75 µs) and dematrix.
the auto-mute function will switch the output sound from
NICAM to whatever sound is on the first sound carrier (FM
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UOCIII series
FM RADIO DEMODULATOR In ASD (Auto Standard Detection) mode, an automatic TV

sound standard and carrier search is performed at a
The above mentioned MPX demodulator can also be used
channel switch, following preferences determined by the
to decode a FM Radio input signal with a 19 kHz pilot tone.
user or the system controller, such that a standard
A freely selectable intermediate frequency (IF) between
detection and identification (stereo / dual) result is
4.5 and 10.7 MHz can be applied to the SIF input. Both the
obtained as fast as the hardware permits. If only the stereo
European and North American modes (pre-emphasis 75
system within a standard changes later, the search
µs and 50 µs, respectively) are supported.
procedure adapts (e.g. B/G A2 to B/G NICAM or vice
versa).
EASY PROGRAMMING
The SSS (Static Standard Selection) mode requires the
For a complete description of DDEP and application hints
user to select the sound standard (incl. stereo system) by
refer to the technical report HSIS/TR0107.
means of a standard code (e.g. code 4 denotes "B/G A2",
the European analog FM two-carrier standard) and no
Overview
searching is done. This mode is like a subset of the ASD
DEMDEC Easy Programming (short DDEP) is the name of mode in that it acts similarly as the ASD mode if the
the high-level control interface to the DEMDEC DSP of the standard detection has found the selected standard.
TV sound processor. Its main intention is to make the However, in SSS mode the decoder never changes to a
development of system control software for the DEMDEC different standard, and the user must supply settings that
as simple as possible, while optimally exploiting the ASD selects by its own expertise (IDENT speed for A2
available hardware and DSP resources. standards and line frequency for BTSC). The SSS mode
can be used to enforce a certain sound standard in case
The functionality of DDEP is divided into three main areas:
ASD was unable to find a sound carrier and is needed to
1. Demodulator and decoder configuration with optional select FM Radio decoding. The ASD routines operate as if
standard and second carrier / subcarrier search; using the SSS mode to select a certain standard.
2. Decoding, signal routing and switching for simple In both of these modes, the DDEP system handles the
handling of broadcast sound signal types, plus other signal processing and settings automatically without
encoding of the main status register;
a need for further interaction, and also allows the same
3. FM overmodulation adaptation: optional adaptive options:
reduction of levels and filter widening in case of
1. It is possible not to use the default NICAM
overmodulation, in order to avoid distortions due to configuration for a detected or selected standard, but
clipping or overflow.
supply other settings via the NICAM configuration
The DDEP software controls both the demodulator register.
hardware and the real-time signal processing software 2. The default thresholds and hysteresis sizes for
running on the same DSP, e.g. by changing filter noise-based automute and SAP detection can be
coefficients, pointers etc., often depending on status overruled.
information generated by hardware or software.
3. The optional overmodulation adaptation may be used
Most functions act like "background processes": small in ASD as well as in SSS mode.
code sections are executed at a reduced rate (for instance 4. A pre-scaling of the EXTAM signal is usually needed
every 32th sample at 32 kHz = 1000 times per second), in to obtain a correct level.
order to accommodate a large amount of program code
5. As NICAM sound often seems softer than the FM
without consuming too much of the available processing
sound, an additional level adjust for this signal path is
power of the DSP. A "control timeslot" is reserved in the
possible.
DSP software in which both control register decoding and
background processing is performed. 6. Levels of the DEMDEC output signals may be
changed individually if a level other than the nominal
DDEP in short -15 dBFS (with nominal modulation degrees) is
desired, all signal levels can be adjusted before the
DDEP can operate in one of two modes, which differ only
first digital crossbar.
in the type of standard handling. Additionally, a few options
are available to the user.
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UOCIII series
DDEP can be switched off completely, allowing user Note that DDEP does not include handling the SIF
access to all low-level settings. All automatism are then frontend (input selection, AGC etc.) since this is
disabled. This so called "DEMDEC expert mode" ("manual application dependent.
mode") requires detailed knowledge and understanding of
Fig.43 sketches the handling of the two different control
the involved hardware and software and will be explained
register sets for DDEP and expert mode and their
in a later report. A satellite TV application unfortunately
translation into software and hardware settings.
requires the expert mode since satellite sound is not
supported by DDEP. As usual for this application, all All central DDEP functions are controlled by writing a
configurations like carrier frequencies and deemphasis single register, the DDEPR register is located in the XRAM
types must be supplied by the set user or have to be (data memory) of the DSP and accessible via the PI bus
pre-programmed. interface (I2C).
DDEP control expert mode

registers control registers
ASD search Overmod.

SSS mode
procedures Adaptation
(export mode only)
standard
dependent
low-level control routines, internal variables, hardware registers
(pointers, coefficients etc.) (detectors)
real time signal processing software
Fig.43 Control Flow
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DEMDEC hardware blocks The dedicated demodulator and decoder hardware

delivers "raw" signals that cannot be used without further
Due to the high bandwidth and computational
processing in the DEMDEC realtime software. Each signal
requirements, the actual demodulation of the sound
comes in with a sample rate of n*32 kHz.
carrier(s) is implemented in dedicated digital hardware.
These are Sample rate for the audio processing and DEMDEC is 32
1. a SSIF frontend with AGC and high-speed ADC; kHz.
2. two FM / AM demodulator channels with Figure 44 shows the described hardware blocks and their
programmable mixer frequencies and four different connection to the DSP. The hardware is usually controlled
filter bandwidths; by the DDEP software, or by the controller via the expert
mode.
3. a NICAM demodulator and decoder for all NICAM
standards;
4. an identification circuit for all standards;
5. an additional "BSJ" ("BTSC, SAP, Japan") block
provides MPX demodulation (for BTSC and FM
Radio), FM subchannel demodulation plus matching
filter (for SAP and the Japanese EIAJ standard), and a
noise detector.
analog
SSIF
FM / AM
mixer decimation
AGC A/D ch. 1 filters
demodulator
#1
MPX 4 fs
(24.576 MHz)
demodulator
clock noise
generation detector
EIAJ lowpass
FM
2 fs EPICS7A
FM sub
channel DSP
demodulator AM Input
Regis-
BSJ block ters (DIO)
FM / AM
mixer decimation
demodulator
ch. 2 filters
#2
FM
Identification
(Europe / Korea /
Japan)
NICAM
demod. &
control signal for decoder
carrier tracking 1 fs
clock
control
Fig.44 Demodulator & Decoder Block Diagram
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Signal processing in DSP software By means of this signal routing, the processing paths in the
audio backend do not need to select a specific source
The output signals of the above-mentioned hardware
depending on the currently activesound standard as it was
blocks (next to signal from other sources like ADC or I2S)
required on earlier Philips stereo decoders (FM/AM,
read in by the DSP, processed, decoded, and forwarded to
NICAM source). For every audio processing path, the
the digital input crossbar for further processing (volume,
controller can select the DEC, MONO etc. output like any
tone control, effects etc.). Fig.45 shows this signal flow in
other signal source (ADC, I2S input,..). The information
a simplified structure.
about the signal type (mono, stereo, dual) on the DEC
The signals from the analogue sound carriers are passing channels is available by two status bits. This also allows
through several filters like down-sampling and the audio backend to implement a “smart matrix” which
deemphasis, noise reduction processing (Wegener-Panda selects one of the two languages in dual mode, or stereo
/ dbx® expanders), and dematrixing. For the NICAM signal in other cases.
only a J17 deemphasis is needed. The decoded signals
The MONO output can be selected in case that stereo/dual
are available at the DEMDEC outputs (identical to inputs
is not wanted, which a two-channel output to another
of the digital input crossbar). The first (topmost) pair of
destination is still possible. A special case is a NICAM
output channels, called DEC (from DECoder), is intended
transmission with independent contents of analogue and
to carry the stereo or bilingual (dual) signal; an extra
NICAM sound carriers (indicated by status flag RSSF=0)
“MONO” channel always contains the mono signal from
when the mono channel carries a different signal than the
the first sound carrier (always FM or AM), or the main
NICAM channels.
channel (baseband, [L+R]/2) of the MPX typestandards
BTSC, FM Radio and EIAJ. (This channel may contain Internal scalings are applied in DDEP mode such that all
different audio contents in case of NICAM.) Another signal outputs signals have a level of -15 dBFS for nominal
channel named “SAP” transports a SAP signal if detected modulation degrees (e.g. 54% full scale sine wave = 27
during a BTSC reception. An “external AM” signal should kHz FM deviation of a B/G FM carrier). Additional level
be used for standard L since the “internal” digital AM adjustments can be performed at the digital crossbar in the
demodulator does usually not achieve the S/N audio DSP. In export mode, the internal scalings, switches
performance of an analogue demodulator operating on the etc. must be controlled via the expert mode registers.
first sound IF. This signal may be available via an ADC
input. If standard L is active, DDEP can feed this signal to
the MONO output of the DEMDEC (and to the DEC as well
if no NICAM is detected), or alternatively use the internal
AM demodulator output.
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UOCIII series
MONOSEL
4x lowpass, lowpass, DC notch, output level
ADC (L)
DIO dec. by 2 dec. by 2 deemph. adjust
ch. 1
scaling
ch. 2 DECPATH
4x lowpass, lowpass, DC notch, MONO
DIO dec. by 2 dec. by 2 deemph.
FM / AM / BTSC FM
dematrix
lowpass, 75 s lowpass, DC
dec. by 2 deem. dec. by 2 notch
lowpass, lowpass, DC
dec. by 2 dec. by 2 notch
dbx® DECSEL
EIAJ main
decimation DEC
2x DC notch,
DIO
by 2 &
deemph.
equalizer
decimation
2x DC notch,
DIO
by 2 &
deemph.
equalizer
FM subch. compromise
lowpass
ordbx®
SAP
DIO
NICAM (J17)
deemphasis
DIO
NICAM
Fig.45 Signal processing modules
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UOCIII series
Audio Processor
The functional overview of Audio part of the Sound DSP is shown in Fig.46
IIS IN
Level adj.
ADC (L, R)
DEC (L,R from DEMDEC)
MONO (from DEMDEC)
(L+R)/2
SAP (from DEMDEC )
L,R
L,R Trim
L,R M/ST EPS or MAIN L,R
EcoSUB
AVL
DVB or DBB in L,R or SUB

Main
Master Volume
ESS or
Ba/Tr SM +
MAIN MSel
3D Sound® Eql DAFO1

MAIN
L,R DPL
Loudn DAFO2
VDS423/422 ®
Bass Management
DPL ® L,R
or
Ps. Hall MAIN
C,S /Matrix BBE®
®
Beeper to DAC2
TruSurround ®
L,R
SUB
Digital Input Crossbar ( SSel, Matrix )
C,S
(L+R)/2
423,422
Digital Output Crossbar

(L-R)/2
C
DPL,423 SUB
Passiv
S SM
e
Matrix
DPL SUB
C
C IN C C C C
Ba/Tr
C
MSel Eql SM
C Loudn
S
S Delay
S IN S S S
S
MSel S Ba/Tr SM I2S1L,R

OUT
Noise/ I2S2L,R
Silence
Silence OUT
Gen.
AUX1,2 AUX1,2 AUX1,2
AUX3 AUX1,2
Vol/Trim SM
2 equal channels for I2S
AUX3 AUX3 AUX3 DAC1

Vol/Trim SM L,R
® ®
DPL , VDS are trademarks of Dolby Labs
Audio Monitor BBE ® or DBB or DVB can be used ® ®
TruSurround , 3D Sound are trademarks of SRS
Labs
BBE ® is a trademark of BBE Sound Inc.
Fig.46 Audio Backend Operation of UOCIII (DSP functions)
The processing of the loudspeaker channels (MAIN, SW, The Noise/Silence Generator is a special source. It is
C, S), the auxiliary channels AUX1 to AUX3 is nested needed as noise source for Dolby® Pro Logic® speaker
between the digital input crossbar and the digital output trim compliant to the Dolby requirements for a noise
crossbar. sequencer
Inputs to the digital input crossbar are the sources The digital input crossbar provides source select and
matrixing for the channels MAIN (L, R), AUX1 to AUX3, but
- DEC, with the four lines L/A, R/B, Mono, SAP,
only source select for centre (C), surround (S) because
- A_ADC 1,2, with L/A, R/B coming from the audio ADC, these are mono channels.
- I2S 1 IN, from the I2S input. Although the selectors are all of the same type not all
facilities will be used in normal applications of UOCIII. E.g.
All these signals pass the level adjust before entering the
the output of the centre and surround selectors can be
crossbar. That adjust is needed to level the source signals
permanently connected to the Noise/Silence Generator.
if they deviate from nominal setting.
The AUX channels need not to be switched to
Noise/Silence.
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Setting of the digital matrix depends on the type of input functions provided can be used according to these signal
signal. The type may be known from the identification in types. Some of them are dedicated to specific modes
the demodulator/decoder as stereo, dual language or leading to constraints. The AVL and Pseudo Hall/Matrix
mono. So the switching can be made dependent from the ((L+R)/2, (L-R)/2) can only be used with stereo or mono
identification. For dual language the preference for signals, VDS only with DPL decoded signals. Extended
language A or B can be set when automatrix is selected. Pseudo Stereo (EPS) or Extended Spatial Stereo (ESS)
In this case the matrix provides the language according to can be selected, but for DPL it has to be switched off to
the preference selected by the end-user. meet the Dolby requirements. Other selections depend on
the speaker system, whether the set is equipped with 5
If an external audio source (ADC, I2S) is chosen the signal
speakers (L, R, SW, C, S) (only possible when external
type is unknown or can only be seen from the label of a
DACs are applied) from which all are used or maybe the
tape etc. Thus the end-user needs to get a selection facility
surround speaker is disconnected or with just 2 speakers
in this case. It should include the choice between
(L, R). Also important is the speaker size/bandwidth.
stereo/dual language (AB), mono (from stereo by (A+B)/2,
also called forced mono), sound A or B and a swap (BA) Some of the functions are set by SNDMODE according to
for stereo if the source has interchanged L and R. the Sound Mode Table. The rest needs to be controlled by
individual settings.
The processing channels are dedicated to loudspeakers
(MAIN, SW, C, S), to I2S OUT (AUX1, AUX2) or DAC1
SOUND MODES OF THE LOUDSPEAKER CHANNELS
(AUX3). AUX1 to AUX3 offer only volume and balance
control (Vol/Bal) and softmute (SM). Appropriate sound modes are defined in the table 256:
In the loudspeaker channels we can process mono,
normal stereo or Dolby® Pro Logic® encoded signals. The
Table 256 Sound Mode Table
Sound Mode FUNCTION

M/ST - Mono/Stereo in case of mono or stereo source signals
M/ST Hall - Mono/Stereo with pseudo Hall in case of mono or stereo source signals
M/ST Matrix - Mono/Stereo with pseudo Matrix in case of mono or stereo source signals
DPL N/W (normal centre) - DPL normal/wide in case of DPL decoded source signals
DPL PH (phantom centre) - DPL Phantom Centre in case of DPL decoded source signals
DPL 3ST (3 stereo) - DPL 3 Stereo in case of DPL decoded source signals
VDS423 - DPL+VDS(423) in case of Virtual Dolby® Surround 423
VDS422 - DPL+VDS(422) in case of Virtual Dolby® Surround 422
SRS® TruSurround - Passive matrix + TruSurround virtualizer (422)
DPL NSEQ - DPL speaker level Trim (noise sequencing)
The Sound Mode sets explicitly the functions AVL, DPL, VDS, Main MSel, C MSel, S MSel, Pseudo Hall/Matrix and it
provides a specific setting for noise sequencing.
The table 257 shows the setting of these functions for the loudspeaker channels by Sound Mode control. All other
functions have to be set by direct control via the related registers and bits.
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Table 257 Sound Mode Settings

SETTING BY SOUND MODE OF FUNCTIONS
SOUND NOISE PSEUDO
MODE VIRTUALI MSEL. MSEL. MSEL.
AVL DPL /SILENCE HALL
ZER MAIN CENTRE SURROUND
GEN. /MATRIX
M/ST active not active active not active connected to not active connected to connected to
L,R M/ST CIN SIN
(note 1) (note 2)
M/ST Hall active not active not active not active connected to Pseudo connected to connected to
Hall active
L,R M/ST (L+R)/2 (L+R)/2
(note 1)
M/ST active not active not active not active connected to Pseudo connected to connected to
Matrix Matrix
L,R M/ST (L+R)/2 (L-R)/2
active
(note 1)
DPL N/W not active DPL N/W not active not active connected to not active connected to connected to
(normal
L,R DPL CDPL,423 SDPL
centre)
DPL PH not active DPL PH not active not active connected to not active connected to connected to
(phantom
centre)
(silence)
(note 3)
DPL 3ST not active DPL 3ST not active not active connected to not active connected to connected to
(3 stereo)
(silence)
VDS423 not active DPL N/W not active VDS423 connected to not active connected to connected to
L,R 423,422 CDPL,423 SDPL
(silence)
VDS422 not active DPL N/W not active VDS422 connected to not active connected to connected to
(silence) (silence)
SRS® not active not active not active TruSurrou connected to not active connected to connected to
TruSur- nd (422)
round
(silence) (silence)
DPL NSEQ not active not active active not active connected to not active connected to connected to
L,R M/ST CIN SIN
Notes
1. AVL active means that the set maker can use all facilities by direct control via related registers and bits
2. the noise/silence generator is active, MSel Centre is connected to CIN and MSel Surround is connected to SIN to
give the set maker the facility to build a noise sequencer application of his choice with the M/ST sound mode.
3. (silence) means that the signal carries silence, no audio or noise.
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DESCRIPTION OF THE FUNCTIONS Noise Sequencer for DPL

Level Adjust The set maker has to provide a program to build a Noise
Sequencer with the components available in the UOCIII.
Level adjust in a range from +15dB to –15dB is provided
The procedure is described in the Dolby Licensee
for input signals from the demodulator/decoder (DEC),
Information Manual: Dolby® Surround Pro Logic®, issue
ADC and I2S. A step of –16 is defined as mute.
6. All channels L, C, R, S (only possible when external
DACs are applied) can be connected to the noise source
Digital Input Crossbar
of the noise/silence generator and by use of the soft-mute
The digital input crossbar can connect any input with every (SM) the noise can be cycled. It is recommended to mute
output channel for source selection. It also includes a the sub-woofer output, while the noise sequence is active.
digital matrix for each stereo output. For input signals A
and B this matrix can provide at the output AA, AB, BA, BB, Virtual Dolby® Surround
(A+B)/2 and (A-B)/2. The specific modes Auto Language
Virtual Dolby® Surround gives a surround sound
A and Auto Language B take care that either language A
impression with use of only two speakers (VDS422) or
or B is selected automatically when dual language is
three speakers (VDS423, only possible when external
detected by the TV sound processor.
DACs are applied). Input to VDS are the L, R, C and S
outputs of the DPL decoder. The surround signal S is
AVL
virtualised and redirected in both cases to the left and right
The AVL reduces the audio input signal in the MAIN channel whereas the centre signal is redirected to L, R
channel (L, R) to a selectable maximum output level if it only when VDS422 is selected. In VDS423 a centre
exceeds this level at the input of the stage. channel is provided.
A detector creates the control signal from L and R. The The intensity of the effect can be controlled.
AVL provides a short attack time and decay times of 20ms,
2s, 4s, 8s and 16s. A weighting filter can be chosen in the SRS® TruSurround
control signal generation. The advantage is that bass
TruSurround is a virtualizer giving a surround sound effect
signals and high frequency components have less impact
with only two speakers (422). It can be used alternatively
on control.
to VDS. TruSurround makes use of a passive matrix which
delivers internally L, R, C and S signals. The virtualizer
The Dolby® Pro Logic® Function (DPL)
then generates a new L, R stereo signal from it to achieve
The Dolby® Pro Logic® Decoder is compliant to the a surround sound effect.
Dolby® Licensee Information Manual: Dolby® Surround
Pro Logic®, Issue 6. Pseudo Hall/Matrix
If the MAIN channel signal L, R is Dolby encoded the Because Dolby® Pro Logic® encoded signals are
decoder can generate appropriate L, R, C and S signals. transmitted not very often a Pseudo Hall and Pseudo
Matrix function is provided.
Auto Balance is always provided. The selection of DPL
normal/wide, Phantom Centre, 3 Stereo delivers output In case of Pseudo Hall the sum signal (L+R)/2 is passed to
signals according to the Dolby requirements. Outputs not the centre and to the surround channel whereas for
used in a specific mode carry digital Silence ‘—‘. Pseudo Matrix the centre channel carries (L+R)/2 and the
surround channel (L-R)/2. The surround signal is delayed
Surround delay is adjustable between 15ms and 30ms.
by 30ms in both cases.
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I-Mono or Extended Pseudo Stereo (EPS) At high volume the resulting loudness curve is flat,
because there is no need to boost high and low
The Incredible Mono module (I-Mono) generates two
frequencies at high sound pressure level. The loudness
channels from one mono input signal. When the sound of
boost becomes active, if the input volume is reduced below
the mono input signal is processed, the listener gets the
the (adjustable) no attack threshold. The resulting gain
impression that the sound is essentially a stereo signal.
depends on the actual input volume level. Within a range
The pseudo stereo effect is adjustable. Additionally the
of 30dB below the no attack threshold the loudness
user can switch this function ON or OFF.
function gives an increasing boost of low and high
frequencies. If the input volume is reduced more than
I-Stereo or Extended Spatial Stereo (ESS)
30dB below the no attack threshold level then the
The I-Stereo module is a Stereo Expander. The listener maximum loudness gain is reached and the loudness
gets the impression of a sound reproduced by two virtual curve for 30dB remains active. The maximum loudness
speakers, positioned at a larger distance between each gain is +18dB at 20 Hz and + 4.5dB at 16 kHz.
other than between the actual speakers. So, the stereo
The frequency where gain is not affected by the loudness
image is expanded by this widening sound effect.
function is called no attack frequency. This no attack
The stereo widening effect is adjustable. Additionally this frequency can be adjusted to 500 Hz or 1 kHz. This results
feature can be switched ON or OFF. in different loudness curves, but the maximum gain at 20
Hz and 16 kHz remains the same.
SRS® 3D Stereo
Loudness is applied in the L, R and C channels.
3D Stereo retrieves the spatial information from any stereo
signal. It produces a larger sweet spot. A centre control BBE®
and a space control is provided.
The BBE® sound process offers 2 primary functions. First
it compensates the time delay over frequency of the
Bass/Treble
loudspeaker. Secondly it provides a dynamic, program
Bass and treble functions are implemented in all four main driven augmentation at the high and low frequency range.
signal paths (L, R, C, S). The user is able to attenuate or Together it restores the transients of the studio signals.
boost the bass and high frequency signals independently This improves the brilliance and clarity of sound. When
within a range of -16dB to +15dB. The external resolution BBE® is selected either DUB or DBE function is disabled.
(under user control) is defined to 1dB steps, whereas the
internal resolution (not under user control, 1/32dB steps) is Bass-ManagemenT (BMT)
used to avoid ‘pop noise’. The internally used 1/32dB per
Every DPL sound IC, which has to be licensed by Dolby
step leads to a maximum speed of amplitude change,
Laboratories, must include a Bass ManagemenT (BMT,
which is defined to 15.625dB/s. The corner frequency of
also called bass redirection). The UOCIII (TDA120xxH)
the bass function is fixed to 40 Hz and for the treble
bass redirection fulfils the different configuration modes
function fixed to 12 kHz.
required by Dolby Laboratories.
Loudness In general the bass redirection is used to redirect the low
frequency components of the audio signal to loudspeakers
The human ear listening curves (Fletcher-Munson
which are able to cope with such power-full low signals
loudness contours) show, that the ears of a human are
(large speakers). In audio equipment all speakers may be
less sensitive for low and high frequencies at low sound
large, but in TV sets either the L and R speakers are large
pressure level (volume level). In general a loudness
or a sub-woofer is applied. Thus a bass redirection can be
function can be used to compensate the human ear
done to the L and R large speakers or to the sub-woofer.
sensitivity loss at low volume levels.
The low frequency components are cut out of the audio
Within a volume range of 30dB the loudness gain varies signals, which are directed to satellite loudspeakers (small
with the total gain value of the volume stage. The loudness speakers); on the other hand, the high frequency
curves are automatically adjusted to the volume level, components are cut out of the audio signals, which are
where the allowed input volume steps can be 1/8dB or redirected to the sub-woofer.
even smaller to avoid step-noise.
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The corner frequency of the high and complementary low BMT2 is equivalent to the bass management described as
pass filters can be selected, to allow specific adjustments configuration 2 (see Dolby® Digital Specification Issue 3,
with respect to the used TV set loudspeakers. The corner Figure 4-22 Configuration 2). The BMT2 mode is used to
frequency of the LP / HP- filters is adjustable within a range redirect the low frequency components of the centre
from 50 Hz to 400 Hz. There are 16 different corner channel to the full-range main loudspeakers (large left and
frequencies to choose from: 50Hz, 60Hz, 70Hz, 80Hz, right speakers). Additionally a separate sub-woofer
90Hz, 100Hz, 110Hz, 120Hz, 130Hz, 140Hz, 150Hz, loudspeaker can be used in this configuration. Like in
200Hz, 250Hz, 300Hz, 350Hz and 400Hz. BMT1 mode the surround channel is not redirected if
UOCIII is used in non-Dolby stereo in the pseudo hall
The bass redirection (BMT) covers three different
(M/ST Hall) or pseudo matrix mode (M/ST Matrix), then
configuration modes:
also the surround channel is filtered and redirected.
As the bass redirection stage will be also used in other
The BMTOFF mode is used if no redirection of the low
applications including Dolby® Digital the Dolby® Digital
frequency components is needed, in case of all three front
implementation of BMT is used within UOCIII as a basis.
loudspeakers (left, right and centre) are large
BMT1 covers the bass management described as loudspeakers.
configuration 1 (see Dolby® Digital Specification Issue 3,
There is an option to switch off the low path filter, which is
Figure 4-21 Configuration 1). The BMT1 mode is used to
located in the sub-woofer output path. This non-processed
redirect the low frequency components of all three front
sub-woofer mode can be used with BMT1 and BMT2, and
channels (left, right and centre) to a separate sub-woofer
gives the possibility to use an external sub-woofer filter.
loudspeaker. As mentioned within the Dolby specification
for Dolby® Pro Logic®, the surround channel is not As recommended by Dolby Laboratories, the UOCIII
redirected. This can be done because surround is already always uses the HP-filter located in the surround channel
frequency band limited from 200 Hz to 7 kHz. If UOCIII is when DPL is active.
used in non-Dolby stereo in the pseudo hall (M/ST Hall) or
The figure 47 gives a general overview about the UOCIII
pseudo matrix mode (M/ST Matrix), then also the surround
bass redirection (BMT).
channel is filtered and redirected.
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BMT1, single woofer system with improved

filtering : small speakers for L, R, C, S; extra SW(subwoofer)
BMT2 , normal center mode with bass splitter (DPL) : large speakers for L, R; small speaker C, S ; SW optional
BMOFF , wide center mode (DPL) : large speakers for L, R, C ; small speaker S
BMT1 BMT2 BMOFF
gain/dB
L b1 L’
a1 -10 -100 -100
a1 a2 -10 -100 -100
a3 -10 -4.5 -100
a4 -10 -4.5 -100
R b2 R’ a4* -100 -100 -100
a2
C b3 C’
S1 b a b
a3 S2 a b a
-10dB
S b4 S’ filter
a4 HP flat flat
b1
b2 HP flat flat
LP b3 HP HP flat
b b4 HP HP flat
S1 b
a 1)
S2 LP SW’ *) If DPL is active a4* is used.
a 1) LP filter can be switched flat, to allow
the use of external sub-woofer filtering.
Overview of the Hercules Bass-Redirection
Fig.47 Overview of the UOCIII Bass-Redirection
Equaliser The acoustical behaviour of this feature has to be tuned to

the TV internal loudspeaker set. Therefore a certain set of
A graphic equaliser is implemented in the L, R and C
filter coefficients has to be found for each used TV set.
channel. It provides five bands at 100, 300 1000, 3000 and
This is done by use of the loudspeaker characteristics as
8000 Hz. For every band the gain is adjustable from -12 dB
well as by listening tests. This coefficient set has to be
to +12 dB in steps of 1 dB.
loaded into the UOCIII once after power on reset. A method
to calculate the coefficients will be available.
Dynamic Ultra Bass ™(DUB) or Dynamic Bass Boost
(DBB) DUB is normally applied to the left and right speakers.
Alternatively it can be provided with different coefficients to
In general the DUB function is used in TV-Sets with small
the sub-woofer signal to enhance the bass reproduction.
speakers that cannot reproduce deep bass signals. The
When using DUB it is not possible to apply DBE or BBE®.
effect is caused by producing harmonics of the low
frequency content. It gives the impression of deep bass
Dynamic Bass Enhancement (DBE) or Dynamic Virtual
reproduction although the fundamentals are missing. The
Bass (DVB)
level of harmonics added to the original signal is made
dependent from the total signal level at the output. This The DBE function is used in TV-sets equipped with large
dynamic behaviour allows a strong amplification of the speakers or sub-woofer system. This feature produces a
harmonics for small volume signals, but only small level depending bass boost. The dynamic behaviour
amplification for high volume signals. Maximum gain and allows a strong bass amplification for small volume
the target output level could be set. signals, but only small bass amplification for high volume
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signals. Q-factor of the boosting filter, maximum gain and input signal of the stage is multiplied with zero. So the
the target output level can be set. output carries digital silence.
This function has to be tuned to the speakers used within Each channel has an independent soft mute stage.
a certain TV-set. The coefficients for the filters as well as Additionally a MAINMUTE is available that provides a
the parameters for the bass boost control have to be common mute of the left and right signal of the main
stored into the UOCIII once after power on reset. A method channel. It overrules when it is activated the MAINLMUTE
to find the best coefficients and parameters for a certain and MAINRMUTE settings.
TV-set will be available.
Beeper
DBE is applied to the left and right speakers or
alternatively with different coefficients to the sub-woofer. The beeper is a sine wave generator for frequencies from
When using DBE it is not possible to provide DUB or 200Hz to 12.5kHz at a sample rate of 32kHz. The level can
BBE®. be set between 0dBFS and –83dBFS. A Mute/off step is
available. The signal is mixed into the left and right
EcoSUB (Economic Subwoofer Mode) channels for the main loudspeakers.
EcoSUB (Economic Subwoofer Mode) allows to drive a If the beeper is not used it needs to be set to the Mute/off
subwoofer without an additional power amplifier. The state.
subwoofer signal will be added differentially to MAIN L, R.
By the use of some passive filter components the Mono Signal (L+R)/2
subwoofer can be driven differentially by the MAIN L, R
The L and R signals of the MAIN channel are added at the
power amplifier. This mode should be combined with the
end of the channel giving (L+R)/2. This signal can be
Bass Redirection in Configuration 1.
provided to outputs for specific applications.
Master Volume and Trim
Audio Monitor
Master volume control is applied to all speaker channels in
The audio monitor is able to monitor the level of the sum
a range from 24dB to –83dB gain. Step width is 1/8 dB. A
(A+B)/2, the left or right signal of all input channels of the
mute step is available. Trim can be set in 1dB steps with
digital input crossbar. A special setting is the (A-B)/2 mode
internal resolution (not under user control) of 1/8 dB. The
in the digital matrix that offers the possibility to identify a
range is the same as for volume control. Maximum speed
signal as a mono or stereo signal. Additionally a variety of
of change is 62.5dB/s.
test points in the DEMDEC and audio processing are
The three-stage gain element per channel is controlled via selectable.
the common master volume register and the respective
The audio monitor provides three different modes:
trim registers. The requested gain values are added
internally. Total gain is limited to +24dB. • Last sample: in this mode the level of the last sample
from the selected input is stored in the monitor register,
Volume and Balance • Peak detection: in this mode the peak level after the last
Stereo channels have separate gain elements in the left read command is stored in the monitor register,
and right branch. In the MAIN channel the L, R trims are • Quasi peak detection: a quasi peak detector with an
used. Shift to the right is done by attenuation of the L trim, attack time of 4ms and a decay time of 1s is applied.
shift to the left by attenuation of the R trim.
If the monitor is used for mono/stereo detection the quasi
In the AUX channels the same is performed by use of peak mode should be selected.
volume left and right.
The read transfer rate via control bus is limited to about
This needs to be programmed by the set maker. 15kHz.
Soft Mute Digital Output Crossbar

When soft mute is activated/disabled the gain is The digital output crossbar provides 10 selectors ‘one out
reduced/increased any 2ms by one of totally 32 steps of 12’. That means each of the outputs e.g. DAFO1 or
according to a cosine function. Thus it takes 64ms from I2S1L can be connected to each of the inputs e.g. MAIN L
maximum gain to mute or vice versa. When muted the or C etc. By this the setmaker is free to assign the outputs
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DAFO1 to DAFO2 and I2S1L, I2S1R, I2S2L, I2S2R to any "Static Volume Mode" - In this mode the master volume +
of the L, R, SW, C, S speakers or other destinations trim gain is limited to a maximum gain of -30dB. The trim
according to his specific application. and the volume/balance in the Aux1-3 are not affected.
The channels AUX1 to AUX2 may be connected to the I2S "Static Control Mode" - In this mode the bass, treble and
outputs. Channel AUX3 normally has to be passed to equaliser gain is limited to a maximum of +8dB. The
output DAC1. Each output can also be connected to a Volume plus Trim setting is limited to -1dB.
silence signal from the NOISE/SILENCE Generator.
"Dynamic Control Mode" - In this mode the master volume
and trim gain is limited to +3dB. If the master volume plus
Auxiliary Channels
trim setting exceeds -12dB the bass and treble are
The channels AUX1 to AUX3 have volume/balance reduced until the sum of amplification of bass and treble
processing and soft mute and can be assigned to outputs plus master volume and trim is less then +3dB. If master
I2S1, I2S2 or DAC1 respectively. volume and trim is in the controlrange between -12dB and
+3dB every 1dB more master volume plus trim results in
Clip Management 1dB less bass and treble.
The clip management is a feature that should prevent "Dynamic Volume Mode" - In the dynamic volume mode
automatically internal clipping. Internal clipping can take the main left and right signal is measured. If the internal
place if in combination bass, treble or equaliser settings signal exceeds a limit of -3dBFS for a longer time, the
introduce large amplification of the signal. To prevent master volume is reduced automatically until the
clipping different strategic ways are possible. Therefore 4 measured signal is lower -3dBFS.
different modes are defined.
Table 258 Clip Management

CLIP MANAGEMENT MODE MASTER VOLUME + TRIM BASS TREBLE LOUDNESS
Static Volume Mode limited to -30dB not affected not affected not affected
Static Control Mode limited to -1dB limited to +8dB limited to +8dB none attack level 0dB
Dynamic Control Mode limited to +3dB see Fig. 48 none attack level 0dB
Dynamic Volume Mode Reduced / limited until the signal not affected not affected none attack level 0dB
is smaller or equal -3dBFS
Bass/Treble
active
-12dB Master Volume
+15dB +Trim
-7dB Master Volume

+10dB +Trim
-2dB Master Volume

+5dB +Trim
+3dB Master Volume

0dB +Trim
-16dB
Bass/Treble
-16dB 0dB +15dB
selected
Hercules Clip Management/ Dynamic Control Mode
Fig.48 Clip management / Dynamic Control Mode
Power On / Reset Condition of the Sound DSP

After a power on or reset all DSP-RAM cells will be cleared. Afterwards all module defined memory spaces will be initialised
and the Control-Register values will be set to the default value. This value is called 'Default@INIT' in the control table.
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ANALOG AUDIO PROCESSING The following is only applicable for Japanese LSB justified
formats:
Audio DAC
The input circuitry is limited in handling the number of
The TV Sound Processor contains four single DACs. Each SCK pulses per WS level. The maximum allowed
of the low-noise high-dynamic range DACs consists of a number of bitclocks per WS is 64(per mono audio word
switched resistor architecture with interpolation filter and 32 bitclocks). Also the number of bitclocks during the low
noise shaper at the input that runs at an oversampling and high phase of WS must be equal or more than the
frequency of 128fs. The outputs are fed into the selected format (24 bits).
videoprocessor.
When the output is enabled, the serial audio data can be
Audio ADC taken from pin SDO. Depending on the signal source,
TV Sound Processor contains two single audio ADCs. This switch and matrix positions, the output can be either mono,
single ADC consists of one bitstream 3rd-order stereo or dual language sound on either output.
sigma-delta audio ADC and a high -order decimation filter. All inputs and the output work with the same sampling
Input is supplied from the videoprocessor. frequency FS, formats and word sizes.
The number of significant bits is 24. The number of
DIGITAL AUDIO INTERFACE significant bits on the output is 24.
General Description The serial data inputs are active at all times, independent
The TV Sound Processor provides a digital stereo input of the serial data outputs being on or off. When the serial
interface and two stereo output interfaces. data outputs are off (either after power-up or via the
appropriate I2C-bus command) serial data and clocks WS
• I2S-bus master input interfaces for one stereo channel at
and SCK from a separate digital audio source can be fed
a sampling rate of Fs=32kHz.
into the TV Sound Processor, be processed and output in
• I2S-bus master output interfaces for two stereo channels accordance with internal selector positions, provided that
at a sampling rate of Fs=32kHz. the following criteria are met:
Three serial audio formats are supported at the Audio multi The number of bitclock (SCK) pulses may vary in the
channel I2S interface: application. When the applied word length is smaller than
Philips IIS format 24 bits, the LSB bits will be set to 0 internally. When the
Sony IIS format applied word length exceeds 24 bits, the LSBs are
skipped.
Japanese LSB justified format 24-bits
The word select output is clocked with the audio sample
The differences of the formats are illustrated in the figures frequency at 32 kHz. The serial clock output (SCK) is
49, 50 and 51. clocked at a frequency of 2.048 MHz. This means, that
In the Philips and Sony formats the left audio channel of a there are 64 clock pulses per pair of stereo output
stereo sample pair is output first and is placed on the serial samples, or 32 clock pulses per sample. Depending again
data line (SDI for input, SDO for output) when the word on the signal source, the number of significant bits on the
select line (WS) is LOW. Data is written at the trailing edge serial data output SDO is 24. The SCK and WS clocks will
of SCK and read at the leading edge of SCK. The most be generated by the TV Sound Processor, which is the
significant bit is sent first. I2S-bus master.
In the Japanese LSB justified format the right audio

channel of a stereo sample pair is output first. The most
significant bit is sent first but data is LSB aligned to the
falling edge of the word select line (WS).
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Possible Formats
PHILIPS IIS-FORMAT
SCK
SD
WS MSB LSB MSB LSB
24.Left 24.Right
MSB first / MSB justified / Justification bit is one bitclock delayed : position fixed.
Fig.49 Philips IIS-Format
SONY IIS-FORMAT
SCK
SD
WS MSB LSB MSB LSB
24.Left 24.Right
: position fixed.
MSB first / MSB justified
Fig.50 Sony IIS-Format
JAPANESE FORMAT
SCK
SD
WS MSB LSB MSB LSB
24.Left 24.Right
MSB first / LSB justified : position fixed.
Fig.51 Japanese Format
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UOCIII series
I2C-BUS USER INTERFACE DESCRIPTION

Introduction
The UOCIII series is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers.
Status information can be read from a set of info registers to enable the controlling microcontroller determine whether
any action is required.
The TV sound processor has an own I2C-bus slave transceiver, which is independent from microcontroller I2C interface.
The specification of this I2C interface is according to the fast-mode specification, with a maximum speed of 400 kbits/s.
Information concerning the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number
9398 393 40011). One slave address is available (see Table 259).
Table 259 Slave address
SLAVE ADDRESS A6 TO A0
1011000
In standby mode the clock for the soundpart will be switched off and the soundpart of UOCIII is not functional. So it cannot
be addressed via I2C.
The device will not respond to a ‘general call’ on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master.
Each address of the address space (see below) will be acknowledged, but in case of an illegal address the following data
will not be acknowledged and the transmission will be aborted. Sound function is not guaranteed if not released registers
are addressed!
Overview address space

The TV sound processor has 64k addresses, a space of 52 XRAM addresses is available for controlling purpose. These
registers are fully DSP software controlled. Other address space is used by internal processing and cannot be used via
I2C.
Here the overview, which addresses are available.
Table 260 Overview full address range
ADDRESS WORDS WORDLENGTH Description
$0000 to $0033 52 words 3 bytes I2C addresses enabled and

usable
$0034 to $003F 12 words 3 bytes I2C addresses enabled but
reserved. Not usable
$0040 to $FFFF - - always disabled
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Power-up state Demodulator outputs are muted

At power-up or after a ‘sleep awake’ the device is in the IIS outputs are disabled
following state: Beeper off
• All outputs muted Monitoring of carrier 1 FM demodulator output.
No sound carrier frequency loaded After power-up a device initialization has to be performed
General-purpose I/O pins ready for input (HIGH) via the I2C-bus to put the UOCIII series into the proper
All level adjusts are set to 0 dB (flat). mode of operation. All reserved bits (i.e. not defined for this
IC) must be set to zero for the I2C protocol, to assure
All volumes are set to 0 dB and all outputs are muted. compatibility to other ICs of the family.
All tone control (bass, treble, equalizer..) settings are
flat. Overview Control Register Table
Source selectors of all audio channels are set to DEC The cluster name gives additional information in which
output. context the register will be used.
All effects (incredible sound, DPL, AVL) are off.
Table 261 Overview UOCIII I2C SSD Control Register Table
Read/ Address Register Cluster

Write
R $001 INF_DEV_STA_REG INFO
R $002 INF_NIC_STA_REG INFO
R $003 INF_NIC_ADD_REG INFO
R $004 INF_LEV_MON_REG INFO
R $005 INF_MPX_LEVEL_REG INFO
R $006 INF_DC1_REG INFO
R $007 INF_SUBMAGN_REG INFO
R $008 INF_NOISELEVEL_REG INFO
R $009 INF_REVISION_ID_REG INFO
W/R $00A DEM_CFG_REG DEMDEC
W/R $00B DEM_CA1_REG DEMDEC
W/R $00C DEM_CA2_REG DEMDEC
W/R $00D DEM_MPXCFG_REG DEMDEC
W/R $00E DEM_FMSUBCFG_REG DEMDEC
W/R $00F DEM_OUT_CFG_REG DEMDEC
W/R $010 MAGDET_THR_REG DEMDEC
W/R $011 NMUTE_FMA2_SAP_REG DEMDEC
W/R $012 NMUTE_MPX_REG DEMDEC
W/R $013 NMUTE_EIAJ_REG DEMDEC
W/R $014 NICAM_CFG_REG DEMDEC
W/R $015 DDEP_CONTROL_REG DEMDEC
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Read/ Address Register Cluster

Write
W/R $016 LEV_ADJ_DEM_REG LEVEL ADJUST
W/R $017 LEV_ADJ_IO_REG LEVEL ADJUST
W/R $018 ASW_MA_C_S_REG AUDIO SWITCHING
W/R $019 ASW_A1_A2_A3_REG AUDIO SWITCHING
W/R $01A ASW_DAFO1_2_REG AUDIO SWITCHING
W/R $01B ASW_DAC_I2S_OCO_REG AUDIO SWITCHING
W/R $01C ASW_MUT_CON_REG AUDIO SWITCHING
W/R $01D SOU_APP_MOD_REG SOUND PROCESSING MODE
W/R $01E SOU_EFF_REG SOUND EFFECTS
W/R $01F MAIN_SOU_EFF_REG SOUND EFFECTS
W/R $020 DBE_COEF_DOWNL_REG SOUND EFFECTS
W/R $021 DUB_COEF_DOWNL_REG SOUND EFFECTS
W/R $022 DOL_CON_REG SOUND EFFECTS
W/R $023 MASTER_VOL_REG SOUND
W/R $024 MAI_VOL_REG SOUND
W/R $025 SW_C_S_VOL_REG SOUND
W/R $026 AUX1_VOL_REG SOUND
W/R $029 MAI_TON_CON_REG SOUND
W/R $02A CENTER_TON_CON_REG SOUND
W/R $02B SUR_TON_CON_REG SOUND
W/R $02C EQMAIN1_TON_CON_REG SOUND
W/R $02D EQMAIN2_TON_CON_REG SOUND
W/R $02E EQCENTER1_TON_CON_REG SOUND
W/R $02F EQCENTER2_TON_CON_REG SOUND
W/R $030 MON_SEL_REG MONITOR
W/R $031 GEN_CTRL_REG GENERAL CONTROL
W/R $032 DCXO_CTRL_REG DEMDEC
W/R $033 DDEP_OPTIONS1_REG DEMDEC
Slave receiver mode

As a slave receiver, the UOCIII series provides 42 XRAM registers for storing commands and data. Each register contains
up to 24 bit and can be accessed via so-called subaddresses. A subaddress is 16 bit long and can be thought of as a
pointer to an internal memory location. Due to the I2C-protocol subaddresses and data are transferred bytewise, so a
subaddress needs 2 and a data word 3 byte packets
Not used bits must be set to 0!!
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2 modes are possible:

autoincrement: only first address must be transmitted from the master, following addresses will be internally calculated
by incrementing the start address
not autoincrement: every single address must be provided by the master
Table 262 Format for a transmission employing auto-increment of subaddresses
S SLAVE 0 A SUBADDR1 A SUBADDR0 A DATA... A DATA... A DATA... A DATA... A P

ADDR
Note
1. DATA...: n data bytes with auto-increment of subaddresses. 3 bytes are 1 dataword. After 3 bytes a new dataword
starts
Table 263 Explanation of previous table
BIT FUNCTION
S START condition
SLAVE ADDRESS 7-bit device address
0 data direction bit (write to device)
A acknowledge by slave
SUBADDR1 Byte 1 (MSB) of write register address
SUBADDR0 Byte 0 (LSB) of write register address
DATA2 Byte2 (MSB) of data word to be written into register
DATA1 Byte1 of data word to be written into register
DATA0 Byte0 (LSB) of data word to be written into register
P STOP condition
It is allowed to send more than one data word per transmission to the UOCIII series. In this event, the subaddress is
automatically incremented after each data word, resulting in storing the sequence of data words at successive register
locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with
A (acknowledge) if address is valid and data byte is properly stored, otherwise a NA (not acknowledge) occurs and aborts
the transmission.
There is no ‘wrap-around’ of subaddresses.
Commands and data are processed as soon as a data word has been completely received. If the transmission is
terminated (STOP condition) before all bytes of a word have been received, the incomplete data for that function are
ignored.
Data patterns sent to the various subaddresses are not checked for being illegal or not at that address.
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Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will
not then be executed.
For each address the data word starts with the most significant byte->most significant bit.
Slave transmitter mode

As a slave transmitter, the UOCIII series provides 9 registers with status information and data. These registers can be
accessed by means of subaddresses.
Besides these read registers all write registers are readable too.
The autoincrement mode is also applicable.
Table 264 General format for reading data from the SSD part of the UOCIII series
S SLAVE ADDR 0 A SUBADDR1 A SUBADDR0 A Sr SLAVE ADDR 1
DATA2 A DATA1 A DATA0 NAm P
Table 265Explanation of previous table
BIT FUNCTION
S START condition
SLAVE ADDRESS 7-bit device address
0 data direction bit (write to device)
A acknowledge by slave
SUBADDR1 Byte 1 (MSB) of read register address
SUBADDR0 Byte 0 (LSB) of read register address
Sr repeated START condition
1 data direction bit (read from device)
DATA2 Byte2 (MSB) of data word to be read from register
DATA1 Byte1 of data word to be read from register
DATA0 Byte0 (LSB) of data word to be read from register
NAm not acknowledge (by the master)
Am acknowledge (by the master)
P STOP condition
Reading of data can start at any valid subaddress. It is allowed to read more than 1 data word per transmission from the
UOCIII series. In this situation, the subaddress is automatically incremented after each data word, which results in
reading the sequence of data bytes from successive register locations, starting at SUBADDRESS.
Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master).
If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF in
hexadecimal notation.
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Detailed Control Register Table

Each absolute HEX address is mapped to one register name. The register name gives some information in mnemo like
manner. The cluster name is omitted as column but occurs as header in the column ‘REGISTER’ in the detailed table,
(see overview table). Not mentioned bit indices are reserved and must be zero.
Table 266 Detailed SSD I2C read + write control register table
ABS.
Reset
ADDR. REGISTER R/W Bitfield Name Data bits DETAILLED INFO($= HEX values)
value
HEX
INFO
$001 INF_DEV_STA_REG R STDRES [4..0] standard detection result (ASD mode), or selected
standard in SSS mode
0 = failed to find any standard
1 = B/G (still searching, SC2 not (yet) found)
2 = D/K (still searching, SC2 not (yet) found)
3 = M (still searching, no ident or pilot found)
4 = B/G A2
5 = B/G NICAM
6 = D/K A2 (1)
7 = D/K A2 (2)
8 = D/K A2 (3)
9 = D/K NICAM
10 = L NICAM
11 = I NICAM
12 = M Korea
13 = M BTSC
14 = M EIAJ
15 = FM Radio, IF = 10.7 MHz, 50 us deemphasis
17 = FM Radio, selectable IF, 50 us deemphasis
31 = still searching for a standard (can occur only
during a few milliseconds)
GST [5] general stereo flag (ident source determined by
currently detected or selected standard)
$0 = No stereo mode
$1 = Stereo mode detected
GDU [6] general dual flag
$0 = No dual mode
$1 = Dual mode detected
APILOT [7] A2 or EIAJ pilot tone detected
$0 = False
$1 = True
ADU [8] A2 or EIAJ ident dual flag
$0 = False
$1 = True
AST [9] A2 or EIAJ ident stereo flag
$0 = False
$1 = True
AAMUT [10] SC2 (if A2 mode) or EIAJ subchannel muted due
to noise
$0 = False
$1 = True
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ABS.
Reset
value
HEX
BPILOT [11] BTSC or FM radio pilot tone detected (stereo indi-
cator)
$0 = False
$1 = True
SAPDET [12] SAP carrier detected
$0 = False
$1 = True
BAMUT [13] BTSC stereo muted due to noise (if noise detector
enabled)
$0 = False
$1 = True
SAMUT [14] SAP muted due to noise (if noise detector
enabled)
$0 = False
$1 = True
VDSP_C [15] NICAM decoder VDSP flag
$0 = DATA or undefined format
$1 = SOUND
NICST_C [16] NICAM decoder stereo flag
$0 = False
$1 = True
NICDU_C [17] NICAM decoder dual flag
$0 = False
$1 = True
NAMUT [18] NICAM automute flag
$0 = not muted
$1 = muted (fallback to analog sound carrier)
RSSF [19] NICAM reserve sound switching flag (=C4), see
NICAM specification
$0 = analog sound carrier conveys different con-
tents than NICAM carrier
$1 = analog sound carrier conveys same contents
as NICAM carrier (M1 if DUAL)
INITSTAT [20] initialization status (set to 0 upon read access)
$0 = no reset performed
$1 = reset has been applied to DSP and init rou-
tine has been executed
- [23..21] reserved
$002 INF_NIC_STA_REG R ERR_OUT [7..0] NICAM error counter: number of parity errors
found in the last 128ms period
CFC [8] NICAM ConFiguration Change
$0 = No configuration change
$1 = Configuration change at the 16 frame (CO)
boundary
CO_LOCKED [9] NICAM frame and CO synchronization
$0 = Audio output from NICAM part is digital
silence
$1 = Device has both frame and CO (16 frames)
synchronization
NACB [13..10] NICAM application control bits (see C1..C4 in
NICAM transmission)
VDSP [14] Identification of NICAM sound
$0 = DATA or undefined format
$1 = SOUND
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ABS.
Reset
value
HEX
NICST [15] NICAM stereo flag
$0 = No NICAM stereo mode (= Mono mode if
NICDU = $0)
$1 = NICAM stereo mode
NICDU [16] NICAM dual mono mode
$0 = No NICAM dual mono mode (= Mono mode if
NICST = $0)
$1 = NICAM dual mono mode
- [23..17] reserved
$003 INF_NIC_ADD_REG R ADW [10..0] NICAM additional data word (11 bit per frame)
- [16..11] reserved, must be written as 0
DCXOCAPS [23..17] DCXO capacitor bank control signal (not yet imple-
mented in PICASSO-100 N1)
$004 INF_LEV_MON_REG R MONLEVEL [23..0] monitor level
$005 INF_MPX_LEVEL_REG R - [5..0] reserved
MPXPLEV [23..6] MPX pilot level
$006 INF_DC1_REG R SC1_DC [23..0] DC offset from FM demodulator channel 1
$007 INF_SUBMAGN_REG R SUBMAGN [23..0] magnitude of FM subchannel
$008 INF_NOISELEVEL_REG R NDETCH_STAT [0] status noise detector channel
0 = channel 1
1 = channel 2
NDETPB_STAT [1] status noise detector passband
0 = low (2.5 fh)
1 = high (7.5 fh)
NOISELEVEL [23..2] noise detector output
$009 INF_REVISION_ID_RE R MAJOR_VERSI [3..0] major version number.
G ON_NR
MINOR_VERSI [7..4] minor version number.
ON_NR incremented number means: control interface may
have extensions for additional functions or func-
tionality may have changed slightly; driver update
recommended.
PATCH_LEVEL [11..8] patch level number.
incremented number indicates bugfixes of the
embedded software without any change of control
interface or functionality.
no driver update needed.
DEVICE_TYPE [15..12] device type ID (internal use)
ROM_ID [23..16] ROM identification code. Unique number for every
ROM code ever released.
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ABS.
Reset
value
HEX
DEMDEC
$00A DEM_CFG_REG R/W DECPATH [2..0] $0 decoder path selection

$0 = FM A2
$1 = FM SAT with adaptive deemphasis
$2= FM Radio
$3 = NICAM + FM mono
$4 = BTSC stereo + SAP with 150 us demphasis
$5= BTSC mono + SAP with dbx
$6 = EIAJ stereo
$7= BTSC stereo flat & SAP flat (test mode)
FMDEEM [5..3] $0 fixed deemphasis for analog sound signals (not
NICAM, not BTSC)
$0 = 50 us (Europe)
$1 = 60 us
$2 = 75 us (M standard)
$3 = J17
$4 = OFF (flat)
CH2MOD [7..6] $0 operating mode of demodulator channel 2
$0 = FM mode
$1 = AM mode
$2 = NICAM
$3 = not used
CH1MOD [8] $0 operating mode of demodulator channel 1
$0 = FM mode
$1 = AM mode
INITLPF [9] $0 initialize loop filters in demodulator
$0 = mormal operation
$1 = initialize (reset states to 0)
- [10] $0 reserved, must be written as 0
FILTBW_M [12..11] $0 FM/AM demodulator filter bandwidth
$0 = narrow
$1 = extra wide (only ch. 1 active)
$2 = medium
$3 = wide
IDMOD_M [14..13] $0 FM ident speed
$0 = slow
$1 = medium
$2 = fast
$3 = off (reset)
IDAREA [16..15] $0 Area/regional code for FM-ident: Europe, Korea,
Japan
$0 = Europe
$1 = Korea
$2 = Japan
$3 = Japan
BPILCAN [17] $0 MPX pilot cancellation
$0 = False
$1 = True
FM_MPX [18] $0 input from demodulator hardware at 4*fs
$0 = FM / AM output
$1 = MPX demodulator output (for BTSC and FM
RADIO)
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ABS.
Reset
value
HEX
ID_DC_LEVEL [20..19] $0 DC level for IDENT pilot detection
$0 = Level > 3
$1 = Level > 4
$2 = Level > 5
$3 = Level > 6
ID_BYBPF [21] $0 bypass bandpass filter level detector
$0 = off
$1 = on (reduced IDENT sensitivity)
ID_PGAIN [22] $00 IDENT pilot bandpass gain
$0 = no gain
$1 = +6 dB gain for EIAJ
$00B DEM_CA1_REG R/W CARRIER1 [23..0] $000000 sound carrier 1 (mixer 1) frequency
$5DC000 = 4.5 MHz
$729555 = 5.5 MHz
$7D0000 = 6.0 MHz
$876AAB= 6.5 MHz
$DEEAAB = 10.7 MHz
$00C DEM_CA2_REG R/W CARRIER2 [23..0] $000000 sound carrier 2 (mixer 2) frequency
$626AAB = 4.724 MHz
$77A100 = 5.742 MHz
$825F00 = 6.258 MHz
$79E000 = 5.85 MHz
$888000 = 6.552 MHz
$8C7665 = 6.742 MHz
$5DC000 = 4.5 MHz
$729555 = 5.5 MHz
$00D DEM_MPXCFG_REG R/W - [0] $0 reserved, must be written as 0
MPX_PLL_BW [1] $0 MPX demodulator pilot PLL bandwidth
$0 = 5Hz (default)
$1 = 10Hz
MPX_FREQ [23..2] $000000 MPX pilot frequency
$29F54 =15734 Hz (standard NTSC line fre-
quency)
$29AAA = 15625 Hz (PAL line frequency)
$32AAA = 19000 Hz (FM radio)
$00E DEM_FMSUBCFG_REG R/W FMSUB_BW [0] $000000 FM subchannel and EIAJ MAIN filter bandwidth
$0 = narrow
$1 = wide
EIAJ_DELAY [2..1] $000000 delay fine adjustment in MAIN path for EIAJ stereo
NDETCH [3] $000000 noise detector channel
$0 = channel 1
$1 = channel 2
NDETPB [4] $000000 noise detector passband
$0 = low (2.5 fh)
$1 = high (7.5 fh)
- [7..5] $0 reserved, must be written as 0
FMSUB_FREQ [23..8] $000000 FM subchannel frequency (SAP or Japan)
$3437 = 5 fh for SAP
$14FB = 2 fh for EIAJ
$00F DEM_OUT_CFG_REG R/W DECSEL [1..0] $0 source for DEC output
$0 = MONO output
$1 = FM dematrix output
$2 = NICAM decoder output
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ABS.
Reset
value
HEX
FMDEMAT [4..2] $0 FM dematrix
$0 = mono CH1
$1 = mono CH2
$2 = dual (identity matrix)
$3 = stereo Europe
$4 = stereo M standards (BTSC, Korea, Japan)
and FM Radio
MONOSEL [5] $0 source for MONO output
$0 = demod. channel 1
$1 = ADC ch.1 = left (external demodulator)
MUTE_DEC_M [6] $1 mute DEC and MONO outputs (softmute)
ONO $0 = no mute
$1 = mute
MUTE_SAP [7] $1 mute SAP output (softmute)
$0 = no mute
$1 = mute
FM_SCALE [11..10] $0 scaling of FM and FM A2 signals
$0 = 27 kHz nominal FM deviation (Europe)
$1 = 15 kHz nominal FM deviation (M standards)
$2 = 0 dB gain (BTSC, EIAJ, FM Radio)
ANLG_SCALE [23..12] $400 expert mode: internal scaling coefficient for all
analog demodulator signals. 1024 means 0 dB.
$010 MAGDET_THR_REG R/W MPX_PILOT_T [3..0] $3 upper threshold for MPX pilot detection (BTSC, FM
HR_UP RADIO) in dB below nominal level
MPX_PILOT_T [7..4] $9 lower threshold for MPX pilot detection (BTSC, FM
HR_LO RADIO) in dB below nominal level
SAP_CAR_TH [11..8] $3 upper threshold for SAP carrier detection in dB
R_UP below nominal level
SAP_CAR_TH [15..12] $6 lower threshold for SAP carrier detection in dB
R_LO below nominal level
ASD_SC1_THR [22..18] $0 threshold for detection of first sound carrier (SC1)
during ASD first step, relative to -30 dBFS. -16 pre-
vents ASD "failure" to produce output regardless of
carrier level.
$011 NMUTE_FMA2_SAP_R R/W NMUTE_SAP_ [4..0] $0 noise threshold for automute of SAP (-16 means
EG THR automute off)
NMUTE_SAP_ [8..5] $4 hysteresis size [dB] for automute of SAP
HYST
NMUTE_SC2_ [13..9] $0 noise threshold for automute of SC2 in FM A2
THR standards (-16 means automute off)
NMUTE_SC2_ [17..14] $4 hysteresis size [dB] for automute of SC2 in FM A2
HYST standards
$012 NMUTE_MPX_REG R/W NMUTE_BTSC [4..0] $0 noise threshold for automute of BTSC stereo car-
_THR rier (-16 means automute off)
NMUTE_BTSC [8..5] $4 hysteresis size [dB] for automute of BTSC stereo
_HYST
NMUTE_FMRA [13..9] $0 noise threshold for automute of FM RADIO stereo
_THR carrier (-16 means automute off)
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ABS.
Reset
value
HEX
NMUTE_FMRA [17..14] $4 hysteresis size [dB] for automute of FM RADIO
_HYST stereo
$013 NMUTE_EIAJ_REG R/W NMUTE_EIAJ_ [4..0] $0 noise threshold for automute of EIAJ FM subcar-
THR rier (-16 means automute off)
NMUTE_EIAJ_ [8..5] $4 hysteresis size [dB] for automute of EIAJ FM sub-
HYST carrier
EIAJ_CAR_TH [12..9] 8 upper threshold for EIAJ SUB carrier detection in
R_UP dB below nominal level
EIAJ_CAR_TH [16..13] 12 lower threshold for EIAJ SUB carrier detection in
R_LO dB below nominal level
EIAJ_CAR_DE [17] 1 enable EIAJ SUB carrier detector
TECT 0 = sub carrier detector disabled
1 = sub carrier detector enabled
$014 NICAM_CFG_REG R/W ONLY_RELATE [0] $0 reproduce only related NICAM on DEC output
D (DDEP only)
$0 = false (NICAM whenever possible)
$1 = true (NICAM suppressed if RSSF=0)
EXTAM [2] $0 fall back source in case of automute in standard L
(DDEP only)
$0 = channel 1 output (AM)
$1 = ADC output (external AM demodulator)
NICDEEM [3] $0 NICAM deemphasis (J17) (all modes)
$0 = ON
$1 = OFF
NIC_AMUTE [4] $0 NICAM auto mute function depending on bit error
rate (DDEP only)
$0 = ON
$1 = OFF
NICLOERRLIM [12..5] $64 NICAM lower error limit (DDEP only)
NICUPERRLIM [20..13] $C8 NICAM upper error limit (DDEP only)
$015 DDEP_CONTROL_REG R/W EPMODE [1..0] $0 DEMDEC Easy Programming (DDEP) mode
$0 = 'AUTOSTANDARD' (ASD). STDSEL[4:0]
defines the set of 'allowed' standards.
$1 = 'STATIC STANDARD SELECT' (SSS). STD-
SEL[4:0] contains standard code.
$2 = Reserved
$3 = DEMDEC expert mode (fully manual mode)
2003 Nov 11 166

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UOCIII series
ABS.
Reset
value
HEX
STDSEL [6..2] $0 Bits multiplexed for ASD and SSS modes.
In ASD mode (EPMODE=0): flags for allowed
standards B/G | D/K | L/L' | I | M (LSB to MSB).
In SSS mode (EPMODE=1): standard code as
defined in status register STDRES, e.g. code 4
selects B/G A2.
For details please consult the documentation.
4 = B/G A2
5 = B/G NICAM
6 = D/K A2 (1)
7 = D/K A2 (2)
8 = D/K A2 (3)
9 = D/K NICAM
10 = L NICAM / L'
11 = I NICAM
12 = M Korea
13 = M BTSC
14 = M EIAJ
REST [7] $0 RESTART decoder and initialize DEMDEC after
channel switch, if changed from 0 to 1.
OVMADAPT [8] $1 FM overmodulation adaptation (avoids distortion,
filter bandwidth and gain is chosen adaptively)
$0 = disabled
$1 = enabled (recommended)
DDMUTE [9] $0 mute DEMDEC output signals (softmute)
$0 = no mute
$1 = mute
FILTBW [11..10] $0 FM/AM demodulator filter bandwidth (like
FILTBW_M). NOT effective if BTSC, EIAJ, FMRA-
DIO active, or if OVMADAPT=1
$0 = narrow (recommended)
$2 = medium
$3 = wide
$1 = extra wide (only ch. 1 active)
IDMOD [13..12] $0 FM ident speed in SSS mode (otherwise not effec-
tive)
$0 = slow
$1 = medium
$2 = fast
$3 = off (reset)
SAPDBX [16] $0 SAP decompression mode
$0 = dbx used for BTSC stereo decoding, fixed
compromise deemphasis for SAP (recommended)
$1 = dbx used for SAP, BTSC stereo forced to
mono
FHPAL [17] $0 line frequency for BTSC decoding
$0 = NTSC line frequency (15.734 kHz) used in
SSS, or preferred in ASD mode
$1 = PAL line frequency (15.625 kHz) used in
SSS, or preferred in ASD mode
2003 Nov 11 167

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UOCIII series
ABS.
Reset
value
HEX
OVMTHR [19..18] $1 overmodulation level threshold relative to nominal
(applies if OVMADAPT=1)
$0 = +3 dB = -12 dBFS
$1 = +6 dB = - 9 dBFS (recommended)
$2 = +9 dB = -6 dBFS
$3 = +12 dB= -3 dBFS
LEVEL ADJUST
$016 LEV_ADJ_DEM_REG R/W DECLEV [4..0] $00 level adjust DEC ( +15..-15dB)(-16 = MUTE)
MONOLEV [9..5] $00 level adjust MONO ( +15..-15dB)(-16 = MUTE)
NICLEV [14..10] $00 extra gain for NICAM ( +15..-15dB)(-16 = MUTE)"
SAPLEV [19..15] $00 Level adjust SAP ( +15..-15dB)(-16 = MUTE)
$017 LEV_ADJ_IO_REG R/W ADCLEV [4..0] $00 level adjust ADC ( +15..-15dB)(-16 = MUTE)
IISLEV [9..5] $00 level adjust IIS ( +15..-15dB)(-16 = MUTE)
AUDIO SWITCHING
$018 ASW_MA_C_S_REG R/W MAINSS [4..0] $00 SIGNAL SOURCE MAIN

$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
$05 = Noise Generator
$06 = Silence Generator
MAINDM [7..5] $0 DIGITAL MATRIX MAIN
$0 = AB [Stereo] (automatrix off)
$1 = (A+B)/2 [Mono] (automatrix off)
$2 = AA [Lang. A] (automatrix off)
$3 = BB [Lang. B] (automatrix off)
$4 = BA [Swap] (automatrix off)
$5 = not used
$6 = Language A (automatrix on)
$7 = Language B (automatrix on)
CENTERSS [12..8] $06 SIGNAL SOURCE CENTER
$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
2003 Nov 11 168

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
SURROUNDSS [17..13] $06 SIGNAL SOURCE SURROUND
$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
$019 ASW_A1_A2_A3_REG R/W AUX1SS [4..0] $00 SIGNAL SOURCE AUX1
$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
AUX1DM [7..5] $0 DIGITAL MATRIX AUX1
$5 = not used
AUX2SS [12..8] $00 SIGNAL SOURCE AUX2
$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
$5 = not used
AUX3SS [20..16] $0 SIGNAL SOURCE AUX3
$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
2003 Nov 11 169

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
$5 = not used
$01A ASW_DAFO1_2_REG R/W ASAFO1 [3..0] $0 OUTPUT SELECTION for DAFO1 to DAC2L
$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
$C = digital silence
ASAFO2 [7..4] $1 OUTPUT SELECTION for DAFO2 to DAC2R
$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
$01B ASW_DAC_I2S_OCO_R R/W ASDAC1L [3..0] $0 OUTPUT SELECTION for DAC1L
EG $0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
2003 Nov 11 170

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
ASDAC1R [7..4] $1 OUTPUT SELECTION for DAC1R
$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
ASI2S1L [11..8] $0 OUTPUT SELECTION for I2S1L
$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
ASI2S1R [15..12] $1 OUTPUT SELECTION for I2S1R
$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
ASI2S2L [19..16] $0 OUTPUT SELECTION for I2S2L
$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
2003 Nov 11 171

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
ASI2S2R [23..20] $1 OUTPUT SELECTION for I2S2R
$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
$01C ASW_MUT_CON_REG R/W MAINMUT [0] $1 Softmute MAIN/L,R output
$0 = OFF
$1 = ON
MAINLMUT [1] $0 Softmute MAIN/L output
$0 = OFF
$1 = ON
MAINRMUT [2] $0 Softmute MAIN/R output
$0 = OFF
$1 = ON
SUBWMUT [3] $1 Softmute SUBWOOFER output
$0 = OFF
$1 = ON
CENTERMUT [4] $1 Softmute CENTER output
$0 = OFF
$1 = ON
SURROUND- [5] $1 Softmute SURROUND output
MUT $0 = OFF
$1 = ON
AUX1MUT [6] $1 Softmute AUX1 output
$0 = OFF
$1 = ON
$0 = OFF
$1 = ON
$0 = OFF
$1 = ON
2003 Nov 11 172

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
SOUND PROCESSING
MODE
$01D SOU_APP_MOD_REG R/W EXEMODTAB [0] $0 Execute 'Mode Table'
After a transition from '0' to '1' the selected 'Mode

Table' is executed once. Afterwards it should be
cleared again.
(If ControlMode='0')
SNDMOD [5..1] $00 Sound Modes
$0 = Mono/Stereo (default)
$1 = Mono/Stereo (HALL)
$2 = Mono/Stereo (MATRIX)
$3 = DPL (normal Centre)
$4 = DPL (3 Stereo)
$5 = DPL (Phantom Centre)
$6 = VDS422
$7 = VDS423
$8 = SRS TruSurround (DPL)
$9 = Noise Sequencing
$A = SRS TruSurround (Passive Matrix)
CLIPMANAGE [8..6] $0 Clip Management
$0 = Clip management OFF (default)
$1 = Static Volume Mode
$2 = Static Control Mode
$3 = Dynamic Control Mode
$4 = Dynamic Volume Mode
$5 = Reserved
$6 = Reserved
$7 = Reserved
MAINSUBCTRL [9] $0 Main/Subwoofer signal output control
$0 = Normal Subwoofer Mode
$1 = Economic Subwoofer Mode
EQBYPASS [10] $0 EQ enable for Main and Center channel
$0 = EQ bypass off
$1 = EQ bypass on
SOUND EFFECTS
$01E SOU_EFF_REG R/W BBECONTOUR [3..0] $0 BBE Contour value
$0 = Min. bass boost

$F = Max. bass boost
BBEPROCESS [7..4] $0 BBE Process value
$0 = Min. process
$F = Max. process
MAINLOUD [8] $0 MAIN loudness
$0 = OFF
$1 = ON
2003 Nov 11 173

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
MAINLONA [11..9] $0 MAIN loudness none attack volume level
$0 = -15dB Volume
$1 = -12dB Volume
$2 = -9dB Volume
$3 = -6dB Volume
$4 = -3dB Volume
$5 = 0dB Volume
$6 = +3dB Volume
$7 = +6dB Volume
MAINLOCH [13..12] $0 MAIN loudness filter characteristic (bass/treble in
dB)
$0 = standard (500Hz)
$1 = extra bass (1000Hz)
bass: 20 Hz -> max. 18.3 dB

treble: 16 kHz -> max. 4.3 dB
BASSFEA- [16..14] $0 DBE, DUB and BBE control
TURECTRL $0 = DBE, DUB and BBE Off
$1 = DBE main channel On
$2 = DUB main channel On
$3 = DBE subwoofer channel On
$4 = DUB subwoofer channel On
$5 = BBE On
$01F MAIN_SOU_EFF_REG R/W SOMOCTRL [1..0] $0 Spatializer sound effect
0 = OFF
1 = I-Stereo
2 = I-Mono
3 = 3D Sound
INSOEF [4..2] $3 I-Mono or I-Stereo Effect: Min..Max (6 steps)
$0 = 1 (Min)
$1 = 2
$2 = 3
$3 = 4
$4 = 5
$5 = 6 (Max)
AVLMOD [7..5] $0 AVL mode
$0 = OFF
$1 = very short decay (20 ms)
$2 = short decay (2 sec)
$3 = medium decay (4 sec)
$4 = long decay (8 sec)
$5 = very long decay (16 sec)
AVLWEIGHT [8] $1 AVL weighting filter
$0 = OFF
$1 = ON (recommended)
AVLLEV [12..9] $7 AVL reference level (16 steps: -6,-8,... -36 dBFS)
$2 = high threshold (-10 dBFS), small reduction
("daytime mode")
$7 = medium threshold (-20 dBFS), medium
reduction ("evening mode")
$C = low threshold (-30 dBFS), strong reduction
("night mode")
2003 Nov 11 174

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
SRS3DCENTE [16..13] $1 SRS 3D Sound Center
R $0 = -9dB
$1 = -14dB
$2 = -15dB
$3 = -16dB
$4 = -17dB
$5 = -18dB
$6 = -19dB
$7 = -20dB
$8 = -21dB
$9 = -22dB
$A = -23dB
$B = -24dB
$C = -25dB
$D = -26dB
$E = -27dB
$F = off
SRS3DSPACE [20..17] $0 SRS 3D Sound Space
$0 = -4dB
$1 = -5dB
$2 = -6dB
$3 = -7dB
$4 = -8dB
$5 = -9dB
$6 = -10dB
$7 = -11dB
$8 = -12dB
$9 = -13dB
$A = -14dB
$B = -15dB
$C = -16dB
$D = -17dB
$E = -18dB
$F = off
SRS3DBYPAS [21] $0 SRS 3D Sound bypass mode switch for test pur-
S pose
$0 = 3D Sound active
$1 = Bypass active
$020 DBE_COEF_DOWNL_R R/W DBEADR [5..0] $0 DBE coefficient address
EG
DBECOEF [23..12] $0 DBE coefficients
$021 DUB_COEF_DOWNL_R R/W DUBADR [7..0] $0 DUB coefficient address
EG
DUBCOEF [23..12] $0 DUB coefficients
$022 DOL_CON_REG R/W VDSMIXLEV [2..0] $0 VDS mix level: 0..100% (5 steps)
$0 = 0%
$1 = 20%
$2 = 40%
$3 = 60%
$4 = 80%
$5 = 100%
>$5 = reserved
2003 Nov 11 175

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
DPLDEL [7..3] $00 Dolby Prologic : Delayline values: 15..30 ms in 32
steps.
$00 = No delay
$01 = min. delay
$1F = max. delay
BAMAMO [9..8] $0 Bass management mode
$0 = OFF (Wide Centre Mode)
$1 = TYP1 configuration (Normal Centre Mode)
$2 = TYP2 configuration (Normal Centre Mode)
BAMASUB [10] $0 Bass Management subwoofer filter control
$0 = Subwoofer filter Off
$1 = Subwoofer filter On
BAMAFC [14..11] $0 Bass management lowpass filtercharacteristics:
50 - 400Hz (in 4 Bit resolution)) cornerfrequency.
Highpass filter is 1/lowpass.
$0 = 50 Hz
$1 = 60 Hz
$2 = 70 Hz
$3 = 80 Hz
$4 = 90 Hz
$5 = 100 Hz
$6 = 110 Hz
$7 = 120 Hz
$8 = 130 Hz
$9 = 140 Hz
$A = 150 Hz
$B = 200 Hz
$C = 250 Hz
$D = 300 Hz
$E = 350 Hz
$F = 400 Hz
FLAT_7KHZ_FI [15] $0 Dolby Surround ProLogic filter for test purpose
LTER $0 = OFF
$1 = ON
B_TYPE_FLAT [16] $0 Dolby Surround ProLogic filter for test purpose
$0 = OFF
$1 = ON
ABALCFG [17] $1 Dolby Surround ProLogic autobalance for test pur-
pose
$0 = OFF
$1 = ON
Delay- [23] $00 Shift the delay from the DLU to the XMEM
LineSwitch $0 = XMEM
$1 = DLU
2003 Nov 11 176

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
SOUND
$023 MASTER_VOL_REG R/W MASTERVOL [10..0] $0 Master volume: (+24..-83.875dB, mute ), controls
MAIN, SW, C and S in 1/8dB steps
192 = +24.000 dB
191 = +23.875 dB
..
184 = +23.000 dB
..
0 = 0.000 dB
-1 = -0.125 dB
..
-671 = -83.875 dB
-672 = mute
BEEPVOL [18..11] $AC Beeper volume: (0..-83dB, mute)
0 = 0 dB
-1 = -1 dB
..
-84 = mute
BEEPFREQ [21..19] $0 Beeper frequency: 200..12500 Hz
$0 = 200 Hz
$1 = 400 Hz
$2 = 1000 Hz
$3 = 2000 Hz
$4 = 3000 Hz
$5 = 5000 Hz
$6 = 8000 Hz
$7 = 12500 Hz
$024 MAI_VOL_REG R/W MAINVOLL [7..0] $00 MAIN volume left: (+24..-83dB, mute)
24 = +24 dB
23 = +23 dB
..
-84 = mute
MAINVOLR [15..8] $00 MAIN volume right: (+24..-83dB, mute)
24 = +24 dB
23 = +23 dB
..
-84 = mute
$025 SW_C_S_VOL_REG R/W SUBWVOL [7..0] $0 SUBWOOFER volume: (+24..-83dB, mute)
24 = +24 dB
23 = +23 dB
..
-84 = mute
2003 Nov 11 177

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
CENTERVOL [15..8] $0 CENTER volume: (+24..-83dB, mute)
24 = +24 dB
23 = +23 dB
..
-84 = mute
SURROUND- [23..16] $0 SURROUND volume: (+24..-83dB, mute)
VOL
24 = +24 dB
23 = +23 dB
..
-84 = mute
$026 AUX1_VOL_REG R/W AUX1VOLL [7..0] $00 AUX1 volume left: (+24..-83dB, mute)
24 = +24 dB
23 = +23 dB
..
-84 = mute
AUX1VOLR [15..8] $00 AUX1 volume rigth: (+24..-83dB, mute)
24 = +24 dB
23 = +23 dB
..
-84 = mute
24 = +24 dB
23 = +23 dB
..
-84 = mute
24 = +24 dB
23 = +23 dB
..
-84 = mute
24 = +24 dB
23 = +23 dB
..
-84 = mute
24 = +24 dB
23 = +23 dB
..
-84 = mute
$029 MAI_TON_CON_REG R/W MAINBASS [4..0] $00 MAIN bass: (+15..-16dB, 1 dB steps)
15 = +15 dB
..
-16 = -16 dB
2003 Nov 11 178

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
MAINTREB [9..5] $00 MAIN treble: (+15..-16dB, 1 dB steps)
15 = +15 dB
..
-16 = -16 dB
$02A CENTER_TON_CON_R R/W CENTERBASS [4..0] $0 CENTERbass: (+15..-16dB, 1 dB steps)
EG
15 = +15 dB
..
-16 = -16 dB
CENTERTREB [9..5] $0 CENTERtreble: (+15..-16dB, 1 dB steps)
15 = +15 dB
..
-16 = -16 dB
$02B SUR_TON_CON_REG R/W SURROUND- [4..0] $0 SURROUNDbass: (+15..-16dB, 1 dB steps)
BASS
15 = +15 dB
..
-16 = -16 dB
SUR- [9..5] $0 SURROUNDtreble: (+15..-16dB, 1 dB steps)
ROUNDTREB
15 = +15 dB
..
-16 = -16 dB
$02C EQMAIN1_TON_CON_ R/W EQCHM1 [4..0] $0 Equalizer MAIN Channel Band 1 (100 Hz)
REG
12 = +12dB
..
-12 = -12dB
EQCHM2 [9..5] $0 Equalizer MAIN Channel Band 2 (300 Hz)
12 = +12dB
..
-12 = -12dB
12 = +12dB
..
-12 = -12dB
$02D EQMAIN2_TON_CON_ R/W EQCHM4 [4..0] $0 Equalizer MAIN Channel Band 4 (3000 Hz)
REG
12 = +12dB
..
-12 = -12dB
12 = +12dB
..
-12 = -12dB
2003 Nov 11 179

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
$02E EQCENTER1_TON_CO R/W EQCHC1 [4..0] $0 Equalizer CENTER Channel Band 1 (100 Hz)
N_REG
12 = +12dB
..
-12 = -12dB
EQCHC2 [9..5] $0 Equalizer CENTER Channel Band 2 (300 Hz)
12 = +12dB
..
-12 = -12dB
12 = +12dB
..
-12 = -12dB
$02F EQCENTER2_TON_CO R/W EQCHC4 [4..0] $0 Equalizer CENTER Channel Band 4 (3000 Hz)
N_REG
12 = +12dB
..
-12 = -12dB
12 = +12dB
..
-12 = -12dB
MONITOR
$030 MON_SEL_REG R/W MON_SRC [4..0] $00 source for monitor function
$00 = FM,AM,MPX (1 fs) input
$01 = FM,AM,MPX (4 fs) input
$02 = FM/AM/BTSC/EIAJ DC
$03 = FM dematrix output (at DECSEL switch)
$04 = NICAM (at DECSEL switch)
$05 = MONO (at DECSEL switch)
$06 = DEC (at dig. input crossbar)
$07 = MONO (at dig. input crossbar)
$08 = SAP (at dig. input crossbar)
$09 = ADC (at dig. input crossbar)
$0A = IIS (at dig. input crossbar)
$0B = Noise / silence generator (at dig. input
crossbar)
$0C = MAIN (at dig. output crossbar)
$0D = SUBWOOFER (at dig. output crossbar)
$0E = CENTER (at dig. output crossbar)
$0F = SURROUND (at dig. output crossbar)
$10 = AUX1 (at dig. output crossbar)
$13 = MAIN SUM (at dig. output crossbar)
$14 = MAIN (after Bass Management)
$15 = SUBWOOFER (after Bass Management)
$16 = CENTER (after Bass Management)
$17 = SURROUND (after Bass Management)
2003 Nov 11 180

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
MON_DET [6..5] $3 detection type for monitor function
$0 = random samples
$1 = absolute value peak detection
$2 = quasi peak detection
$3 = off / reset peak detector
MON_MAT [9..7] $0 matrix for monitor source
$0 = A
$1 = (A+B)/2
$2 = B
$3 = (A-B)/2 (2-ch. sources only)
GENERAL CONTROL
$031 GEN_CTRL_REG R/W I2S_FORMAT [1..0] $0 IIS format control

$0 = Philips format
$1 = Sony format
$2 = Japanese 24 bit
$3 = Japanese 24 bit
DAC_DWA [2] $00 DAC: data weighted averaging
$0 = uni-directional, better THD at low levels
$1 = bi-directional
DEMDEC
$032 DCXO_CTRL_REG R/W NICLPINV [0] 1 DCXO scaling control inverter

0 = not inverted
1 = inverted
NICLPSCALE [3..1] 3 DCXO scaling control gain
0 = 1.0
1 = 0.125
2 = 0.250
3 = 0.375
4 = 0.500
5 = 0.625
6 = 0.750
7 = 0.875
NICLPLIM [12..4] 511 DCXO scaling control limit (+/- limit), no clipping of
control signal if >= 256*scalefactor
NICLPCENTER [22..13] 0 DCXO scaling control center
- [23] 0 reserved, must be written as 0
$033 DDEP_OPTIONS1_REG R/W - [3..0] 0 reserved, must be written as 0
IDMOD_SLOW [5..4] 0 in ASD mode, IDMOD setting when European A2
_EUR standards (B/G, D/K) are detected
0 = slow
1 = medium
2 = fast
2003 Nov 11 181

CONFIDENTIAL

UOCIII series
ABS.
Reset
value
HEX
IDMOD_SLOW [7..6] 0 in ASD mode, IDMOD setting when M Korea stan-
_KOR dard detected
0 = slow
1 = medium
2 = fast
IDMOD_SLOW [9..8] 1 in ASD mode, IDMOD setting when EIAJ standard
_JAP detected
0 = slow
1 = medium
2 = fast
- [18..10] 0 reserved, must be written as 0
SAP_BW [19] 0 SAP filter bandwidth selection
0 = narrow filter
1 = wide filter
- [23..20] 0 reserved, must be written as 0
Refresh cycle
Minimum refresh cycle period (worst case) can be calculated as follows:
Max 42 write registers with 3 datawords each. Each dataword consists of 8 databits + acknowledge bit. If auto increment
is applied 1 deviceaddress + 1 subaddress (2 Bytes) is additionally needed. So in total 43* 3 * 9 = 1161 Bits are needed
for one transfer. Assuming max. I2C speed (400 kbits/sec) a total time of 1/400k * 1161 = 2.9 msec is needed. So the
next transfer cycle (=refresh) cannot start earlier.
The following table is an extract of the full address range. Refresh procedure depends on automatic feature
(autostandard detection).
Table 267 Overview SSD I2C address range wrt. refresh cycle
Address
Refresh with DDEP mode Refresh without DDEP
space
$0001-$0009 Read only Read only
$000A-$000F - Yes
$0010-$0015 Yes Yes
$0016-$0033 End refresh cycle End refresh cycle
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LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VP supply voltage − 5.5 V
VDDA supply voltage (analogue) −0.5 3.6 V
VDDP supply voltage (periphery) −0.5 3.6 V
VDDC supply voltage (core) −0.5 1.95 V
VI digital inputs note 1 −0.5 VDD+ 0.5 V
VO digital outputs note 1 −0.5 VDD+ 0.5 V
IO output current (each output) − ±10 mA
Tstg storage temperature −25 +150 °C
Tamb operating ambient temperature 0 70 °C
Tsol soldering temperature for 5 s − 260 °C
Tj operating junction temperature − 150 °C
Ves electrostatic handling HBM; all pins; notes 2 and 3 −2000 +2000 V
MM; all pins; notes 2, 4 and 5 −200 +200 V
Notes
1. This maximum value has an absolute maximum of 5.5 V independent of VDD.
2. All pins are protected against ESD by means of internal clamping diodes.
3. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.
4. Machine Model (MM): R = 0 Ω; C = 200 pF.
5. All pins meet this requirement except pin 68 (VSScomb) which can handle a stress voltage of ±150 V.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air (QFP-128) tbf K/W
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611E”.
Latch-up
At an ambient temperature of 70 °C all pins meet the following specification:
• Itrigger ≥ 100 mA or ≥1.5VDD(max)
• Itrigger ≤ −100 mA or ≤−0.5VDD(max).
Note:
The SDA pin (pin 109 of the “standard version” or pin 20 of the “face down version) does not meet this specification and
has a maximum trigger current of −20 mA. For the positive current it meets the requirement of 100 mA.
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CHARACTERISTICS OF MICRO-COMPUTER AND TEXT DECODER

VDD = 3.3 V ± 10%; VSS = 0 V; Tamb = 0 to +70 °C; unless otherwise specified
NUMBER PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies
VM.1.1 supply voltage (VDDA) 3.0 3.3 3.6 V
VM.1.2 supply voltage (VDDP) 3.0 3.3 3.6 V
VM.1.3 supply voltage (VDDC) 1.65 1.8 1.95 V
VM.1.4 periphery supply current (IDDP) note 1 1 − − mA
VM.1.5 core supply current (IDDC) normal mode − 440 tbf mA
VM.1.6 supply current IDDA + IDDP normal mode − 28 tbf mA
VM.1.7 supply current IDDA + IDDP stand-by mode − 15 tbf mA
VM.1.8 supply current IDDA + IDDP idle mode − 9 tbf mA
VM.1.9 supply current IDDA + IDDP power down mode − 7.5 tbf mA
Digital input/outputs
P0.0 TO P0.5, P1.0 TO P1.5, P2.0 TO P2.5 AND P3.0 TO P3.3
IO.1.1 low level input voltage − − 0.8 V
IO.1.2 high level input voltage 2 − − V
IO.1.3 hysteresis of Schmitt Trigger 0.4 − − V
input
IO.1.4 low level output voltage IOL = 4 mA − − 0.4 V
IO.1.5 high level output voltage open drain − − 3.3 V
IO.1.6 high level output voltage IOH = 4 mA; push pull VDDE − 0.4 − − V
IO.1.7 output rise time (push-pull only) load 40 pF − 5 − ns
10% to 90%
IO.1.8 output fall time 10% to 90% load 40 pF − 5 − ns
IO.1.9 load capacitance − − 100 pF
IO.1.10 capacitance of input pin − − 1 pF
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P1.6 AND P1.7 (OPEN DRAIN)
IO.2.1 low level input voltage (VIL) − − 0.8 V
IO.2.2 high level input voltage (VIH) 2 − − V
IO.2.3 hysteresis of Schmitt-trigger 0.4 − − V
input
IO.2.4 low level output voltage sink current 4 mA − − 0.4 V
IO.2.5 high level output voltage − − 3.3 V
IO.2.6 output fall time 10% to 90% P1.6; load 160 pF − 180 − ns
IO.2.7 output fall time 10% to 90% P1.7; load 400 pF − 140 − ns
IO.2.8 bus load capacitance − − 400 pF
IO.2.9 capacitance of IO pin − − 1 pF
Crystal oscillator
OSCIN; NOTE 2
X.1.1 resonator frequency − 24.576 − MHz
X.1.2 input capacitance (Ci) − tbf − pF
X.1.3 output capacitance (Co) − tbf − pF
X.1.4 Ri (crystal) − − 100 Ω
X1.5 maximum load capacitance Cx1 or Cx2 in Fig 52 − − 25 pF
Note
1. Peripheral current is dependent on external components and voltage levels on I/Os
2. The simplified circuit diagram of the oscillator is given in Fig.52.
A suitable crystal for this oscillator is the Saronix type 9922 520 20264.
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CHARACTERISTICS OF STEREO DECODER AND DIGITAL AUDIO PROCESSOR

VSIF(p-p) = 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain setting in accordance with note tbn;
VDD1,2,3 = 3.3 V;VDDA5 = 5.0 V; Tamb = 25 °C; settings in accordance with B/G standard; FM deviation ±50 kHz;
fmod = 1 kHz; FM sound parameters in accordance with system A2; NICAM in accordance with EBU specification; 1 kΩ
measurement source resistance for AF inputs; unless otherwise specified;
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VSSC4 digital supply ground for - 0.0 - V
Audio-DAC
VDDC4 digital supply voltage for 1.65 1.8 1.95 V
Audio-DAC
VDDA3 analogue supply voltage for VREF_POS 3.3 3.6 V
Audio-DAC -0.25
VDDA analogue supply voltage for 1.6 1.8 2.0 V
Audio-ADC
GNDA analogue supply ground for - 0.0 - V
Audio-ADC
VDDA2 analogue supply voltage for 3.0 3.3 3.6 V
Audio-ADC
SIF-ADC
SIF-ADC
Audio-ADC
Audio-ADC
References
VREF_POS positive analog reference 0.8 3.3 3.6 V
_LSL voltage for SDAC “LSL”
VREF_NEG negative analog reference - 0.0 - V
_LSL+LSR voltage for SDAC “LSL+LSR”
_LSR+HPL voltage for SDAC “LSR+HPL”
VREF_NEG negative analog reference - 0.0 - V
_HPL+HPR voltage for SDAC “HPL+HPR”
_HPR voltage for SDAC “HPR”
VREFAD positive analog reference 3.0 3.3 3.6 V
_POS voltage for Audio-ADC
VREFAD negative analog reference - 0.0 - V
_NEG voltage for Audio-ADC
VREFAD analog reference voltage for VDDA2/2 V
Audio-ADC
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Demodulator performance;
THD + N total harmonic distortion plus from FM source to any − 0.35 0.5 %
noise output; Vo = 1 V (rms) with
low-pass filter
from NICAM source to any − 0.1 0.3 %
output; Vo = 1 V (rms) with
low-pass filter
S/N signal-to-noise ratio SC1 from FM source to any 64 70 − dB
output; Vo = 1 V (rms);
CCIR468; quasi peak
SC2 from FM source to any 60 66 − dB
output; Vo = 1 V (rms);
CCIR468; quasi peak
NICAM source; NICAM in accordance with
Vo = 1 V (rms) EBU specification; note tbn
B−3 −3 dB bandwidth from FM source to any 14.5 15 − kHz
output
from NICAM source to any 14.5 15 − kHz
output
FR frequency response from FM or NICAM to any − ±2 − dB
20 Hz to 14 kHz output; fref = 1 kHz;
inclusive pre-emphasis and
de-emphasis
αcs(dual) dual signal channel separation 65 70 − dB
αcs(stereo) stereo channel separation 40 45 − dB
αAM AM suppression for FM AM: 1 kHz, 50 − − dB
30% modulation; reference:
1 kHz, 50 kHz deviation
S/NAM AM demodulation 2ndSIF level 100 mV (rms); 36 45 − dB
54% AM; 1 kHz AF;
CCIR468; quasi peak
IDENTIFICATION FOR FM SYSTEMS
modp pilot modulation for 25 50 75 %
identification
C/Np pilot sideband C/N for − 27 − dBc
----------
identification start Hz
fident identification window B/G stereo
slow mode 116.85 − 118.12 Hz
medium mode 116.11 − 118.89 Hz
fast mode 114.65 − 120.46 Hz
B/G dual
slow mode 273.44 − 274.81 Hz
medium mode 272.07 − 276.20 Hz
fast mode 270.73 − 277.60 Hz
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tident total identification time ON or slow mode − − 2 s
OFF medium mode − − 1 s
fast mode − − 0.5 s
Audio performance (D/A)
THD + N total harmonic distortion plus output voltage at 0dBFS; − 0.1 0.3 %
noise Vo = 1.0 V (rms); fi = 1 kHz;
bandwidth 20 Hz to 14 kHz;
S/N signal-to-noise ratio output reference level - 80 − dB
Vo = 1.0 V (rms); fi = 1 kHz;
CCIR468; RMS; from I2S to
D/A;
αct crosstalk attenuation between any analog audio 70 − − dB
signal pairs; fi = 1 kHz
αcs channel separation between left and right of 65 − − dB
any analog audio signal
pair
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CHARACTERISTICS OF TV-PROCESSOR
VP = 5 V; Tamb = 25 °C; unless otherwise specified.

Supplies
MAIN SUPPLY; NOTE 1
V.1.1 main supply voltage note 2 4.7 5.0 5.3 V
V.1.2 digital supply voltage 3.0 3.3 3.6 V
V.1.3 audio supply voltage note 3 4.7 8.0 8.4 V
V.1.4 main supply current (5 V) − 190 − mA
V.1.5 digital supply current (3.3 V) − 8 − mA
V.1.6 audio supply current (5.0/8.0 V) − 0.5 − mA
V.1.7 total power dissipation − 980 − mW
IF circuit
VISION IF AMPLIFIER INPUTS
input sensitivity (RMS value) note 4
M.1.1 fi = 38.90 MHz − 75 150 µV
M.1.2 fi = 45.75 MHz − 75 150 µV
M.1.3 fi = 58.75 MHz − 75 150 µV
M.1.4 input resistance (differential) note 5 − 2 − kΩ
M.1.5 input capacitance (differential) note 5 − 3 − pF
M.1.6 gain control range 64 − − dB
M.1.7 maximum input signal 150 − − mV
(RMS value)
PLL DEMODULATOR; NOTES 6 AND 7
M.2.1 Free-running frequency of VCO PLL not locked, deviation −500 − +500 kHz
from nominal setting
M.2.2 Catching range PLL without SAW filter − ±1 − MHz
M.2.3 delay time of identification via LOCK bit − − 20 ms
VIDEO AMPLIFIER OUTPUT (IFOUT); NOTE 8
M.3.1 zero signal output level negative modulation; note 9 − 3.6 − V
M.3.2 positive modulation; note 9 − 1.4 − V
M.3.3 top sync level negative modulation 1.3 1.4 1.5 V
M.3.4 white level positive modulation − 3.4 − V
M.3.5 difference in amplitude between − 0 15 %
negative and positive modulation
M.3.6 video output impedance − 50 − Ω
M.3.7 internal bias current of NPN 1.0 − − mA
emitter follower output transistor
M.3.8 maximum source current − − 5 mA
M.3.9 bandwidth of demodulated at −3 dB 6 7 − MHz
output signal
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VIDEO AMPLIFIER (CONTINUED)
M.3.10 differential gain note 10 − 2 5 %
M.3.11 differential phase notes 10 and 11 − − 5 deg
M.3.12 video non-linearity note 12 − − 5 %
M.3.13 white spot clamp level − 3.8 − V
M.3.14 noise inverter clamping level note 13 − 1.2 − V
M.3.15 noise inverter insertion level note 13 − 2.3 − V
(identical to black level)
intermodulation notes 11 and 14
M.3.16 blue Vo = 0.92 or 1.1 MHz 60 66 − dB
M.3.17 Vo = 2.66 or 3.3 MHz 60 66 − dB
M.3.18 yellow Vo = 0.92 or 1.1 MHz 56 62 − dB
M.3.19 Vo = 2.66 or 3.3 MHz 60 66 − dB
signal-to-noise ratio notes 11 and 15
M.3.20 weighted 56 60 − dB
M.3.21 unweighted 49 53 − dB
M.3.22 residual carrier signal note 11 − 5.5 − mV
M.3.23 residual 2nd harmonic of carrier note 11 − 2.5 − mV
signal
VIDEO OUTPUT/INPUT (IFVO/SVO/CVBSI), CONTROLLED BY THE SVO1/SVO0 BITS; SEE NOTE 16
M.3.24 output signal amplitude SVO1/SVO0 = 0/0 or 0/1 − 2.0 − V
M.3.25 top sync level SVO1/SVO0 = 0/0 or 0/1 − 0.5 − V
M.3.26 output impedance SVO1/SVO0 = 0/0 or 0/1 − − 50 Ω
M.3.27 CVBS input voltage SVO1/SVO0 = 1/0 − 1.0 1.4 V
M.3.28 input current SVO1/SVO0 = 1/0 − 2 − µA
GROUP DELAY CORRECTION, SEE FIGURES 63 AND 64; NOTE 17
M.3.29 group delay sound trap only at f=4.43MHz; sound trap − 180 − ns
frequency 5.5 MHz
M.3.30 group delay sound trap plus at f=4.43MHz; sound trap − 170 − ns
group delay correction filter frequency 5.5 MHz
SOUND TRAP
M.3.31 -3 dB video bandwidth (sound fSC1=4.5MHz 3.90 4.00 − MHz
trap + group delay) fSC1=5.5MHz 4.80 4.90 − MHz
fSC1=6.0MHz 5.25 5.35 − MHz
fSC1=6.5MHz 5.70 5.80 − MHz
M.3.32 Attenuation at first sound carrier 4.5 and 5.5MHz 30 36 − dB
fSC1 6.0 and 6.5MHz 26 32 − dB
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SOUND TRAP (CONTINUED)
M.3.33 Attenuation at second sound f=4.726Mhz; fSC1=4.5MHz 21 27 − dB
carrier fSC2 f=5.742MHz; fSC1=5.5MHz 21 27 − dB
f=6.55Mhz; fSC1=6.0MHz 12 18 − dB
f=6.742MHz; fSC1=6.5MHz 18 24 − dB
M.3.34 amplitude response at the colour f=3.58 MHz; fSC1=4.5 MHz − 1.0 2.0 dB
subcarrier frequency f=4.43 MHz; fSC1=5.5 MHz − 1.0 2.0 dB
f=4.43 MHz; fSC1=6.0 MHz − 1.0 2.0 dB
f=4.28 MHz; fSC1=6.5 MHz − 1.0 2.0 dB
IF AND TUNER AGC; NOTE 18
Timing of IF-AGC
M.4.1 modulated video interference 30% AM for 1 mV to 100 mV; − − 10 %
0 to 200 Hz (system B/G)
M.4.2 response time to IF input signal positive and negative − 2 − ms
amplitude increase of 52 dB modulation
M.4.3 response to an IF input signal negative modulation − 50 − ms
M.4.4 amplitude decrease of 52 dB positive modulation − 100 − ms
Tuner take-over adjustment (via I2C-bus)
M.5.1 minimum starting level for tuner − 0.4 0.8 mV
take-over (RMS value)
M.5.2 maximum starting level for tuner 50 150 − mV
take-over (RMS value)
Tuner control output
M.6.1 max. tuner AGC output voltage maximum tuner gain; note 5 − − 5 V
M.6.2 output saturation voltage minimum tuner gain; IO=2 mA − − 300 mV
M.6.3 maximum tuner AGC output 1.0 − − mA
swing
M.6.4 leakage current RF AGC − − 1 µA
M.6.5 input signal variation for 0.5 2 4 dB
complete tuner control
AFC OUTPUT (VIA I2C-BUS); NOTE 19
M.7.1 AFC resolution − 2 − bits
M.7.2 window sensitivity − 125 − kHz
M.7.3 window sensitivity in large − 275 − kHz
window mode
VIDEO IDENTIFICATION OUTPUT (VIA IFI BIT IN OUTPUT BYTE 00)
M.8.1 delay time of identification after − − 10 ms
the AGC has stabilized on a new
transmitter
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DVB IF, note 20
DVB IF AMPLIFIER INPUTS
VS.1.1 input sensitivity (RMS value) fi = 36/44 MHz − 75 150 µV
VS.1.2 input resistance (differential) note 5 − 2 − kΩ
VS.1.3 input capacitance (differential) note 5 − 3 − pF
VS.1.4 gain control range 64 − − dB
VS.1.5 maximum input signal 150 − − mV
(RMS value)
I-MIXER, NOTE 21
VS.2.1 oscillator frequency; note OFDM application − 43.008 − MHz
VS.2.11 VSB application − 49.152 − MHz
VS.2.2 maximum oscillator phase noise −106 − − dB
VS.2.5 lower limit passband − − 1.0 MHz
VS.2.6 upper limit passband 7.0 − − MHz
VS.2.7 passband ripple − − 0.5 dB
VS.2.8 stopband − 29 − MHz
VS.2.9 stopband attenuation 40 − − dB
EXTERNAL AGC CONTROL
VS.3.1 voltage range for full control of 1 − 3 V
the amplifier
VS.3.2 input impedance 1 − − MΩ
MIXED DOWN OUTPUT SIGNAL
VS.4.1 output voltage (peak-to-peak − 1 − V
value)
VS.4.2 output impedance − 25 − Ω
VS.4.3 dc output level − 2.0 − V
QSS Sound IF circuit
SOUND IF AMPLIFIER
Q.1.1 input sensitivity (RMS value) −3 dB − 45 tbf dBµV
Q.1.3 maximum input signal tbf 100 − dBµV
Q.1.5 input resistance (differential) note 5 − 2 − kΩ
Q.1.6 input capacitance (differential) note 5 − 3 − pF
Q.1.7 gain control range − 55 − dB
Q.1.8 crosstalk attenuation between 50 − − dB
SIF and VIF input
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SOUND IF INTERCARRIER OUTPUT; WITH AM = 0
Q.2.1 output signal amplitude (RMS SC-1; sound carrier 2 off 75 100 125 mV
value)
Q.2.2 bandwidth (-3 dB) 7.5 10 − MHz
Q.2.3 residual IF sound carrier (RMS − 2 − mV
value)
Q.2.4 output resistance − 300 − Ω
Q.2.5 DC output voltage − 2.0 − V
Q.2.6 internal bias current of emitter − 1.0 − mA
follower
Q.2.7 maximum AC and DC sink − 1.0 − mA
current
Q.2.8 maximum AC and DC source − 1.0 − mA
current
Q.2.9 weighted S/N ratio (SC1/SC2). black picture 53/48 58/55 − dB
Q.2.10 Ratio of PC/SC1 at vision IF white picture 52/47 55/53 − dB
input of 40 dB or higher, note 22
Q.2.11 6 kHz sinewave 44/42 48/46 − dB
(black-to-white modulation)
Q.2.12 250 kHz sine wave 44/25 48/30 − dB
(black-to-white modulation)
Q.2.13 sound carrier subharmonics 45/44 51/50 − dB
(f=2.75 MHz ± 3 kHz)
Q.2.14 sound carrier subharmonics 46/45 52/51 − dB
(f=2.87 MHz ± 3 kHz)
AM SOUND OUTPUT; DEPENDING ON SETTING OF CMB0/CMB1 AND AM BITS
Q.3.1 AF output signal amplitude 54% modulation 200 250 300 mV
(RMS value)
Q.3.2 total harmonic distortion 54% modulation − 1.0 2.0 %
Q.3.21 total harmonic distortion 80% modulation − 2.0 5.0 %
Q.3.3 AF bandwidth −3 dB 100 125 − kHz
Q.3.4 weighted signal-to-noise ratio 54% modulation, weighted − 45 − dB
with CCIR-1k filter, RMS SIF
level @ 80 dBµV
Q.3.5 DC output voltage − 2.5 − V
Q.3.6 power supply ripple rejection − 20 − dB
2nd Sound IF AGC circuit
2ND SOUND IF EXTERNAL INPUT, NOTE 23
Q.4.1 input voltage range 17 − 300 mVRMS
Q.4.2 input frequency range note 24 4.5 − 10.7 MHz
Q.4.3 input resistance note 5 − 25 − kΩ
Q.4.4 input capacitance note 5 − 3 − pF
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2ND SOUND IF AGC
Q.5.1 gain control range − 24 − dB
Q.5.2 charge current AGC pin FM mode − − 12.5 µA
Q.5.3 discharge current AGC pin FM mode − − 50 µA
Q.5.4 charge current AGC pin AM mode − − 2.5 µA
Q.5.5 discharge current AGC pin AM mode − − 2.5 µA
Q.5.6 discharge current AGC pin overload condition − 1 − mA
FM demodulator and audio pre-amplifier
FM-PLL DEMODULATOR
G.1.2 gain control range AGC amplifier 26 30 − dB
G.1.7 AM rejection note 25 40 46 − dB
EXTERNAL SOUND IF INPUT (SSIF, WHEN SELECTED)
G.1.8 input limiting for lock-in of PLL − 1 2 mV
(RMS value)
G.1.9 input resistance note 5 − 50 − kΩ
G.1.10 input capacitance note 5 − − 1.0 pF
DE-EMPHASIS OUTPUT
G.2.1 output signal amplitude (RMS notes 26 and 27 − 125 − mV
value)
G.2.2 output resistance − 15 − kΩ
G.2.3 DC output voltage − 2.5 − V
G.2.31 signal-to-noise ratio (RMS value) note 28 − 50 − dB
AUDIO INPUT VIA DEEMPHASIS OUTPUT; NOTE 29
G.2.4 input signal amplitude (RMS − 125 − mV
value)
G.2.5 input resistance − 15 − kΩ
G.2.6 voltage gain between input and − −3 − dB
output
Audio Selectors and Volume control
EXTERNAL AUDIO INPUTS; NOTE 30
A.1.1 maximum input voltage (RMS 5V audio supply − 1.0 1.3 Vrms
A.1.11 value) 8V audio supply − 1.0 1.4 Vrms
A.1.2 input resistance 24 32 − kΩ
A.1.3 gain from audio inputs to fixed DSG = 0 − 0 − dB
A.1.31 audio outputs (stereo versions) DSG = 1 − 6 − dB
A.1.4 gain from audio inputs to DSG = 0 − 6 − dB
A.1.41 AUDOUT output at maximum DSG = 1 − 12 − dB
volume (mono versions)
A.1.5 crosstalk between channels 5 V audio supply − tbf − dB
A.1.6 crosstalk between left and right 5 V audio supply − tbf − dB
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FIXED AUDIO OUTPUTS (STEREO AND AV STEREO VERSIONS)
A.2.1 maximum output signal 5V audio supply 1.0 − − Vrms
A.2.2 amplitude (RMS value) 8V audio supply 2.0 − − Vrms
A.2.3 output impedance − 500 650 Ω
A.2.4 total harmonic distortion at +6 dBV − tbf − dB
A.2.5 at -54 dBV; A-weighted − tbf − dB
A.2.6 signal-to-noise ratio referred to +6dBV output − tbf − dB
level; A-weighted
A.2.7 frequency range 20 − 15.000 Hz
ANALOGUE VOLUME CONTROLLED AUDIO OUTPUT(S)
A.3.1 controlled output signal 5 V audio supply; note 31 250 350 450 mV
A.3.11 amplitude (RMS value) 8 V audio supply; note 31 500 700 900 mV
A.3.2 output resistance − 500 − Ω
A.3.3 DC output voltage 5 V audio supply − 2.2 − V
A.3.31 8 V audio supply − 3.3 − V
A.3.4 total harmonic distortion note 32 − − 0.5 %
A.3.5 power supply rejection note 11 − 20 − dB
A.3.6 internal signal-to-noise ratio note 11 + 28 + 33 − 50 − dB
A.3.7 external signal-to-noise ratio note 11 + 33 − 60 − dB
A.3.8 control range see also Fig.53 − 70 − dB
A.3.9 suppression of output signal − 70 − dB
when mute is active
A.3.10 DC shift output during muting − 10 50 mV
ANALOGUE AUTOMATIC VOLUME LEVELLING; NOTE 34
A.4.1 gain at maximum boost − +6 − dB
A.4.2 gain at minimum boost − -14 − dB
A.4.3 charge (attack) current − 1 − mA
A.4.4 discharge (decay) current − 200 − nA
A.4.5 control voltage at maximum − 1 − V
boost
A.4.6 control voltage at minimum boost − 3 − V
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CVBS, Y/C and RGB/YUV/YPRPB INPUTS
CVBS-Y/C SWITCH
S.1.1 CVBS or Y input voltage note 35 − 1.0 1.4 V
S.1.2 CVBS or Y input current − 2 − µA
S.1.3 suppression of non-selected notes 11 and 36 50 − − dB
CVBS input signal
S.1.4 chrominance input voltage (burst note 5 and 37 − 0.3 1.0 V
amplitude)
S.1.5 chrominance input impedance − 50 − kΩ
CVBS OUTPUT ON CVBSO
S.1.9 output signal amplitude − 2.0 − V
S.1.10 top sync level − 0.5 − V
S.1.11 output impedance − − 50 Ω
EXTERNAL RGB / YUV / YPBPR INPUT
S.2.1 RGB input signal amplitude for note 38 − 0.7 0.8 V
an output signal of 1.2 V
(black-to-white) (peak-to-peak
value)
S.2.2 RGB input signal amplitude note 11 1.0 − − V
before clipping occurs
S.2.3 Y input signal amplitude input signal amplitude for an − 1.4/1.0 2.0 V
(peak-to-peak value) output signal of 1.2 V
S.2.4 U/PB input signal amplitude (black-to-white); when − −1.33/ 2.0 V
(peak-to-peak value) activated via the YUV2-YUV0 +0.7
bits; note 39
S.2.5 V/PR input signal amplitude − −1.05/ 1.5 V
(peak-to-peak value) +0.7
S.2.6 difference between black level of − − 20 mV
internal and external signals at
the outputs
S.2.7 input currents no clamping; note 5 − 0.1 1 µA
S.2.8 delay difference for the three note 11 − 0 20 ns
channels
BASE-BAND TINT CONTROL
S2.9 tint control range 63 steps; see Fig.56 − ±30 − deg
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FAST INSERTION
S.3.1 input voltage no insertion − − 0.4 V
S.3.2 insertion 0.9 − − V
S.3.3 maximum input pulse insertion − − 5.0 V
S.3.4 delay time from RGB in to insertion; note 11 − − 20 ns
RGB out
S.3.5 delay difference between insertion; note 11 − − 20 ns
insertion to RGB out and RGB in
to RGB out
S.3.6 input impedance − 500 − kΩ
S.3.7 suppression of internal RGB notes 11 and 36; insertion; − 55 − dB
signals fi = 0 to 5 MHz
S.3.8 suppression of external RGB notes 11 and 36; no − 55 − dB
signals insertion; fi = 0 to 5 MHz
YUV INTERFACE (COLOUR DIFFERENCE OUTPUT AND INPUT SIGNALS); NOTE 40
S.4.1 signal amplitude (R−Y) INTF = 1, note 5 0.94 1.05 1.16 V
S.4.2 signal amplitude (B−Y) INTF = 1, note 5 1.19 1.33 1.47 V
S.4.3 signal amplitude (PR) INTF = 0, note 5 0.63 0.7 0.77 V
S.4.4 signal amplitude (PB) INTF = 0, note 5 0.63 0.7 0.77 V
S.4.5 output impedance − 500 − Ω
YUV INTERFACE (LUMINANCE OUTPUT AND INPUT SIGNAL); NOTE 40
S.5.1 output signal amplitude top sync-white, INTF=0 tbf 1.0 tbf V
S.5.2 output signal amplitude top sync-white, INTF=1 tbf 1.4 tbf V
S.5.3 top sync level INTF=0 − 1.5 − V
S.5.4 top sync level INTF=1 − 1.4 − V
S.5.5 output impedance INTF=0 − 250 − Ω
S.5.6 output impedance INTF=1 − 250 − Ω
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PAL / NTSC Comb Filter
LUMINANCE SIGNAL
F.1.1 luminance gain error −1 0 +1 dB
F.1.2 -3 dB luminance bandwidth COMB mode, fSC = 4.43 MHz 6 − − MHz
F.1.3 COMB mode, fSC = 3.58 MHz 5 − − MHz
F.1.4 YC mode, fSC = 4.43 MHz 6 − − MHz
F.1.5 YC mode, fSC = 3.58 MHz 5 − − MHz
residues of clock frequencies in COMB mode
F.1.6 the luminance signal (Vrms/1V) f = 4 x fSC − − −30 dB
F.1.7 f = 2 x fSC − − −30 dB
F.1.8 f = 1.33 x fSC − − −30 dB
F.1.9 f = fSC − − −40 dB
F.1.10 cross talk suppression at vertical see note 41, vertical 26 − − dB
transient black ↔ multi-burst transition active video ↔
(1V/V (p-p)) vertical blanking, see the
figures 68 and 69.
suppression (comb depth) with fSC = 4.43 MHz; see Fig.70
F.1.11 respect to luminance band pass f = fSC 30 − − dB
nearest to fSC
F.1.12 f = ((283.75-74)/283.75)x fSC − 10 − dB
F.1.13 f = ((283.75+74)/283.75)x fSC − 10 − dB
PAL-M; see Fig.70
F.1.14 f = fSC 30 − − dB
F.1.15 f = ((227.25-59)/227.25)x fSC − 10 − dB
F.1.16 f = ((227.25+59)/227.25)x fSC − 10 − dB
PAL N; see Fig.70
F.1.17 f = fSC 30 − − dB
F.1.18 f = ((229.25-59)/229.25)x fSC − 10 − dB
F.1.19 f = ((229.25+59)/229.25)x fSC − 10 − dB
NTSC M, see Fig.70
F.1.20 f = fSC 30 − − dB
F.1.21 f = ((227.5-59)/227.5) x fSC − 10 − dB
F.1.22 f = ((227.5+59)/227.5) x fSC − 10 − dB
NTSC 4.4 MHz, see Fig.70
F.1.23 f = fSC 30 − − dB
F.1.24 f = ((281.75-74)/281.75) x fSC − 10 − dB
F.1.25 f = ((281.75+74)/281.75) x fSC − 10 − dB
Y DELAY ADJUSTMENT (VALID FOR PAL, NTSC AND SECAM)
F.1.26 tuning range delay time 8 steps; note 42 −150 − +150 ns
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CHROMINANCE SIGNAL
F.2.1 chrominance gain error −1 0 +1 dB
F.2.2 -3 dB chrominance bandwidth COMB mode, around fSC, 1.5 − − MHz
F.2.3 chrominance signal-to-noise unweighted; fSC±0.3fSC 56 − − dB
ratio (0.7V/Vrms noise)
residues of clock frequencies in COMB mode
F.2.4 the chrominance signal f = 4 x fSC − − −30 dB
(Vrms/0.7V)
F.2.5 f = 2 x fSC − − −30 dB
F.2.6 f = 1.33 x fSC − − −40 dB
F.2.7 f = fSC − − −50 dB
F.2.8 cross talk suppression at vertical see note 43, vertical 26 − − dB
transient no-colour ↔ colour transition active video ↔
(0.7V/V (p-p)) vertical blanking, see the
figures 68 and 69
suppression (comb depth) with fSC = 4,43 MHz; see Fig.71
F.2.9 respect to chrominance band f = (284/283.75) x fSC 30 − − dB
pass at f = fSC
F.2.10 f = ((284-74)/283.75) x fSC 30 − − dB
F.2.11 f = ((284+74)/283.75) x fSC 30 − − dB
PAL M, see Fig.71
F.2.12 f = (227/227.25) x fSC 30 − − dB
F.2.13 f = ((227-59)/227.25) x fSC 30 − − dB
F.2.14 f = ((227+59)/227.25) x fSC 30 − − dB
PAL N, see Fig.71
F.2.15 f = (229/229.25) x fSC 30 − − dB
F.2.16 f = ((229-59)/229.25) x fSC 30 − − dB
F.2.17 f = ((229+59)/229.25) x fSC 30 − − dB
NTSC M, see Fig.71
F.2.18 f = (227/227.5) x fSC 30 − − dB
F.2.19 f = ((227-59)/227.5) x fSC 30 − − dB
F.2.20 f = ((227+59)/227.5) x fSC 30 − − dB
NTSC 4.4 MHz, see Fig.71
F.2.21 f = (282/281.75) x fSC 30 − − dB
F.2.22 f = ((282-74)/281.75) x fSC 30 − − dB
F.2.23 f = ((282+74)/281.75) x fSC 30 − − dB
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Chrominance and Luminance filters
CHROMINANCE TRAP CIRCUIT; NOTE 44
F.3.1 trap frequency − fsc − MHz
F.3.2 Bandwidth at fSC = 3.58 MHz −3 dB − 2.7 − MHz
F.3.3 Bandwidth at fSC = 4.43 MHz −3 dB − 3.3 − MHz
F.3.4 colour subcarrier rejection 24 26 − dB
F.3.5 trap frequency during SECAM − 4.3 − MHz
reception
CHROMINANCE BANDPASS CIRCUIT
F.4.1 centre frequency (CB = 0) − fsc − MHz
F.4.2 centre frequency (CB = 1) − 1.1×fsc − MHz
F.4.3 bandpass quality factor − 3 −
CLOCHE FILTER
F.5.1 centre frequency CLO = 0 4.26 4.29 4.31 MHz
F.5.2 Bandwidth 241 268 295 kHz
Picture Improvement Features
PEAKING CONTROL; NOTE 45
P.1.1 width of preshoot or overshoot setting PF1/PF0 = 0/0 − 190 − ns
setting PF1/PF0 = 0/1 − 160 − ns
P.1.2 peaking signal compression − 50 − IRE
threshold
P.1.3 overshoot at maximum peaking positive, direction “white” − 45 − %
P.1.4 negative − 75 − %
P.1.5 Ratio negative/positive − 1.7 −
overshoot; note 46
P.1.6 peaking control curve 63 steps see Fig.54
P.1.7 peaking centre frequency setting PF1/PF0 = 0/0 − 2.7 − MHz
P.1.8 setting PF1/PF0 = 0/1 − 3.1 − MHz
CORING STAGE; NOTE 47
P.1.10 coring range − 10 − IRE
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BLACK LEVEL STRETCHER; NOTE 48
P.2.1 Maximum black level shift BSD = 0 25 30 35 IRE
P.2.11 Maximum black level shift BSD = 1 10 15 20 IRE
P.2.2 level shift at 100% peak white −1 0 1 IRE
P.2.3 level shift at 50% peak white −1 − 3 IRE
P.2.4 level shift at 15% peak white BSD = 0 10 12 14 IRE
P.2.5 level shift at 15% peak white BSD = 1 4 6 8 IRE
DYNAMIC SKIN TONE (FLESH) CONTROL; NOTE 49
P.4.1 control angle − 123 − deg
P.4.32 correction range (angle) − 45 − deg
GAMMA CONTROL; NOTE 50
P.6.1 break point of characteristic maximum white is 100% 40 50 60 %
P.6.2 maximum expansion set by the bits WS1/WS0 6 8 12 %
P.6.3 mismatch for YIN = 100 IRE at maximum expansion −2 − +8 IRE
P.6.4 mismatch for YIN = 0 IRE at maximum expansion −2 − +4 IRE
BLUE STRETCH; NOTE 51
P.7.1 increase of small signal gain for BLS = 1 − 20 − %
the blue channel
P.7.2 decrease of small signal gain for BLS = 1 − 20 − %
the red channel
DC TRANSFER RATIO OF LUMINANCE SIGNAL; NOTE 52
P.8.1 reduction of black level for white TFR = 1 − 10 − IRE
picture (100 IRE)
SCAN VELOCITY MODULATION OUTPUT; NOTES 53 AND 54
P.9.1 output signal amplitude VMA1/VMA0 = 1/1 − 1.5 − V
(peak-to-peak value
SMD1/SMD0 = 0/1
P.9.11 output signal amplitude VMA1/VMA0 = 1/1 − 1.8 − V
(peak-to-peak value
SMD1/SMD0 = 1/0
P.9.2 delay of RGB output signal with SVM2-SVM0 = 000, PF1-PF0 − 170 − ns
respect to SVM output = 01 (peaking frequency of
3.1 MHz) and 50% input
signal amplitude
P.9.3 coring range CRA0 = 0 − 8 − %
P.9.4 maximum DC-current through VMA1/VMA0 = 0/0 − 100 − µA
the SVM output
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Horizontal and vertical synchronization and drive circuits
SYNC VIDEO INPUT
H.1.1 sync pulse amplitude note 5 50 300 350 mV
H.1.2 slicing level for horizontal sync note 55 − 45 − %
H.1.3 slicing level for vertical sync note 55 − 35 − %
HORIZONTAL OSCILLATOR
H.2.1 free running frequency − 15625 − Hz
H.2.2 spread free running frequency − − ±2 %
H.2.3 frequency variation with respect VP = 8.0 V ±10%; note 11 − 0.2 0.5 %
to the supply voltage
H.2.4 frequency variation with Tamb = 0 to 70 °C; note 11 − − 80 Hz
temperature
FIRST CONTROL LOOP; NOTE 56
H.3.1 holding range PLL − ±0.8 ±1.1 kHz
H.3.2 catching range PLL note 11 ±0.5 ±0.8 − kHz
H.3.3 S/N ratio video input signal to − 24 − dB
switch the time constant
H.3.4 hysteresis at the switching point − 3 − dB
SECOND CONTROL LOOP
H.4.1 control sensitivity − 150 − µs/µs
H.4.2 control range from start of − 19 − µs
horizontal output to flyback at
nominal shift position
H.4.3 horizontal shift range 63 steps ±2 − − µs
H.4.4 control sensitivity for dynamic − 13 − µs/V
compensation
H.4.5 Voltage to switch-on the ‘flash’ note 57 4.0 − − V
protection
H.4.6 Input current during protection − − 1 mA
H.4.7 control range parallelogram note 58 − ±0.75 − µs
correction
H.4.8 control range bow correction note 58 − ±1.0 − µs
HORIZONTAL OUTPUT; NOTE 59
H.5.1 LOW level output voltage IO = 10 mA − − 0.3 V
H.5.2 maximum allowed output current 10 − − mA
H.5.3 maximum allowed output voltage − − VP V
H.5.4 duty factor VOUT = LOW (TON); SDC = 0 − 55 − %
H.5.41 duty factor VOUT = LOW (TON); SDC = 1 − 60 − %
H.5.5 switch-on time horizontal drive − 1175 − ms
pulse
H.5.6 switch-off time horizontal drive − 43 − ms
pulse
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FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT
H.6.1 required input current during note 5 100 − 300 µA
flyback pulse
H.6.2 output voltage during burst key 4.5 5.0 5.5 V
during blanking 2.8 3.0 3.2 V
H.6.3 clamped input voltage during 1.7 2.0 2.3 V
flyback
H.6.4 pulse width burst key pulse 3.3 3.5 3.7 µs
H.6.5 vertical blanking, note 60 − 14/9.5 − lines
H.6.6 delay of start of burst key to start 4.8 5.0 5.2 µs
of sync
H.6.7 output voltage of H/V timing CSY = 1 − tbf − V
signal
VERTICAL OSCILLATOR; NOTE 61
H.7.1 free running frequency − 50/60 − Hz
H.7.2 locking range 45 − 64.5/72 Hz
H.7.3 divider value not locked − 625/525 − lines
H.7.4 locking range 434/488 − 722 lines/
frame
VERTICAL RAMP GENERATOR
H.8.1 sawtooth amplitude VS = 1FH; − 1.8 − V
(peak-to-peak value) C = 150 nF; R = 39 kΩ
H.8.2 discharge current − 1 − mA
H.8.3 charge current set by external note 62 − 14 − µA
resistor
H.8.4 vertical slope 63 steps; see Fig. 88 −20 − +20 %
H.8.5 charge current increase f = 60 Hz − 19 − %
H.8.6 LOW level of ramp − 1.5 − V
VERTICAL DRIVE OUTPUTS
H.9.1 differential output current VA = 1FH − 1.0 − mA
H.9.2 common mode current − 400 − µA
H.9.3 output voltage range 0 − 2.5 V
EHT TRACKING/OVERVOLTAGE PROTECTION
H.10.1 input voltage 1.2 − 2.8 V
H.10.2 scan modulation range −5 − +5 %
H.10.3 vertical sensitivity − 6.3 − %/V
H.10.4 EW sensitivity when switched-on − −6.3 − %/V
H.10.5 EW equivalent output current +120 − −120 µA
H.10.6 overvoltage detection level note 57 − 3.9 − V
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DE-INTERLACE
H.11.1 first field delay − 0.5H −
EW WIDTH; NOTE 63
H.12.1 control range 63 steps; see Fig. 91 100 − 65 %
H.12.2 equivalent output current 0 − 700 µA
H.12.3 EW output voltage range 1.0 − 5.0 V
H.12.4 EW output current range 0 − 1200 µA
EW PARABOLA/WIDTH
H.13.2 equivalent output current EW=3FH; CP=11H; TC=1FH 0 − 460 µA
EW UPPER/LOWER CORNER/PARABOLA
H.14.1 control range 63 steps; see Fig. 93 −55 − +55 %
H.14.2 equivalent output current PW=3FH; EW=3FH; TC=1FH −262 − +262 µA
EW TRAPEZIUM
H.15.2 equivalent output current EW=1FH; CP=11H; PW=1FH −100 − +100 µA
VERTICAL AMPLITUDE
H.16.2 equivalent differential vertical SC = 0EH 800 − 1200 µA
drive output current
VERTICAL SHIFT
H.17.2 equivalent differential vertical −50 − +50 µA
drive output current
S-CORRECTION
H.18.1 control range 63 steps; see Fig. 90 −10 − 25 %
VERTICAL LINEARITY
H.18.2 control range, ratio bottom/top of 63 steps; see Fig. 95; 85 − 117 %
screen (full screen linearity VSH=1FH; SC=0;
setting) VL1/VL0=0/0
VERTICAL ZOOM MODE (OUTPUT CURRENT VARIATION WITH RESPECT TO NOMINAL SCAN); NOTE 64
H.19.1 vertical expand factor 0.75 − 1.38
H.19.2 output current limiting and RGB − 1.05 −
blanking
VERTICAL SCROLL
H.20.1 Control range (percentage of vertical zoom setting at 3FH −18 − 19 %
nominal visible picture
amplitude)
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Colour demodulation part
CHROMINANCE AMPLIFIER
D.1.1 ACC control range note 65 26 − − dB
D.1.2 change in amplitude of the − − 2 dB
output signals over the ACC
range
D.1.3 threshold colour killer ON CHSE1/CHSE0 = 0/0 −30 − − dB
D.1.4 hysteresis colour killer OFF strong signal conditions; − +3 − dB
S/N ≥ 40 dB; note 11
D.1.5 noisy input signals; note 11 − +1 − dB
ACL CIRCUIT; NOTE 66
D.2.1 chrominance burst ratio at which − 3.0 −
the ACL starts to operate
REFERENCE PART
Phase-locked loop
D.3.1 catching range all standards ±500 − − Hz
D.3.2 phase shift for a ±400 Hz note 11 − − 2 deg
deviation of the oscillator
frequency
HUE CONTROL
D.5.1 hue control range 63 steps; see Fig.55 ±35 ±40 − deg
D.5.2 hue variation for ±10% VP note 11 − 0 − deg
D.5.3 hue variation with temperature Tamb = 0 to 70 °C; note 11 − 0 − deg
DEMODULATORS
General
D.6.3 spread of signal amplitude ratio note 11 −1 − +1 dB
between standards
D.6.5 bandwidth of demodulators −3 dB; note 67 − 650 − kHz
PAL/NTSC demodulator
D.6.6 gain between both demodulators INTF = 0 1.26 1.41 1.58
G(B−Y) and G(R−Y)
D.6.12 change of output signal note 11 − 0.1 − %/K
amplitude with temperature
D.6.13 change of output signal note 11 − − ±0.1 dB
amplitude with supply voltage
D.6.14 phase error in the demodulated note 11 − − ±5 deg
signals
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SECAM demodulator
D.7.1 black level off-set SBO1/SBO0 = 1/0 − − 7 kHz
D.7.2 pole frequency of deemphasis 77 85 93 kHz
D.7.3 ratio pole and zero frequency − 3 −
D.7.4 non linearity − − 3 %
D.7.5 calibration voltage 1.8 2.3 2.8 V
Base-band delay line
D.8.1 variation of output signal for −0.1 − 0.1 dB
adjacent time samples at
constant input signals
D.8.2 residual clock signal − − 5 mV
D.8.3 delay of delayed signal 63.94 64.0 64.06 µs
D.8.4 delay of non-delayed signal 40 60 80 ns
D.8.5 difference in output amplitude − − 5 %
with delay on or off
COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT)
PAL/SECAM mode; (R−Y) and (B−Y) not affected
D.9.1 ratio of demodulated signals − −0.51 −
(G−Y)/(R−Y) ±10%
D.9.2 ratio of demodulated signals − −0.19 −
(G−Y)/(B−Y) ±25%
NTSC mode; the matrix results in the following signals (nominal hue setting)
MUS-bit = 0
D.9.6 (B−Y) signal: 2.03/0° 2.03UR
D.9.7 (R−Y) signal: 1.59/95° −0.14UR + 1.58VR
D.9.8 (G−Y) signal: 0.61/240° −0.31UR − 0.53VR
MUS-bit = 1
D.9.9 (B−Y) signal: 2.03/0° 2.03UR
D.9.10 (R−Y) signal: 1.59/102° −0.24UR + 1.55VR
D.9.11 (G−Y) signal: 0.61/236° −0.31UR − 0.51VR
REFERENCE SIGNAL OUTPUT/SWITCH OUTPUT; NOTE 68
D.10.1 reference frequency CMB1/CMB0 = 01 3.58/4.43 MHz
D.10.2 output signal amplitude CMB1/CMB0 = 01 0.2 0.25 0.3 V
D.10.3 output level (mid position) CMB1/CMB0 = 01 1.9 2.1 2.3 V
D.10.4 SWO output level LOW CMB1/CMB0 = 10 − − 0.8 V
D.10.5 SWO output level HIGH CMB1/CMB0 = 11 4.5 − − V
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Control part
SATURATION CONTROL; NOTE 38
C.1.1 saturation control range 63 steps; see Fig.57 52 − − dB
CONTRAST CONTROL; NOTE 38
C.2.1 contrast control range 63 steps; see Fig.58 − 20 − dB
C.2.2 tracking between the three − − 0.5 dB
channels over a control range of
10 dB
C.2.6 contrast reduction − 10 − dB
BRIGHTNESS CONTROL
C.3.1 brightness control range 63 steps; see Fig.59 − ±0.4 − V
RGB AMPLIFIERS
C.4.1 output signal amplitude at nominal luminance input − 1.2 − V
(peak-to-peak value) signal, nominal settings for
contrast, white-point
adjustment and cathode drive
level(CL3-CL0 = 7H)
C.4.101 output signal control range due 0.5 − 2.5 V
to the CCC gain loop
C.4.2 maximum signal amplitude note 69 − 3.0 − V
(black-to-white)
C.4.3 maximum peak white level − 4.0 − V
C.4.4 output signal amplitude for the at nominal settings for − 1.26 − V
‘red’ channel (peak-to-peak contrast and saturation
value) control and no luminance
signal to the input (R−Y, PAL)
C.4.41 output impedance − 300 − Ω
C.4.5 nominal black level voltage − 1.65 − V
C.4.6 black level voltage when black level stabilisation − 1.65 − V
is switched-off (via AKB bit)
C.4.61 black level voltage control range AVG bit active; note 70 1.0 1.65 2.3 V
C.4.71 timing of wide blanking with start of blanking; WBI = 0 3.5 − 5.9 µs
C.4.72 respect to mid sync (HBL = 1); end of blanking; WBI = 0 7.8 − 10.2 µs
note 71
C.4.73 start of blanking; WBI = 1 9.7 − 12.1 µs
C.4.74 end of blanking; WBI = 1 14.0 − 16.4 µs
C.4.8 control range of the black-current − ±0.65 − V
stabilisation
C.4.81 RGB output level when RGBL=1 − 0.8 − V
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C.4.9 blanking level difference with black level, − −0.3 − V
C.4.91 blanking level when RBL = 1 note 69 − −1.1 − V
C.4.10 level during leakage test − −0.07 − V
C.4.11 level ‘low’ measuring pulse − 0.15 − V
C.4.12 level ‘high’ measuring pulse − 0.6 − V
(current setting 220 µA); note 72
C.4.13 adjustment range of the cathode note 69 − ±3 − dB
drive level
C.4.14 variation of black level with note 11 − − 1.0 mV/K
temperature
C.4.141 black level off-set adjustment on 63 steps − ±100 − mV
the Red and Green channel
C.4.21 signal-to-noise ratio of the output RGB input; note 73 60 − − dB
C.4.22 signals CVBS input; note 73 50 − − dB
C.4.23 residual voltage at the RGB at fosc − − 15 mV
C.4.24 outputs (peak-to-peak value) at 2fosc plus higher harmonics − − 15 mV
C.4.25 bandwidth of output signals RGB input; at −3 dB − 7 − MHz
C.4.26 CVBS input; at −3 dB; − 2.8 − MHz
fosc = 3.58 MHz
C.4.27 CVBS input; at −3 dB; − 3.4 − MHz
fosc = 4.43 MHz
C.4.28 S-VHS input; at −3 dB 5 − − MHz
WHITE-POINT ADJUSTMENT
C.5.1 I2C-bus setting for nominal gain HEX code − 20H −
C.5.2 adjustment range of the relative − ±3 − dB
R, G and B drive levels
2-POINT BLACK-CURRENT STABILIZATION, NOTES 74
C.6.1 amplitude of ‘low’ reference − 10 − µA
current
C.6.2 amplitude of ‘high’ reference SLG0/SLG1 = 0/0 − 220 − µA
current; note 72
C.6.3 acceptable leakage current − ±75 − µA
C.6.4 input impedance during scan − 500 − kΩ
BEAM CURRENT LIMITING
C.7.1 contrast reduction starting − 2.8 − V
voltage
C.7.2 voltage difference for full contrast − 1.8 − V
reduction
C.7.3 brightness reduction starting CBS = 0 − 1.7 − V
voltage
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C.7.31 brightness reduction starting CBS = 1 − 2.4 − V
voltage
C.7.4 voltage difference for full − 0.9 − V
brightness reduction
C.7.5 internal bias voltage − 3.3 − V
C.7.8 maximum allowable current − 1 − mA
FIXED BEAM CURRENT SWITCH-OFF; NOTE 75
C.8.1 discharge current during 0.85 1.0 1.15 mA
switch-off
C.8.2 discharge time of picture tube − 38 − ms
PEAK WHITE LIMITER AND SOFT CLIPPING; NOTES 76 AND 77
C.9.1 CVBS signal amplitude at which PWL range (15 steps); at 0.40 − 0.60 V
peak white limiter is activated max. contrast
(black-to-white value)
C.9.2 soft clipper gain reduction maximum contrast; note 77, − 8 − dB
see Fig.84
General purpose switch output SWO1 (controlled by SWO1 bit)
O.1.1 output voltage HIGH 3.5 5.0 5.5 V
O.1.2 output voltage LOW − 0.2 0.4 V
O.1.3 sink current 2 − − mA
O.1.4 source current 2 − − mA
Vertical guard input and LED drive output; note 78
I/O.1.1 output voltage HIGH vertical guard activated − 3.3 − V
I/O.1.2 output voltage HIGH vertical guard not activated − − 5.5 V
I/O.1.3 output voltage LOW − 0.2 0.4 V
I/O.1.4 sink current 2 − − mA
I/O.1.5 detection level for vertical guard tbf 3.6 tbf V
and input port
Notes
1. When the 3.3 V supply is present and the µ-Controller is active a ‘low-power start-up’ mode can be activated. When
all subaddress bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be
switched-on via the STB-bit (subaddress 3DH). In this condition the horizontal drive signal has the nominal TOFF and
the TON grows gradually from zero to the nominal value. As soon as the 5 V supply is present the switch-on procedure
(e.g. closing of the second loop) is continued.
2. The various parameters in this specification are guaranteed for a supply voltage range between 4.75 V and 5.5 V.
For supply voltages between 4.5 V and 4.75 v some output signals may be distorted or clipped, however, the
operation of the circuit is not affected at these supply voltages.
3. The supply voltage of the analogue audio part may have a value between 5V and 8V. For a supply voltage of 5V the
maximum amplitude of the output signals is 1Vrms. For a supply voltage of 8V the maximum amplitude of the output
signals is 2Vrms.
4. On set AGC.
5. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
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6. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
FPLL input signal level).
7. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
digital control circuit which uses the clock frequency of the µ-Controller as a reference. The required IF frequency for
the various standards is set via the IFA-IFC bits in subaddress 2FH. When the system is locked the resulting IF
frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
8. Measured at 10 mV (RMS) top sync input signal.
9. So called projected zero point, i.e. with switched demodulator.
10. Measured in accordance with the test line given in Fig.60. For the differential phase test the peak white setting is
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
11. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
12. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.61.
13. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal)
14. The test set-up and input conditions are given in Fig.62. The figures are measured with an input signal of
10 mV RMS. This test can only be carried out in a test set-up in which the test options of the IC can be activated.
This because the IF-AGC control input is not available in this IC.
15. Measured at an input signal of 10 mVRMS. The S/N is the ratio of black-to-white amplitude to the black level noise
voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567.
16. Via this pin both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.
The pin can also be used as CVBS input. The selection between both signals is realised by means of the SVO bits
in subaddress 39H.
17. The cascade of sound trap and group delay correction filter compensates for the group delay pre-distortion of the BG
standard, curve A (see “Rec. ITU-R BT.470-4”). The indicated values are the difference between the group delay at
4.43 MHz and the group delay at 10 kHz.
18. The time-constant of the IF-AGC is internal and the speed of the AGC can be set via the bits AGC1 and AGC0 in
subaddress 30H. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The
values given are valid for the ‘norm’ setting (AGC1-AGC0 = 0-1) and when the PLL is in lock.
19. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses the
clock frequency of the TCG µ-Controller as a reference and is therefore very accurate. For this reason no maximum
and minimum values are given for the window sensitivity figures (parameters M.7.2 and M.7.3). The tuning
information is supplied to the tuning system via the AFC bits in output byte 04H. The AFC value is valid only when
the LOCK-bit is 1.
20. The QSS IF circuit can also be used for the preprocessing of digital TV signals. The modulated signal has to be
supplied to the sound IF input (via a suitable filter) and the mixed down I-signal is available at the DVB outputs.
The AGC has two modes of operation: the internal mode in which the IC sets the gain with its own reference and an
external mode in which the gain can be controlled with an external circuit. In the second case the QSS-IF AGC pin
is used as an input to control the IF gain with an external circuit.
21. The reference signal for the I-mixer (frequency 43.008 or 49.152 MHz) is internally generated. It is also possible to
supply an external reference signal to the mixer. This external mode is activated by means of the CMB2-CMB0 and
IFD bits. The signal has to be supplied to the pin which is normally used as the reference signal output of the colour
decoder (REFO).
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22. The weighted S/N ratio is measured under the following conditions:
a) The vision IF modulator must meet the following specifications:
Incidental phase modulation for black-to-white jumps less than 0.5 degrees.
QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio) better
than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation.
Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter).
b) The measurements must be carried out with the Siemens SAW filters G3962 for vision IF and G9350 for sound
IF. Input level for sound IF 10 mVRMS with 27 kHz deviation.
c) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filter
PC/SC ratio. This PC/SC ratio is necessary to achieve the S/N(W) values as indicated.
23. The input should be shunted with a resistor of 470 Ω - 10 kΩ
24. If a 10.7MHz FM radio IF signal is supplied to the external 2nd SIF input, an external 10.7MHz bandpass filter must
be used.
25. f = 4.5/5.5 MHz; FM: 70 Hz, ± 50 kHz deviation; AM: 1.0 kHz, 30% modulation.
26. f = 5.5 MHz; modulation frequency: 1 kHz, ∆f = ± 27 kHz.
27. Depending on the application (FM or AM reception) the amplitude of the output signal can be increased with 6 dB by
the AGN bit in subaddress 33H (FM reception) or AMLOW bit in subaddress 35H (AM reception). The resulting output
signal amplitudes are given in Table 268.
28. The signal-to-noise ratio is measured under the following conditions:
a) Input signal to the SSIF pin (activated via the CMB2-CMB0 bits) with an amplitude of 100mVRMS, fMOD = 1 kHz
and ∆f = 27 kHz
b) Output signal measured at the AUDEEM pin. The noise (RMS value) is measured according to the CCIR 468
definition.
29. In the “Mono” versions the deemphasis pin can also be used as additional audio input. In that case the internal
(demodulated FM signal) must be switched off. This can be realised by means of the SM (sound mute) bit. When the
vision IF amplifier is switched to positive modulation the signal from the FM demodulator is automatically switched
off. The external signal must be switched off when the internal signal is selected.
30. The “Stereo” and “AV Stereo” versions have 4 stereo inputs. The maximum output signal amplitude of the selector
(1.0 VRMS or 2.0 VRMS) is dependent on the supply voltage (5 V or 8 V) of the audio selector supply pin (VCC8V).
31. Audio attenuator at −6 dB, input signal 500 mVRMS
32. Audio input signal 200 mVRMS. Measured with a bandwidth of 15 kHz and the audio attenuator at −6 dB.
33. Unweighted RMS value, audio input signal 500 mVRMS, audio attenuator at −6 dB.
34. In versions without stereo decoder and digital sound processing circuits an analogue Automatic Volume Levelling
(AVL) function can be activated. The pin to which the external capacitor has to be connected can be chosen by
means of the AVLE bit (subaddress 34H). When the East-West output is not used (90° picture tubes) the capacitor
can be connected to the EW output pin. In 110° applications a choice has to be made between the AVL function and
a sub-carrier output / general purpose switch output. The selection must be made by means of the CMB0 to CMB2
bit in subaddress 4AH. More details about the sub-carrier output are given in the parameters D.10.
The Automatic Volume Levelling (AVL) circuit stabilises automatically the audio output signal to a certain level which
can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation
of the modulation depth of the transmitter. The AVL can be switched on and off via the AVL bit in subaddress 34H.
The AVL is active over an input voltage range (measured at the deemphasis output) of 50 to 1500 mVRMS. The AVL
control curve is given in Fig.65. The control range of +6 dB to −14 dB is valid for input signals with 50% of the
maximum frequency deviation.
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35. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
36. This parameter is measured at nominal settings of the various controls.
37. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1).
38. The contrast and saturation control is active on the internal signal (YUV) and on the external RGB/YUV/YPRPB input.
The Text/OSD input can be controlled on brightness only. Nominal contrast is specified with the DAC in position 20
HEX. Nominal saturation as maximum −10 dB.
39. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation.
40. Depending on the setting of the INTF bit (subaddress 42H) the saturation of the output signal is 75% (YUV signal)
or 100% (YPRPB signal). The luminance and colour difference out- and inputs can directly be connected. When
additional picture improvement ICs (like the TDA 9178) are applied the inputs of these ICs must be ac coupled
because of the black level clamp requirement. The output signal of the picture improvement IC can directly be
coupled to the luminance and colour difference inputs as long as the dc level of these signals have a value between
1 and 4 V (for the luminance signal) or between 1 and 4 V (for the UV signals). When the dc level of the input signals
exceed these levels the signals must be ac coupled and biased to a voltage level within these limits.
41. Test signal:
For PAL B, G, H, D, I and N: CCIR-18 multi-burst (see Fig. 66).
For PAL M and NTSC M: 100% amplitude FCC multi-burst (see Fig. 67).
42. This control range is valid for a colour carrier frequency of 4.43 MHz. For a colour carrier frequency of 3.58 MHz the
control range has a value of ± 190 µs (see also Table 132).
43. Test signal:
For PAL B, G, H, D, I and N: 100/0/75/0 EBU colour bar.
For PAL M and NTSC M: 100% white 75% amplitude FCC colour bar.
44. When the decoder is forced to a fixed subcarrier frequency (via the CM-bits) the chroma trap is always switched-on,
also when no colour signal is identified. In the automatic mode the chroma trap is switched-off when no colour signal
is identified.
45. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.
46. The ratio between the positive and negative peaks can be varied by means of the bits RPO1 and RPO0 in
subaddress 47H. For ratios which are smaller than 1.7 the positive peak is not affected and the negative peak is
reduced.
47. The coring can be activated in the low-light part of the picture. This effectively reduces the noise while having
maximum peaking in the bright parts of the picture. The setting the video content at which the coring is active can be
adapted by means of the COR1/COR0 bits in subaddress 47H.
48. For video signals with a black level which deviates from the back-porch blanking level the signal is “stretched” to the
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.72). The black level is
detected by means of an internal capacitor. The black level stretcher can be switched on and off via the BKS bit in
subaddress 45H. The values given in the specification are valid only when the luminance input signal has an
amplitude of 1 Vp-p.
49. The Dynamic Skin Tone Correction circuit is designed such that it corrects (instantaneously and locally) the hue of
those colours which are located in the area in the UV plane that matches to skin tones. The correction is dependent
on the luminance, saturation and distance to the preferred axis. Because the amount of correction is dependent on
the parameters of the incoming YUV signal it is not possible to give exact figures for the correction angle. The
correction angle of 45 (±22.5) degrees is just given as an indication and is valid for an input signal with a luminance
signal amplitude of 75% and a colour saturation of 50%. A graphical representation of the control behaviour is given
in Figure 73 on page 229.
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50. The gamma control is realised by inserting a non-linear transfer characteristic in the luminance path. The shape of
the curve can be adapted by means of the WS1/WS0 bits in subaddress 45H. The control curves are given in Fig. 74.
It is possible to make the gamma control dependent on the Average Picture Level (APL). This function is identical to
the previous white stretch function. Then the GAM bit (subaddress 44H) must be set to “0”. The control curve can
again be adapted by means of the WS1/WS0 bits (see also Fig. 75). When the gamma control is active the colour
saturation is adapted to the variation of the luminance linearity.
51. Via the ‘blue stretch’ (BLS bit) function the colour temperature of the bright scenes (amplitudes which exceed a value
of 80% of the nominal amplitude) can be increased. This effect is obtained by increasing the small signal gain of the
blue channel and decreasing the small signal gain for the red channel for signals which exceed the 80% level. The
effect is illustrated in Figure 76 on page 230.
52. When this function is activated (TFR = 1) the black level of the RGB output signals is dependent on the average
picture information. For a ‘black’ picture the black level is unaffected and the maximum black level shift for a complete
‘white’ picture (100 IRE) is 10 IRE in the direction ‘black’. The black level shift is linearly dependent on the picture
content.
53. The SVM is specified for a 2T-pulse input signal with an amplitude (100%) of 700 mVP-P. The coring system on the
SVM output signal has to levels. The SVM output signal amplitude is dependent on the setting of the coring and on
SVMA (see Fig. 77).
54. The delay between the RGB output signals and the SVM output signal can be adjusted (by means of the
SVM2-SVM0 bits in subaddress 48H) so that an optimum picture performance can be obtained. Furthermore a video
dependent coring function can be activated. Another feature is that the SVM output signal can be made dependent
on the horizontal position on the screen (parabola on the SVM output). The screen is equally divided into 6 parts (see
Fig. 78). By multiplying a gain factor with the SVM output signal as a function of the horizontal position several
discrete curves can be made. The shape of the curve can be programmed by means of the SPR2-SPR0 bits (in
subaddress 48H).
55. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
level and the top sync level. When the amplitude of the sync pulse exceeds the value of 350 mV the sync separator
will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 0.4 Vp-p. By
means of the SSL bit (subaddress 3FH) the slicing level can be changed to 30% (SSL = 1).
The vertical slicing level is dependent on the S/N ratio of the incoming video signal. For a S/N ≤ 24 dB the slicing
level is 35%, for a S/N ≥ 24 dB the slicing level is 60%. With the bit FSL (Forced Slicing Level) the vertical slicing
level can be forced to 60%.
56. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the POC, FOA, FOB and VID bits in
subaddress 3DH. The circuit contains a noise detector and the time constant is switched to ‘slow’ when too much
noise is present in the signal. In the ‘fast’ mode during the vertical retrace time the phase detector current is increased
50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching of the time
constant can be automatically or can be set by means of the control bits.
The circuit contains a video identification circuit which is independent of the first loop. This identification circuit can
be used to close or open the first control loop when a video signal is present or not present on the input. This enables
a stable On Screen Display (OSD) when just noise is present at the input.
To prevent that the horizontal synchronisation is disturbed by anti copy signals like Macrovision the phase detector
is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width
of the gate pulse is about 22 µs. During weak signal conditions (noise detector active) the gating is active during the
complete scan period and the width of the gate pulse is reduced to 5.7 µs so that the effect of noise is reduced to a
minimum.
The output current of the phase detector in the various conditions are shown in Table 269.
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57. The ICs have 2 protection inputs. The protection on the second phase detector pin is intended to be used as ‘flash’
protection. When this protection is activated the horizontal drive is switched-off immediately and then switched-on
again via the slow start procedure.
The protection on the EHT input is intended for overvoltage (X-ray) protection. When this protection is activated the
horizontal drive is directly switched-off (via the slow stop procedure).
The EHT protection input can also be used to switch-off the TV receiver in a correct way when it is switched off via
the mains power switch or when the power supply is interrupted by pulling the mains plug. This can be realised by
means of a detection circuit which monitors the main supply voltage of the receiver. When this voltage suddenly
decreases the EHT protection input must be pulled HIGH and then the horizontal drive is switched off via the slow
stop procedure. Whether the EHT capacitor is discharged in the overscan or not during the switch-off period depends
on the setting of the OSO bit (subaddress 3EH, D4). See also note 75.
58. The control range indicates the maximum phase difference at the top and the bottom of the screen. Compared with
the phase position at the centre of the screen the maximum phase difference at the top and the bottom of the screen
is ±0.75 µs for the parallelogram and ±1.0 µs for the bow correction.
59. During switch-on the horizontal drive starts-up in a soft-start mode. The horizontal drive starts with a very short TON
time of the horizontal output transistor, the ‘off time’ of the transistor is identical to the ‘off time’ in normal operation.
The starting frequency during switch-on is therefore about 2 times higher than the normal value. The ‘on time’ is
slowly increased to the nominal value in a time of about 1175 ms (see Fig.81). The rather slow rise of the TON
between 75% and 100% of TON is introduced to obtain a sufficiently slow rise of the EHT for picture tubes with
Dynamic Astigmatic Focus (DAF) guns. When the nominal frequency is reached the PLL is closed in such a way that
only very small phase corrections are necessary. This ensures a safe operation of the output stage.
During switch-off the soft-stop function is active. This is realised by doubling the frequency of the horizontal output
pulse. The switch-off time is about 43 ms (see Fig.81). When the ‘switch off command’ is received the soft-stop
procedure is started after a delay of about 2 ms. During the switch-off time the EHT capacitor of the picture tube is
discharged with a fixed beam current which is forced by the black current loop (see also note 75). The discharge time
is about 38 ms.
The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on
during the flyback time.
60. The vertical blanking pulse in the RGB outputs has a width of 27 or 22 lines (50 or 60 Hz system). The vertical pulse
in the sandcastle pulse has a width of 14 or 9.5 lines (50 or 60 Hz system). This to prevent a phase distortion on top
of the picture due to a timing modulation of the incoming flyback pulse.
61. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
During TV reception this divider circuit has 3 modes of operation:
a) Search mode ‘large window’.
This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines
per frame outside the range between 311 and 314(50 Hz mode) or between 261 and 264 (60 Hz mode) is
received). In the search mode the divider can be triggered between line 244 and line 361 (approximately
45 to 64.5 Hz).
b) Standard mode ‘narrow window’.
This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
The IVWF bit in output byte 03 is set to “1” when 7 succeeding vertical sync pulses are detected in the narrow
window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical
ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small.
The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found
within the window.
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c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).
When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are
in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched
to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical
sync pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit
in subaddress 3EH.
When RGB signals are inserted the maximum vertical frequency is increased to 72 Hz. This has the consequence
that the circuit can also be synchronised by signals with a higher vertical frequency like VGA.
62. Conditions: frequency is 50 Hz; normal mode; VS = 1F.
63. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 µA
variation in E-W output current is equivalent to 20% variation in picture width.
64. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason an extra DAC
has been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38
of the nominal scan. At an amplitude of 1.06 of the nominal scan the output current is limited and the blanking of the
RGB outputs is activated. This is illustrated in Fig. 79.
When the vertical amplitude is compressed (zoom factor <1) it is still possible to display the black-current measuring
lines in the vertical overscan. The feature is activated by means of the OSVE-bit in subaddress 40H. Because the
vertical deflection output stage needs some time for the excursion from the top of the picture to the required position
on the screen the vertical blanking is increased when the OSVE-bit is activated. The shape of the vertical deflection
current for a zoom factor of 0.75 with OSVE activated is given in Fig. 80. The exact timing of the measuring pulses
and vertical blanking for the various conditions is given in Fig. 82.
The nominal scan height must be adjusted at a position of 19 HEX of the vertical ‘zoom’ DAC.
65. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)) the dynamic range of the ACC is +6 and −20 dB.
66. The ACL function can be activated by via the ACL bit in the subaddress 3BH. The ACL circuit reduces the gain of
the chroma amplifier for input signals with a chroma-to-burst ratio which exceeds a value of 3.0.
67. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass
filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.
68. The subcarrier output is combined with a 3-level switch output which can be used to switch external circuits like
sound traps etc. This output is controlled by the CMB1 and CMB0 bits in control byte 22H. The subcarrier signal is
available when CMB1/0 are set to 0/1. During the demodulation of SECAM signals the subcarrier signal is only
available during the vertical retrace period. The frequency is 4.43 MHz in this condition.
69. Because of the 2-point black current stabilization circuit both the black level and the amplitude of the RGB output
signals depend on the drive characteristic of the picture tube. The system checks whether the returning measuring
currents meet the requirement and adapts the output level and gain of the circuit when necessary. Therefore the
typical value of the black level and amplitude at the output are just given as an indication for the design of the RGB
output stage.
The 2-point black level system adapts the drive voltage for each cathode in such a way that the 2 measuring currents
have the right value. This has the consequence that a change in the gain of the output stage will be compensated
by a gain change of the RGB control circuit. Because different picture tubes may require different drive voltage
amplitudes the ratio between the output signal amplitude and the inserted measuring pulses can be adapted via the
I2C-bus. This is indicated in the parameter C.4.13.
Because of the dependence of the output signal amplitude on the application the soft clipping limiting has been
related to the input signal amplitude.
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70. The alignment system for the Vg2 voltage of the picture tube can be activated by means of the AVG bit. In that
condition a certain black level is inserted at the RGB outputs during a few lines. The value of this level can be
adjusted by means of the brightness control DAC. An automatic adjustment of the Vg2 of the picture tube can be
realised by using the WBC and HBC bits in output byte 01. These bits indicate whether the black level feedback
current is inside or outside the window between 12 and 20 µA. The indication of these bits can be made visible on
the screen via OSD so that this alignment procedure can also be used for service purposes. Because the gain loop
is digital quantization steps may occur in the read-out of the WBC and HBC bits.
71. When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realised by means of a reduction of the horizontal
scan amplitude the edges of the picture may slightly be disturbed. This effect can be prevented by adding an
additional blanking to the RGB signals. The blanking pulse is derived form the horizontal oscillator and is directly
related to the incoming video signal (independent of the flyback pulse). This blanking is activated with the HBL bit.
The width of the blanking can be set by means of the bits WBF3-WBF0 (start of blanking) and WBR3-WBR0 (end of
blanking) in subaddress 26H (see Fig.85).
When the Double Window feature is activated it may be necessary to increase the width of the wide blanking. This
can be realised by means of the WBI bit (subaddress 3EH).
72. This parameter is valid only when the CCC loop is active.
73. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).
74. This is a current input. The timing of the measuring pulses and the vertical blanking for the 50/60 Hz standard are
given in Fig.82
The start-up procedure is as follows.
When the TV receiver is switched-on the RGB outputs are blanked and the black-current loop will try to adjust the
picture tube to the right bias levels. The RGB drive signals are switched-on as soon as the black current loop is
stabilised. This results in the shortest switch-on time.
When this switch-on system results in a visible disturbance of the picture it is possible to add a further switch-on delay
via a software routine. In that case the RGB outputs must be blanked by means of the RBL bit. The condition of the
gain loop and the total black current loop can be read from the GLOK and BCF bits. This information can be used to
switch-on the RGB outputs after some additional delay.
75. During switch-off the magnitude of the discharge current of the picture tube is controlled by the black current loop.
Dependent on the setting of the OSO bit the vertical scan can be stopped in an overscan position during that time so
that the discharge is not visible on the screen. The switch-off procedure is as follows:
a) When the switch-off command is received the RGB outputs are blanked for a time of about 2 ms.
b) If OSO = 1 the vertical scan is placed in an overscan position
c) If OSO = 0 the vertical deflection will keep running during the switch-off time
d) The soft-stop procedure is started by doubling the frequency of the horizontal output pulse
e) The fixed beam current is forced via the black current loop
f) The soft-stop time has a value of 43 ms, the fixed beam current is flowing during a time of 38 ms.
76. The control circuit contains a Peak White Limiting (PWL) circuit and a soft clipper.
a) The detection level of the PWL is adjustable via the I2C-bus and has a control range between 0.4 and 0.6 VBL-WH
(this amplitude is related to the CVBS/Y input signal (typical amplitude 0.7 VBL-WH) at maximum contrast setting).
The high frequency components of the video signal are suppressed so that they do not activate the limiting action.
The contrast reduction of the PWL is obtained by discharging the capacitor of the beam current limiting input.
b) In addition to the PWL circuit the IC contains a soft clipper function which limits the high frequency signals when
they exceed the peak white limiting level. The difference between the peak white limiting level and the soft clipping
level is adjustable via the I2C-bus and can be varied between 0 and 10% in 3 steps (soft clipping level equal or
higher than the PWL level). It is also possible to switch-off the soft clipping function.
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77. The soft clipper gain reduction is measured by applying a sawtooth signal with rising slope and 0.7 VBL-WH at the
CVBS input. To prevent the beam current limiter from operating a DC voltage of 3.5V must be applied to BCLIN pin.
The contrast is set at the maximum value, the PWL (peak white limiting) level at the minimum value, and the soft
clipping level is set at 0% above the PWL level (SOC10=00). The tangents of the sawtooth waveform at one of the
RGB outputs is now determined at begin and end of the sawtooth. The soft clipper gain reduction is defined as the
ratio of the slopes of the tangents for black and white, see Fig.84.
78. The VGUARD/SWIO pin can be used for various purposes. The various combinations are given below.
a) Just vertical guard input.
b) Combination of vertical guard and LED drive output. In this condition the output is high-ohmic during the vertical
retrace (1 ms) so that the vertical guard pulse can be detected.
c) Single ended output switch
d) Input port
The functionality of this pin is controlled by the VGM1/0 and LED bits.
Table 268 Output signal amplitude of deemphasis pin as function of AGN and AMLOW bits; note 1
OUTPUT LEVEL DURING FM OUTPUT LEVEL DURING AM
AGN AMLOW
RECEPTION RECEPTION
0 0 125 mVRMS 250 mVRMS
Note
1. The indicated values are valid for a modulation index of 54% for both the FM and AM signal
Table 269 Output current of the phase detector in the various conditions
I2C-BUS COMMANDS IC CONDITIONS ϕ-1 CURRENT/MODE
VID POC FOA FOB IFI SL NOISE SCAN V-RETR GATING MODE
− 0 0 0 yes yes no 200 300 yes (1) normal
− 0 0 0 yes yes yes 30 30 yes(2) normal
− 0 0 0 yes no − 200 300 no normal
− 0 0 1 yes yes − 30 30 yes(2) slow
− 0 0 1 yes no − 200 300 no slow
− 0 1 0 yes yes − 6 6 no OSD
− − 1 1 − − − 200 300 yes(1) fast
0 0 − − no − − 6 6 no OSD
− 1 − − − − − − − − off
Note
1. Gating is active during vertical retrace, the width is 22 µs. This gating prevents disturbance due to Macro Vision Anti
Copy signals.
2. Gating is continuously active and is 5.7 µs wide
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UOCIII series
handbook, halfpage gm
1
f osc = -----------------------------------------
C i × C tot
Co 2π L i × ----------------------
Ci 276 kΩ
100 C i + C tot
XTALIN
XTALI XTALOUT
XTALO
Ca × Cb
C tot = C p + -------------------
-
Ca + Cb
Li crystal
Ci Ri or
Cp ceramic
resonator
Ca = Ci + Cx1
Cx1 Cx2 Cb = Co + Cx2
Ca Cb
MGR447
Fig.52 Simplified diagram crystal oscillator.
dB 0 80
-20
60
-40
40
-60
20
-80 0
0 10 20 30 40
DAC (HEX)
−20
0 20 40 60 80
DAC (HEX)
Overshoot in direction ‘black’.
Fig. 53 Volume control curve Fig. 54 Peaking control curve.
2003 Nov 11 218

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UOCIII series
+50 +50
(deg) (deg)
+30 +30
+10 +10
−10 −10
−30 −30
−50 −50
0 10 20 30 40 0 10 20 30 40
DAC(HEX) DAC(HEX)
Fig.55 Hue control curve. Fig.56 Base-band tint control curve.
MLA740 - 1
300 MLA741 - 1
250
(%)
% 225 100
250 (%)
200 90
175 80
200
150 70
150
125 60
100 50
100
75 40
50 30
50
25 20
00 10
0 10 20 30 40
DAC (HEX)
0 10 20 30 40
DAC (HEX)
Fig. 57 Saturation control curve. Fig. 58 Contrast control curve.
2003 Nov 11 219

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UOCIII series
(V)
MLA742 - 1
+0.4
0.7
(V)
+0.2 MBC212
0.35
100%
16 % 92%
0 0
-0.2
0.35
30%
for negative modulation

-0.4
0.7 100% = 10% rest carrier
0
0 10 20 30 40
DAC (HEX)
Fig. 59 Brightness control curve. Fig. 60 Video output signal.
MBC211
100%
86%
72%
58%
44%
30%
10 12 22 26 32 36 40 44 48 52 56 60 64 µs
Fig. 61 Test signal waveform.
2003 Nov 11 220

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UOCIII series
3.2 dB
10 dB
13.2 dB 13.2 dB
30 dB 30 dB
SC CC PC SC CC PC
MBC213
BLUE YELLOW
PC
TEST SPECTRUM
SC Σ ATTENUATOR CIRCUIT ANALYZER
gain setting
adjusted for blue
CC
MBC210
Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier.

All amplitudes with respect to top sync level.
V O at 3.58 or 4.4 MHz
Value at 0.92 or 1.1 MHz = 20 log ------------------------------------------------------------ + 3.6 dB

Value at 2.66 or 3.3 MHz = 20 log ------------------------------------------------------------
Fig. 62 Test set-up intermodulation.
2003 Nov 11 221

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UOCIII series
Apr 16, 2002

18:39:04
- y1-axis - (LIN)
225.0n
grp_55
200.0n _4.43M 197.853n
- Subvar -
175.0n
GD: 0.0
ST1: 0.0
150.0n
ST0: 0.0
FILCON: 1.962
125.0n
100.0n
75.0n
50.0n
25.0n
0.0
-25.0n
0.0 1.0M 2.0M 3.0M 4.0M 5.0M
500.0k 1.5M 2.5M 3.5M 4.5M
Analysis: AC
(LIN) F
User: nyoudees Simulation date: 16-04-2002, 16:54:30
File: /user/nyoudees/kn10241d/simulation/kn10241d_sndgrp_sim/sndgrp_sim1/Pstar/schematic/netlist/sndgrp_sim1.c.sdif
Fig.63 Group delay characteristic without group delay correction (sound trap: 5.5 MHz)
Apr 16, 2002

18:51:44
- y1-axis - (LIN)
400.0n
grp_gd
350.0n
- Subvar - 300.0n
GD: 1.0
ST1: 0.0
250.0n
ST0: 0.0
FILCON: 1.962
200.0n
_4.43M 177.613n
150.0n
100.0n
50.0n
0.0 _3.74M 406.163p
-50.0n _2.42M -60.205n
-100.0n
0.0 1.0M 2.0M 3.0M 4.0M 5.0M
500.0k 1.5M 2.5M 3.5M 4.5M
Analysis: AC
(LIN) F
User: nyoudees Simulation date: 16-04-2002, 16:54:30
File: /user/nyoudees/kn10241d/simulation/kn10241d_sndgrp_sim/sndgrp_sim1/Pstar/schematic/netlist/sndgrp_sim1.c.sdif
Fig.64 Group delay characteristic with group delay correction (sound trap: 5.5 MHz)
2003 Nov 11 222

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UOCIII series
CHARACTERISTIC POINTS AVL A B C D UNIT

Deemphasis voltage 60 125 250 600 mVRMS
1.8 V
1.0 V
Output voltage
A B C D
0.1 V
10 mV 100 mV 1V
Deemphasis voltage
These curves are valid for an audio supply voltage of 5 V. When the supply voltage is increased to 8 V the audio
output signal is increased with 6 dB.
Fig. 65 AVL characteristic
2003 Nov 11 223

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UOCIII series
(V)
1.0
0.5 1.0 2.0 3.8 4.8 5.8 MHz

0.86
0.65
0.45
0.44
0.3
0.15
0.0
Fig.66 CCIR-18 multi-burst
(V)
0.5 1.5 2.0 3.0 3.58 4.1 MHz
1.0
0.65
0.45
0.3
0.15
0.0
Fig.67 100% amplitude FCC multi-burst
2003 Nov 11 224

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UOCIII series
Transition at top of field:
input:
line n-2 line n-1 line n line n+1 line n+2 line n+3
output:
line n-1 line n
line n-2 line n+1 line n+2 line n+3
cross talk cross talk

Transition at bottom of field:
input:
output:
line n+1 line n+2
line n-2 line n-1 line n line n+3
cross talk cross talk
Fig.68 Vertical transitions active video ↔ vertical blanking from line to line, PAL systems.
Transition at top of field:
input:
output:
line n
line n-2 line n-1 line n+1 line n+2 line n+3
cross talk
Transition at bottom of field:
input:
output:
line n+1
line n-2 line n-1 line n line n+2 line n+3
cross talk
Fig.69 Vertical transitions active video ↔ vertical blanking from line to line, NTSC system
2003 Nov 11 225

CONFIDENTIAL

UOCIII series
Luminance
1
0.5
0
0 1 fsc 2 fsc
Detailed view:
Comb depth at f = fSC
1 Y Y
0.5 U V U V U
Fig.70 Luminance transfer characteristic
2003 Nov 11 226

CONFIDENTIAL

UOCIII series
Chrominance
1
0.5
0
0 1 fsc 2 fsc
Comb depth at f = (284/283.75)fSC

Detailed view:
U V U V
1
Y Y
0.5
Fig.71 Chrominance transfer characteristic
2003 Nov 11 227

CONFIDENTIAL

UOCIII series
OUTPUT (IRE)
100
80
60
40
20
B INPUT (IRE)
0
A 20 40 60 80 100
-20
A-A: MAXIMUM BLACK LEVEL SHIFT
B-B: LEVEL SHIFT AT 15% OF PEAK WHITE
Fig. 72 I/O relation of the black level stretch circuit (BSD = 0)
2003 Nov 11 228

CONFIDENTIAL

UOCIII series
red
V
I-axis
fully saturated colours
yellow
Fig.73 Skin tone correction range for the correction angle of 123 deg.
100%
YOUT
maximum
expansion
Expansion is dependent on the

setting of the WS1/WS0 bits
0%
0% YIN 100%
Fig.74 Gamma control characteristic
2003 Nov 11 229

CONFIDENTIAL

UOCIII series
Gain
increase
WS1/WS0 = 1/1
10%
WS1/WS0 = 1/0
5%
WS1/WS0 = 0/1
10 20 30 40 50
APL-level
Fig.75 Gamma control (white stretch) characteristic; Gain increase as function of APL level and WS1/WS0 setting
104 BLUE (BLS=1)

Output (%)
RGB (BLS=0)
100 GREEN (BLS=1)
RED (BLS=1)
95
90
85
80 85 90 95 100
Peak white level (%)
Fig.76 Blue stretch characteristic
2003 Nov 11 230

CONFIDENTIAL

UOCIII series
output- output-
amplitude amplitude
SVMA = 0 SVMA = 1
soft-clipping
CRA0=0
1.8Vp-p 1.8Vp-p
CRA0=0 CRA0=1
CRA0=1
gain gain
0 0
coring coring
50% 100% 50% 100%
input-amplitude input-amplitude
(% of nominal input) (% of nominal input)
Fig.77 SVM Gain-curve
SVM gain
* 0dB
-3dB
-6dB
A B C C B A
Horizontal position
Depending on VMA0, VMA1
*
curve at SPR2=1, SPR1=0 and SPR0=1
Fig.78 Parabola on the SVM output
2003 Nov 11 231

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UOCIII series
TOP
PICTURE
%
60
50
VERTICAL POSITION
138%
40 100%
30
75%
20
10
TIME
T/2 T
0
-10
-20
-30
-40
-50
BOTTOM
-60 PICTURE
BLANKING FOR EXPANSION OF 138%
Fig. 79 Vertical position and blanking pulse for 110° types
2003 Nov 11 232

CONFIDENTIAL

UOCIII series
V-DRIVE
I-COIL
Measuring lines
Vertical blanking
Fig.80 Measuring lines in vertical overscan for vertical compressed scan
2003 Nov 11 233

CONFIDENTIAL
2003 Nov 11
100
75
Soft start
TON
CONFIDENTIAL
(%) Soft stop
50
Frequency
234
HOUT = 2xFH
25
57 73 1045 50
12
Time (ms)
UOCIII series
Discharge current
picture tube
38
Fig. 81 Soft start and soft stop behaviour of horizontal output and timing picture tube discharge current
RESET LINE COUNTER 23
625
50Hz
Video
signal
2003 Nov 11
internal
2fH clock 1ST
Reset Vert. Saw

14 lines FIELD
Vert. Blank
4.5 lines (OSVE and EVB = 0)

12.5 lines (OSVE = 1) end line 23 (OSVE and EVB = 0)
9.5 lines (EVB = 1) L R G B end line 33 (OSVE = 1)
Black current pulses line 27.5 (EVB = 1)
17 18 19 20
336
312
Video
signal
2ND
Vert. Blank FIELD

4.5 lines (OSVE and EVB = 0)

12 lines (OSVE = 1) line 335.5 (OSVE and EVB = 0)
9.5 lines (EVB = 1) end line 345 (OSVE = 1)
L R G B
Black current pulses end line 340 (EVB = 1)
329 330 331 332
RESET LINE COUNTER 60Hz 19

525
Video
235
signal
internal
2fH clock 1ST
FIELD
CONFIDENTIAL
Reset Vert. Saw
9.5 lines
end line 20 (OSVE and EVB = 0)
end line 30 (OSVE = 1)
Vert. Blank end line 23 (EVB = 1)
4 lines (OSVE and EVB = 0)
14.5 lines (OSVE = 1)
9 lines (EVB = 1)
L R G B
Black current pulses 17 18 19 20
RESET LINE COUNTER 281

262
Video
signal
line 282.5 (OSVE and EVB = 0)

end line 292 (OSVE = 1)
line 285.5 (EVB = 1)
Vert. Blank
4 lines (OSVE and EVB = 0) 2ND
14 lines (OSVE = 1) FIELD
9 lines (EVB = 1)
L R G B
Black current pulses
279 280 281 282
Note 1: When OSVE and EVB are ‘1’ the OSVE blanking value is valid
Note 2: The vertical blanking is also dependent on the vertical “Zoom” and “Scroll” setting
Fig.82 Timing of vertical blanking and black current measuring pulses
UOCIII series

UOCIII series
φ-1 REF
2nd FIELD
φ-1 REF
SYNC
1st FIELD
CSY
SYNC
CSY
Fig.83 H/V timing output (CSY) on the flyback input pin (FBISO) in the “LCD/100 Hz” mode
14 lines
14 lines
2003 Nov 11 236

CONFIDENTIAL

UOCIII series
2.4
clipper off
Soft clipping
range
(Defined by
SOC1/SOC0 bits)
1.8
RGBout
(Vb-w)
1.2 clipper on
0.6
20 40 60 80 100 120 130

CVBS IN (IRE)
00H 08H 0FH
PWL setting
Fig.84 Peak White Limiting / Soft clipper characteristic.
VIDEO
REF Φ-1
BURST KEY
3.5 µs 7.8 µs BLANKING

5.9 µs 10.2 µs
15 steps of 0.16 µs 15 steps of 0.16 µs
Fig.85 Timing of horizontal wide blanking
2003 Nov 11 237

CONFIDENTIAL

UOCIII series
TEST AND APPLICATION INFORMATION The value of REW must be:

East-West output stage V scan
R EW = R c × -----------------------
In order to obtain correct tracking of the vertical and 36 × V ref
horizontal EHT-correction, the EW output stage should be
dimensioned as illustrated in Fig.86.
Example: With Vref = 1.95 V; Rc = 39 kΩ and
Resistor REW determines the gain of the EW output stage. Vscan = 120 V then REW = 68 kΩ.
Resistor Rc determines the reference current for both the
vertical sawtooth generator and the geometry processor.
The preferred value of Rc is 39 kΩ which results in a
reference current of 50 µA (Vref = 1.95 V).
book, full pagewidth VDD
HORIZONTAL
DEFLECTION V scan
STAGE
R ew
TDA8366
TDA110XXH*
TDA 935X
TDA120XXH* 4321
21 DIODE V EW
series EWD MODULATOR
EW output
28
27
50 27
26
49 stage
V ref
Rc C saw
39 kΩ
(2%) 150
100nF
nF
(5%) MLA744 - 1
I ref
Fig.86 East-West output stage
2003 Nov 11 238

CONFIDENTIAL

UOCIII series
700
IVERT 500
(µA) 300
100
-100
-300
-500
-700
0 T/2 TIME T
VA = 0, 20H and 3FH; VSH = 1FH; SC = 0EH. VS = 0, 20H and 3FH; VA = 1FH; VSH = 1FH; SC = 0EH.
Fig. 87 Control range of vertical amplitude. Fig. 88 Control range of vertical slope.
IVERT
(µA)
600
400
200
-200
-400
-600 -1.0 -500.0m 0.0 500.0m 1.0

-750.0m -250.0m 250.0m 750.0m
0 T/2 TIME T
VSH = 0, 20H and 3FH; VA = 1FH; SC = 0EH. SC = 0, 0EH and 3FH; VA = 1FH; VSH = 1FH.
Fig. 89 Control range of vertical shift. Fig. 90 Control range of S-correction.
2003 Nov 11 239

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UOCIII series
IEW IEW
(µA) (µA)
1200 500
1000
400
800
300
600
200
400
100
200
0 0
0.0 400.0m 800.0m
0 200.0m T/2 600.0m TIME T 1.0 0.0
0 200.0m
400.0m
T/2 600.0m TIME800.0m T 1.0
PW = 0, 20H and 3FH; EW = 3FH; TC = 1FH; CP = 10H.
EW = 0, 20H and 3FH; PW = 3FH; TC = 1FH; CP = 10H.
Fig. 91 Control range of EW width. Fig. 92 Control range of EW parabola/width ratio.
IEW IEW
(µA) (µA)
500 650
600
400
550
300
500
200
450
100
400
0 350 0.0 400.0m 800.0m

200.0m 600.0m 1
0.0 400.0m
TIME800.0m 0 T/2 TIME T
0 200.0m T/2600.0m T 1.0
CP = 0, 20H and 3FH; EW = 3FH; PW = 3FH;TC = 1FH. TC = 0, 20H and 3FH; EW = 1FH; PW = 1FH; CP = 10H.
Fig. 93 Control range of EW corner/parabola ratio. Fig. 94 Control range of EW trapezium correction.
2003 Nov 11 240

CONFIDENTIAL

UOCIII series
IVERT
(µA)
600
400
200
-200
-400
-600
0.0 400.0m 800.0m
0 200.0m T/2 600.0m TIME T 1.0
VLIN = 0, 20H and 3FH; VA=1FH; VSH=1FH; SC=0
Fig.95 Vertical linearity control
2003 Nov 11 241

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UOCIII series
Adjustment of geometry control parameters For adjustment of the vertical shift and vertical slope
independent of each other, a special service blanking
The deflection processor offers the following parameters
mode can be entered by setting the SBL bit HIGH. In this
for picture alignment, viz:
mode the RGB-outputs are blanked during the second half
• vertical amplitude of the picture. There are 2 different methods for alignment
• vertical slope of the picture in vertical direction. Both methods make use
of the service blanking mode.
• S-correction
• vertical shift The first method is recommended for picture tubes that
have a marking for the middle of the screen. With the
• Vertical zoom and vertical scroll
vertical shift control the last line of the visible picture is
• Vertical linearity correction, when required the linearity positioned exactly in the middle of the screen. After this
setting of the upper and lower part of the screen can be adjustment the vertical shift should not be changed. The
different. top of the picture is placed by adjustment of the vertical
• horizontal shift. amplitude, and the bottom by adjustment of the vertical
slope.
• EW width
• EW parabola width The second method is recommended for picture tubes that
have no marking for the middle of the screen. For this
• EW upper/lower corner parabola
method a video signal is required in which the middle of the
• EW trapezium correction. picture is indicated (e.g. the white line in the circle test
• Horizontal parallelogram and bow correction pattern). With the vertical slope control the beginning of the
blanking is positioned exactly on the middle of the picture.
It is important to notice that the ICs are designed for use Then the top and bottom of the picture are placed
with a DC-coupled vertical deflection stage. This is the symmetrical with respect to the middle of the screen by
reason why a vertical linearity alignment is not necessary adjustment of the vertical amplitude and vertical shift.
(and therefore not available). After this adjustment the vertical shift has the right setting
For a particular combination of picture tube type, vertical and should not be changed.
output stage and EW output stage it is determined which If the vertical shift alignment is not required VSH should be
are the required values for the settings of S-correction, EW set to its mid-value (i.e. VSH = 1F). Then the top of the
parabola/width ratio and EW corner/parabola ratio. These picture is placed by adjustment of the vertical amplitude
parameters can be preset via the I2C-bus, and do not need and the bottom by adjustment of the vertical slope. After
any additional adjustment. The rest of the parameters are the vertical picture alignment the picture is positioned in
preset with the mid-value of their control range (i.e. 1FH), the horizontal direction by adjustment of the EW width and
or with the values obtained by previous TV-set
the horizontal shift. Finally (if necessary) the left- and
adjustments.
right-hand sides of the picture are aligned in parallel by
The vertical shift control is meant for compensation of adjusting the EW trapezium control.
off-sets in the external vertical output stage or in the
To obtain the full range of the vertical zoom function the
picture tube. It can be shown that without compensation
adjustment of the vertical geometry should be carried out
these off-sets will result in a certain linearity error,
at a nominal setting of the zoom DAC at position 19 HEX.
especially with picture tubes that need large S-correction.
The total linearity error is in first order approximation
proportional to the value of the off-set, and to the square of
the S-correction needed. The necessity to use the vertical
shift alignment depends on the expected off-sets in vertical
output stage and picture tube, on the required value of the
S-correction, and on the demands upon vertical linearity.
2003 Nov 11 242

CONFIDENTIAL

UOCIII series
PACKAGE OUTLINE
QFP128: plastic quad flat package;

128 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; lead angle 60 o SOT320-3
c
y
X
96 65
97 64 ZE
A A2
E HE A1 (A3)
θ
wM θ1
Lp
bp
L
pin 1 index detail X
128 33
1 32
wM ZD v M A
e bp
D B
HD v M B
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D(1) E(1) e HD HE L Lp v w y ZD(1) ZE(1) θ θ1
max.
0.25 3.70 0.45 0.23 28.1 28.1 32.2 32.2 0.95 1.8 1.8 7o 65o
mm 3.95 0.25 0.8 1.95 0.25 0.2 0.1
0.05 3.15 0.30 0.11 27.9 27.9 31.6 31.6 0.55 1.4 1.4 0o 55o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
SOT320-3 --- MO-112 03-02-19
2003 Nov 11 243

CONFIDENTIAL

UOCIII series
SOLDERING WAVE SOLDERING

Introduction Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
There is no soldering method that is ideal for all IC
closely-spaced leads and the possibility of incomplete
packages. Wave soldering is often preferred when
solder penetration in multi-lead devices.
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is If wave soldering cannot be avoided, for QFP
not always suitable for surface mounted ICs, or for packages with a pitch (e) larger than 0.5 mm, the
printed-circuits with high population densities. In these following conditions must be observed:
situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward
This text gives a very brief insight to a complex technology. pressure followed by a smooth laminar wave)
A more in-depth account of soldering ICs can be found in soldering technique should be used.
our “IC package Databook” (order code 9398 652 90011). • The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
QFP downstream and at the side corners.
REFLOW SOLDERING During placement and before soldering, the package must
Reflow soldering techniques are suitable for all QFP be fixed with a droplet of adhesive. The adhesive can be
packages. applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
The choice of heating method may be influenced by larger adhesive is cured.
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are Maximum permissible solder temperature is 260 °C, and
not absolutely dry (less than 0.1% moisture content by maximum duration of package immersion in solder is
weight), vaporization of the small amount of moisture in 10 seconds, if cooled to less than 150 °C within
them can cause cracking of the plastic body. For details, 6 seconds. Typical dwell time is 4 seconds at 250 °C.
refer to the Drypack information in our “Quality Reference A mildly-activated flux will eliminate the need for removal
Handbook” (order code 9397 750 00192). of corrosive residues in most applications.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied REPAIRING SOLDERED JOINTS
to the printed-circuit board by screen printing, stencilling or Fix the component by first soldering two diagonally-
pressure-syringe dispensing before package placement. opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
Several methods exist for reflowing; for example,
time must be limited to 10 seconds at up to 300 °C. When
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary using a dedicated tool, all other leads can be soldered in
between 50 and 300 seconds depending on heating one operation within 2 to 5 seconds between
270 and 320 °C.
method. Typical reflow peak temperatures range from
215 to 250 °C.
2003 Nov 11 244

CONFIDENTIAL

UOCIII series
DEFINITIONS
Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 Nov 11 245

CONFIDENTIAL

Data Sheet: Device Specification

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INTEGRATED CIRCUITS

Versatile signal processor for low- and

Versatile signal processor for low- and

Versatile signal processor for low- and

• NICAM decoding (B/G, I, D/K and L standard) • Graphic equaliser

• Two-carrier multistandard FM demodulation (B/G, D/K • Processed or non processed subwoofer

Versatile signal processor for low- and

• 8-bit A/D converter with 4 multiplexed inputs • Fringe colour selectable

Versatile signal processor for low- and

ROM SIZE (k)

AUX RAM SIZE (k)

DISPLAY RAM (k)

DRCS RAM (k)

TDA11000H/H1 √ √ NTSC √ 128 4 1.25 2.25

TDA11011H/H1 √ √ √ MULTI √ 128 4 1.25 2.25

TDA12006H/H1 BTSC(3) NTSC 128/256 8 1.25 2.25

ROM SIZE (k)

AUX RAM SIZE (k)

DISPLAY RAM (k)

DRCS RAM (k)

TDA12060H/H1 √ MULTI √ 128/256 8 1.25 2.25

TDA12067H/H1 √ √ √ MULTI √ √ √ √ √ 128/256 8 1.25 2.25

TDA12072H/H1(2) MULTI 128/256 8 10 2.25

Versatile signal processor for low- and

Type Number Definition and Feature Indication

Virtual Dolby® (VDS)

Versatile signal processor for low- and

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

SWITCH AUDIO CONTROL BLOCK DIAGRAMS

PLL DEMOD. PAL/SECAM/NTSC BASE-BAND µ-PROCESSOR AND TELETEXT DECODER

DIGITAL PEAKING RGB CONTROL

V-DRIVE EHTO BL G/Y

EWD R/PR B/PB

Fig.1 Block diagram of the “Stereo” TV processor

SWITCH AUDIO CONTROL

Fig.2 Block diagram of the “AV-stereo” TV processor with audio DSP

Fig.3 Block diagram of the “AV-stereo” TV processor without audio DSP

SWITCH SOUND PLL

V-DRIVE (EWD) EHTO

Fig. 4 Block diagram of the “Mono” TV processor

VDDA3(3.3V) 4 4 4 125 125 125 supply (3.3 V)

VREF_POS_HPR 9 − − 120 − − positive reference voltage SDAC (3.3 V)

VSC 26 26 26 103 103 103 vertical sawtooth capacitor

30 30 30 99 99 99 SIF input 2 / DVB input 2

VCC8V 45 45 45 84 84 84 8 Volt supply for audio switches

AUDIOIN4 49 80 audio 4 input

AUDOUTHPR 63 − − 66 − − audio output for headphone channel (right signal)

HOUT 67 67 67 62 62 62 horizontal output

VREFAD_NEG 89 89 89 40 40 40 negative reference voltage (0 V)

P0.2/I2SDO2 104 − − 25 − − port 0.2 or I2S digital output 2

P2.5/PWM4 123 123 123 6 6 6 port 2.5 or PWM4 output

P1.4/RX 127 127 127 2 2 2 port 1.4 or UART bus

SSIF/ SWO/ REFO SSIF/ SWO/ SSIF/ SWO/

Versatile signal processor for low- and

Versatile signal processor for low- and

Fig.6 Pin configuration of “AV stereo” versions without Audio DSP

Versatile signal processor for low- and

Fig.7 Pin configuration “mono” versions

Versatile signal processor for low- and

Versatile signal processor for low- and

Fig.9 Pin configuration of “AV stereo” versions without Audio DSP

Versatile signal processor for low- and