29

CHAPTER 3

FOUR WIRE INVERTER FOR UPS APPLICATIONS

3.1 INTRODUCTION

The conventional three phase three wire inverters are suitable for
supplying balanced three phase loads. But when the load is unbalanced, the
four wire inverters become the best choice as they provide a neutral
connection for a three phase unbalanced system using a fourth leg in the
inverter topology. Four wire inverter is a method of providing a neutral
connection for three phase four wire unbalanced systems using a four leg
inverter topology by tying the neutral in high power UPS applications. Four
leg inverter is able to provide a path for the neutral current, flexibility to
control the neutral voltage and hence produces balanced voltage across each
phase. In this section the four wire inverter for UPS system is simulated and
results are verified with experimental researches. The analysis is based on
power quality for linear and non linear loads particularly for rectifier loads.

3.2 BLOCK DIAGRAM OF THE PROPOSED UPS SYSTEM

The block diagram of the four wire inverter UPS is depicted in

Figure 3.1. When the main supply is ON, the rectifier provides power to the
inverter as well as the battery. The load is always fed by the inverter. The
main static switch is always OFF. Only when the UPS fails, the load will be
connected directly to the supply mains through the static switch which will be
 30

in ON state at that time. When the supply is off, then the inverter will be
supplied by the battery.

Figure 3.1 Block Diagram of the Conventional FWI based UPS System

If the mains static switch is not available, the load will be isolated
from supply at times of UPS failure. Thus an inverter is always on and it takes
power from the input ac supply or battery. The voltage feedback is given to
the controller which produces the necessary gating signals to the four wire
inverter switches. Under any unbalanced or nonlinear load circumstances, the
four wire inverter is used to provide the balanced and undistorted voltage to
the load (Eyyup et al 2007).

3.3 CIRCUIT DIAGRAM OF UPS SYSTEM

In four leg inverters the load neutral wire is connected to the fourth
leg as shown in Figure 3.2. This makes the control of neutral voltage more
flexible and hence produces balanced voltage Vdc across each phase. The two
additional power switches in four wire system, double the number of inverter
output states from 8(=23) to 16(=24).The UPS requires sinusoidal output with
minimum total harmonic distortion. It is achieved by using space vector pulse
width modulation technique. By this technique, the load voltage is compared
 31

with a reference voltage and the difference in amplitude is used to control the
modulating signal in the control circuit of the inverter. The circuit diagram
giving the load neutral point voltage for the three phase four wire inverter is
illustrated in Figures 3.2(a) and (b).

Figure 3.2 (a) Circuit Diagram of Three Phase Four Wire Inverter with
Midpoint Capacitors

Figure 3.2 (b) Circuit Diagram of Three Phase Four Wire Inverter
 32

3.4 LITERATURE SURVEY

The paper proposed by Kumar et al (2005) a new software

implementation of SVPWM has given out a new way of implementing the
SVM technique in three phase inverter using MATLAB and PSIM software
packages. Space Vector PWM can be used to generate an averaged sinusoidal
voltage which utilizes DC bus voltage more efficiently and generates less
harmonic distortion. During voltage sag and power quality problems in UPS
the three phase inverters are not sufficient to provide quality power output.
The paper proposed by Pinheiro et al (2002), space vector modulation for
voltage-source inverters has given a brief description and implementation of
space vector modulation technique for various inverter configurations.
A generalized methodology is described in an understandable manner like
switching vectors, separation and boundary planes, as well as decomposition
matrices and also possible switching sequences are presented. However
attention has not been paid to predict the performance of inverter for
nonlinear loads.

The paper proposed by Mohd et al (2010) on four wire voltage

source inverters under unbalanced load conditions, the authors have
developed control functions and 3D SVM implementation for three-leg four
wire inverters. It is capable of providing good power quality to loads under
extreme unbalanced conditions. But it is inefficient during voltage sag
conditions. Broeck et al (1988) have analyzed the pulse width modulator
based on voltage space vectors concept to derive the switching instants for
voltage source inverters. It also gives a comparative study of space vector
concept and sinusoidal concept. Compared with SPWM the SVPWM can
work with higher modulation index. However the inverter is sensitive towards
nonlinearities, which is important especially at low modulation index.
 33

Lihua Li et al (2009) have discussed a new controller for three

phase four wire voltage generation inverters for generating high quality three
phase output voltages for all sorts of linear/nonlinear and balanced/unbalanced
loads. The proposed controller employs a circuit level decoupling method and
it is implemented by logic circuitry in combination with a control core and a
feedback signal processor. Almost all DC-DC control methods can be adapted
as the control core, while the feedback signal processor can be implemented
by either voltage compensator or current compensator. The implementation of
the controller is simple and flexible with only logic and analog circuitry
needed.

3.5 SPACE VECTOR MODULATION FOR THREE LEG FOUR

WIRE INVERTER

Space vector modulation is based on vector selection in the

(stationary) or in the dqo (rotating) reference frame. A set of three vectors V a,
Vb and Vc in the -frame can generate a normalized reference vector Vref in
the same plane using PWM averaged approximation. The average reference
vector can be obtained by sequentially applying these vectors in a modulation
period (Rajesh and Narayanan 2008).

TS T T TS
1 1 1 1 2 1
Vref dt= Va dt+ Vb dt+ Vcdt (3.1)
TS 0 TS 0 TS T TS T +T
1 1 2

where TS is the modulation period and T1 + T2 TS. Since Vref remains

constant during the modulation period, it can be approximated as

Vref =Da .Va +D b .Vb +D c .Vc (3.2)

in which Da, Db and Dc are the duty cycles of vectors Va, Vb and Vc. In
3D-SVM algorithm, based on generating a zero-vector has been introduced.
 34

Still, the proposed algorithm has a drawback of stressing the Insulated Gate
Bipolar Transistors (IGBTs) unequally. In this work, another SVM algorithm
without using a zero-vector is launched. This algorithm based on vectors
compensation (compensated vectors approach) is more practical as it is not
only stressing the IGBTs equally but less as well. The proposed SVM
algorithm can be achieved through the following steps:

1. Determining the switching combinations and the corresponding

vectors.

2. Calculating the voltage drop related to each vector.

3. Identifying the position for each vector in the -space vector

diagram.

4. Identifying the reference vector position.

5. Calculating the duty cycles.

6. Building a vector sequence.

7. Computing pulse patterns.

3.5.1 Steps One, Two and Three

In a similar way to two level three phase inverters, there are eight
different switching combinations where the output terminals will be
connected to +1/2 or -1/2 of the input DC voltage. However, unlike two-level
three-leg inverters none of these switching combinations is generating zero
voltage at the output terminals, which make the implementation of SVM more
difficult. Table 3.1 presents the eight possible switching vectors and the
corresponding output voltages related to the DC-voltage as reference voltage.
The switching vectors can be represented in the -coordinates using
Clarke’s transformation. Table 3.1 also shows the normalized -values of
 35

each switching vector. Figure 3.3 depicts representation of these switching

vectors in space.

Figure 3.3 3D Space Vectors

The vectors are taking place in layers according to the value of their
component. Three vectors (V2, V4 and V6) are located at the layer
V =1/6(VDC). The vectors (V1, V3 and V5) are lying at the layer
V = -1/6(VDC). The vectors V7 and V0 are located at the axis at
V =1/2(VDC) and V =-1/2(VDC), respectively. The projection of the vectors in
the frame is shown in Figure 3.3 which is divided into six prisms. The six
prisms in the space are shown in Figure 3.4. Each prism is divided into
two tetrahedrons, upper and lower tetrahedron. Each tetrahedron is
characterized by three vectors.
 36

Table 3.1 Switching States the Corresponding Output Voltages and

Normalized Components of each Switching Vector

Switches Normalised output voltage Normalised -components

Vectors
(ON) Va /VDC Vb /VDC Vc /VDC V /VDC V /VDC V /VDC
S4 S6 S2 V0 -1/2 -1/2 -1/2 0 0 -1/2
S1 S6 S2 V1 1/2 -1/2 -1/2 2/3 0 -1/6
S1 S3 S2 V2 1/2 1/2 -1/2 1/3 1/ 3 1/6
S4 S3 S2 V3 -1/2 1/2 -1/2 -1/3 1/ 3 -1/6
S4 S3 S5 V4 -1/2 -1/2 1/2 -2/3 0 1/6
S4 S6 S5 V5 -1/2 -1/2 1/2 -1/3 -1/ 3 -1/6
S1 S6 S5 V6 1/2 1/2 1/2 1/3 -1/ 3 1/6
S1 S3 S5 V7 1/2 1/2 1/2 0 0 ½

3.5.2 Step Four: Reference Vector Position Identification

Given that 12 tetrahedrons exist, there are 12 possibilities for the

reference vector position. The position of the reference vector can be
identified using the boundary planes limiting the tetrahedron. Each
tetrahedron is limited by three planes. The boundary planes can be determined
by means of the following linear equations.

1
E 71: V =0 (3.3)
3

E 1 2 :V - 3V +4V =0 (3.4)

3 1
E 27 : V - V =0 (3.5)
6 6

E 2 3 :- 2 V +2V =0 (3.6)
 37

3 1
E 37 : V + V =0 (3.7)
6 6

E 3 4 :V + 3V +4V =0 (3.8)

Figure 3.4 3D Prisms for Three Leg Four Wire Inverter

The zero-vector is compensated by the vectors V0 and V7, both

lying against each other direction on the -axis. The reference vector can be
expressed as follows

Vref =Da .Va +D b .Vb +D .Vc (3.9)

 38

where

Vc =V7 and D =D 7 -D0

Vc =V0 and D =D 0 -D 7 (3.10)

3.5.3 Step Five: Duty Cycles Calculation

Once the target tetrahedron is defined the nearest three vectors are
chosen. By normalizing the standard vectors at the intermediate circuit
voltage, the duty cycles in matrix form can be written as follows

Da V
1 -1 -ref
Db = Va Vb Vc V -ref (3.11)
Vdc
Dc V -ref

The duty cycles for the vectors V7 and/or V0 can be determined

according to the position of the reference vector. For the upper tetrahedron
and for the lower tetrahedron it is found using the equation

1-(Da +D b )+D
D7 = D0 =D 7 -D (3.12)
2

1-(Da +D b )+D
D0 = D7 =D 0 -D (3.13)
2

Table 3.2 Vector Sequence for the Upper and Lower Tetrahedrons in
Each Prism

Prism Sequence
1 v0-v1-v2-v7-v7-v2-v1-v0
2 v0-v3-v2-v7-v7-v2-v3-v0
3 v0-v3-v4-v7-v7-v4-v3-v0
4 v0-v5-v4-v7-v7-v4-v5-v0
5 v0-v5-v6-v7-v7-v6-v5-v0
6 v0-v1-v6-v7-v7-v6-v1-v0
 39

3.5.4 Steps Six and Seven: Building Vector Sequence and Pulse
Pattern Computation

In order to reduce the current ripples, switching vectors adjacent to

the reference vector should be selected as they produce non conflicting
voltage pulses (same voltage polarity). Table 3.2 shows the vector sequence
for the upper and lower tetrahedrons in each prism. An example for
determining the switching sequence for the first prism is shown in Figure 3.5 (a).
The pulse sequence can be achieved by comparing the duty cycles with a
carrier signal. The pulse sequence for phase a, b and c are shown in Figure 3.5 (b)
for the same mentioned case.

(a) (b)

Figure 3.5 Building Vector Sequence and Pulse Pattern Computation

(a) Steps for the Modulation in the First Prism and
(b) Symmetric Modulation in the First Prism
 40

3.6 OPERATING MODES OF FOUR WIRE SYSTEM

Three phase four wire VSI is commonly used for three phase
voltage generation. It consists of eight switches Tap Txn and filters comprising of
inductors LA LX and capacitors CA CC, interfacing a dc source with three
phase ac loads. The switches operate at switching frequency to chop the dc
bus voltage E into high frequency chunks; the LC network filter out the
switching harmonics and pass the fundamental to output terminals. The VSI is
very well controlled and it is able to generate balanced high quality AC output
voltage irrespective of the loading conditions.

Figure 3.6 Three Phase Output Voltage

Figure 3.7 Vector Diagram of Three Phase Output Voltage

 41

Figure 3.8 Active Voltage Vectors for Region (a) 0°-60°, (b) 120°-180°
and (c) 180°-240°

The expected three phase output voltage vectors are depicted in

Figure 3.6. It is equivalent to an equilateral triangle in the vector plane as
illustrated in Figure 3.7, where the three outer lines represent line voltages
VAB, VBC and VCA, the three inner lines correspond to phase voltages VAO,
VBO and VCO. It is observed that there are only three independent lines within
the triangle, i.e., if the position and length of three independent lines are
determined then the rest of the lines in the triangle are automatically settled.
For example, if lines that correspond to VAB, VBC and VBO are drawn, lines
that represent VAO, VCO and VAC will be determined by the nature of this
vector triangle. This indicates that the active control of any two line voltages
and one phase voltage can lead to the full control of a three phase four wire
system. The circuit level decoupling method proposed for three phase three
wire system can therefore be extended to three phase four wire domain based
on the earlier analysis.

As shown in Figure 3.7, one line cycle is divided into six regions.
In region 0°-60°, 120°–180°and 240°-300°, the voltage waveforms as
depicted in Figure 3.8 follow the same pattern, i.e., one phase voltage is
always lower than the other two. The selection of actively controlled voltage
vectors is as follows. The lowest phase voltage is selected as the active phase
voltage under control (in 0°-60°, it is –VBO) and the line voltages between the
lowest phase voltage and the other two phases are selected as the active line
voltages under control (in 0 –60 , it is VAB and VCB).
 42

The switching logics of the proposed controller are sustained in the

following method. Table 3.3 shows the switching parameters (in 0º - 60º, it is
VAB and VCB). The switching sequence in Table3.3 minimizes the switching
stress and harmonics and thus improves the four wire inverter operation.
Figure 3.9 illustrates the equivalent circuit for the proposed three phase, four
wire voltage source inverter during (0-60o) internal mode.
Table 3.3 Switching Logics for Proposed System

Switches
S1 S2 S3 S4 S5 S6 N1 N2
Intervals
-60 ON OFF OFF OFF OFF ON ON OFF
60 -120 ON ON OFF OFF OFF OFF OFF ON
120 -180 OFF ON ON OFF OFF OFF ON OFF
180 -240 OFF OFF ON ON OFF OFF OFF ON
240 -300 OFF OFF OFF ON ON OFF ON OFF
300 -360 OFF OFF OFF OFF ON ON OFF ON

Figure 3.9 Equivalent Circuit for Four Wire System during (a) 00-600
and (b) 60°-120°
 43

Figure 3.10 Active Voltage Vectors during (a) 60°-120°, (b) 180°- 240° and
(c) 300°-360°

1. The switch T in (a, b, c) for the phase with the lowest voltage is
always turned ONand the corresponding Tip for this phase is
always turned OFF.

2. The switches Tin and Tip for the other two phases are driven
complementarily, where the duty ratio of one Tip is defined by
Dp; the duty ratio of the other Tip is defined by dn.

3. The switches Txn and Txp for the neutral phase are driven
complementarily, where the duty ratio of Txp is defined by Dx.

With this treatment, Figure 3.2 becomes equivalent to Figure 3.9 (a)
in 0°–60° region, which can be further rearranged into Figure 3.9 (b).
The same equivalent circuit is also applicable to 120°-180° and 240°-300°
regions, where the selection of active phase/line voltages follows Figure 3.8.
 44

Figure 3.11 Equivalent Circuit for Four Wire System during (a) 00-600
and (b) 60°-120°

While in region 60°-120°,180°-240and 300°-360°, the voltage

waveforms in Figure.3.6.have another pattern, i.e., one phase is always higher
than the other two. The selection of actively controlled voltage vectors is as
follows: the highest phase voltage is selected as the active phase voltage
under control (in 60°-120°, it is VAO); the line voltages between the highest
phase voltage and the other two phases are selected as the active line voltages
under control (in 60°-120°, it is VAB and VAC). Figure 3.10 shows the selected
active voltage vectors for region 60°-120°, 180°-240°and 300°-360°.
Correspondingly following modulation method is used.

For further analysis, following assumptions are made.

1) LA=LB=LC=LX=L

2) CA=CB=CC=C
 45

3) Switching frequency is much higher than fundamental

frequency

4) dp>dn>dx

Equivalent circuit for four wire system during (a) 00-600 and
(b) 600-1200 is shown in Figure 3.11. The first three assumptions usually
become true in three phase voltage generation application, while the last one
is made for the ease of analysis. Detailed analysis is performed in region 0°-
60° as illustrated in Figure 3.9 (b), while similar derivation can be extended to
all other regions. With output voltages VAB, VCB and VBO following their
respective reference voltages, Figure 3.9 (b) is redepicted with outputs
replaced by three voltage sources for the ease of analysis. Assuming
d >d >d , the equivalent circuit in one switching cycle is depicted. The
p n x

voltage applied on each inductor in one switching cycle is derived through the
application of superposition, i.e., combining the voltage drop from individual
voltage.

3.7 STABILITY ANALYSIS OF THREE PHASE FOUR WIRE

INVERTER

The physical elements of the UPS system are replaced with

equivalent control blocks and the system depicted in Figure 3.12 can be
represented with a continuous time system block diagram illustrated in
Figure 3.13. In the diagram, each component of the UPS system is modeled
with an appropriate continuous time transfer function block which will be
detailed in the following discussion. Employing this model, the system
stability can be investigated via tools such as Routh-Hurwitz stability
criterion. The controller gain limits for stability can be established based on
the control bandwidth requirements and the controller parameters can then be
optimized based on the control bandwidth requirements.
 46

VˆCan

iˆc

Figure 3.12 Design of the UPS Control System

Vinv* (S)
VC* ( S )

VˆC ( S )

Figure 3.13 Simplified S-Domain Mathematical Model

Figure 3.13 depicts the block diagram of the UPS control system
which includes the control elements with their simplified S-domain
mathematical model. The UPS system control block diagram includes
measurement delay block, sampling delay block and PWM delay blocks.
 47

1
1 s measure
Iˆc(S) Ic(S)

1 1 1 IL(S) 1
1 s samp 1 s PWM Ls I L
*
V (S)
C
cs
VˆC ( S )
I0(S)
1 VC ( S )
1 s measure

Figure 3.14 First Order Delay Transfer Function

In the implemented system, the output voltages are measured by

isolated voltage transducers with considerable delay and are applied to the
digital control unit as the feedback signals of the closed loop system. These
output voltages are the main control variables of the four leg inverter based
UPS system. This results in a measurement delay ( measure). Thus, the
measurement delay depicted in Figure 3.14 can be modeled with a first order
delay transfer function with unity gain.

The current transducer is used to measure the capacitor current.

Similar to the modeling of the voltage measurement delay, current
measurement delay can be modeled with a first order delay transfer function.

The sampled feedback signals are utilized in the control algorithm

to generate the voltage reference signals (VC*), these voltage reference signals
are applied to the PWM blocks at the end of the sampling period (Ts). For the
sake of simplicity, the delays, which are discussed above and illustrated in
Figure 3.14 can be considered as total system delay and can be modeled with
 48

an equivalent single delay block as shown in Figure 3.15. The system in

Figure 3.15 can be represented with simplified control block diagrams as
shown in Figure 3.16. In the diagram, Gv(s) is the transfer function of the
inverter reference voltage to output voltage.

Ic(S)

1 1 IL(S) 1
Gc ( s) Ls I L
*
V (S) 1 s T cs
C

VˆC (S )
I0(S)
VC (S )

Figure 3.15 Equivalent Single Delay Block

Ic(S)
Gi ( s)

Gc ( s ) Gv (s)
VC*( S )

VˆC ( S )

Figure 3.16 Simplified Control Block Diagram

The output voltage controlled transfer function of Figure 3.16 is

given in Equation (3.14). For simplification, single resonant frequency
controller rather than a resonant filter bank is taken for stability analysis

1
G v (s)=
3 2
(3.14)
T L f Cf s +Cf (L f + T rL )s +[Cf (K ad +rL )+ T ]s+1
 49

where,

Kad- is gain appears to play a significant role in determining the

Characteristic equation and the stability behavior of the system.

T measure samp PWM (3.15)

In order to investigate the stability of the given linear system, the

Routh-Hurwitz stability criterion is employed. For this purpose the output
voltage is expressed in Equation (3.16) in terms of numerator and
denominator terms C(s), D(s) and R(s) as given in Equations (3.17) to (3.19).
R(s) is the characteristic equation of the control system.

C(s) * D(s)
VC (s)= VC (s)+ I o (s) (3.16)
R(s) R(s)

2 2
C(s)=K ps +2Kim s+K p (m e ) (3.17)

2 2
D(s)=-(L f s+rL )(1+s T )(s +(m e ) ) (3.18)

5 4 3 2 5
R(s)=a 0 s +a1s +a 2 s +a 3s +a 0s +a 5 (3.19)

In the above denominator term R(s), the coefficients are given in

terms of the circuit parameters and controller parameters in Equations (3.20)
to (3.24).

a1 =Cf ( T rL +Lf ) (3.20)

2
a 2 =C f (rL + T L f (m e) +K ad )+ T (3.21)

2
a 3 =Cf (m e) ( T rL +Lf )+K p +1 (3.22)
 50

2 2
a 4 =C f (m e) (rL +K ad )+K im + T (m e ) (3.23)

2
a 5 =(m e) (K p +1) (3.24)

The Routh-Hurwitz stability criterion states that the necessary (but not
sufficient) condition for stability is that all the coefficients of the
characteristic equation R(s) must be positive. Since for the system stability
negative feedback is employed, all the controller coefficients Kad, Kimand Kp
must be positive by definition. With this assumption, reviewing the above
coefficient equations, it can be clearly seen that all the coefficients are
positive for positive controller gains. Thus, the necessary condition for
stability is satisfied. The sufficient condition involves ordering the
coefficients according to the Routh-Hurwitz criterion ordering table shown in
Table 3.4 and then obtaining the additional coefficients b1, b2, c1, c2, d1, e1
defined in Equations (3.25) to (3.30). Using the values of coefficients from
the Table 3.4, stability analysis is done and shown in Figure3.17

Table 3.4 Routh Hurwitz Criterion

S5 a0 a2 a4
S4 a1 a3 a5
S3 b1 b2 0
S2 c1 c2
S d1 0
e1
 51

2
a1a 2 -a 0 a 3 T rL - T K p Lf
b1 = =Cf (K ad +rL )+ (3.25)
a1 r +L f
T L

2
a1a 4 -a 0 a 5 2 K p (m e) Lf T
b2 = =K im +(K ad +rL )Cf (m e) - (3.26)
a1 T rL +L f

2
C f ( T rL +L f )Cf (m e) rL K
b1a 3 -b 2 a1 im
c1 = =K p +1- (3.27)
b1 Cf K ad - T K p

b1a 5 -b 3 a1 2
c2 = =(m e) K p +1 (3.28)
b1

c 1b 2 -b 1c 1
d1 = (3.29)
c1

d1c2 -c1d1
e1 = =(m e ) 2 (K p +1) (3.30)
d1

Assuming that L f >> T rL and K ad >> rL the above coefficients can be

approximated in the following equations.

b1 Cf K ad - T K p (3.31)

b2 K im +(m e )2 (Cf K ad - T K p ) (3.32)

Cf Lf K im
c1 K p +1- (3.33)
C f K ad - T K p

Figure 3.17 shows the bode plot of open loop controller for three
phase four wire inverter. From the Figure it is observed that the system is
stable for the input voltages of 180V to 270V.
 52

Bode Diagram
Gm = 246 dB (at 5.77e+005 rad/sec) , Pm = -180 deg (at 0 rad/sec)

-50

-100

-150

-45

-90

-135

-180

-225
-4 -3 -2 -1 0 1 2 3
10 10 10 10 10 10 10 10
Frequency (rad/sec)

Figure 3.17 Magnitude and Phase Plots of Output Voltage Control of

Four Wire Inverter

3.8 SIMULATION RESULTS

The proposed three phase four wire inverter with controller is tested
with online UPS system and it is simulated on Matlab/Simulink. The AC
output voltage is generated by the four wire inverter with filter and without
filter condition. To validate the simulation results 3kVA, 1200V, 10A, 50HZ
prototype four wire inverter is fabricated in the laboratory.

From the simulation analysis it is evident that the neutral leg

provides a lower impedance loop for unbalanced current and triplen
harmonics, so the imbalance of output is drastically reduced. The neutral
inductance LX can reduce the current that flows through the switching
components of neutral leg. Figure 3.18 shows the simulated line and phase
 53

voltages of four wire inverter. It shows the neutral voltage during balanced
condition. Figure 3.19 shows the line and phase voltages during unbalanced
conditions. Figure 3.20 shows the simulated line current waveforms with filter
circuit. Figure 3.21 shows the simulated waveform of four wire inverter with
controller. The controller provides constant terminal voltage during sag conditions.

Figure 3.18 Simulation Result for Output Line Voltage after Filter

Figure 3.19 Simulation Result for Output Line Voltage before Filter
 54

Figure 3.20 Simulation Result for Output Current

Figure 3.21 Closed Loop Output Voltage for Controller

To predict the performance of the proposed UPS system, the load

test is conducted and the corresponding input current and output voltage THD
are measured and tabulated as shown in Table 3.5.The input THD is almost
same for different loading conditions but the output voltage THD is varying
with respect to load variations as shown in Figure 3.22. The input current
 55

THD is varying with respect to switching frequency as shown in Figure 3.23.

The higher the value of the switching frequency, more is the harmonics
injected into the input side of the converter and hence greater is the value of
THD.

Fundamental (50Hz) = 190.1 , THD= 4.86%

1.5

0.5

0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order

Figure 3.22 THD for the Terminal Voltage of Four Wire Inverter With
Filter

Fundamental (50Hz) = 190 , THD= 30.99%

20

15

10

0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order

Figure 3.23 THD for the Terminal Voltage of Four Wire Inverter
Without Filter
 56

3.9 EXPERIMENTAL RESULTS AND DISCUSSION

To validate the simulation results, an experimental setup of 1kVA,

440v, 50Hz 3phase four wire inverter is fabricated in the laboratory. The
simulation results very well coincide with experimental results. The PIC
microcontroller is used to generate the gating pulses to the four wire inverter.
The power IGBT is used as power switch. The line voltages across the phases
without filter at switching frequency of 1200 HZ are measured and shown in
Figures 3.24 to 3.28. From the Figures it is observed that the magnitudes of
line voltages of all the phases are equal with desired phase displacement
because of the neutral voltage control in FWI where as it is not so in
traditional three wire inverter.

The disturbances if any is due to the approximation in the time

calculation as explained below. The first step was to determine the values for
all parameters used to obtain the time variables. These parameters affect the
values of time variables and also the pulse width of the output pattern. The
fundamental frequency was set to the desired value of 50 Hz. The
implementation process of the project was initially conducted for low
switching frequency of 300Hz. Next the sampling frequency was increased to
1200 Hz and results were obtained.

Figure 3.24 Line-Line Voltage (A-B) of FWI at Switching Frequency of

1200Hz
 57

Figure 3.25 Line-Line Voltage (B-C) of FWI at Switching Frequency of

1200Hz

Figure 3.26 Line-Line Voltage (C-A)of FWI at Switching Frequency of

1200Hz

Figure 3.27 shows the line to line voltages of FWI with filter. From the Figure it is
observed that the voltage spikes are present in some of the lines where the
magnitude of voltage is around 270 V. This may damage the switches during the
active mode of operation.
 58

Figure 3.27 Line-Line Voltage of FWI at Switching Frequency of

1200Hz with Filter

Figures 3.28 to 3.30 show the gating pulses for the three legs of the inverter.
Each figure shows two pulses that are complementary in operation .i.e.
whenever upper switch is on, lower switch is off. Table 3.5 shows the line
voltages of four wire inverter across the phases with filter at switching
frequency of 300 Hz.

Figure 3.28 Gating Pulses for Upper and Lower Switches of A Phase
 59

Figure 3.29 Gating Pulses for Upper and Lower Switches of B Phase

Figure 3.30 Gating Pulses for Upper and Lower Switches of C Phase

Table 3.5 gives the variation of output voltage THD for two
different value of switching frequency in FWI. From the table it is observed
that the % of THD of output voltage is around 80% higher than the % THD
with filter. The lower value of switching frequency introduced more
 60

harmonics in its output voltage. The percentage of THD in 300Hz switching

frequency is around 60% higher than THD in 1200Hz switching frequency.

Table 3.5 Voltage and THD at Two Switching Frequencies of FWI

Switching DC Link %THD

Vrms Vpeak
Frequency Phases Voltage Before After
(V) (V)
(HZ) (V) Filter Filter
A-B 190 115 192 81 12.4
300 B-C 190.1 116 198 85 8.4
C-A 190 115 191 89.5 8.2
A-B 190 100 120 32.34 6
1200 B-C 189.7 102 117 31.12 5.7
C-A 190.2 100 115 30.99 4.86

Results taken are for two different switching frequencies i.e. 300Hz
and 1200Hz. First the experiment was performed for 300Hz. Later the number
of samples was increased to 24. PIC has following advantages like low cost,
wide availability, extensive collection of application notes, availability of low
cost or free development tools etc. PIC 16f877A is a low end processor and
hence it has limitations in terms of processing speed where a lot of online
mathematical calculation is involved. Probably it won’t be a problem with
high level processors like DSPIC, DSP, FPGA etc. Considering the accuracy
of time calculation, one should use float numbers in order to obtain accurate
time variables. All embedded C program is converted to assembly level
before compiling and time consumption for processing float variables is more
in assembly language. Rounding up the time values to nearest integer by
means of some offline calculations, it was possible to get the fundamental
frequency of 50Hz.Results were taken for two sets of sampling frequency i.e.
300Hz and 1200Hz .As the Sampling frequency increases, THD decreases.
 61

3.10 SUMMARY

The basic operation and drawbacks of conventional four wire

system are briefly explained in this chapter. In order to overcome these
drawbacks, a solid state four wire inverter has been implemented for the UPS
systems. The four wire inverter based UPS system is simulated and analyzed
for various input and output conditions. The stability of the system is
analyzed using transfer function model. The Space Vector PWM scheme is
used to control the FWI. Two switching frequencies are used to predict the
performance of FWI. At higher switching frequency the FWI provides lower
value of THD whereas switching losses are higher. The dead time in the
PWM inverter the output and input side THD is around 31 % and 42 %
respectively. The limitations in the conventional FWI are overcome by
introduction of FWZSI and ZSMLI for UPS systems and to be discussed in
chapter 4 and 5.