SAT-based Complete Logic Implication With Application To Logic Optimization

SAT-based Complete Logic Implication
with Application to Logic Optimization
Yung-Chih Chen1 and Kung-Ming Ji2

Yuan Ze University, Taiwan1
ITRI, Taiwan2
30/04/2014
Outline
 Introduction
 Background
 SAT-based complete logic implication
 Enhanced node-merging method
 Experimental results
 Conclusion
2
Introduction
 Logic implication
 A process to find the necessary assignments for a given set
of value assignments in a Boolean circuit
1 1
1 1
1
 The core engine of several EDA techniques on

 Logic optimization
 Design verification
 ATPG
 The qualities of these techniques largely depend on
the completeness of logic implication
 More complete -> better quality -> more execution time
3
Previous works on logic
implication
 Most of them focus on efficiently identifying logic
dependencies and are not guaranteed to find all
necessary assignments
 The process is computation-intensive
 The performance of previous computers is not good
enough
 Recursive learning technique [Kunz et al, 1994]
 Work by recursively calling certain learning functions
 Possible to identify all necessary assignments when the
recursion depth is unbounded
 Time complexity is exponential to the recursion depth
 The recursion depth is often bounded to 1 or a low value
4
Motivation
 The performance of computers has been improved

enormously
 Previous efficient methods could be too efficient,
especially for dealing with small or middle-sized circuits
 Efficiency benefit may not be worth the equality expense
 Developing a complete logic implication method
with reasonable efficiency is desirable
 SAT solving techniques have been dramatically
advancing in the past decade
 Applying them to logic implication seems promising
5
Problem formulation
 Given a Boolean network and a set of value

assignments in it, find all the necessary
assignments for the given value
assignments
 Inputs
 A Boolean network
 A set of value assignments
 Output
 All the necessary assignments
6
Outline
 Introduction
 Background
 Conclusion
7
Boolean SAT problem (1/2)
 In Boolean logic, a formula is said to be in

conjunctive normal form (CNF), if it is a
conjunction of one or more clauses
 Each clause is a disjunction of one or
more literals
 Each literal is a variable or a negated
variable
( A)  (A  B  C )  (B  D )  (C  D )
clause negated
variable
8
Boolean SAT problem (2/2)
 Boolean SAT is a problem of

 finding an assignment (or a solution) under
which a given CNF formula evaluates to true
(i.e., satisfiable), or
 proving that there is no such assignment (i.e.,
unsatisfiable)
 NP-complete
9
Backbone
 In a CNF formula, a variable is said to be a

backbone if it has a fixed value in all the
solutions for the formula
( A)  (A  B  C )  (B  D )  (C  D )
A = 1 and D = 1 are backbones
 Finding all the necessary assignments is

similar to finding all the backbones in a
formula
10
Outline
 Introduction
 Background
 Conclusion
11
Our intention
 Model the problem of finding all necessary

assignments as a backbone computation
problem
 Two-stage approach
 Candidate collection
Random simulation
 Candidate validation
Iteratively eliminate invalid candidates by SAT
solving
Finally, only valid candidates are left and they are
all the necessary assignments
12
Candidate collection
 Simulate a set of random patterns and analyze

the simulation results
 A node n with a value v is said to be a
candidate if n=v for all the random patterns
satisfying all the given value assignments
1 0 1 1 0 1
1 0 1 n0 n8
n3 1 1 1 n10
1 1 0
1 1 1 n1 n5 1 1 0 n12
n7
n4 n11
n2 n6 n9
1 1 1 1 1 0
1 1 0
1 1 1 1 1 0
Given value assignment: n7 = 1
Candidates: n1=1, n2=1, n4=1, n5=1, n6=1, n9=1, n10=0, n11=1, n12=1 13
Candidate validation (1/2)
 Iteratively identify invalid candidates and

eliminate them
 Finally, all the remaining candidates are
valid, and they are all the necessary
assignments
 How to identify invalid candidates
 A candidate n = v (v is 0 or 1) is invalid, if there exists an
input pattern that generates all the given value
assignments and n = v’ (v’ is the inverse of v)
 We model the invalid candidate
identification problem as a SAT problem
 Use a SAT solver to find such input patterns
14
•A Boolean network C
•A set of given value Sg: n7 = 1
assignments Sg Sc: n1=1, n2=1, n4=1, n5=1, n6=1, n9=1, n10=0, n11=1,
•A set of candidates Sc n12=1
Transform C into a CNF

formula and add the CNFC  ( n7 )
clauses with respect to Sg
into the formula
b0=0 implies n1=1 is invalid
Add the clauses with CNFC  (n7 )  (b0  n1 )  (b1  n2 )  (b2  n4 )  (b3  n5 ) 
respect to Sc into the (b4  n6 )  (b5  n9 )  (b6  n10 )  (b7  n11 )  (b8  n12 ) 
formula (b0  b1  b2  b3  b4  b5  b6  b7  b8 )
No All necessary
SAT? assignments Suppose b1 and b2 are 0 and the other bi are 1
Yes Eliminate n2 and n4
Eliminate invalid candidates CNFC  ( n7 )  (b0  n1 )  (b1  n2 )  (b2  n4 )  (b3  n5 ) 
and add learnt clauses into (b4  n6 )  (b5  n9 )  (b6  n10 )  (b7  n11 )  (b8  n12 ) 
the formula based on the (b0  b1  b2  b3  b4  b5  b6  b7  b8 ) 
reported solution
(b1 )  (b2 ) 15

clauses with respect to Sg
into the formula
Add the clauses with CNFC  (n7 )  (b0  n1 )  (b1  n2 )  (b2  n4 )  (b3  n5 ) 
respect to Sc into the (b4  n6 )  (b5  n9 )  (b6  n10 )  (b7  n11 )  (b8  n12 ) 
No All necessary
SAT? assignments Suppose b5 is 0 and the other bi are 1
Yes Eliminate n9
reported solution
(b1 )  (b2 )  (b5 ) 16

• We
clauses with iteratively
respect to Sg identify invalid candidates and eliminate them,
into theuntil
formula all the invalid candidates are removed
• At each iteration of
CNF
SAT ( n
solving,
)  ( b  n
at
)  (
least
b  n )
one
 ( b 
invalid
n4 )  (b3  n5 ) 
Add the clauses with C 7 0 1 1 2 2
candidate is removed
respect to S into the (b  n )  (b  n )  (b  n )  (b  n )  (b  n ) 
c 4 6 5 9 6 10 7 11 8 12
No All necessary Finally, UNSAT
SAT? assignments n1=1, n5=1, n6=1, n10=0, n11=1, and n12=1 are all
Yes the necessary assignments
reported solution
(b1 )  (b2 )  (b5 ) 17
Outline
 Introduction
 Background
 Conclusion
18
Node merging
 Node merging is a logic optimization

technique
 Replace one node with another node in a logic circuit
v8 can be replaced with v6 without affecting the functionality
The node count decreases by 1
v12
v1 v5 v9
v2 v6 v10
v13
v3
v7
v11 v6 is a substitute node of v8
v4
v8 And Inverter Graph 19
ATPG-based node-merging
method
 For each node in the network, the method finds
its substitute nodes to replace it
 Substitute node identification procedure for each
node involves two logic implications
 The optimization quality largely depends on the
completeness of the logic implications
 Replace the original logic implication method

with the proposed complete logic implication
method
 Two speedup methods are proposed
 The key idea is to eliminate candidates before SAT solving
Y. C. Chen and C. Y. Wang, “Fast Detection of Node Mergers Using Logic Implications,” in Proc. ICCAD, 2009 20
Outline
 Introduction
 Background
 Conclusion
21
Experimental results
 IWLS 2005 benchmarks

 Small or middle-sized benchmarks
 Totally 20 benchmarks cost less than 1 hour
Benchmark Node Original version Enhanced version
count
Reduction (%) T (s) Reduction (%) T (s)
tv80 7233 3.6 7.0 9.1 556.2
s38417 8185 0.3 0.7 0.9 261.4
mem_ctrl 8815 16.9 4.7 19.4 720.6
s38584 9990 1.3 8.2 2.1 525.2
ac97_ctrl 10395 0.2 1.3 0.2 327.0
systemcaes 10585 0.6 7.8 1.3 590.5
usb_funct 13320 2.1 4.1 4.5 867.8
pci_bridge32 17814 0.4 8.5 1.1 1479.2
aes_core 20509 0.6 8.9 3.3 2284.7
Average reduction ratio is 2.3

Y. C. Chen and C. Y. Wang, “Fast Detection of Node Mergers Using Logic Implications,” in Proc. ICCAD, 2009 22
Outline
 Introduction
 Background
 Conclusion
23
Conclusion
 We propose a SAT-based method for

complete logic implication
 It takes advantage of the efficiency of modern
SAT solvers
 We apply the method to enhance an ATPG-

based node-merging method
 Other techniques that require complete

logic implication could benefit by adopting
the proposed method
24
Thank you for your attention!!
25

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SAT-based Complete Logic Implication

with Application to Logic Optimization

Yung-Chih Chen1 and Kung-Ming Ji2

 The core engine of several EDA techniques on

 The performance of computers has been improved

 Given a Boolean network and a set of value

 In Boolean logic, a formula is said to be in

 Boolean SAT is a problem of

 In a CNF formula, a variable is said to be a

 Finding all the necessary assignments is

 Model the problem of finding all necessary

 Simulate a set of random patterns and analyze

 Iteratively identify invalid candidates and

Transform C into a CNF

Transform C into a CNF

Transform C into a CNF

 Node merging is a logic optimization

 Replace the original logic implication method

 IWLS 2005 benchmarks

Average reduction ratio is 2.3

 We propose a SAT-based method for

 We apply the method to enhance an ATPG-

 Other techniques that require complete

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