3 Phase Inverter Design and Verification Application Note

3 Phase Inverter Design and verification with RCP
Application Note
3 Phase Inverter Design with Rapid Control
Prototyping using PSIM and Typhoon-HIL
June 2017
1 www.powersimtech.com
3 phase inverter design and verification

Table of Contents
Introduction .................................................................................................................................... 5
Hardware and Software setup ........................................................................................................ 5
Open loop with PSIM ...................................................................................................................... 6
The power stage.......................................................................................................................... 7
The control circuit ....................................................................................................................... 8
Simulation results ..................................................................................................................... 10
Open Loop code generation simulation ....................................................................................... 11
Generating the code ................................................................................................................. 13
Generated Project import into CCS .......................................................................................... 15
Target Configurations ........................................................................................................... 16
Typhoon HIL power stage setup ............................................................................................... 18
Running the open loop HIL simulation ..................................................................................... 20
ADC conversion setup and SCI communications .......................................................................... 24
Tuning the ADC feedback .......................................................................................................... 27
Scaling the HIL output ............................................................................................................... 31
Scaling the DSP gain and offset................................................................................................. 31
Close loop design .......................................................................................................................... 36
Digital Delay Modelling ............................................................................................................. 37
The simulation results ............................................................................................................... 37
Control Design with SmartCtrl .................................................................................................. 37
Close loop operation ..................................................................................................................... 39
Step Response Simulation......................................................................................................... 41
Protection Setup and Design Iteration ......................................................................................... 43
HIL simulation of faults ............................................................................................................. 45
Overcurrent fault .................................................................................................................. 46
Overvoltage/Undervoltage fault........................................................................................... 47
Heastsink overtemperature condition.................................................................................. 47
Figure 1- Open loop 3 phase VSI ..................................................................................................... 6

Figure 2 - Open loop power stage................................................................................................... 7
Figure 3 - Open loop control circuit ................................................................................................ 8
Figure 4 - Simulation Control setup ................................................................................................ 9
Figure 5 - Open loop current waveforms...................................................................................... 10
Figure 6 - Open loop Carrier and modulation waveforms (wide view) ........................................ 10
Figure 7 - Open loop carrier and modulation waveform (close view) .......................................... 10
Figure 8 - Open Loop PSIM schematic with PWM code generation ............................................. 11
Figure 9 - PSIM F28335 PWM control block ................................................................................. 11
Figure 10 - PSIM F28335 3 phase PWM attributes ....................................................................... 12
Figure 11 - Simulation Control SimCoder setup for F28335 ......................................................... 13
Figure 12 - Generating Code from PSIM ....................................................................................... 13
Figure 13 - PSIM generated code folder ....................................................................................... 14
Figure 14 - PSIM generated code files .......................................................................................... 14
Figure 15 - Import Legacy CCSv3.3 project menu option ............................................................. 15
Figure 16 - Legacy CCS project import file selection screen ......................................................... 15
Figure 17 - Legacy project import compiler selection .................................................................. 16
Figure 18 - Successfully imported project files from PSIM to CCS................................................ 16
Figure 19 - Target Configurations panel ....................................................................................... 17
Figure 20 - Target configuration setup screen.............................................................................. 17
Figure 21 - Target Configuration being set to 'Default' ................................................................ 17
Figure 22 - The CCS Debug launch tool bar button ...................................................................... 18
Figure 23 - Typhoon HIL schematic of a three-phase inverter power stage ............................... 18
Figure 24 - Three phase inverter component switch mapping .................................................... 19
Figure 25 - HIL docking station PWM pin mapping ...................................................................... 19
Figure 26 – HIL SCADA screen with voltage source setting for open loop simulation ................. 20
Figure 27 - HIL DSP interface card with TI F28335 controlCARD mounted .................................. 21
Figure 28 - Shows the CCS Debug screen after a successful launch into pause state .................. 21
Figure 29 – SCADA panel for visualization and simulation control of the loaded inverter. ......... 22
Figure 30 – Typhoon HIL phase current signals coming from Capture/Scope widget ................. 22
Figure 31 - PSIM simulation results .............................................................................................. 22
Figure 32 - 3 phase inverter with SCI comms schematic .............................................................. 24
Figure 33 - dq reference frame open loop control ....................................................................... 25
Figure 34 - Addition of ADC block to control cicuit ...................................................................... 25
Figure 35- ADC sampling settings ................................................................................................. 26
Figure 36 - PWM settings for ADC conversion.............................................................................. 26
Figure 37 - DSP Oscilloscope location in Utilities menu ............................................................... 27
Figure 38 - Select SCI COM port .................................................................................................... 27
Figure 39 - Successfully connected DSP 'scope' displaying the 3 phase feedback signals ........... 28
Figure 40 - SCI out element implementation................................................................................ 29
Figure 41 - Unscaled analog input singals..................................................................................... 30
Figure 42 - Ia_fb with HIL 1 A per Vdac......................................................................................... 31
Figure 43 - Ia_fb with HIL 10 A per Vdac....................................................................................... 31
Figure 44 - ADC signal before software offset and scaling ........................................................... 32
Figure 45 - HIL simulation signal to be matched .......................................................................... 32
Figure 46 - Adjusting the DSP scale for sensitive adjustments ..................................................... 33
Figure 47 - Adjusting the offset with the DSP scope .................................................................... 33
Figure 48 - Analog feedback signal with proper gain and offset .................................................. 34
Figure 49 - 3 Properly scaled feedback signals ............................................................................. 35
Figure 50 - AC sweep simulation................................................................................................... 36
Figure 51 - AC Sweep control ........................................................................................................ 36
Figure 52 - AC probe element ....................................................................................................... 36
Figure 53 - Open loop frequency response .................................................................................. 37
Figure 54 - SmartCtrl Design space ............................................................................................... 38
Figure 55 - Closed loop dq control ................................................................................................ 39
Figure 56 - HIL Waveforms with closed loop simulation .............................................................. 40
Figure 57 - A01 & A02 channels probed with external oscilloscope ............................................ 40
Figure 58 - DSP scope waveforms of closed loop HIL simulation ................................................. 41
Figure 59 - Offline simulation step response in Iq_ref ................................................................. 41
Figure 60 - Real-time simulation of step response in Iq_ref ....................................................... 41
Figure 61 - Over/under voltage protection .................................................................................. 43
Figure 62 - C block being used to define the overcurrent fault response .................................... 44
Figure 63- Heatsink over temperature detection ......................................................................... 44
Figure 64 - ADC & HIL setup for DC bus detection and heatsink temperature ............................ 44
Figure 65 - Typhoon HIL three-phase inverter schematic with fault-testing elements............... 45
Figure 66 - Inverter View panel for fault and system simulation ................................................. 46
Figure 67 - Contactor control settings .......................................................................................... 46
Figure 68 - HIL simulation of line to line fault with control clearing ............................................ 46
Figure 69 - Control response to DC bus overvoltage .................................................................... 47
Figure 70 - Control response to heatsink over-temperature with Iq_ref reduction .................... 47
Introduction
This application note will introduce how to implement a 3 phase voltage source inverter with dq
control and implement on a TI C2000 MCU (TMS320F28335). Verification of the control algorithm
will be performed with a Typhoon HIL real-time Hardware-In-the-Loop simulation. The concept of
rapid control prototyping, RCP, will be used to test and verify the operation of the inverter. Rapid
control prototyping is made possible by combining automated embedded code generation from
PSIM with a high fidelity real-time hardware simulation from Typhoon–HIL. A properly defined RCP
platform should allow the question “Does it work?” to be answered in real-time and if it does not
work a solution can be quickly implemented and tested again. The workflow for sequential
implementation and testing is as follows:
1. Simple open loop simulation and HIL verification

2. Perform control design simulation
3. Verify close loop with HIL simulation
4. Introduce faults and other test scenarios
5. Iterate the design
The open loop section will cover the initial PSIM schematic setup and open loop code generation.
The most important part of this section is the setup of the analog feedback signals while the
inverter is working in open loop.
The close loop section introduces a method for designing stable PI controllers for Id and Iq in the z-
domain. These controllers are then implemented with PSIM and tested with the HIL system
The final part of this document covers some preliminary fault handling and operational scenarios. In
this section the concepts and methods used can be applied to a broad range of test scenarios.
These methods should act as the starting point for continued analysis and design iteration of the
inverter from a proof of concept to a robust field ready design.
Hardware and Software setup
Offline simulation and embedded code PSIM Professional with Digital control,
generation platform (required): SimCoder & F28335 target
Control loop design software (optional): SmartCtrl Pro
Hardware-in-the-Loop simulation platform: HIL 402, 600, or 602*
*The HIL 602 is used in this document and was used to generate the files. All of the HIL simulations
performed can be done with the 402, 600, or 602 unit.
Open loop with PSIM
PSIM file: 3phase VSI open-loop no code.psimsch

Typhoon-HIL files: None – not used in this section
In this section an open loop 3 phase voltage source inverter will be simulated with PSIM. Once open
loop operation is confirmed the simulation will be setup to generate code to program an F28335
MCU from Texas Instruments. The operation of the open loop code will be confirmed with a real-
time Hardware-In-the-Loop simulation using Typhoon HIL.
Referring to the PSIM schematic “3phase VSI open-loop no code”
There are two main parts to the simulation:

the power stage (red traces) and the control
circuit (green traces). Progressing to the
implementation of a full dq reference
controller the power stage will remain
essentially constant while increasing
complexity is added to the control circuit.
Figure 1- Open loop 3 phase VSI
Figure 2 - Open loop power stage
The power stage
DC bus voltage source

 Defines the DC bus voltage
6 ideal switches
 Models an ideal switch the “MOSFET”
variant is being used which can model
an Rdson conduction loss. The ideal bi-
directional, ideal MOSFET, and ideal
IGBT are equivalent apart from how
conduction losses are modelled.
3 current sense elements: Ia, Ib, Ic

 These are monitoring the current
flowing through the wires connecting
the load to the inverter
A balanced 3phase RL load, 10 ohms and 1 mH

 This is the RL3 element from the library
models a balanced 3 phase load. It is
convenient to use when doing balanced
three phase simulations as it is the
equivalent of 6 discrete elements.
6 on/off switch elements

 This element converts the control
gating signal into a power circuit gating
signal. This element is required to gate
an ideal switch in PSIM.
The control circuit
Figure 3 - Open loop control circuit
Reference phase voltage source

 Provides the modulation waveforms for
open loop operation
 Initial setting is 0.8 V peak
 120 phase shift between the three
sources
Comparator element
 Compares the modulation waveform
with the carrier waveform to get the
gating signals for the switches
Triangular Voltage source

 Generates the carrier waveform
 Initial setting is a Vpk-pk = 2V with Vmin
= -1V and Vmax = 1V with a 50% duty
cycle
Logic not gate

 Negates the top switch gating signal to
generate the bottom switch signal
Simulation Control sets the simulation

run parameters for the PSIM engine.
Time Step and total time can be set
here. A good default setting for speed
and accuracy is to have 100 data points
for the switching period.
1/(Fsw*100)
We are simulating a fundamental

frequency of 60 Hz with a switching
Figure 4 - Simulation Control setup
speed of 10k, a Time step of 1 us gives
us 100 point per switching period. A
simulation time of 30ms gives us ~2
cycles of the fundamental.
Simulation results
Figure 5 - Open loop current waveforms
Figure 6 - Open loop Carrier and modulation waveforms Figure 7 - Open loop carrier and modulation waveform (close
(wide view) view)
Figures 5 – 7, show the open loop PSIM simulation results. Figure 5 shows three balanced
currents compared with the modulation waveform for phase A. Figure 6 and 7 shows how the
modulation waveform, Vma, is being compared with the carrier waveform, V_car.
Open Loop code generation simulation

PSIM file: 3 phase inverter open loop code gen.psimsch
Typhoon-HIL files: None – not used in this section
Figure 8 - Open Loop PSIM schematic with PWM code generation
There are a few changes between the simple open loop simulation from the previous section
and the one that is code generation compatible. The way the device gating signals are
generated has changed and there are changes to be made in the simulation control element.
The gating waveforms are now generated by a 3-ph PWM (F28335) control block.
Figure 9 - PSIM F28335 PWM control block
The 3-ph PWM control block is fed with the modulation waveform and has an internal carrier
waveform setup.
Figure 10 - PSIM F28335 3 phase PWM attributes
The default values of the 3-phase PWM block which defines a carrier waveform of Vmax = 1V
Vmin = 1V @ 10KHz with a duty cycle of 50% can be used. The PWM signals will output on:
 PWM 1A & 1B – ‘up’ & ‘un’ (pins 5 & 6)

 PWM 2A & 2B – ‘vp’ & ‘vn’ (pins 7 & 10)
 PWM 3A & 3B – ‘wp’ & ‘wn’ (pins 11 & 12)
A detailed discussion of the settings can be found in the SimCoder user manual and a brief
explanation can be read by clicking the components “Help”. This setting are important as the
output pins from the MCU will need to be mapped to the proper input pins of the HIL and
eventually the real hardware.
There is a setting to define the deadband; however, this block will not implement deadband
during simulation as this can impact simulation time-step requirements and can lead to slow
simulations and it is not necessary for a system level simulation. If you are interested in
simulating deadband, example circuits exist in the PSIM examples folder.
The “SimCoder” tab of simulation control is now setup to generate code for the F28335
processor, figure 11.
Figure 11 - Simulation Control SimCoder setup for F28335
The only setting that needs to be selected is that the CPU version matches the hardware that
you will be programming, the Delfino F28335 is assumed. The F28335 is a floating point
processor and floating point code will be generated. If a fixed point processor is used fixed
point code will be generated. Fixed point code generation is covered in a separate application
note.
Generating the code
To generate the code go to “Simulate-

>Generate Code”
Figure 12 - Generating Code from PSIM
In the folder that the schematic is saved in a new folder will be created with the schematic file
name and (C code) appended.
Figure 13 - PSIM generated code folder
This folder contains the generated code and associated files required to program the target
MCU.
Figure 14 - PSIM generated code files
The generated files define a full Code Composer Studio Project that can be imported into CCS.
The *.c file contains the converted code from the simulation, the other files are generated by
PSIM and are used by CCS when compiling the *.out file that will be loaded to the target MCU.
Generated Project import into CCS
Figure 15 - Import Legacy CCSv3.3 project menu option Figure 16 - Legacy CCS project import file selection screen
Browse the “*.pjt” file in the wizard that will

From CCS go to “Project->Import Legacy pop up.
CCSv3.3 Projects…”
Click “Next >”
The generated files are compatible with the
free license of CCS version 3.3 and higher.
Figure 18 - Successfully imported project files from PSIM to

CCS
Figure 17 - Legacy project import compiler selection
Click “Finish”. In your Project Explorer view you will see the
project files imported.
A warning will likely pop up mentioning a
missing path to “xdias” this can be ignored.
Important note: once the project is imported you do not need to repeat the process.
Generating code from PSIM from the original schematic will update the associated “*.c” file in
the imported project.
Target Configurations
The target configuration defines the processor and the connection method used to program it.
Defining the correct target configuration is critical for a successful upload of the compiled *.out
file to the target MCU. Thankfully, defining the proper configuration is a relatively easy task
covered in this section. The target configuration is the *.ccxml file in your CCS project.
To open the target configuration panel go to

‘View->Target Configurations’
Figure 19 - Target Configurations panel
Figure 20 - Target configuration setup screen
Use these settings to program a TMS320F28335 processor with XDS100v2 JTAG interface. The
XDS100v2 debug probe is the most common type as it is built onto most development kits
and later generation controlCARDs. There is an option to test the connection on the right.
Save the target configuration and give it an

appropriate name. In the figure to the left,
the configurations have been named based
on the processor variant and connection
method. Right click on the “*.ccxml” file that
you want to use and set it as default.
Figure 21 - Target Configuration being set to 'Default'
The project is now ready to build and load onto the MCU. The default action of the “Debug”
button is to build a new “.out” file and to load it to the MCU. There is no need to clean or
rebuild the project.
Figure 22 - The CCS Debug launch tool bar button
Typhoon HIL power stage setup
PSIM file: 3 phase inverter open loop code gen.psimsch

Typhoon HIL schematic: HIL 600 3 phase inverter.tse
Typhoon HIL SCADA panel: 3 Phase Inverter SCADA.cus
Typhoon HIL model settings: simple settings_inverter.runx
Figure 23 - Typhoon HIL schematic of a three-phase inverter power stage
The HIL power stage, “HIL 600 3 phase inverter.tse”, will be identical to the PSIM power stage.
At the moment we are only interested in the inverter connected to the upper three-phase load.
Contactors for load switching and fault simulation as well as the heat sink circuit will be
discussed later. There are four main components:
 Voltage source – parameters defined from the HIL SCADA

 Load Resistors and Inductors R1, R2, R3, L1, L2, L3. As per PSIM 5 Ohms and 5 mH
 Three phase inverter – a predefined configuration of 6 switches forming a single level
inverter
 Phase current measurements IA, IB, & IC
 R4 is defined with a small impedance 0.01 Ohms to prevent degeneration of the power
stage during simulation
The only settings that need to be adjusted from the schematic are which digital input ports drive
the switches.
Figure 24 - Three phase inverter component switch mapping Figure 25 - HIL docking station PWM pin mapping
From Table 2 of TI Docking Station User Guide, t-ug009.pdf, the PWM signals of interest are
 DI 1 & 7 PWM 1A/1B

 DI 2 & 8 PWM 2A/2B
 DI 3 & 9 PWM 3A/3B
This circles back to the 3 Phase PWM settings discussed in figure 10, from the PSIM embedded code
generation schematic, as the mapping needs to match what the code is setup to drive.
The model is ready to be compiled and loaded to the HIL as is. Once the model is loaded the HIL
SCADA screen will load.
Figure 26 – HIL SCADA screen with voltage source setting for open loop simulation
Load the model settings file, “simple settings_inverter.runx”. This file sets the source as a DC source
with a value of 100V, and also it maps current signals IA, IB, and IC to analog outputs A01, A02, and
A03 respectively.
Additionally, for simulation visualization and providing stimulus in runtime, you need to load the
SCADA panel file, “3 Phase Inverter SCADA”.
Running the open loop HIL simulation
To run the open loop simulation on the HIL, you will need to have successfully compiled and loaded
the three-phase inverter schematic, as well as the model and HIL SCADA settings. You will also need
to have successfully built the generated code project.
Figure 27 - HIL DSP interface card with TI F28335 controlCARD mounted
The figure 27 shows the test setup. An F28335 controlCARD is loaded in the TI docking station. A
JTAG XDS100v2 debug probe is visible at the bottom right connected via a ribbon cable to the JTAG
header. The TI docking station is interfaced with the Typhoon HIL 600 unit.
From CCS clicking the ‘debug’ button will build and load the .out file onto the DSP using the defined
target configuration parameters. Once loaded the debug session starts in the “pause” state.
Figure 28 - Shows the CCS Debug screen after a successful launch into pause state
Hit the play button from

the CCS Debug window.
Your HIL SCADA panel
should look like the one
in Figure 29. Press play
from HIL SCADA.. There is
no timing or order
sensitivity with respect to
CCS/HIL SCADA
simulation start. The
processor or the HIL unit
can be started first, one
of the advantages of this
type of testing is that
there is minimal potential
for damage to the HIL
Figure 29 – SCADA panel for visualization and simulation control of the loaded inverter. unit or MCU.
Figure 30 – Typhoon HIL phase current signals coming from Capture/Scope widget
Figure 31 - PSIM simulation results
Figures 30 & 31 compare the HIL real-time simulation results with the PSIM simulation results. The
current ripple in both sense is comparable and the peak to peak values are both +/- 7.5 Amps.
ADC conversion setup and SCI communications
PSIM file: 3 Phase inverter open loop_SCI comms.psimsch

Typhoon-HIL schematic: HIL 600 3 phase inverter.tse
Typhoon-HIL panel: 3 Phase Inverter SCADA.cus
Typhoon-HIL model settings: inverter_system.runx
Referring now to “3 Phase inverter open loop_SCI comms.psimsch”
Figure 32 - 3 phase inverter with SCI comms schematic
The power stage has remained constant but the control stage has now changed drastically from the
simple open loop simulations. The most significant change being that the modulation waveform
that drive the inverter are being generated from dq reference frame values.
There are three DC quantity inputs that define

Id, Iq and the frequency. The frequency
control block is defined in Hz and is scaled by
2*PI before being used by the resetting
integrator to generate theta which is used by
the dq0-abc transformation block.
Figure 33 - dq reference frame open loop control
The theory behind the dq frame will not be covered in this document.
The next major change is the addition of the ADC block.
Figure 34 - Addition of ADC block to control cicuit
The F28335 ADC element setups the analog input channels. The side labeled A0, A1..B7 defines the
input side to the DSP from the analog conditioning circuits of the hardware. The side labelled D0,
D1… D15 represents the sampled and converted signal. On the hardware side an offset is being
applied of 1.65 volts as the raw current feedback signals are AC and the ADC will not accept
negative input signals. This offset is removed by individual offsets, offset_A, offset_B, & offset_C,
for each channel on the code side of the ADC element. The gain of the current feedback signals can
be adjusted individually with the Gain_A, Gain_B, & Gain_C control blocks. The real-time offset and
gain adjustment of the ADC channels is a critical debugging procedure that will be covered later in
this section.
In this circuit the ADC conversion is being triggered by the 3-phase PWM element. Figure 35 shows
the ADC setting, and figure 36 shows the settings from the PWM element.
Figure 35- ADC sampling settings Figure 36 - PWM settings for ADC conversion
The PWM settings show that the PWM timer will trigger the ADC group A with a trigger position at
the beginning of the period. The carrier wave starting low corresponds with the bottom side switch
switching on at the beginning of the period. More information about these settings can be found in
the PSIM SimCoder user manual.
This project makes use of the Serial Communications Interface, SCI, and the controlCARD has
jumper settings that need be properly configured. ‘SW1’ on the controlCARD needs be toggled
depending on your controlCARD rev and connection method. Please refer to the PSIM Tutorial –
“Using SCI for waveform monitoring” for further details.
Generate the code for this project and “legacy import” into CCS following the method describe
earlier you will have two projects defined in CCS now.
3_phase_inverter_open_lopp_code_gen_sci_comms.pjt is the file name that you will be looking for
during import.
The active project is the one that is in

bold type face with the [Active –
1_RamDebug] tag.
As long as the target configuration from

earlier has not been adjusted you are
now ready to debug and flash the MCU
with this program. Again the default
action of “debug” will be to build and
load the ‘out’ file.
 As before the program will launch in the pause state you will need to hit the “Resume”
button from CCS Debug .

 Start the HIL simulation, the power stage model will remain constant HIL 600 3 phase
inverter.
 Identical waveforms from the HIL waveform viewer should be visible.
Tuning the ADC feedback
With 3_phase_inverter_open_lopp_code_gen_sci_comms running on the MCU and with the HIL 600
3 phase inverter running on the HIL unit the DSP oscilloscope utility will be used to monitor the
signals that the ADC has converted.
To connect to the DSP Oscilloscope tool go to

“Utilities->DSP Oscilloscope “
Figure 37 - DSP Oscilloscope location in Utilities menu
Hit the “…” button to browse the available

com ports. If there is more than one COM
port present and you do not know which is
the right one, a unnsuccesful connetion is
OK. If nothing shows up in this menu please
refer to the troubleshooting steps here in the
PSIM Tutorial for SCI connection. Clicking the
Figure 38 - Select SCI COM port
‘Test’ button is part of a more detailed
hardware troubleshooting setup and won’t
help if you are curious which port to connect
to.
Figure 39 - Successfully connected DSP 'scope' displaying the 3 phase feedback signals
After a successful connection the

“Select output variables” will populate
with 4 signals. In the figure 39 the
input current signals have already
been moved over to be displayed.
 Vma
 Ia_fb
 Ib_fb
 Ic_fb
The output signals are defined by the

‘SCI out’ elements.
Figure 40 - SCI out element implementation
The “Set input variables” will also

populate with all of the input variables
that are available.
 freq  Offset_C
 Id_ref  Gain_A
 Iq_ref  Gain_B
 Offset_B  Gain_C
 Offset_A
The input variables are defined by the

“SCI Input” elements.
The analog signals are

generated by the
Typhoon HIL unit and
are controlled from
HIL SCADA “Model
Settings”. The initial
settings that were
loaded (.runx file)
define the analog
mapping.
The initial settings also define that 1 Amp = 1 Volt and that there is no offset applied to the signal.
With these initial settings we should observer the 3 phase feedback signals below with the DSP
Scope.
Figure 41 - Unscaled analog input singals
The waveforms should appear clipped at top and bottom and un-evenly offset with a negative peak
of -1.5V and a positive peak of 1.25V. It doesn’t matter if your waveforms match the figure 41, just
as long as there are three sinusoidal signals present. In the next few steps the signals will be
properly offset and scaled.
Scaling the HIL output
Looking at phase A (Ia_fb) first we can see that the output signal is clipped, this means that the HIL
output scaling needs to be increased changing the scaling to 10 A per 1 Vdac will address this issue.
The difference can be seen in figures 42 & 43.
Changing the
Scaling from 1.0 A
per Vdac to 10 A
per Vdac.
Figure 42 - Ia_fb with HIL 1 A per Vdac Figure 43 - Ia_fb with HIL 10 A per Vdac
Ia_fb = 500mv/DIV Ia_fb = 500mv/DIV
Increasing the scaling of the HIL outputs has addressed the signal clipping. The same change is
applied to all three HIL output settings These settings are saved as “scaled run settings.runx”.
Scaling the DSP gain and offset
This is a critical step, with real hardware the analog feedback of simple DC signals is usually
accomplished with a simple voltage divider circuit. AC signals need to be scaled and offset which is
typically accomplished with Op. Amp circuits. Each one of these Op. Amp circuits can exhibit slightly
different gains and offsets from the theoretical calculations as real components with tolerances
need to be used.
As observed in the example the ADC is currently displaying a sinusoidal signal with a negative offset.
The negative offset needs to be corrected so that the signal is centered on ‘0’ and the gain will be
adjusted so that the real “current” value is observed. The MCU needs to provide a signal that
matches what the HIL waveforms are.
Figure 44 - ADC signal before software offset and Figure 45 - HIL simulation signal to be matched
scaling
The raw MCU feedback signal shows a The HIL waveforms show a peak value of 7.44A
peak to peak ~500mA and a negative centered on 0. The DSP scope waveforms will be
offset. scaled to match the HIL waveforms.
Increase the scale of the DSP scope waveform to allow for more sensitive adjustments.
Figure 46 - Adjusting the DSP scale for sensitive adjustments
Adjust offset_A to shift the signal to so that it is centered on ‘0’.
Figure 47 - Adjusting the offset with the DSP scope
In the figure below the offset_A has been changed to 1.525 from 1.65 and the feedback signal is
now centered on ‘0’. The change required by your hardware will likely be slightly different.
To adjust the amplitude ‘Gain_A’ will need to be adjusted.
Figure 48 - Analog feedback signal with proper gain and offset
With Gain_A adjusted the feedback signal now mirrors what the HIL simulation waveform is an
easy way to check if you have applied proper gain and offset is to insert the peak value into the
display offset and see if the waveform touches ‘0’.
Use the ‘A’ parameters as the starting point for ‘B’ & ‘C’ and adjust as needed.
Figure 49 - 3 Properly scaled feedback signals
Figure 49 shows the three properly scaled feedback signals. The new offset and gain values are not
‘saved’ as the default values and you will need to replace the offset values in the schematic for the
next code generation cycle.
Close loop design
PSIM files 3 phase inverter_acsweep.psimsch

Typhoon-HIL files none
Figure 50 - AC sweep simulation
This simulation is setup to generate a frequency response for the open loop converter. A
perturbation is introduced into the open loop Iq reference with vsin1, the impact of the
perturbation is observed on the feedback value of Iq. PSIM will compare the gain and phase of the
open loop perturbation with the value observed at the ‘ac’ probe element, figure 52.
Figure 51 - AC Sweep control Figure 52 - AC probe element
The parameters for the AC sweep are defined by AC Sweep m-sine element, figure 51. During the
AC sweep the m-sine element drives the vsin1 voltage source through the specified frequency
range. More information about the setup of the AC sweep is covered in the PSIM user manual in
and through various tutorial videos available online.
Digital Delay Modelling
A critical part of the simulation setup for control design is the modelling of digital delay. The delay is
modelled with the addition of two elements the ZOH and the 1/Z blocks. The Zero Order Hold, ZOH,
is inserted after the current sense element, it is modelling the sampling impact of converting a
continuous time signal into a discrete time signal. The 1/Z or unit delay element is delaying the
input to the element by one sampling period which represents the delay of implementing a
controller on an MCU or DSP as the new PWM duty cycle can only be updated at the beginning of
the next timing pulse.
The simulation results

Running the simulation will
generate the bode plot
shown in figure 53. Since
the load is symmetric the Id
& Iq response will be
identical.
This frequency plot is saved

with an *.fra extension and
this file will be imported
into SmartCtrl to generate
PI control values for the
Figure 53 - Open loop frequency response close loop design.
Control Design with SmartCtrl
SmartCtrl is a graphical control loop tuning program, it works by combing the transfer function
of the plant, sensor, and controller together. The plant can be defined with a pre-defined
topology, a set of equations, or as in this case with a frequency response waveform file. With
SmartCtrl the control options are PI, Type 2, or a Type 3 controller.
Figure 54 - SmartCtrl Design space
Once the initial design parameters have been input into SmartCtrl and design space resembling
Figure 54 should appear. The bode plots at left of figure 54 show the control to output or loop
gain plot (pink) and the open loop plant response (green). As the phase margin vs cross
frequency is manipulated in the solution space all of the plots will update.
A robust control design will have a large DC gain, adequate phase margin at the cross over
frequency, and strong attenuation of the switching frequency. All of these control parameters
are observed from the control to output (pink) bode plots. A large DC gain will ensure a fast
response, a phase margin of >40 degrees will ensure stability, and attenuation of the switching
>-20 dB will provide good noise immunity.
From SmartCtrl the control parameters for a cross frequency of 500Hz with a phase margin of
40 degrees for a PI controller are below:
Kp 238.716m
Ti 498.313u
The control parameters from above describe an s-domain transfer function and will need to be
converted to the z-domain with backwards Euler, bilinear, or some other conversion method. The
PSIM element “Digital PI Controller” takes s-domain coefficients and automatically converts to z-
domain with backwards Euler.
Close loop operation
PSIM file: 3 phase inverter close loop code.psimsch

Typhoon-HIL schematic: HIL 600 3 phase inverter.tse
Typhoon-HIL panel: 3 Phase Inverter SCADA.cus
Typhoon-HIL model settings: inverter_system.runx
Open the schematic, ‘3 phase inverter close loop code.psimsch’. This schematic features a
parameter file which is defining simulation vs code generation parameters with conditional
logic to define which set of parameters to use based on the user’s needs. The control
coefficient will be uniform for all use cases. The code generation coefficients might be different
based on your Hardware/HIL systems, adjust the “gain” and “offset” settings for the code gen
based on the numbers that were determined in section “Tuning the ADC feedback”
Generate the code and import to CCS using the steps outlined previously. In the parameter file
ensure that gen_flag = 0, as the state of this flag determines if offsets and gains for code
generation or for simulation will be used. The reason for the difference between the two sets of
parameters is dependent on the scaling of analog outputs from the HIL and how they are
interpreted and scaled by the hardware for the MCU analog inputs. This scaling is covered in
the HIL user guides.
In Figure 55, the full dq

reference control scheme
has been implemented.
Iq and Id can be directly

controlled via the DSP
oscilloscope along with the
frequency.
The current feedback values

can also be observed
Figure 55 - Closed loop dq control
With the HIL power stage running simply start the debug of the MCU, the three phase currents
should be equal and balanced as observed in the Capture/Scope widget, figure 56. The current
values can also be externally observed by probing the analog feedback test points for A01, A02, &
A03, figure 57.
The HIL waveforms show

a peak current waveform
of 8 Amps when Iq_ref =
8 Amps.
Figure 56 - HIL Waveforms with closed loop simulation
Figure 57 - A01 & A02 channels probed with external oscilloscope
Using an external oscilloscope channels A01 & A02 are probed and the analog feedback waveforms
generated by the HIL can be observed. In figure 57, we can see that the HIL scaling output is
showing +/- 0.8V which corresponds with the output being scaled 10A per 1 V in the initial settings.
In figure 58, the DSP scope

utility is used to monitor the
current feedback signals after
they have been converted and
scaled by the F28335 MCU
analog to digital converter. The
signals are properly offset and
scaled at +/- 8 Amps which
corresponds to the HIL
waveforms.
Figure 58 - DSP scope waveforms of closed loop HIL simulation
Step Response Simulation
In figures 59 & 60, the offline simulation of a step response is compared with the real-time
simulation of the same step. In both instances the Iq_ref is changed to 8 Amps and the observing
Iq_fb signal is monitored.
Figure 59 - Offline simulation step response in Iq_ref

Figure 60 - Real-time simulation of step response in Iq_ref
To recreate this real-time simulation, you will need to use the trigger options in the DSP
oscilloscope interface, the settings are in the bottom right of figure 60.
 Trigger on Iq_fb
 Select trigger ‘on’
 Rising edge mode
 Check box “Once” is enabled
 Level = 5
With the trigger setup, simply change the Iq_ref from ‘4’ to ‘8’ and the scope will trigger on the
rising edge.
Protection Setup and Design Iteration
PSIM file: 3 phase inverter close loop code_protection

Tyhpoon-HIL schematic file: HIL 600 3 phase inverter.tse
Typhoon-HIL panel file: 3 Phase Inverter SCADA.cus
Tyhpoon-HIL model settings: inverter_system.runx
This section covers the PSIM schematic “3 phase inverter close loop code_protection.psimch”. This
simulation starts to implement some rudimentary protection and fault response for the inverter.
There are three operating conditions that prompt the protections to activate.
Operating condition Response

DC bus over or under voltage PWM shutdown until condition clears
Over current condition Latched PWM shutdown until rising edge of
reset flag is detected
Heatsink over temperature Reduce power of inverter by reducing Iq
reference by 75%
Figure 61 - Over/under voltage protection
In figure 61 the DC bus feedback voltage is compared with pre-defined voltage thresholds, if the
limit is exceed it stops the PWM timer. The stop/start PWM blocks are active high.
Figure 62 - C block being used to define the overcurrent fault response
In figure 62, a simplified c block is being used to define the over current latch state. The
overcurrent state is reset on the rising edge of ‘cur_rst’.
Figure 63- Heatsink over temperature detection
In figure 63, the heatsink over temperature detection is defined with a simplified c block. In this
case, when the heatsink cross a pre-defined threshold the Iq_ref is reduced by 25%.
For simulation purposes, the DC bus and heatsink analog signals are routed to pins B0 and B1 of
the ADC. When the code is generated and run in a real-time simulation with the HIL assigning
control signals to AO9 and AO10 will correspond with these two analog feedback signals.
Figure 64 - ADC & HIL setup for DC bus detection and heatsink temperature
HIL simulation of faults
The HIL model HIL 600 3 phase inverter.tse needs to be loaded and compiled. This HIL model
has contactors setup to switch between loads, introduce line faults, & has an external source
defining the heatsink temperature.
Figure 65 - Typhoon HIL three-phase inverter schematic with fault-testing elements
As shown in figure 65, both line-to-line and line-to-ground faults are implemented. The “Load
Select” is a triple pole double throw contactor that switches between two three-phase RL loads.
The voltage source labelled ‘heatsink_temp’ will serve as a proxy for the heatsink temperature
feedback circuit. These components will create the over current and over temperature faults
that will be cleared by the code created by the elements in figure 62 and 63.
Compile and load the schematic to your HIL system, once loaded open the SCADA panel ‘3
Phase Inverter SCADA.cus’. Figure 66, has built in widgets to introduce the faults, switching
loads, and monitoring the system status easier to perform.
Figure 66 - Inverter View panel for fault and system simulation
Generate code for “3 phase inverter close loop code_protection.psimch” and load it to the
MCU. Also ensure that the proper HIL simulation is loaded.
Overcurrent fault
The line-to-line fault is simulated by closing contactor “Fault A to B”. It is important that the
contactor has the “SW Control” enabled as in figure 67. This checkbox ensures that HIL SCADA
is in charge of controlling the contactor.
Figure 67 - Contactor control settings
Figure 68 - HIL simulation of line to line fault with control clearing
Overvoltage/Undervoltage fault
Figure 69 shows the response to an overvoltage condition, to trigger this condition the source
Vs1 was set to 155V which exceeds the 150V limit defined in figure 61.
Figure 69 - Control response to DC bus overvoltage
Heastsink overtemperature condition
Figure 70, shows the response to the heatsink temperature hitting 150 dC. This achieved by
changing the source heatsink_temp to 150.
Figure 70 - Control response to heatsink over-temperature with Iq_ref reduction
The fault scenarios presented are just a few of the various scenarios that could be encountered
by a product in the field. Other scenarios could include maximum power limits, frequency
operating range, etc. for each scenario introducing the fault in PSIM or with the Typhoon HIL
allows the designer to understand the characteristics of the fault and then the best method to
respond. The solution can then be implemented and tested.

3 Phase Inverter Design and Verification Application Note

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3 Phase Inverter Design and verification with RCP

3 phase inverter design and verification

Figure 1- Open loop 3 phase VSI ..................................................................................................... 6

1. Simple open loop simulation and HIL verification

Hardware and Software setup

Open loop with PSIM

PSIM file: 3phase VSI open-loop no code.psimsch

Referring to the PSIM schematic “3phase VSI open-loop no code”

There are two main parts to the simulation:

Figure 1- Open loop 3 phase VSI

Figure 2 - Open loop power stage

The power stage

DC bus voltage source

3 current sense elements: Ia, Ib, Ic

A balanced 3phase RL load, 10 ohms and 1 mH

6 on/off switch elements

The control circuit

Figure 3 - Open loop control circuit

Reference phase voltage source

Triangular Voltage source

Logic not gate

Simulation Control sets the simulation

We are simulating a fundamental

Figure 5 - Open loop current waveforms

Open Loop code generation simulation

Figure 8 - Open Loop PSIM schematic with PWM code generation

Figure 9 - PSIM F28335 PWM control block

Figure 10 - PSIM F28335 3 phase PWM attributes

 PWM 1A & 1B – ‘up’ & ‘un’ (pins 5 & 6)

Figure 11 - Simulation Control SimCoder setup for F28335

Generating the code

To generate the code go to “Simulate-

Figure 12 - Generating Code from PSIM

Figure 13 - PSIM generated code folder

Figure 14 - PSIM generated code files

Generated Project import into CCS

Browse the “*.pjt” file in the wizard that will

Figure 18 - Successfully imported project files from PSIM to

To open the target configuration panel go to

Figure 19 - Target Configurations panel

Figure 20 - Target configuration setup screen

Save the target configuration and give it an

Figure 21 - Target Configuration being set to 'Default'

Figure 22 - The CCS Debug launch tool bar button

Typhoon HIL power stage setup

PSIM file: 3 phase inverter open loop code gen.psimsch

Figure 23 - Typhoon HIL schematic of a three-phase inverter power stage

 Voltage source – parameters defined from the HIL SCADA

 DI 1 & 7 PWM 1A/1B

Running the open loop HIL simulation

Figure 27 - HIL DSP interface card with TI F28335 controlCARD mounted

Hit the play button from

Figure 31 - PSIM simulation results

ADC conversion setup and SCI communications

PSIM file: 3 Phase inverter open loop_SCI comms.psimsch

Referring now to “3 Phase inverter open loop_SCI comms.psimsch”

Figure 32 - 3 phase inverter with SCI comms schematic

There are three DC quantity inputs that define

The next major change is the addition of the ADC block.

Figure 34 - Addition of ADC block to control cicuit

The active project is the one that is in

As long as the target configuration from

button from CCS Debug .