PCI-EXPRESS EDGE CONNECTOR

+3.3V_BUS

+3.3V_BUS +1V

2
R1022
18 17 16 15 9 1 +3.3V_BUS +3.3V_BUS +12V_BUS +12V_BUS
+1V_PG

+3.3V_BUS +3.3V_BUS 17 16 15 14 12

3
17 16 15 9 1 +3.3V_BUS 1 +12V_BUS 17 16 15 14 12 11 9 1 +12V_BUS 10K
+3.3V_BUS

1
18 17 16 15 9 1 1+3.3V_BUS
15
9
18
17
16 +3.3V_BUS 18 11 9 1
+3.3V_BUS R1021 Q1004
1K MMBT3904 16 15 9 1 +3.3V_BUS
+3.3V_BUS

3
18 17 16 15 9 1 +3.3V_BUS 18 17

1 2

2
1
1 Q1003 15 9 1 +3.3V_BUS

1
2 3 MPCIE1 MMBT3904 18 17 16
R1002 Q1002

5
R1001
45.3K/X BSH111 B1 +12V PRSNT1_A1 A1 PRESENCE
1 C1021

2
1%
45.3K/X B2 +12V +12V A2 0.1uF

2
1% 6.3V

1
DNI B3 +12V +12V A3

2
B4 GND GND A4 C1011

2
IN
SMBCLK 1 2
R1004
SMCLK B5 SMCLK JTAG2 A5 0.1uF
6.3V U4B

BI
SMBDATA 0R/X 1 2
R1003
SMDAT B6 SMDAT JTAG3 A6 JTDIO_LOOP
C1012 R1005 NC7SZ08P5X_NL

3
0R/X B7 GND JTAG4 A7 0.1uF
6.3V
10K
DNI
B8 +3.3V JTAG5 A8 U4A

1
+3.3V_BUS B9 JTAG1 +3.3V A9 1
2 3
Q1001 B10 3.3Vaux +3.3V A10 4 PERST#_BUF
OUT
18 17 16 15 9 1 +3.3V_BUS BSH111 B11 WAKE_ PERST_ A11 2
Mechanical Key
B12 RSVD_B12 GND A12 NC7SZ08P5X_NL

1
B13 GND REFCLK+ A13 PCIE_REFCLKP
OUT PERST#
OUT
PETP0_GFXRP0 B14 PETp0 REFCLK- A14 PCIE_REFCLKN
OUT
OUT
PETN0_GFXRN0 B15 PETn0 GND A15
DNI
B16 GND PERp0 A16 PERP0
IN
B17 PRSNT2_B17 PERn0 A17 PERN0
IN
1
R1007 2 0R/X

B18 GND GND A18

OUT
PETP1_GFXRP1 B19 PETp1 RSVD_A19 A19 Place R61 in U100

OUT
PETN1_GFXRN1 B20 PETn1 GND A20
B21 GND PERp1 A21 PERP1
IN
B22 GND PERn1 A22 PERN1
IN
OUT
PETP2_GFXRP2 B23 PETp2 GND A23
OUT
PETN2_GFXRN2 B24 PETn2 GND A24
B25 GND PERp2 A25 PERP2
IN
Place these caps as close to the PCIE B26 GND PERn2 A26 PERN2
IN
CAP CER 10UF 20% 16V X5R
OUT
PETP3_GFXRP3 B27 PETp3 GND A27
connector as possible
OUT
PETN3_GFXRN3 B28 PETn3 GND A28
(1206)1.8MM H MAX B29 GND PERp3 A29 PERP3
IN
B30 RSVD_B30 PERn3 A30 PERN3
IN
B31 PRSNT2_B31 GND A31
B32 GND RSVD_A32 A32
16
+12V_BUS OUT
PETP4_GFXRP4 B33 PETp4 RSVD_A33 A33
14
11 OUT
PETN4_GFXRN4 B34 PETn4 GND A34
1 B35 GND PERp4 A35 PERP4
IN
9 B36 A36 PERN4
12 GND PERn4 IN
15 OUT
PETP5_GFXRP5 B37 PETp5 GND A37
17
OUT
PETN5_GFXRN5 B38 PETn5 GND A38
C1001 B39 GND PERp5 A39 PERP5
IN
10UF B40 GND PERn5 A40 PERN5
IN
OUT
PETP6_GFXRP6 B41 PETp6 GND A41
OUT
PETN6_GFXRN6 B42 PETn6 GND A42
+12V_BUS B43 GND PERp6 A43 PERP6
IN
B44 GND PERn6 A44 PERN6
IN
17 16 15 14 12 11 9 1 +12V_BUS
OUT
PETP7_GFXRP7 B45 PETp7 GND A45
OUT
PETN7_GFXRN7 B46 PETn7 GND A46
1

B47 GND PERp7 A47 PERP7

IN
C1002 C1003 B48 PRSNT2_B48 PERn7 A48 PERN7
IN
0.15uF
16V
0.15uF
16V
B49 GND GND A49
OUT
PETP8_GFXRP8 B50 PETp8 RSVD_A50 A50
2

OUT
PETN8_GFXRN8 B51 PETn8 GND A51
B52 GND PERp8 A52 PERP8
IN
+3.3V_BUS B53 GND PERn8 A53 PERN8
IN
OUT
PETP9_GFXRP9 B54 PETp9 GND A54
18 17 16 15 9 1 +3.3V_BUS CAP CER 10UF 10% 6.3V X5R
OUT
PETN9_GFXRN9 B55 PETn9 GND A55
(0805)1.4MM MAX THICK B56 GND PERp9 A56 PERP9
IN
1

B57 GND PERn9 A57 PERN9

IN
C1004 OUT
PETP10_GFXRP10 B58 PETp10 GND A58
10uF
6.3V OUT
PETN10_GFXRN10 B59 PETn10 GND A59
B60 GND PERp10 A60 PERP10
IN SYMBOL LEGEND
2

B61 GND PERn10 A61 PERN10

IN
OUT
PETP11_GFXRP11 B62 PETp11 GND A62
+3.3V_BUS OUT
PETN11_GFXRN11 B63 PETn11 GND A63 DNI DO NOT
B64 GND PERp11 A64 PERP11
IN INSTALL
18 17 16 15 9 1 +3.3V_BUS B65 GND PERn11 A65 PERN11
IN
OUT
PETP12_GFXRP12 B66 PETp12 GND A66 # ACTIVE
1

OUT
PETN12_GFXRN12 B67 PETn12 GND A67 LOW

C1005 C1006 C1007 B68 GND PERp12 A68 PERP12

IN
0.1uF
6.3V
1uF
6.3V
0.01uF
10V
B69 GND PERn12 A69 PERN12
IN DIGITAL

OUT
PETP13_GFXRP13 B70 PETp13 GND A70 GROUND
2

OUT
PETN13_GFXRN13 B71 PETn13 GND A71
B72 GND PERp13 A72 PERP13
IN ANALOG
B73 GND PERn13 A73 PERN13
IN GROUND

OUT
PETP14_GFXRP14 B74 PETp14 GND A74
OUT
PETN14_GFXRN14 B75 PETn14 GND A75 BUO BRING UP

+12V_BUS B76 GND PERp14 A76 PERP14

IN
ONLY

B77 GND PERn14 A77 PERN14

IN
17 16 15 14 12 11 9 1 +12V_BUS
OUT
PETP15_GFXRP15 B78 PETp15 GND A78
OUT
PETN15_GFXRN15 B79 PETn15 GND A79
B80 GND PERp15 A80 PERP15
IN
1

1
PRESENCE B81 PRSNT2_B81 PERn15 A81 PERN15
IN
C1008 C1009 C1010 B82 RSVD_B82 GND A82
0.1uF 0.1uF 0.1uF
16V 16V 16V
2

x16 PCIe

Title
GIGABYTE
Power Supply III: PCI-E Edge Connector
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 1 of 20
Cape_Verde PCIe Interface

NOTE: Some of the PCIE testpoints will

be available through vias on traces.

U1B
220nF for GEN3

PART 2 OF 15

IN
PETP0_GFXRP0 AA38 PCIE_RX0P PCIE_TX0P Y33 PCIE_TX0P
C1101 2 10.22uF PERP0
OUT
IN
PETN0_GFXRN0 Y37 PCIE_RX0N PCIE_TX0N Y32 PCIE_TX0N 2
C1102 1
0.22uF PERN0
OUT

IN
PETP1_GFXRP1 Y35 PCIE_RX1P PCIE_TX1P W33 PCIE_TX1P 2
C1103 1
0.22uF PERP1
OUT
IN
PETN1_GFXRN1 W36 PCIE_RX1N PCIE_TX1N W32 PCIE_TX1N 2
C1104 10.22uF PERN1
OUT

IN
PETP2_GFXRP2 W38 PCIE_RX2P PCIE_TX2P U33 PCIE_TX2P 2
C1105 1
0.22uF PERP2
OUT
IN
PETN2_GFXRN2 V37 PCIE_RX2N PCIE_TX2N U32 PCIE_TX2N 2
C1106 10.22uF PERN2
OUT

IN
PETP3_GFXRP3 V35 PCIE_RX3P PCIE_TX3P U30 PCIE_TX3P 2
C1107 1
0.22uF PERP3
OUT
IN
PETN3_GFXRN3 U36 PCIE_RX3N PCIE_TX3N U29 PCIE_TX3N 2
C1108 1
0.22uF PERN3
OUT

IN
PETP4_GFXRP4 U38 PCIE_RX4P PCIE_TX4P T33 PCIE_TX4P 2
C1109 10.22uF PERP4
OUT
IN
PETN4_GFXRN4 T37 PCIE_RX4N PCIE_TX4N T32 PCIE_TX4N 2
C1110 1
0.22uF PERN4
OUT

IN
PETP5_GFXRP5 T35 PCIE_RX5P PCIE_TX5P T30 PCIE_TX5P C1111 1 20.22uF PERP5
OUT
R36 T29 0.22uF
C11122 1
PETN5_GFXRN5 PCIE_TX5N PERN5
IN PCIE_RX5N PCIE_TX5N OUT
R38 P33 0.22uF
C11132 1
PETP6_GFXRP6 PCIE_TX6P PERP6
IN PCIE_RX6P PCIE_TX6P OUT
P37 P32 0.22uF
C11142 1
PETN6_GFXRN6 PCIE_TX6N PERN6
IN PCIE_RX6N PCIE_TX6N OUT
P35 P30 0.22uF
C11152 1
PETP7_GFXRP7 PCIE_TX7P PERP7
IN PCIE_RX7P PCIE_TX7P OUT
0.22uF
IN
PETN7_GFXRN7 N36 PCIE_RX7N PCIE_TX7N P29 PCIE_TX7N
C11162 1 PERN7
OUT
N38 N33 0.22uF
C11172 1
PETP8_GFXRP8 PCIE_TX8P PERP8
IN PCIE_RX8P PCIE_TX8P OUT
M37 N32 0.22uF
C11182 1
PETN8_GFXRN8 PCIE_TX8N PERN8
IN PCIE_RX8N PCIE_TX8N OUT
0.22uF
IN
PETP9_GFXRP9 M35 PCIE_RX9P PCIE_TX9P N30 PCIE_TX9P
C11192 1 PERP9
OUT
L36 N29 0.22uF
C11202 1
PETN9_GFXRN9 PCIE_TX9N PERN9
IN PCIE_RX9N PCIE_TX9N OUT
L38 L33 0.22uF
C11212 1
PETP10_GFXRP10 PCIE_TX10P PERP10
IN PCIE_RX10P PCIE_TX10P OUT
K37 L32 0.22uF
C11222 1
PETN10_GFXRN10 PCIE_TX10N PERN10
IN PCIE_RX10N PCIE_TX10N OUT
K35 L30 0.22uF
C11232 1
PETP11_GFXRP11 PCIE_TX11P PERP11
IN PCIE_RX11P PCIE_TX11P OUT
J36 L29 0.22uF
C11242 1
PETN11_GFXRN11 PCIE_TX11N PERN11
IN PCIE_RX11N PCIE_TX11N OUT
0.22uF
IN
PETP12_GFXRP12 J38 PCIE_RX12P PCIE_TX12P K33 PCIE_TX12P
C11252 1 PERP12
OUT
0.22uF
IN
PETN12_GFXRN12 H37 PCIE_RX12N PCIE_TX12N K32 PCIE_TX12N
C11262 1 PERN12
OUT
H35 J33 0.22uF
C11272 1
PETP13_GFXRP13 PCIE_TX13P PERP13

PCIEXPRESS
IN PCIE_RX13P PCIE_TX13P OUT
G36 J32 0.22uF
C11282 1
PETN13_GFXRN13 PCIE_TX13N PERN13
IN PCIE_RX13N PCIE_TX13N OUT
0.22uF
IN
PETP14_GFXRP14 G38 PCIE_RX14P PCIE_TX14P K30 PCIE_TX14P
C11292 1 PERP14
OUT
F37 K29 0.22uF
C11302 1
PETN14_GFXRN14 PCIE_TX14N PERN14
IN PCIE_RX14N PCIE_TX14N OUT
F35 H33 0.22uF
C11312 1
PETP15_GFXRP15 PCIE_TX15P PERP15
IN PCIE_RX15P PCIE_TX15P OUT
0.22uF
IN
PETN15_GFXRN15 E37 PCIE_RX15N PCIE_TX15N H32 PCIE_TX15N
C11322 1 PERN15
OUT

+1V

PCIE_REFCLKP AB35 PCIE_REFCLKP PCIE_CALR_TX Y30 PCIE_CALRP 9 7 +1V PCIE_CALR_TX 1.69k pull up for Verde
IN
IN
PCIE_REFCLKN AA36 PCIE_REFCLKN PCIE_CALR_RX Y29 PCIE_CALRN
R1013
1 21.69K
PX_EN
OUT
R1014
R1015 1 2 1K/X AL21 PX_EN GND#177 AB39 1 2 1K
DNI GND#178 E39
GND#179 F34 PCIE_CALR_RX 1k pull up for Verde
IN
PERST#_BUF AA30 PERSTB GND#180 F39
+1.8V GND#181 G33
GND#182 G34
GND#183 H31
B11 GND#184 H34
1 2 +PCIE_PVDD AB37 PCIE_PVDD GND#185 H39
1

1
120R
GND#186 J31
C1143 C1189 C1173 C1175 GND#187 J34
10uF
6.3V
1uF
6.3V
1uF
6.3V
0.1uF
6.3V GND#188 K31
AA31 NC_PCIE_VDDR GND#189 K34
2

+1.8V AA32 NC_PCIE_VDDR GND#190 K39

AA33 NC_PCIE_VDDR GND#191 L31
AA34 NC_PCIE_VDDR GND#192 L34
W30 NC_PCIE_VDDR GND#193 M34
Y31 NC_PCIE_VDDR GND#194 M39
1

GND#195 N31
C1144 C1145 C1146 C1148 V28 NC_BIF_VDDC GND#196 N34
1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
W29 NC_BIF_VDDC GND#197 P31
GND#198 P34
2

GND#199 P39
G30 PCIE_VDDC GND#200 R34
G31 PCIE_VDDC GND#201 T31
+1V H29 PCIE_VDDC GND#202 T34
H30 PCIE_VDDC GND#203 T39
J29 PCIE_VDDC GND#204 U31
J30 PCIE_VDDC GND#205 U34
L28 PCIE_VDDC GND#206 V34
1

1
M28 PCIE_VDDC GND#211 V39
C1160 C1159 C1158 C1150 C1151 C1152 C1153 C1154 C1155 N28 PCIE_VDDC GND#207 W31
10uF
6.3V
10uF
6.3V
10uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
R28 PCIE_VDDC GND#208 W34
T28 PCIE_VDDC GND#209 Y34
2

U28 PCIE_VDDC GND#210 Y39

NA

Title
GIGABYTE
Power Supply III: Cape Verde PCIE Interface
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 2 of 20
 CAPE VERDE MEM Interface Ch A&B

U1C U1D

PART 3 OF 15 PART 4 OF 15
DQA0_[31..0] DQA1_[31..0] DQB0_[31..0] DQB1_[31..0]
BI 4 BI BI 4 BI
0 3 DQA0_0 C37 DQA0_0 4 3C18
DQA1_0
DQA1_0 0 0 3 DQB0_0 C5 DQB0_0 4 3AA4
DQB1_0
DQB1_0 0
4
3 1 DQA0_1 C35 DQA0_1 4 3A18
DQA1_1
DQA1_1 1 3
4 1 DQB0_1 C3 DQB0_1 4 3AB6
DQB1_1
DQB1_1 1
4
3 2 DQA0_2 A35 DQA0_2 4 3F18
DQA1_2
DQA1_2 2 3
4 2 DQB0_2 E3 DQB0_2 4 3AB1
DQB1_2
DQB1_2 2
4
3 3 DQA0_3 E34 DQA0_3 4 3D17
DQA1_3
DQA1_3 3 3
4 3 DQB0_3 E1 DQB0_3 4 3AB3
DQB1_3
DQB1_3 3
4
3 4 DQA0_4 G32 DQA0_4 4 3A16
DQA1_4
DQA1_4 4 3
4 4 DQB0_4 F1 DQB0_4 4 3AD6
DQB1_4
DQB1_4 4
4
3 5 DQA0_5 D33 DQA0_5 4 3F16
DQA1_5
DQA1_5 5 3
4 5 DQB0_5 F3 DQB0_5 4 3AD1
DQB1_5
DQB1_5 5
4
3 6 DQA0_6 F32 DQA0_6 4 3D15
DQA1_6
DQA1_6 6 3
4 6 DQB0_6 F5 DQB0_6 4 3AD3
DQB1_6
DQB1_6 6
4
3 7 DQA0_7 E32 DQA0_7 4 3E14
DQA1_7
DQA1_7 7 3
4 7 DQB0_7 G4 DQB0_7 4 3AD5
DQB1_7
DQB1_7 7
4
3 8 DQA0_8 D31 DQA0_8 4 3F14
DQA1_8
DQA1_8 8 3
4 8 DQB0_8 H5 DQB0_8 4 3AF1
DQB1_8
DQB1_8 8
4
3 9 DQA0_9 F30 DQA0_9 4 3D13
DQA1_9
DQA1_9 9 3
4 9 DQB0_9 H6 DQB0_9 4 3AF3
DQB1_9
DQB1_9 9
4
3 10 DQA0_10 C30 DQA0_10 4 3F12
DQA1_10
DQA1_10 10 3
4 10 DQB0_10 J4 DQB0_10 4 3AF6
DQB1_10
DQB1_10 10
4
3 11 DQA0_11 A30 DQA0_11 4 3A12
DQA1_11
DQA1_11 11 3
4 11 DQB0_11 K6 DQB0_11 4 3AG4
DQB1_11
DQB1_11 11
4
3 12 DQA0_12 F28 DQA0_12 4 3D11
DQA1_12
DQA1_12 12 3
4 12 DQB0_12 K5 DQB0_12 4 3AH5
DQB1_12
DQB1_12 12
4
3 13 DQA0_13 C28 DQA0_13 4 3F10
DQA1_13
DQA1_13 13 3
4 13 DQB0_13 L4 DQB0_13 4 3AH6
DQB1_13
DQB1_13 13
4
3 14 DQA0_14 A28 DQA0_14 4 3A10
DQA1_14
DQA1_14 14 3
4 14 DQB0_14 M6 DQB0_14 4 3AJ4
DQB1_14
DQB1_14 14
4
3 15 DQA0_15 E28 DQA0_15 4 3C10
DQA1_15
DQA1_15 15 3
4 15 DQB0_15 M1 DQB0_15 4 3AK3
DQB1_15
DQB1_15 15
4
3 16 DQA0_16 D27 DQA0_16 4 3G13
DQA1_16
DQA1_16 16 3
4 16 DQB0_16 M3 DQB0_16 4 3AF8
DQB1_16
DQB1_16 16
4
3 17 DQA0_17 F26 DQA0_17 4 3H13
DQA1_17
DQA1_17 17 3
4 17 DQB0_17 M5 DQB0_17 4 3AF9
DQB1_17
DQB1_17 17
4
3 18 DQA0_18 C26 DQA0_18 4 3J13
DQA1_18
DQA1_18 18 3
4 18 DQB0_18 N4 DQB0_18 4 3AG8
DQB1_18
DQB1_18 18
4
3 19 DQA0_19 A26 DQA0_19 4 3H11
DQA1_19
DQA1_19 19 3
4 19 DQB0_19 P6 DQB0_19 4 3AG7
DQB1_19
DQB1_19 19
4
3 20 DQA0_20 F24 DQA0_20 4 3G10
DQA1_20
DQA1_20 20 3
4 20 DQB0_20 P5 DQB0_20 4 3AK9
DQB1_20
DQB1_20 20
4
3 21 DQA0_21 C24 DQA0_21 4 3G8
DQA1_21
DQA1_21 21 3
4 21 DQB0_21 R4 DQB0_21 4 3AL7
DQB1_21
DQB1_21 21
4
3 22 DQA0_22 A24 DQA0_22 4 3K9
DQA1_22
DQA1_22 22 3
4 22 DQB0_22 T6 DQB0_22 4 3AM8
DQB1_22
DQB1_22 22
4
3 23 DQA0_23 E24 DQA0_23 4 3K10
DQA1_23
DQA1_23 23 3
4 23 DQB0_23 T1 DQB0_23 4 3AM7
DQB1_23
DQB1_23 23
4
3 24 DQA0_24 C22 DQA0_24 4 3G9
DQA1_24
DQA1_24 24 3
4 24 DQB0_24 U4 DQB0_24 4 3AK1
DQB1_24
DQB1_24 24
4
3 25 DQA0_25 A22 DQA0_25 4 3A8
DQA1_25
DQA1_25 25 3
4 25 DQB0_25 V6 DQB0_25 4 3AL4
DQB1_25
DQB1_25 25
4
3 26 DQA0_26 F22 DQA0_26 4 3C8
DQA1_26
DQA1_26 26 3
4 26 DQB0_26 V1 DQB0_26 4 3AM6
DQB1_26
DQB1_26 26
4
3 27 DQA0_27 D21 DQA0_27 4 3E8
DQA1_27
DQA1_27 27 3
4 27 DQB0_27 V3 DQB0_27 4 3AM1
DQB1_27
DQB1_27 27
4
3 28 DQA0_28 A20 DQA0_28 4 3A6
DQA1_28
DQA1_28 28 3
4 28 DQB0_28 Y6 DQB0_28 4 3AN4
DQB1_28
DQB1_28 28
4
3 29 DQA0_29 F20 DQA0_29 4 3C6
DQA1_29
DQA1_29 29 3
4 29 DQB0_29 Y1 DQB0_29 4 3AP3
DQB1_29
DQB1_29 29
4
3 30 DQA0_30 D19 DQA0_30 4 3E6
DQA1_30
DQA1_30 30 3
4 30 DQB0_30 Y3 DQB0_30 4 3AP1
DQB1_30
DQB1_30 30
4
3 31 DQA0_31 E18 DQA0_31 4 3A5
DQA1_31
DQA1_31 31 3
4 31 DQB0_31 Y5 DQB0_31 4 3AP5
DQB1_31
DQB1_31 31

MAA0_[8..0] MAA1_[8..0] MAB0_[8..0] MAB1_[8..0]

OUT 4 OUT OUT 4 OUT
0 3 MAA0_0 G24 MAA0_0 4 3H19
MAA1_0
MAA1_0 0 0 3 MAB0_0 P8 MAB0_0 4 3Y9
MAB1_0
MAB1_0 0

MEMORY INTERFACE BANK A

4
3 1 MAA0_1 J23 4 3H20 MAA1_1 1 3
4 1 MAB0_1 T9 4 3W9 MAB1_1 1

MEMORY INTERFACE BANK B

MAA0_1 MAA1_1 MAB0_1 MAB1_1
4
3 2 MAA0_2 H24 MAA0_2 4 3L13
MAA1_2
MAA1_2 2 3
4 2 MAB0_2 P9 MAB0_2 4 3AC8
MAB1_2
MAB1_2 2
4
3 3 MAA0_3 J24 MAA0_3 4 3G16
MAA1_3
MAA1_3 3 3
4 3 MAB0_3 N7 MAB0_3 4 3AC9
MAB1_3
MAB1_3 3
4
3 4 MAA0_4 H26 MAA0_4 4 3J16
MAA1_4
MAA1_4 4 3
4 4 MAB0_4 N8 MAB0_4 4 3AA7
MAB1_4
MAB1_4 4
4
3 5 MAA0_5 J26 MAA0_5 4 3H16
MAA1_5
MAA1_5 5 3
4 5 MAB0_5 N9 MAB0_5 4 3AA8
MAB1_5
MAB1_5 5
4
3 6 MAA0_6 H21 MAA0_6 4 3J17
MAA1_6
MAA1_6 6 3
4 6 MAB0_6 U9 MAB0_6 4 3Y8
MAB1_6
MAB1_6 6
4
3 7 MAA0_7 G21 MAA0_7 4 3H17
MAA1_7
MAA1_7 7 3
4 7 MAB0_7 U8 MAB0_7 4 3AA9
MAB1_7
MAB1_7 7
4
3 8 MAA0_8 H23 MAA0_8 4 3J19
MAA1_8
MAA1_8 8 3
4 8 MAB0_8 T8 MAB0_8 4 3W8
MAB1_8
MAB1_8 8
M21 MAA0_9 MAA1_9 M20 U12 MAB0_9 MAB1_9 V12

BI
WCKA0_0 A32 WCKA0_0 WCKA1_0 C14 WCKA1_0
BI BI
WCKB0_0 H3 WCKB0_0 WCKB1_0 AE4 WCKB1_0
BI
BI
WCKA0B_0 C32 WCKA0B_0 WCKA1B_0 A14 WCKA1B_0
BI BI
WCKB0B_0 H1 WCKB0B_0 WCKB1B_0 AF5 WCKB1B_0
BI

BI
WCKA0_1 D23 WCKA0_1 WCKA1_1 E10 WCKA1_1
BI BI
WCKB0_1 T3 WCKB0_1 WCKB1_1 AK6 WCKB1_1
BI
BI
WCKA0B_1 E22 WCKA0B_1 WCKA1B_1 D9 WCKA1B_1
BI BI
WCKB0B_1 T5 WCKB0B_1 WCKB1B_1 AK5 WCKB1B_1
BI

BI
EDCA0_0 C34 EDCA0_0 EDCA1_0 E16 EDCA1_0
BI BI
EDCB0_0 F6 EDCB0_0 EDCB1_0 AB5 EDCB1_0
BI
BI
EDCA0_1 D29 EDCA0_1 EDCA1_1 E12 EDCA1_1
BI BI
EDCB0_1 K3 EDCB0_1 EDCB1_1 AH1 EDCB1_1
BI
BI
EDCA0_2 D25 EDCA0_2 EDCA1_2 J10 EDCA1_2
BI BI
EDCB0_2 P3 EDCB0_2 EDCB1_2 AJ9 EDCB1_2
BI
BI
EDCA0_3 E20 EDCA0_3 EDCA1_3 D7 EDCA1_3
BI BI
EDCB0_3 V5 EDCB0_3 EDCB1_3 AM5 EDCB1_3
BI

BI
DDBIA0_0 A34 DDBIA0_0 DDBIA1_0 C16 DDBIA1_0
BI BI
DDBIB0_0 G7 DDBIB0_0 DDBIB1_0 AC4 DDBIB1_0
BI
BI
DDBIA0_1 E30 DDBIA0_1 DDBIA1_1 C12 DDBIA1_1
BI BI
DDBIB0_1 K1 DDBIB0_1 DDBIB1_1 AH3 DDBIB1_1
BI
BI
DDBIA0_2 E26 DDBIA0_2 DDBIA1_2 J11 DDBIA1_2
BI BI
DDBIB0_2 P1 DDBIB0_2 DDBIB1_2 AJ8 DDBIB1_2
BI
BI
DDBIA0_3 C20 DDBIA0_3 DDBIA1_3 F8 DDBIA1_3
BI BI
DDBIB0_3 W4 DDBIB0_3 DDBIB1_3 AM3 DDBIB1_3
BI

BI
ADBIA0 J21 ADBIA0 ADBIA1 G19 ADBIA1
BI BI
ADBIB0 T7 ADBIB0 ADBIB1 W7 ADBIB1
BI

OUT
CSA0B_0 K24 CSA0B_0 CSA1B_0 M13 CSA1B_0
OUT OUT
CSB0B_0 P10 CSB0B_0 CSB1B_0 AD10 CSB1B_0
OUT
K27 CSA0B_1 CSA1B_1 K16 L10 CSB0B_1 CSB1B_1 AC10

OUT
CASA0B K20 CASA0B CASA1B K17 CASA1B
OUT OUT
CASB0B W10 CASB0B CASB1B AA10 CASB1B
OUT
OUT
RASA0B K23 RASA0B RASA1B K19 RASA1B
OUT OUT
RASB0B T10 RASB0B RASB1B Y10 RASB1B
OUT
OUT
WEA0B K26 WEA0B WEA1B L15 WEA1B
OUT OUT
WEB0B N10 WEB0B WEB1B AB11 WEB1B
OUT

OUT
CKEA0 K21 CKEA0 CKEA1 J20 CKEA1
OUT OUT
CKEB0 U10 CKEB0 CKEB1 AA11 CKEB1
OUT

OUT
CLKA0 H27 CLKA0 CLKA1 J14 CLKA1
OUT OUT
CLKB0 L9 CLKB0 CLKB1 AD8 CLKB1
OUT
OUT
CLKA0B G27 CLKA0B CLKA1B H14 CLKA1B
OUT OUT
CLKB0B L8 CLKB0B CLKB1B AD7 CLKB1B
OUT

+MVDD +MVDD

1
R3602 R3603
40.2R/X 40.2R/X
1%
MVREFDA L18 MVREFD_A 1% MVREFDB Y12 MVREFD_B

1 2

1 2
1

1
C3602 C3603
1uF/X 1uF/X
6.3V R3606 6.3V R3607
MVREFD/S =0.7* 120R 1% MEM_CALRP1
100R/X 1
R3601 2 M27 MEM_CALRP0
100R/X
2

2
1% MVREFD/S =0.7* 1%
VDDR1 L27 NC_MEM_CALRN0
2

2
For Verde, only stuff R3601 with 120ohm VDDR1
(GDDR3/4/5)
M12 NC_MEM_CALRP1 (GDDR3/4/5)
N12 NC_MEM_CALRN1

AH12 NC_MEM_CALRP2
AG12 NC_MEM_CALRN2

OUT
DRAM_RST 1 2
R3630
DRAM_RST_RR 1 2
R3615
DRAM_RST_R AH11 DRAM_RST MVREFSA L20 MVREFSB AA12
1

49.9R 10R
2

C3607
120pF
50V R3612 NA NA
5.1K
2

Title
GIGABYTE
Power Supply III: Cape Verde MEMORY INTERFAC
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 3 of 20
GDDR5 Memory Channel A&B

GDDR5

23CNOPN001 +MVDD
DQB1_[31..0] U2300
BI 4
GDDR5
GDDR5 29 3 DQB1_29 M2 DQ31__DQ7 VDDQ_B1 B1
DQA0_[31..0] 23CNOPN001 +MVDD 23CNOPN001 +MVDD DQB0_[31..0] 23CNOPN001 +MVDD 3
4 31 DQB1_31 M4 DQ30__DQ6 VDDQ_B3 B3
BI U2000 U2100
BI U2200
4
DQA1_[31..0]
4 4
3
4 30 DQB1_30 N2 DQ29__DQ5 VDDQ_B12 B12
BI
30 3 DQA0_30 M2 DQ31__DQ7 VDDQ_B1 B1 30 3 DQA1_30 M2 DQ31__DQ7 VDDQ_B1 B1 30 3 DQB0_30 M2 DQ31__DQ7 VDDQ_B1 B1 3
4 24 DQB1_24 N4 DQ28__DQ4 VDDQ_B14 B14
3
4 31 DQA0_31 M4 DQ30__DQ6 VDDQ_B3 B3 4
3 31 DQA1_31 M4 DQ30__DQ6 VDDQ_B3 B3 3
4 31 DQB0_31 M4 DQ30__DQ6 VDDQ_B3 B3 3
4 28 DQB1_28 T2 DQ27__DQ3 VDDQ_D1 D1
3
4 29 DQA0_29 N2 DQ29__DQ5 VDDQ_B12 B12 4
3 29 DQA1_29 N2 DQ29__DQ5 VDDQ_B12 B12 3
4 29 DQB0_29 N2 DQ29__DQ5 VDDQ_B12 B12 3
4 25 DQB1_25 T4 DQ26__DQ2 VDDQ_D3 D3
3
4 28 DQA0_28 N4 DQ28__DQ4 VDDQ_B14 B14 4
3 28 DQA1_28 N4 DQ28__DQ4 VDDQ_B14 B14 3
4 28 DQB0_28 N4 DQ28__DQ4 VDDQ_B14 B14 3
4 27 DQB1_27 V2 DQ25__DQ1 VDDQ_D12 D12
3
4 26 DQA0_26 T2 DQ27__DQ3 VDDQ_D1 D1 4
3 26 DQA1_26 T2 DQ27__DQ3 VDDQ_D1 D1 3
4 26 DQB0_26 T2 DQ27__DQ3 VDDQ_D1 D1 3
4 26 DQB1_26 V4 DQ24__DQ0 VDDQ_D14 D14
3
4 25 DQA0_25 T4 DQ26__DQ2 VDDQ_D3 D3 4
3 24 DQA1_24 T4 DQ26__DQ2 VDDQ_D3 D3 3
4 24 DQB0_24 T4 DQ26__DQ2 VDDQ_D3 D3 3
4 17 DQB1_17 M13 DQ23__DQ15 VDDQ_E5 E5
3
4 27 DQA0_27 V2 DQ25__DQ1 VDDQ_D12 D12 4
3 27 DQA1_27 V2 DQ25__DQ1 VDDQ_D12 D12 3
4 27 DQB0_27 V2 DQ25__DQ1 VDDQ_D12 D12 3
4 16 DQB1_16 M11 DQ22__DQ14 VDDQ_E10 E10
3
4 24 DQA0_24 V4 DQ24__DQ0 VDDQ_D14 D14 4
3 25 DQA1_25 V4 DQ24__DQ0 VDDQ_D14 D14 3
4 25 DQB0_25 V4 DQ24__DQ0 VDDQ_D14 D14 3
4 19 DQB1_19 N13 DQ21__DQ13 VDDQ_F1 F1
3
4 17 DQA0_17 M13 DQ23__DQ15 VDDQ_E5 E5 4
3 19 DQA1_19 M13 DQ23__DQ15 VDDQ_E5 E5 3
4 17 DQB0_17 M13 DQ23__DQ15 VDDQ_E5 E5 3
4 18 DQB1_18 N11 DQ20__DQ12 VDDQ_F3 F3
3
4 16 DQA0_16 M11 DQ22__DQ14 VDDQ_E10 E10 4
3 16 DQA1_16 M11 DQ22__DQ14 VDDQ_E10 E10 3
4 16 DQB0_16 M11 DQ22__DQ14 VDDQ_E10 E10 3
4 22 DQB1_22 T13 DQ19__DQ11 VDDQ_F12 F12
3
4 18 DQA0_18 N13 DQ21__DQ13 VDDQ_F1 F1 4
3 18 DQA1_18 N13 DQ21__DQ13 VDDQ_F1 F1 3
4 18 DQB0_18 N13 DQ21__DQ13 VDDQ_F1 F1 3
4 21 DQB1_21 T11 DQ18__DQ10 VDDQ_F14 F14
3
4 19 DQA0_19 N11 DQ20__DQ12 VDDQ_F3 F3 4
3 17 DQA1_17 N11 DQ20__DQ12 VDDQ_F3 F3 3
4 19 DQB0_19 N11 DQ20__DQ12 VDDQ_F3 F3 3
4 20 DQB1_20 V13 DQ17__DQ9 VDDQ_G2 G2
3
4 21 DQA0_21 T13 DQ19__DQ11 VDDQ_F12 F12 4
3 20 DQA1_20 T13 DQ19__DQ11 VDDQ_F12 F12 3
4 21 DQB0_21 T13 DQ19__DQ11 VDDQ_F12 F12 3
4 23 DQB1_23 V11 DQ16__DQ8 VDDQ_G13 G13
3
4 22 DQA0_22 T11 DQ18__DQ10 VDDQ_F14 F14 4
3 22 DQA1_22 T11 DQ18__DQ10 VDDQ_F14 F14 3
4 22 DQB0_22 T11 DQ18__DQ10 VDDQ_F14 F14 3
4 14 DQB1_14 F13 DQ15__DQ23 VDDQ_H3 H3
3
4 20 DQA0_20 V13 DQ17__DQ9 VDDQ_G2 G2 4
3 23 DQA1_23 V13 DQ17__DQ9 VDDQ_G2 G2 3
4 20 DQB0_20 V13 DQ17__DQ9 VDDQ_G2 G2 3
4 15 DQB1_15 F11 DQ14__DQ22 VDDQ_H12 H12
3
4 23 DQA0_23 V11 DQ16__DQ8 VDDQ_G13 G13 4
3 21 DQA1_21 V11 DQ16__DQ8 VDDQ_G13 G13 3
4 23 DQB0_23 V11 DQ16__DQ8 VDDQ_G13 G13 3
4 13 DQB1_13 E13 DQ13__DQ21 VDDQ_K3 K3
3
4 14 DQA0_14 F13 DQ15__DQ23 VDDQ_H3 H3 4
3 14 DQA1_14 F13 DQ15__DQ23 VDDQ_H3 H3 3
4 13 DQB0_13 F13 DQ15__DQ23 VDDQ_H3 H3 3
4 12 DQB1_12 E11 DQ12__DQ20 VDDQ_K12 K12
3
4 12 DQA0_12 F11 DQ14__DQ22 VDDQ_H12 H12 4
3 15 DQA1_15 F11 DQ14__DQ22 VDDQ_H12 H12 3
4 15 DQB0_15 F11 DQ14__DQ22 VDDQ_H12 H12 3
4 10 DQB1_10 B13 DQ11__DQ19 VDDQ_L2 L2
3
4 15 DQA0_15 E13 DQ13__DQ21 VDDQ_K3 K3 4
3 13 DQA1_13 E13 DQ13__DQ21 VDDQ_K3 K3 3
4 12 DQB0_12 E13 DQ13__DQ21 VDDQ_K3 K3 3
4 9 DQB1_9 B11 DQ10__DQ18 VDDQ_L13 L13
3
4 13 DQA0_13 E11 DQ12__DQ20 VDDQ_K12 K12 4
3 12 DQA1_12 E11 DQ12__DQ20 VDDQ_K12 K12 3
4 14 DQB0_14 E11 DQ12__DQ20 VDDQ_K12 K12 3
4 11 DQB1_11 A13 DQ9__DQ17 VDDQ_M1 M1
3
4 10 DQA0_10 B13 DQ11__DQ19 VDDQ_L2 L2 4
3 10 DQA1_10 B13 DQ11__DQ19 VDDQ_L2 L2 3
4 11 DQB0_11 B13 DQ11__DQ19 VDDQ_L2 L2 3
4 8 DQB1_8 A11 DQ8__DQ16 VDDQ_M3 M3
3
4 9 DQA0_9 B11 DQ10__DQ18 VDDQ_L13 L13 4
3 9 DQA1_9 B11 DQ10__DQ18 VDDQ_L13 L13 3
4 9 DQB0_9 B11 DQ10__DQ18 VDDQ_L13 L13 3
4 1 DQB1_1 F2 DQ7__DQ31 VDDQ_M12 M12
3
4 11 DQA0_11 A13 DQ9__DQ17 VDDQ_M1 M1 4
3 11 DQA1_11 A13 DQ9__DQ17 VDDQ_M1 M1 3
4 10 DQB0_10 A13 DQ9__DQ17 VDDQ_M1 M1 3
4 0 DQB1_0 F4 DQ6__DQ30 VDDQ_M14 M14
3
4 8 DQA0_8 A11 DQ8__DQ16 VDDQ_M3 M3 4
3 8 DQA1_8 A11 DQ8__DQ16 VDDQ_M3 M3 3
4 8 DQB0_8 A11 DQ8__DQ16 VDDQ_M3 M3 3
4 2 DQB1_2 E2 DQ5__DQ29 VDDQ_N5 N5
3
4 1 DQA0_1 F2 DQ7__DQ31 VDDQ_M12 M12 4
3 1 DQA1_1 F2 DQ7__DQ31 VDDQ_M12 M12 3
4 1 DQB0_1 F2 DQ7__DQ31 VDDQ_M12 M12 3
4 3 DQB1_3 E4 DQ4__DQ28 VDDQ_N10 N10
3
4 0 DQA0_0 F4 DQ6__DQ30 VDDQ_M14 M14 4
3 0 DQA1_0 F4 DQ6__DQ30 VDDQ_M14 M14 3
4 0 DQB0_0 F4 DQ6__DQ30 VDDQ_M14 M14 3
4 5 DQB1_5 B2 DQ3__DQ27 VDDQ_P1 P1
3
4 2 DQA0_2 E2 DQ5__DQ29 VDDQ_N5 N5 4
3 2 DQA1_2 E2 DQ5__DQ29 VDDQ_N5 N5 3
4 2 DQB0_2 E2 DQ5__DQ29 VDDQ_N5 N5 3
4 6 DQB1_6 B4 DQ2__DQ26 VDDQ_P3 P3
3
4 4 DQA0_4 E4 DQ4__DQ28 VDDQ_N10 N10 4
3 3 DQA1_3 E4 DQ4__DQ28 VDDQ_N10 N10 3
4 3 DQB0_3 E4 DQ4__DQ28 VDDQ_N10 N10 3
4 4 DQB1_4 A2 DQ1__DQ25 VDDQ_P12 P12
3
4 5 DQA0_5 B2 DQ3__DQ27 VDDQ_P1 P1 4
3 5 DQA1_5 B2 DQ3__DQ27 VDDQ_P1 P1 3
4 5 DQB0_5 B2 DQ3__DQ27 VDDQ_P1 P1 3
4 7 DQB1_7 A4 DQ0__DQ24 VDDQ_P14 P14
3
4 7 DQA0_7 B4 DQ2__DQ26 VDDQ_P3 P3 4
3 7 DQA1_7 B4 DQ2__DQ26 VDDQ_P3 P3 3
4 7 DQB0_7 B4 DQ2__DQ26 VDDQ_P3 P3 VDDQ_T1 T1
3
4 3 DQA0_3 A2 DQ1__DQ25 VDDQ_P12 P12 4
3 4 DQA1_4 A2 DQ1__DQ25 VDDQ_P12 P12 3
4 4 DQB0_4 A2 DQ1__DQ25 VDDQ_P12 P12 VDDQ_T3 T3
3
4 6 DQA0_6 A4 DQ0__DQ24 VDDQ_P14 P14 4
3 6 DQA1_6 A4 DQ0__DQ24 VDDQ_P14 P14 3
4 6 DQB0_6 A4 DQ0__DQ24 VDDQ_P14 P14 VDDQ_T12 T12
VDDQ_T1 T1 VDDQ_T1 T1 VDDQ_T1 T1 VDDQ_T14 T14
VDDQ_T3 T3 VDDQ_T3 T3 VDDQ_T3 T3 MAB1_[8..0]
OUT
VDDQ_T12 T12 MAA1_[8..0] VDDQ_T12 T12 VDDQ_T12 T12 8 4 3 MAB1_8 J5 RFU_A12_NC +MVDD
OUT
VDDQ_T14 T14 VDDQ_T14 T14 VDDQ_T14 T14 0 4 3 MAB1_0 K4 A7_A8__A0_A10 VDD_C5 C5
MAA0_[8..0] +MVDD MAB0_[8..0] 1 4 3 MAB1_1 K5 A6_A11__A1_A9 VDD_C10 C10
OUT OUT
8 4 3 MAA0_8 J5 RFU_A12_NC 8 4 3 MAA1_8 J5 RFU_A12_NC +MVDD 8 4 3 MAB0_8 J5 RFU_A12_NC +MVDD 3 4 3 MAB1_3 K10 A5_BA1__A3_BA3 VDD_D11 D11
7 4 3 MAA0_7 K4 A7_A8__A0_A10 VDD_C5 C5 0 4 3 MAA1_0 K4 A7_A8__A0_A10 VDD_C5 C5 7 4 3 MAB0_7 K4 A7_A8__A0_A10 VDD_C5 C5 2 4 3 MAB1_2 K11 A4_BA2__A2_BA0 VDD_G1 G1
6 4 3 MAA0_6 K5 A6_A11__A1_A9 VDD_C10 C10 1 4 3 MAA1_1 K5 A6_A11__A1_A9 VDD_C10 C10 6 4 3 MAB0_6 K5 A6_A11__A1_A9 VDD_C10 C10 5 4 3 MAB1_5 H10 A3_BA3__A5_BA1 VDD_G4 G4
5 4 3 MAA0_5 K10 A5_BA1__A3_BA3 VDD_D11 D11 3 4 3 MAA1_3 K10 A5_BA1__A3_BA3 VDD_D11 D11 5 4 3 MAB0_5 K10 A5_BA1__A3_BA3 VDD_D11 D11 4 4 3 MAB1_4 H11 A2_BA0__A4_BA2 VDD_G11 G11
4 4 3 MAA0_4 K11 A4_BA2__A2_BA0 VDD_G1 G1 2 4 3 MAA1_2 K11 A4_BA2__A2_BA0 VDD_G1 G1 4 4 3 MAB0_4 K11 A4_BA2__A2_BA0 VDD_G1 G1 6 4 3 MAB1_6 H5 A1_A9__A6_A11 VDD_G14 G14
3 4 3 MAA0_3 H10 A3_BA3__A5_BA1 VDD_G4 G4 5 4 3 MAA1_5 H10 A3_BA3__A5_BA1 VDD_G4 G4 3 4 3 MAB0_3 H10 A3_BA3__A5_BA1 VDD_G4 G4 7 4 3 MAB1_7 H4 A0_A10__A7_A8 VDD_L1 L1
2 4 3 MAA0_2 H11 A2_BA0__A4_BA2 VDD_G11 G11 4 4 3 MAA1_4 H11 A2_BA0__A4_BA2 VDD_G11 G11 2 4 3 MAB0_2 H11 A2_BA0__A4_BA2 VDD_G11 G11 VDD_L4 L4
1 4 3 MAA0_1 H5 A1_A9__A6_A11 VDD_G14 G14 6 4 3 MAA1_6 H5 A1_A9__A6_A11 VDD_G14 G14 1 4 3 MAB0_1 H5 A1_A9__A6_A11 VDD_G14 G14 VDD_L11 L11
0 4 3 MAA0_0 H4 A0_A10__A7_A8 VDD_L1 L1 7 4 3 MAA1_7 H4 A0_A10__A7_A8 VDD_L1 L1 0 4 3 MAB0_0 H4 A0_A10__A7_A8 VDD_L1 L1 VDD_L14 L14
VDD_L4 L4 VDD_L4 L4 VDD_L4 L4 WCKB1_0 D4 WCK01__WCK23 VDD_P11 P11
IN
VDD_L11 L11 VDD_L11 L11 VDD_L11 L11 WCKB1B_0 D5 WCK01#__WCK23# VDD_R5 R5
IN
VDD_L14 L14 VDD_L14 L14 VDD_L14 L14 VDD_R10 R10
WCKA0_0 D4 WCK01__WCK23 VDD_P11 P11 WCKA1_0 D4 WCK01__WCK23 VDD_P11 P11 WCKB0_0 D4 WCK01__WCK23 VDD_P11 P11 WCKB1_1 P4 WCK23__WCK01
IN IN IN IN
WCKA0B_0 D5 WCK01#__WCK23# VDD_R5 R5 WCKA1B_0 D5 WCK01#__WCK23# VDD_R5 R5 WCKB0B_0 D5 WCK01#__WCK23# VDD_R5 R5 WCKB1B_1 P5 WCK23#__WCK01#
IN IN IN IN
VDD_R10 R10 VDD_R10 R10 VDD_R10 R10 VSSQ_A1 A1
WCKA0_1 P4 WCK23__WCK01
WCKA1_1 P4 WCK23__WCK01
WCKB0_1 P4 WCK23__WCK01
EDCB1_3 R2 EDC3__EDC0 VSSQ_A3 A3
IN IN IN OUT
WCKA0B_1 P5 WCK23#__WCK01#
WCKA1B_1 P5 WCK23#__WCK01#
WCKB0B_1 P5 WCK23#__WCK01#
EDCB1_2 R13 EDC2__EDC1 VSSQ_A12 A12
IN IN IN OUT
VSSQ_A1 A1 VSSQ_A1 A1 VSSQ_A1 A1 EDCB1_1 C13 EDC1__EDC2 VSSQ_A14 A14
OUT
EDCA0_3 R2 EDC3__EDC0 VSSQ_A3 A3 EDCA1_3 R2 EDC3__EDC0 VSSQ_A3 A3 EDCB0_3 R2 EDC3__EDC0 VSSQ_A3 A3 EDCB1_0 C2 EDC0__EDC3 VSSQ_C1 C1
OUT OUT OUT OUT
EDCA0_2 R13 EDC2__EDC1 VSSQ_A12 A12 EDCA1_2 R13 EDC2__EDC1 VSSQ_A12 A12 EDCB0_2 R13 EDC2__EDC1 VSSQ_A12 A12 VSSQ_C3 C3
OUT OUT OUT
EDCA0_1 C13 EDC1__EDC2 VSSQ_A14 A14 EDCA1_1 C13 EDC1__EDC2 VSSQ_A14 A14 EDCB0_1 C13 EDC1__EDC2 VSSQ_A14 A14 DDBIB1_3 P2 DBI3#__DBI0# VSSQ_C4 C4
OUT OUT OUT BI
EDCA0_0 C2 EDC0__EDC3 VSSQ_C1 C1 EDCA1_0 C2 EDC0__EDC3 VSSQ_C1 C1 EDCB0_0 C2 EDC0__EDC3 VSSQ_C1 C1 DDBIB1_2 P13 DBI2#__DBI1# VSSQ_C11 C11
OUT OUT OUT BI
VSSQ_C3 C3 VSSQ_C3 C3 VSSQ_C3 C3 DDBIB1_1 D13 DBI1#__DBI2# VSSQ_C12 C12
BI
DDBIA0_3 P2 DBI3#__DBI0# VSSQ_C4 C4 DDBIA1_3 P2 DBI3#__DBI0# VSSQ_C4 C4 DDBIB0_3 P2 DBI3#__DBI0# VSSQ_C4 C4 DDBIB1_0 D2 DBI0#__DBI3# VSSQ_C14 C14
BI BI BI BI
DDBIA0_2 P13 DBI2#__DBI1# VSSQ_C11 C11 DDBIA1_2 P13 DBI2#__DBI1# VSSQ_C11 C11 DDBIB0_2 P13 DBI2#__DBI1# VSSQ_C11 C11 VSSQ_E1 E1
BI BI BI
DDBIA0_1 D13 DBI1#__DBI2# VSSQ_C12 C12 DDBIA1_1 D13 DBI1#__DBI2# VSSQ_C12 C12 DDBIB0_1 D13 DBI1#__DBI2# VSSQ_C12 C12 VSSQ_E3 E3
BI BI BI
DDBIA0_0 D2 DBI0#__DBI3# VSSQ_C14 C14 DDBIA1_0 D2 DBI0#__DBI3# VSSQ_C14 C14 DDBIB0_0 D2 DBI0#__DBI3# VSSQ_C14 C14 VSSQ_E12 E12
BI BI BI
VSSQ_E1 E1 VSSQ_E1 E1 VSSQ_E1 E1 +MVDD
CASB1B G3 RAS#__CAS# VSSQ_E14 E14
IN
VSSQ_E3 E3 VSSQ_E3 E3 VSSQ_E3 E3 RASB1B L3 CAS#__RAS# VSSQ_F5 F5
IN
VSSQ_E12 E12 +MVDD VSSQ_E12 E12 VSSQ_E12 E12 R2301 1 2 CLKB1B
VSSQ_F10 F10
RASA0B G3 E14 CASA1B G3 E14 RASB0B G3 E14 1 60.4R
2 CLKB1 H2
+MVDD IN RAS#__CAS# VSSQ_E14 IN RAS#__CAS# VSSQ_E14 +MVDD IN RAS#__CAS# VSSQ_E14 R2300 VSSQ_H2
CASA0B L3 F5 RASA1B L3 F5 CASB0B L3 F5 60.4R CKEB1 J3 H13
CAS#__RAS# VSSQ_F5 CAS#__RAS# VSSQ_F5 CAS#__RAS# VSSQ_F5 CKE# VSSQ_H13
IN IN IN IN
R2001 1 2 CLKA0B
VSSQ_F10 F10 R2101 1 2 CLKA1B
VSSQ_F10 F10 R2201 1 2 CLKB0B
VSSQ_F10 F10 J11 CK# VSSQ_K2 K2
IN
R2000 1 2
60.4R CLKA0
VSSQ_H2 H2 R2100 1 2
60.4R CLKA1
VSSQ_H2 H2 R2200 1 2
60.4R CLKB0
VSSQ_H2 H2 J12 CK VSSQ_K13 K13
60.4R 60.4R 60.4R IN
CKEA0 J3 CKE# VSSQ_H13 H13 CKEA1 J3 CKE# VSSQ_H13 H13 CKEB0 J3 CKE# VSSQ_H13 H13 VSSQ_M5 M5
IN IN IN
J11 CK# VSSQ_K2 K2 J11 CK# VSSQ_K2 K2 J11 CK# VSSQ_K2 K2 VSSQ_M10 M10
IN IN IN
J12 CK VSSQ_K13 K13 J12 CK VSSQ_K13 K13 J12 CK VSSQ_K13 K13 WEB1B G12 CS#__WE# VSSQ_N1 N1
IN IN IN IN
VSSQ_M5 M5 VSSQ_M5 M5 VSSQ_M5 M5 CSB1B_0 L12 WE#__CS# VSSQ_N3 N3
IN
VSSQ_M10 M10 VSSQ_M10 M10 VSSQ_M10 M10 VSSQ_N12 N12
CSA0B_0 G12 CS#__WE# VSSQ_N1 N1 WEA1B G12 CS#__WE# VSSQ_N1 N1 CSB0B_0 G12 CS#__WE# VSSQ_N1 N1 VSSQ_N14 N14
IN IN IN
WEA0B L12 WE#__CS# VSSQ_N3 N3 CSA1B_0 L12 WE#__CS# VSSQ_N3 N3 WEB0B L12 WE#__CS# VSSQ_N3 N3 1 2
R2302 1% J13 ZQ VSSQ_R1 R1
IN IN IN 120R
VSSQ_N12 N12 VSSQ_N12 N12 VSSQ_N12 N12 J10 SEN VSSQ_R3 R3
VSSQ_N14 N14 VSSQ_N14 N14 VSSQ_N14 N14 VSSQ_R4 R4
1 2
R2002 1% J13 ZQ VSSQ_R1 R1 1 2
R2102 1% J13 ZQ VSSQ_R1 R1 1 2
R2202 1% J13 ZQ VSSQ_R1 R1 VSSQ_R11 R11
120R J10 R3 120R J10 R3 120R J10 R3 DRAM_RST J2 R12
SEN VSSQ_R3 SEN VSSQ_R3 SEN VSSQ_R3 IN RESET# VSSQ_R12
VSSQ_R4 R4 VSSQ_R4 R4 VSSQ_R4 R4 +MVDD J1 MF VSSQ_R14 R14
VSSQ_R11 R11 VSSQ_R11 R11 VSSQ_R11 R11 VSSQ_V1 V1
DRAM_RST J2 RESET# VSSQ_R12 R12 DRAM_RST J2 RESET# VSSQ_R12 R12 DRAM_RST J2 RESET# VSSQ_R12 R12 VSSQ_V3 V3
IN IN IN
J1 MF VSSQ_R14 R14 +MVDD J1 MF VSSQ_R14 R14 J1 MF VSSQ_R14 R14 VSSQ_V12 V12
VSSQ_V1 V1 VSSQ_V1 V1 VSSQ_V1 V1 VSSQ_V14 V14
VSSQ_V3 V3 VSSQ_V3 V3 VSSQ_V3 V3 A5 Vpp_NC
VSSQ_V12 V12 VSSQ_V12 V12 VSSQ_V12 V12 +MVDD 1
R2305 2 1% V5 Vpp_NC1
V14 V14 V14 1 2.37K/X
2 B5
VSSQ_V14 VSSQ_V14 VSSQ_V14 R2306 1% VSS_B5
A5 Vpp_NC A5 Vpp_NC A5 Vpp_NC 1
C2301 2
5.49K/X VREFD1_B1 A10 VREFD1 VSS_B10 B10
1 2 V5 1 2 V5 1 2 V5 1uF/X V10 D10
+MVDD R2005 1% Vpp_NC1 +MVDD R2105 1% Vpp_NC1 +MVDD R2205 1% Vpp_NC1 6.3V VREFD2 VSS_D10
1 2.37K/X
2 B5 1 2.37K/X
2 B5 1 2.37K/X
2 B5 G5
R2006 1% VSS_B5 R2106 1% VSS_B5 R2206 1% VSS_B5 VSS_G5
1 5.49K/X
2 A10 B10 1 5.49K/X
2 A10 B10 5.49K/X
C2201 1 2 A10 B10 G10
VREFD1_A0 VREFD1_A1 VREFD1_B0
C2001 VREFD1 VSS_B10 C2101 VREFD1 VSS_B10 VREFD1 VSS_B10 VSS_G10
1uF/X V10 D10 1uF/X V10 D10 1uF/X V10 D10 H1
6.3V VREFD2 VSS_D10 6.3V VREFD2 VSS_D10 6.3V VREFD2 VSS_D10 VSS_H1
VSS_G5 G5 VSS_G5 G5 VSS_G5 G5 VSS_H14 H14
VSS_G10 G10 VSS_G10 G10 VSS_G10 G10 VSS_K1 K1
VSS_H1 H1 VSS_H1 H1 VSS_H1 H1 J14 VREFC VSS_K14 K14
VSS_H14 H14 VSS_H14 H14 VSS_H14 H14 VSS_L5 L5
VSS_K1 K1 VSS_K1 K1 VSS_K1 K1 +MVDD R2309 1 2 1% VSS_L10 L10
J14 VREFC VSS_K14 K14 J14 VREFC VSS_K14 K14 J14 VREFC VSS_K14 K14 R2310 1 2.37K2
1% VSS_P10 P10
L5 L5 L5 1 5.49K
2 VREFC_B1 J4 T5
VSS_L5 VSS_L5 VSS_L5 C2305 ABI# VSS_T5
VSS_L10 L10 VSS_L10 L10 +MVDD R2209 1 1% 2 1% VSS_L10 L10 1uF
6.3V VSS_T10 T10
+MVDD R2009 1 1% 2 1% VSS_P10 P10 +MVDD R2109 1 1%
2 1% VSS_P10 P10 R2210 1 2.37K2
1% VSS_P10 P10
1 2.37K2 J4 T5 1 2.37K2 J4 T5 5.49K
C2205 1 2 J4 T5
VREFC_B0
R2010 1% ABI# VSS_T5 R2110 1% ABI# VSS_T5 ABI# VSS_T5
1
C2005 2
5.49K VREFC_A0
VSS_T10 T10 1
C2105 2
5.49K VREFC_A1
VSS_T10 T10 1uF
VSS_T10 T10 ADBIB1
1uF 1uF
6.3V IN
6.3V 6.3V

ADBIA0 ADBIA1 ADBIB0

IN IN IN

Use internal Vref memory voltage

+MVDD
+MVDD
+MVDD
1C2023

1C2024

1C2025

1C2026
C2019

C2020

+MVDD
1

1
C2007

C2008

C2009

C2010

C2012

C2013

C2014

C2015

C2016

C2107

C2108

C2109

C2110

C2111

C2112

C2113

C2114

C2115

C2116

C2117

C2118

C2119

C2120

C2121
1

C2207

C2208

C2209

C2210

C2211

C2212

C2213

C2214

C2215

C2216

C2217

C2218

C2219

C2220

C2221
1

C2307

C2308

C2309

C2310

C2311

C2312

C2313

C2314

C2315

C2316

C2317

C2318

C2319

C2320

C2321
1

1
6.3V

6.3V

6.3V

6.3V

6.3V

6.3V
2

2
6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V
2

2
6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V
2

2
0.1uF

0.1uF

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V
0.1uF

0.1uF

0.1uF

0.1uF

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V
2

2
0.1uF

0.1uF

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V
0.1uF

0.1uF

0.1uF

0.1uF
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

+MVDD
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
+MVDD +MVDD
+MVDD +MVDD
1 C2039

+MVDD +MVDD
1 C2122

1 C2123

1 C2124

1 C2125

1 C2126

1 C2127

1 C2128

1 C2129

+MVDD
1

1
C2028

C2029

C2030

C2032

C2035

C2036

C2038

C2041

1 C2222

1 C2223

1 C2224

1 C2225

1 C2226

1 C2227

1 C2228

1 C2229
1

1
C2040

1 C2322

1 C2323

1 C2324

1 C2325

1 C2326

1 C2327

1 C2328

1 C2329
C2130

C2131
1

C2230

C2231
1

C2330

C2331
2

1
2

6.3V

6.3V

6.3V

6.3V
2

2
6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V
2

2
1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

2
1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

6.3V

6.3V
10uF

10uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF
10uF

10uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF
10uF

10uF

10uF

10uF

Title
GIGABYTE
Power Supply III: GDDR5 CHA&B
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 4 of 20
 CAPE VERDE GPIOs Strap CF XTAL OSC

PN 2280007900G for 1Mbit (PM25LV010A-100SCE)

U1E
+3.3V_BUS
+3.3V_BUS BIOS1
PART 5 OF 15
+3.3V_BUS VIDEO BIOS
AF23 VDDR3#1 GPIO_0 AH20 GPIO_0
5 FIRMWARE

1
AF24 VDDR3#2 GPIO_1 AH18 GPIO_1
5
BIOS

2
C1 AG23 VDDR3#3 GPIO_2 AN16 GPIO_2
5

2
1uF AG24
R4073 R4074 6.3V VDDR3#4
10K 10K
R14

2
2.2K BIOS(113-C445xx00-xxx)
GPIO_5_AC_BATT AH17 +3.3V_BUS

1
U11
GPIO_6_TACH AJ17

1
SCL AK26 SCL GPIO_7_BLON AK17 GPIO_7_VDDCI_VID GPIO_22_R 1 CE VDD 8
OUT OUT

1
SDA AJ26 SDA GPIO_8_ROMSO AJ13 GPIO_8 1 8
RP1A 5 GPIO_8_R 2 SO HOLD 7
BI 33R
GPIO_9_ROMSI AH15 GPIO_9 2 7
RP1B 3 WP SCK 6 C4
AJ16 GPIO_10 3 33R
6 4 5 0.1uF
GPIO_10_ROMSCK RP1C GND SI GPIO_9_R
6.3V
AK16 33R
GPIO_11
GPIO_11 5

2
GPIO_12 AL16 GPIO_12
5 PM25LV010A-100SCE
SMBCLK AJ23 SMBCLK GPIO_13 AM16 GPIO_13
5 5 GPIO_9_R
OUT SMBDATA AH23 SMBDATA GPIO_14_HPD2 AM14 HPD2 GPIO_10_R
BI OUT
GPIO_15_PWRCNTL_0 AM13 GPIO_15_VID0
OUT
GPIO_16 AK14
PIN BASED STRAPS
GPIO_17_THERMAL_INT AG30 GPIO_17_THERMINT
IN
GPIO_18_HPD3 AN14 +3.3V_BUS

GPIO
GPIO_19_CTF AM17 GPIO_19_CTF GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)
OUT
AF35 RSVD#1 GPIO_20_PWRCNTL_1 AL13 GPIO_20_VID1 1R1 4.7K/X
2 GPIO_0
5 0: 50% Tx output swing for mobile mode
OUT
AG36 RSVD#2 GPIO_21 AJ14 1: full Tx output swing (Default setting for Desktop)
AJ27 RSVD#3 GPIO_22_ROMCSB AK13 GPIO_22 4 5
RP1D
AK27 AN13 CLKREQB 33R
RSVD#4 CLKREQB 5 GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)

GPIO29 AG32 GPIO_29_VID3 1R2 4.7K/X

2 GPIO_1
5 0: Tx de-emphasis disabled for mobile mode
OUT
AN36 RSVD#6 GPIO30 AG33 GPIO_30_VID2 1: Tx de-emphasis enabled (Default setting for Desktop)
OUT
AP37 RSVD#7 GENERICA AJ19
+1.8V GENERICB AK19
R3 4.7K/X
GENERICC AJ20 DNI 1 2 GPIO_2
5 PCIe Gen3 capability
GENERICD AK20 1 = PCIe Gen3 is supported Cape Verde default 1
1 GENERICE_HPD4 AJ24 DNI
MR3
1 4.7K/X
2 0 = PCIe Gen3 is not supported
R98 GENERICF_HPD5 AH26
R5 4.7K/X
1K/X AJ21 SWAPLOCKA GENERICG_HPD6 AH24 DNI 1 2 GPIO_9_R
5 VGA DISABLE : 1 for disable (set to 0 for normal operation)
AK21 SWAPLOCKB
2

HPD1 AK24 HPD1

IN
TEST_PG AH16 TEST_PG GPIO(13,12,11) - CONFIG[2..0]
1

R6 4.7K/X
1 2 GPIO_13
5 100 - 512Kbit M25P05A (ST)
101 - 1Mbit M25P10A (ST)
R33 NA DNI CONFIG[2]
1K R7 4.7K/X 101 - 2Mbit M25P20 (ST)
1 2 GPIO_12
5
101 - 4Mbit M25P40 (ST)
CONFIG[1]
2

101 - 8Mbit M25P80 (ST)

R8 4.7K/X
1 2 GPIO_11
5 100 - 512Kbit Pm25LV512 (Chingis)

CONFIG[0] 101 - 1Mbit Pm25LV010 (Chingis)

R19 10K/X
1 2 GPIO_19_CTF 5 17
PWRGOOD must be connected to

VIP_DEVICE_STRAP_DIS
GND for normal operation
V2SYNC H2SYNC ?

1R4 10K/X
2 CLKREQB 5

RESERVED:

R10 4.7K
1 2 V1SYNC Internal use only. Other logic must not affect these signals
OUT
during RESET.

DNI
U1F R11 4.7K
1 2 H1SYNC
OUT
+1.8V DNI BIF_CLK_PM_EN
PART 6 OF 15 R13 4.7K/X
1 2 GPIO_8_R
5 0 - Disable CLKREQ# power management capability
AD12 VDDR4 DVPDATA_0 AU1 1 - Enable CLKREQ# power management capability

AF11 VDDR4 DVPDATA_1 AU3

1

AF12 VDDR4 DVPDATA_2 AW3

C6 C7 AF13 VDDR4 DVPDATA_3 AP6 Internal use only. Other logic must not RESERVED:
1uF 1uF AF15 AW5 affect these signals
6.3V 6.3V VDDR4 DVPDATA_4 STRAP_BIOS_ROM_EN
during RESET.
AG11 VDDR4 DVPDATA_5 AU5 CLKREQ# that requires open drain connection, and cannot be used as pinstrap
2

AG13 VDDR4 DVPDATA_6 AR6 Don't set high at reset

AG15 VDDR4 DVPDATA_7 AW6
DVPDATA_8 AU6
DVPDATA_9 AT7
4.7K/X
DVPDATA_10 AV7 R95 1 2 GENLK_VSYNC
IN
DVPDATA_11 AN7
DVP

DVPDATA_12 AV9 DNI

AR1 DVPCLK DVPDATA_13 AT9
4.7K/X
DVPDATA_14 AR10 R96 1 2 GENLK_CLK
IN
AP8 DVPCNTL_0 DVPDATA_15 AW10 SMS_EN_HARD
AW8 DVPCNTL_1 DVPDATA_16 AU10
AR3 DVPCNTL_2 DVPDATA_17 AP10
DVPDATA_18 AV11
AR8 DVPCNTL_MVP_0 DVPDATA_19 AT11

R4104
2.61K/X
AU8 DVPCNTL_MVP_1 DVPDATA_20 AR12
DVPDATA_21 AW12 1 2 TS_FDO_ASIC MLPS DISABLE
IN
+1.8V DVPDATA_22 AU12
1 221R
2 VREFG AH13 AP12
R17 VREFG DVPDATA_23
1 110R
2
R18
1C8 20.1uF
NA

+3.3V_BUS
B2
BLM15AG121SN1D/X
VDD33_100M 2 1
VDD33_27M 2 B31

1
BLM15AG121SN1D/X

Y1 XIN_OSC C9 C10
XOUT_OSC 1 3 0.1uF/X 0.1uF/X
6.3V 6.3V
2 4 +3.3V_BUS

2
27.000MHz_10PPM_30R/X
U12
U1G
2 1
C11 XTALOUT 10 XTALIN 1 1 2
C12

2
12pF/X 12pF/X
PART 7 OF 15 50V 50V
+1.8V VDD_100M 4 R20 R21
AM32 AF30 2 5.1K/X 5.1K/X
R22 1 5 8
XO_IN2 CLK_100M
DP_VDDR#19 NC_XTAL_PVDD 100M_OUT VDD_27M
1

0R/X

1
C14 NC_XTAL_PVSS AF31 SS_SEL0 7 SS_SEL0
1uF AN32 3 SS_SEL1
6.3V DP_VSSR#35 Share pad R26 and R19 SS_SEL1
2 R26 1
CLK_27M
27M_OUT 9
2

2
0R/X 6
+1V GND_100M
XO_IN2 AW35 GND_27M 2 R28 R29
AN31 11 5.1K/X 5.1K/X
DP_VDDC#13 GND_PAD
1

1
C16 SL16010DCT

C45
1uF AW34
6.3V XO_IN
XTAL_IN 2 1
PLLS XTAL
2

12pF
+1.8V Divider for 1.8V signaling.
50V
1 B52
+SPV18 AM10 SPLL_PVDD
1

120/500mA
Keep XIN_OSC and XOUT_OSC as short as possible

3
4
27.000MHz_10PPM_30R
to minimize stray capacitance
C18 C19 C20
10uF 1uF 0.1uF AN10 AV33

Y2
6.3V 6.3V 6.3V SPLL_PVSS XTALIN R37
2

1
2
2 1M

C44
+1V
1 B62
+SPV10 AN9 SPLL_VDDC XTALOUT AU34 XTALOUT 2 R36 1 2 1
1

120/500mA 0R 12pF
50V
C21 C22
1uF 0.1uF
6.3V 6.3V
B7

+1.8V
1 2

1 2

1 2 CLKTESTA AK10
1

BLM15AG121SN1D H7 MPLL_PVDD
C24 C34 C35 C26 C27 H8 MPLL_PVDD CLKTESTB AL10
10uF 4.7uF 4.7uF 1uF 0.1uF
6.3V 6.3V 6.3V 6.3V 6.3V
2

NA

Title
GIGABYTE
Power Supply III:Cape Verde GPIO STRAP CF P
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 5 of 20
 OPTIONAL ESD PROTECTION DIODES

D1700
2 1 ESD5V3U1U-02LRH A_R_DAC1_F
6 9
D1701
2 1 ESD5V3U1U-02LRH A_G_DAC1_F
6 9
See BOM for qualified filters
D1702
Pseudo differential RGB should be routed from the ASIC to the display 2 1 ESD5V3U1U-02LRH A_B_DAC1_F
6 9
D1703
connector without switching reference plane or running over split plane.
2 1 ESD8V0R1B-02LRH DDCDATA_DAC1_R
6 9
U1H
D1704
2 1 DDCCLK_DAC1_R

L1710

L1700
ESD8V0R1B-02LRH 6 9
PART 8 OF 15
+1.8V B1700 D1705
2 1 +VDD1DI AC33 VDD1DI R AD39 R_DAC1 1R1731 2 0R 1 2 1 2 2 1 ESD8V0R1B-02LRH A_HSYNC_DAC1_R
6 9

1
120/500mA AVSSN#1 AD37 47nH 47nH D1706

1
C1700 C1701 R1701 C1704 C1707 2 1 ESD8V0R1B-02LRH A_VSYNC_DAC1_R
6 9
1uF
6.3V
0.1uF
6.3V
AC34 VSS1DI R1711 MR1731
150R/X 8pF/X
50V
12pF/X
50V
150R 402 402

2
AE36 0R/X
G +5V_VESA

2
AD35 R_VGA

L1711

L1701
+1.8V AVSSN#2 6
B1701
2 1 +AVDD_DAC1 AD34 AVDD
G_DAC1 1R1732 2 0R 1 2 1 2

1
120/500mA 0R 47nH

1
DACI
C1702 C1703 B AF37 B_DAC1
R1702 C1705 C1708 R1704 R1705
1uF
6.3V
0.1uF
6.3V
AE34 AVSSQ AVSSN#3 AE38 R1712 MR1732
150R/X 8pF/X
50V
12pF/X
50V
2.2K 2.2K
150R 402
402

2
0R/X

2
G_VGA A_R_DAC1_F

L1712

L1702
6 OUT

R1700
HSYNC AC36 A_G_DAC1_F
OUT
1 2 RSET AB34 RSET VSYNC AC38 1R1733 2 0R 1 2 1 2 A_B_DAC1_F
OUT

1
499R 47nH
0R

1
R1707
R1703 C1706 C1709 BI
DDC4DATA 2 1 DDCDATA_DAC1_R
BI
DDCVGACLK AJ30 R1713 MR1733
150R/X 8pF/X
50V
12pF/X
50V 33R
DDCVGADATA AJ31 150R 402 402 DDC4CLK 2 R1706
1 DDCCLK_DAC1_R TO DVI CONNECTOR
IN OUT

2
0R/X
33R

2
A_HSYNC_DAC1_R
OUT
B_VGA A_VSYNC_DAC1_R
NA 6 OUT

Please pay attention to the grounding

HSYNC_VGA
6

1
strategies for these filter capacitors to

1
maintain a close loop for current.
C1741
12pF/X

24R/X
50V
MR1708

2
U1700A

R1708
OUT
H1SYNC 2 3 HSYNC_DAC1_B 1 2

1
24R
74VHCT125
C1711
12pF

1
50V

2
DNI
+5V_VESA

R1709
74VHCT125

OUT
V1SYNC 5 6 VSYNC_DAC1_B 1 2

1
24R/X

1
U1700B C1710
MR1709 12pF/X

24R
50V

2
2
C1712
+5V_VESA

2
VSYNC_VGA
U1700C 6

1
1 2

14
C1760

1
0.1uF
6.3V
9 8 C1740

10V
12pF
U1700E R1744 R1745

1
50V
74VHCT125 2.2K

2
2.2K

L1730

L1720
13 10

2
74VHCT125

1uF
J1501
6
R_VGA 1 2 1 2 6 R_VGA_R 1
7 R

1
47nH 47nH
6 G_VGA_R 2
74VHCT125
6 B_VGA_R 3 G
R1734 C1731 C1734
12 11 150R 8pF 12pF 11 B
402 50V 402 50V MS0
6
DDC2DATA_VGA 12

2
U1700D 4 MS1
DDC2CLK_VGA 15 MS2

L1731

L1721
6
9 MS3
G_VGA 1 2 1 2 HSYNC_VGA 13 NC
6 6
HS

1
47nH 47nH 6
VSYNC_VGA 14
5 VS
R1735 C1732 C1735
150R 8pF 12pF 6 VSS
402 50V 50V VSS#6
402 7

2
8 VSS#7
10 VSS#8

L1732

L1722
16 VSS#10
B_VGA 1 2 1 2 17 CASE
6
CASE#17

1
47nH
47nH VGA/tCON_WIESON_31796219
R1736 C1733 C1736
150R 8pF 12pF
402 50V 402 50V

2
U1I

MLPS
PART 9 OF 15
+1.8V R1051 1 2 3.24K PS_0
6
R1052 1 2 5.62K
R1746
C1052 1 2 0.1uF/X 16V 6
PS_0 AM34 PS_0 IN
DDC2CLK 2 1 DDC2CLK_VGA
6
OPTIONAL ESD PROTECTION DIODES 33R
R1747
6
PS_1 AD31 PS_1 CEC1 AC30 BI
DDC2DATA 2 1 DDC2DATA_VGA
6
D1710 33R
MLPS 6
PS_2 AG31 PS_2 2 1 ESD5V3U1U-02LRH R_VGA_R
6
+1.8V R1053 1 2 8.45K PS_1
6 D1711
R1054 1 2 2.0K 6
PS_3 AD33 PS_3 2 1 ESD5V3U1U-02LRH G_VGA_R
6
C1054 1 2 0.1uF/X 16V GENLK_CLK AD29 GENLK_CLK
OUT
D1712
GENLK_VSYNC AC29 GENLK_VSYNC
OUT
2 1 ESD5V3U1U-02LRH B_VGA_R
6
D1713
2 1
MLPS

ESD8V0R1B-02LRH DDC2DATA_VGA
6
MLPS D1714

+1.8V R1055 1 2 4.75K PS_2

6 2 1 ESD8V0R1B-02LRH DDC2CLK_VGA
6
R1056 1 2 5.1K/X AF32 NC D1715
C1056 1 2 680nF 16V AC32 NC 2 1 ESD8V0R1B-02LRH VSYNC_VGA
6
AD32 NC D1716
AA29 NC 2 1 ESD8V0R1B-02LRH HSYNC_VGA
6
AC31 NC
MLPS AD30 NC
+1.8V R1057 1 2 5.1K/X PS_3
6 AG21 NC
R1058 1 2 4.75K U13 NC
C1058 1 2 10NF 16V V13 NC NC_TSVSSQ AF33

NA

Title
GIGABYTE
Power Supply III: Cape Verde DAC and MLPS
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 6 of 20
 +1.8V
U1J

17 15 10 9 +1.8V
PART 10 OF 15

AU28 NC_DP_VDDR#10 TX2P_DPA0P AT27

1
10V TX2M_DPA0N AR26
C2509 C2510 C2511
0.1uF
4.7uF
6.3V
1uF
6.3V TX1P_DPA1P AU26
AV27 DP_VSSR

2
TX1M_DPA1N AV25

TX0P_DPA2P AT25

Please pay attention to the grounding TX0M_DPA2N AR24

strategies for these filter capacitors to AV29 NC_DP_VDDR#12
maintain a close loop for current.
TXCAP_DPA3P AU24

TXCAM_DPA3N AV23

AR28 DP_VSSR

+1V
AUX1P AM27
9 2 +1V
AP31 DP_VDDC AUX1N AL27
AP32 DP_VDDC

1
10V
C2515 C2516 C2517 DDC1CLK AM26
4.7uF 1uF 0.1uF
6.3V 6.3V
DDC1DATA AN26

2
AN33 DP_VDDC
AP33 DP_VDDC

TMDP A/B
AN24 NC_DP_VDDR#1
AP24 NC_DP_VDDR#6

TX5P_DPB0P AT33
AP25 NC_DP_VDDR#7
AP26 NC_DP_VDDR#8 TX5M_DPB0N AU32

TX4P_DPB1P AR32

TX4M_DPB1N AT31

TX3P_DPB2P AV31
2 1
R2500
DPAB_CALR AW28 DPAB_CALR
150R
TX3M_DPB2N AU30

AN27 DP_VSSR TXCBP_DPB3P AR30

AP27 DP_VSSR
AP28 DP_VSSR TXCBM_DPB3N AT29
AW24 DP_VSSR
AW26 DP_VSSR
AN29 DP_VSSR
AP29 DP_VSSR
AP30 DP_VSSR DDCCLK_AUX4P AL29 DDC4CLK
OUT
AW30 DP_VSSR
AW32 DP_VSSR DDCDATA_AUX4N AM29 DDC4DATA
BI

NA

Title
GIGABYTE
Power Supply III: Cape Verde TMDP AB unused
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 7 of 20
 2011.12.20 移移2個DP，修修HDMI GBT用用

+1.8V
U1K

PART 11 OF 15

AU18 NC_DP_VDDR#9 TX2P_DPC0P AT17

1
C1800 C1803 C1804 TX2M_DPC0N AR16
4.7uF 1uF 0.1uF
6.3V 6.3V 6.3V
TX1P_DPC1P AU16

2
AV17 DP_VSSR
TX1M_DPC1N AV15

TX0P_DPC2P AT15

TX0M_DPC2N AR14
Please pay attention to the grounding AV19 NC_DP_VDDR#11
TXCCP_DPC3P AU14
strategies for these filter capacitors to

maintain a close loop for current. TXCCM_DPC3N AV13

AR18 DP_VSSR
+1V

AUX2P AN20

AP13 NC_DP_VDDC#1 AUX2N AM20

1

1
AT13 NC_DP_VDDC#4
C1813 C1814 C1815
4.7uF 1uF 0.1uF AM19 DDC2CLK

TMDP C/D
6.3V 6.3V 6.3V DDC2CLK
2

2
DDC2DATA AL19
DDC2DATA
AP14 NC_DP_VDDC#2
AP15 NC_DP_VDDC#3

To use Mini DP: 6141073900G

AP20 NC_DP_VDDR#2 OUT
AP21 NC_DP_VDDR#3 Watch out for spacing and Bracket

BI due to connectors' spring

TX5P_DPD0P AT23 DPD_C0P 1 2

C1822 8 DPD_0P
AP22 NC_DP_VDDR#4
0.1uF
6.3V
AP23 NC_DP_VDDR#5 TX5M_DPD0N AR22 DPD_C0N 1 2
C1823 8 DPD_0N
0.1uF
6.3V
TX4P_DPD1P AU22 DPD_C1P 1 2
C1824 8 DPD_1P
0.1uF
6.3V
TX4M_DPD1N AV21 DPD_C1N 1 2
C1825 8 DPD_1N
0.1uF
6.3V
TX3P_DPD2P AT21 DPD_C2P 1 2
C1826 8 DPD_2P
2 1
R1800
DPCD_CALR AW18 DPCD_CALR
0.1uF
6.3V
150R
TX3M_DPD2N AR20 DPD_C2N 1 2
C1827 8 DPD_2N
0.1uF
6.3V
AN17 DP_VSSR TXCDP_DPD3P AU20 DPD_C3P 1 2
C1828 8 DPD_3P
AP16 DP_VSSR
0.1uF
6.3V
AP17 DP_VSSR TXCDM_DPD3N AT19 DPD_C3N 1 2
C1829 8 DPD_3N
AW14 DP_VSSR 2.2K
0.1uF
6.3V
R2703
AW16 DP_VSSR +5V_VESA 2 1
AN19 MR1830
1 2 0R
DP_VSSR 2.2K
R2701
AP18 DP_VSSR 2 1
AP19 DP_VSSR DDCCLK_AUX5P AN21 DDCCLK_AUX5P 1 2
C1830 8 DPD_AUXP
AW20 DP_VSSR
0.1uF/X
6.3V
1 2
R1810
AW22 DP_VSSR DDCDATA_AUX5N AM21 DDCDATA_AUX5N 1 2
C1831 8 DPD_AUXN 100K/X
0.1uF/X
6.3V
2 1
R1811 +3.3V_BUS
100K/X
MR1831
NA 1 2 0R

OPTIONAL ESD PROTECTION

DIODES

D1801
D Y4
8
DPD_0P 5 6 DPD_0P
8
C Y3
8
DPD_0N 4 7 DPD_0N
8
GND GND1
3 8
B Y2
8
DPD_1P 2 9 DPD_1P
8
A Y1
8
DPD_1N 1 10 DPD_1N
8

RCLAMP0524P
+3.3V_BUS
8
D1803
+5V_VESA

3
D Y4
8
DPD_2P 5 6 DPD_2P
8
C Y3
8
DPD_2N 4 7 DPD_2N
8 HDMI Q1805 1 1 2
R1814 HPD_DPD HPD_DPD
GND GND1
3 8 8
DPD_0P 1 20 MMBT3904 10K
DPD_3P 2 B Y2
9 DPD_3P 2 1 GND#20 21
8 8

2
DPD_3N 1 A Y1
10 DPD_3N DPD_0N 3 2 GND#21 22
8 8 8 OUT
DPD_1P 4 3 GND#22 23
HPD1
8
4 GND#23

1
RCLAMP0524P 5
DPD_1N 6 5
8 R1815
DPD_2P 7 6 10K
8
8 7

2
DPD_2N 9 8
8
DPD_3P 10 9
8
11 10
D1807 2 1 ESD5V3U1U-02LRH DPD_AUXN DPD_3N 12 11
8 8
13 12
D1806 2 1 ESD5V3U1U-02LRH DPD_AUXP 14 13
8
DPD_AUXP 15 14
8
DPD_0N

DPD_1N

DPD_3N

15
DPD_0P

DPD_1P

DPD_2P

DPD_3P

8
DPD_AUXN 16
16
1

17
18 17
R2713 R2714 R2715 R2716 R2717 R2718 R2719 R2720
499R 499R 499R 499R 499R 499R 499R 499R HPD_DPD 19 18
8
19
2

MJ1801
C2722
1uF
6.3V
2011.12.15 Modify
2
3

Q2701

IN
TMDP_EN 1 2N7002E

GIGABYTE
2

Title
Power Supply III: Cape Verde TMDP C & D DP D
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 8 of 20
 CAPE VERDE LVTMDP E&F dDVI-I

+1.8V ATIPartNo = 216NOPNCAPEVERDEDDR5

U1L

17 15 10 7 +1.8V
PART 12 OF 15
DPEF_GND
1EFTX2P 2
R1501
AM37 DP_VDDR T2X2P_DPE0P AP35 DPE_TX2P 1 2
C1501
499R EFTX2P
9
0.1uF
6.3V

1
10V T2X2M_DPE0N AR35 DPE_TX2N 1 2
C1502
EFTX2M
9
Please pay attention to the grounding C1520 C1521 C1522
0.1uF
6.3V
2EFTX1P 1
R1503 1EFTX2M 2
R1502
0.1uF
strategies for these filter capacitors to 4.7uF
6.3V
1uF
6.3V T2X1P_DPE1P AR37 DPE_TX1P 1 2
C1503
499R 499R EFTX1P
9
maintain a close loop for current.
AN38 DP_VSSR
0.1uF

2
6.3V
T2X1M_DPE1N AU39 DPE_TX1N 1 2
C1504
EFTX1M
9
0.1uF
6.3V
2 1
R1505 2EFTX1M 1
R1504
T2X0P_DPE2P AW37 DPE_TX0P 1 2
C1505
499R 499R EFTX0P
9
0.1uF
6.3V
T2X0M_DPE2N AU35 DPE_TX0N 1 2
C1506
EFTX0M
9
AL38 DP_VDDR
0.1uF
6.3V
2EFTXCP 1
R1507 2EFTX0M 1
R1506
T2XCEP_DPE3P AP34 DPE_TXCAP 1 2
C1507
499R 499R EFTXCP
9
0.1uF
6.3V
T2XCEM_DPE3N AR34 DPE_TXCAN 1 2
C1508
EFTXCM
9
0.1uF
6.3V
2EFTXCM 1
R1508
AM35 DP_VSSR
499R

+1V
DDCCLK_AUX3P AL30
7 2 +1V
AL33 DP_VDDC DDCDATA_AUX3N AM30
AM33 DP_VDDC

LVTMDP E/F
10V

C1523 C1524 C1525

4.7uF 1uF
6.3V 6.3V 0.1uF

2
AK33 DP_VDDC
AK34 DP_VDDC

AH34 DP_VDDR
AJ34 DP_VDDR

2 1
R1509
T2X5P_DPF0P AG38 DPF_TX5P 1 2
C1509
EFTX5P 499R
9
AF34 DP_VDDR
0.1uF
6.3V
AG34 DP_VDDR T2X5M_DPF0N AH37 DPF_TX5N 1 2
C1510
EFTX5M
9
0.1uF
6.3V
2 1
R1511 2 1
R1510
T2X4P_DPF1P AH35 DPF_TX4P 1 2
C1511
EFTX4P 499R 499R
9
0.1uF
6.3V
T2X4M_DPF1N AJ36 DPF_TX4N 1 2
C1512
EFTX4M
9
0.1uF
6.3V
2 1
R1513 2 1
R1512
T2X3P_DPF2P AJ38 DPF_TX3P 1 2
C1513
EFTX3P 499R 499R
9
2 1
R1500
DPEF_CALR AM39 DPEF_CALR
0.1uF
6.3V
150R
T2X3M_DPF2N AK37 DPF_TX3N 1 2
C1514
EFTX3M
9
0.1uF
6.3V +12V_BUS 2 1
R1514
AN34 DP_VSSR T2XCFP_DPF3P AK35 499R

AP39 DP_VSSR 17 16 15 14 12 11 1 +12V_BUS

AR39 DP_VSSR T2XCFM_DPF3N AL36
AU37 DP_VSSR

3
AF39 DP_VSSR R1544
AH39 DP_VSSR
10K
AK39 DP_VSSR DDCCLK_AUX6P AK30 Q1501

2
AL34 DP_VSSR
OUT
TMDP_EN 1 2N7002E

DDCDATA_AUX6N AK29

2
C1543 +5V_VESA
0.1uF
DEVICE_NAME = NA 16V +5V_VESA
15

2
J1500
25
CASE
9
EFTX2M 1
EFTX2P 2 TMDS Data2-
9
3 TMDS Data2+
EFTX4M 4 TMDS Data2/4 Shield
9
OPTIONAL ESD PROTECTION DIODES
EFTX4P 5 TMDS Data4-
9
DDCCLK_DAC1_R 6 TMDS Data4+
IN DDC Clock
BI
DDCDATA_DAC1_R 7
A_VSYNC_DAC1_R 8 DDC Data
IN Analog VSYNC
9
EFTX1M 9
EFTX1P 10 TMDS Data1-
9
11 TMDS Data1+
EFTX3M 12 TMDS Data1/3 Shield
9
D1600 D1601 EFTX3P 13 TMDS Data3-
9
EFTX2P 5 D Y4
6 EFTX2P EFTX5P 5 D Y4
6 EFTX5P 2 1 14 TMDS Data3+
9 9 9 9 C1526
EFTX2M 4 C Y3
7 EFTX2M EFTX5M 4 C Y3
7 EFTX5M 1uF 15 +5V Power
9 9 9 9 10V
3 GND GND1
8 3 GND GND1
8 HPD_DVIEF 16 GND (for +5V)
EFTX1P 2 B Y2
9 EFTX1P EFTX4P 2 B Y2
9 EFTX4P EFTX0M 17 Hot Plug Detect
9 9 9 9 9
EFTX1M 1 A Y1
10 EFTX1M EFTX4M 1 A Y1
10 EFTX4M EFTX0P 18 TMDS Data0-
9 9 9 9 9
DNI DNI 19 TMDS Data0+
RCLAMP0524P/X EFTX5M 20 TMDS Data0/5 Shield
9
RCLAMP0524P/X
EFTX5P 21 TMDS Data5-
9
22 TMDS Data5+
EFTXCP 23 TMDS Clock Shield
9
EFTXCM 24 TMDS Clock+
+3.3V_BUS 9
D1602 D1603 TMDS Clock-
D Y4 D Y4
9
EFTX0M 5 6 EFTX0M
9 9
EFTX3M 5 6 EFTX3M
9 18 17 16 15 1 +3.3V_BUS
IN
A_R_DAC1_F C1
EFTX0P 4 C Y3
7 EFTX0P EFTX3P 4 C Y3
7 EFTX3P A_G_DAC1_F C2 Analog Red
9 9 9 9 IN
3 GND GND1
8 3 GND GND1
8 A_B_DAC1_F C3 Analog Green
B Y2 B Y2 IN Analog Blue
9
EFTXCP 2 9 EFTXCP
9 2 9 IN
A_HSYNC_DAC1_R C4
Analog HYNC

3
A Y1 A Y1
9
EFTXCM 1 10 EFTXCM
9 9
HPD_DVIEF 1 10 HPD_DVIEF
9 C5
DNI DNI
Q1502
1 HPD2_IN 1 9 2 HPD_DVIEF C6 Analog GND
R1518
MMBT3904 10K Analog GND#C6
RCLAMP0524P/X RCLAMP0524P/X
26

2
HPD2
27 CASE#26
OUT CASE#27
28
CASE#28

1
29
30 CASE#29
R1517
10K CASE#30
DVI-D/24P/SC/RA/D

2
2011.12.20 修修DVI-I GBT用用

Title
GIGABYTE
Power Supply III: Cape Verde TMDP E&F dDVI
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 9 of 20
 +VDDC

CAPE VERDE Power & GND

1
C117 C118 C119 C88 C89 C106 C107 C108
2.2UF 1uF 1uF 1uF 2.2UF 1uF 2.2UF 2.2UF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V

2
1

1
C109 C110 C111 C112 C113 C114 C115 C116
1uF 1uF 2.2UF 1uF 2.2UF 1uF 2.2UF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V

2
U1N
U1M
+MVDD
PART 14 OF 15
14 +MVDD PART 13 OF 15
B31 GND GND A3
AC7 VDDR1 VDDC AA15 B33 GND GND A37

1
AD11 VDDR1 VDDC AA17 B7 GND GND AA16
AF7 VDDR1 VDDC AA20 C182 C168 C169 C170 C171 C172 C173 C85 C174 B9 GND GND AA18
AG10 VDDR1 VDDC AA22 2.2UF
6.3V
1uF
6.3V
1uF
6.3V
2.2UF
6.3V
2.2UF
6.3V
2.2UF
6.3V
1uF
6.3V
2.2UF
6.3V
2.2UF
6.3V
C1 GND GND AA2
AJ7 VDDR1 VDDC AA24 C39 GND GND AA21

2
AK8 VDDR1 VDDC AA27 E35 GND GND AA23
AL9 VDDR1 VDDC AB16 E5 GND GND AA26

1
G11 VDDR1 VDDC AB18 F11 GND GND AA28
G14 VDDR1 VDDC AB21 C183 C184 C185 C186 C187 C188 C189 C190 F13 GND GND AA6

1
G17 VDDR1 VDDC AB23 1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
2.2UF
6.3V
2.2UF
6.3V
1uF
6.3V
F15 GND GND AB12
C141 G20 VDDR1 VDDC AB26 F17 GND GND AB15

2
0.1uF
10V
G23 VDDR1 VDDC AB28 F19 GND GND AB17
G26 VDDR1 VDDC AC17 F21 GND GND AB20

2
G29 VDDR1 VDDC AC20 F23 GND GND AB22
H10 VDDR1 VDDC AC22 F25 GND GND AB24
J7 VDDR1 VDDC AC24 F27 GND GND AB27
1

1
J9 VDDR1 VDDC AC27 F29 GND GND AC11
C134 C135 C136 C137 C138 C139 C140 K11 VDDR1 VDDC AD18 C176 C178 C191 C192 C300 C301 C302 F31 GND GND AC13
1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
1uF
6.3V
K13 VDDR1 VDDC AD21 4.7uF/X
6.3V
4.7uF/X
6.3V
4.7uF/X
6.3V
4.7uF/X
6.3V
4.7uF/X
6.3V
4.7uF/X
6.3V
4.7uF/X
6.3V
F33 GND GND AC16
K8 VDDR1 VDDC AD23 F7 GND GND AC18
2

2
L12 VDDR1 VDDC AD26 F9 GND GND AC2
L16 VDDR1 VDDC AF17 G2 GND GND AC21
L21 VDDR1 VDDC AF20 G6 GND GND AC23
1

L23 VDDR1 VDDC AF22 MC176 MC178 MC191 MC192 MC300 MC301 MC302 H9 GND GND AC26
22uf 47uf 47uf 47uf 47uf 47uf
MC130 MC131 L26 VDDR1 VDDC AG16 47UF J2 GND GND AC28
4.7uF/X
6.3V
4.7uF/X
6.3V
L7 VDDR1 VDDC AG18 Overlap cap pair foorprints (0805 with 0603) J27 GND GND AC6
M11 VDDR1 J6 GND GND AD15
2

N11 VDDR1 VDDC AH22 J8 GND GND AD17

P7 AH27 K14 AD20
R11
VDDR1 VDDC
AH28 47u 修修修22u K7
GND GND
AD22

POWER
VDDR1 VDDC GND GND
1

U11 VDDR1 VDDC M26 L11 GND GND AD24

C130 C131 U7 VDDR1 VDDC N24 L17 GND GND AD27
10uF
6.3V
10uF
6.3V
Y11 VDDR1 L2 GND GND AD9
Y7 VDDR1 VDDC R18 L22 GND GND AE2
2

VDDC R21 L24 GND GND AE6

Overlap cap pair foorprints (0805 with 0603)
VDDC R23 L6 GND GND AF10
VDDC R26 M17 GND GND AF16
VDDC T17 M22 GND GND AF18
VDDC T20 M24 GND GND AF21
VDDC T22 N16 GND GND AG17
T24 N18 AG2

GROUND
VDDC GND GND
N2 GND GND AG20
VDDC U16 N21 GND GND AG22
VDDC U18 N23 GND GND AG6
VDDC U21 N26 GND GND AG9
VDDC U23 N6 GND GND AH21
VDDC U26 R15 GND GND AJ10
VDDC V17 R17 GND GND AJ11
VDDC V20 R2 GND GND AJ2
VDDC V22 R20 GND GND AJ28
VDDC V24 R22 GND GND AJ6
VDDC V27 R24 GND GND AK11
VDDC Y16 R27 GND GND AK31
VDDC Y18 R6 GND GND AK7
VDDC Y21 T11 GND GND AL11
VDDC Y23 T13 GND GND AL14
VDDC Y26 T16 GND GND AL17
+1.8V VDDC Y28 T18 GND GND AL2
+1.8V
T21 GND GND AL20
17 15 9 7
T23 GND
T26 GND GND AL23
AF26 VDD_CT GND AL26
AF27 VDD_CT U15 GND GND AL32
1

AG26 VDD_CT BIF_VDDC#2 T27 +1V U17 GND GND AL6

C161 C162 C163 AG27 VDD_CT U2 GND GND AL8
1uF
6.3V
1uF
6.3V
0.1uF
6.3V BIF_VDDC#1 N27 U20 GND GND AM11
U22 GND GND AM31
2

AA13 VDDCI U24 GND GND AM9

AB13 VDDCI U27 GND GND AN11
AC12 VDDCI U6 GND GND AN2
AC15 VDDCI V11 GND GND AN30
+VDDCI AD13 VDDCI GND AN6
Overlap cap pair foorprints AD16 VDDCI V16 GND GND AN8
+VDDCI (0805 with 0603) M15 VDDCI V18 GND GND AP11
M16 VDDCI V21 GND GND AP7
M18 VDDCI V23 GND GND AP9
1

M23 VDDCI V26 GND GND AR5

C101 MC101 C196 MC196 C195 C194 C193 C87 C86 N13 VDDCI W2 GND
10uF
6.3V
4.7uF/X
6.3V
10uF
6.3V
4.7uF/X
6.3V
1uF
6.3V
1uF
6.3V
0.1uF
6.3V
0.1uF
6.3V
0.1uF
6.3V
N15 VDDCI W6 GND GND B11
N17 VDDCI Y15 GND GND B13
2

N20 VDDCI Y17 GND GND B15

N22 VDDCI Y20 GND GND B17
R12 VDDCI TS_A AL31 Y22 GND GND B19
R13 VDDCI Y24 GND GND B21
R16 VDDCI Y27 GND GND B23
T12 VDDCI GND B25
T15 VDDCI A39 VSS_MECH GND B27
V15 VDDCI FB_VDDC AF28 AW1 VSS_MECH GND B29
1

Y13 VDDCI AW39 VSS_MECH

MC103 C90 C91 C92
4.7uF/X 0.1uF 0.1uF 0.1uF
6.3V 6.3V 6.3V 6.3V
AG28 FB_VDDCI FB_GND AH29 NA
2

NA

Title
GIGABYTE
Power Supply III: Cape Verde Power&GND
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 10 of 20
 +12V_BUS

1
C833
0.15uF C815 C816 C817 C819
16V
603 10UF 10UF 10UF 10UF/X

2
0805 0805

Input MLCC

5
6
7
8
Q801

Thermal
Pad
R801
+1V_UGATE_CTR 1 2 +1V_UGATE
11
0R 2011.12.20 修修H-L side & Chock
402

4
3
2
1
+1V

F_102-C44501-00 rev 15 2.2uH

+1V_PHASE
L801
11

1
R819
300R/X +
C823 C824 C829 C825

9
5
6
7
8
0.1uF 0.015uF 10uF 820uF
Q802 805

2 1
10V
402 10V
402 6.3V 2.5V
0805 6.3V

2
C808
603
16V
1uF/X

1
4
3
2
1
R803
11
+1V_LGATE_CTR 1 2 +1V_LGATE_1
0R
603

NTMD4903NFR2G

+12V_BUS IN
17 16 15 14 12 11 9 1 +12V_BUS

1
C806
0.15uF/X
16V

2
D801
+1V
BAT54KFILM/X
Type III Compensation

C805
1

1 2 11 +1V_PHASE +1V_PHASE
C811 R812

16V
1 2 2 18.0K 1 2 R8091
0.1uF 8.2NF 0R R814,R809 NS800
10V
U801 share pad

2
+1V_BOOT 1 BOOT PHASE 8 C812 1 2 R813 NS_VIA/X
22pF
50V
1 2 2 1
C813
11
+1V_UGATE_CTR 2 UGATE COMP/EN 7 +1V_EN 0R/X
R814
470PF
16V
0R
R811 R800

1
R805
1 2 3 OSC FB 6 +1V_FB 1 2 2 1 +1V_ASIC_FB
0R 10K 0R
17 16 15 603
11 +1V_LGATE_CTR 4 LGATE VCC 5 +1V_VCC 14 12 RFB1
1

11 9 Reserve for
1 R807 +12V_BUS
9 12 2 1
1
GND1 GND4 Loop Measurement
R815
5.9K 10 GND2 GND3 11 2.2R
C803
0.22uF 805
2

25V
805
uP1529QSU8 OUT
2

+12V_BUS

Title
GIGABYTE
Power Supply III: 0.95V REGULATER
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 11 of 20
 +12V_BUS

17 16 15 14 12 11
9 1

2
L602
C609 B704 B705 0.47uH
10UF/X 60R 60R
0805

1
GND
8x8 TH

Overlap
+VDDC_Source +VDDC_Source

12 12

1
C621 C622 C634 C624 C625 Input Bulk CAP
10U 10UF/X 10UF/X C635 10UF 10UF/X 10UF/X C676 C682 C628 C629 C631 C633 C640 C665
0805 0805 0805 0805
+ + 0805 0805 0805 0805
10UF

2
0805 GND 0805 GND GND GND 270UF 270UF 10UF 10UF 10UF/X 0805 10UF 10UF

2
Mirrored on PCB Mirrored on PCB Mirrored on PCB 6.3x7 TH 6.3x7 TH Mirrored on PCB Mirrored on PCB

8
7
6
5

9
Input MLCC 此6PCS Input MLCC電電電電電電PCB T& B，并并并并并并并電 此6PCS Input MLCC電電電電電電PCB T& B，并并并并并并并電 Input MLCC Q602

5
6
7
8

5
6
7
8
Q601 Q611

8
7
6
5

9
Q612

Thermal
Pad
Thermal

Thermal

Thermal
Pad

Pad

Pad
2011.12.20 修修H-L side & Chock NTMFS4921N/N/6.95m/PPAKSO8

1
2
3
4
603

4
3
2
1

4
3
2
1
NTMFS4921N/N/6.95m/PPAKSO8/X NTMFS4921N/N/6.95m/PPAKSO8 NTMFS4921N/N/6.95m/PPAKSO8/X

1
2
3
4
603

12
VDDC_UGATE1_CTR 1 R601 2 VDDC_UGATE_1 0.00072R +VDDC 0.00072R
QR602
40A 40A
VDDC_UGATE_2 1 2 VDDC_UGATE2_CTR
12

5%
0R 12 12
VDDC_PHASE_1 L601 0.3uH/V/30A/MD/D
12 +VDDC12 L612 0.3uH/V/30A/I-H/D VDDC_PHASE_2

5%
0R
COMMON COMMON
11LC5-30300C-13R HT

2
9
5
6
7
8

9
5
6
7
8

8
7
6
5
9

8
7
6
5
9
Pass transistor Circuit Q661 and R661 for 8V Gate Drive Q603 Q604 R606 Q624 Q623
300R/X 300R/X
NS602 R616
NS_VIA/X
805 NS601 NS611 805

2 1

2 1
NS_VIA/X NS_VIA/X
This Circuit is only for 8V gate drive circuit application. NS612
NS_VIA/X
Assume VCC consumes 200mA total including 5VCC providing
buffered output source a minimum 20mA requirement C606 C616
603 603
NTMFS4935N/N/3.2mm/PPAKSO8
NTMFS4935N/N/3.2mm/PPAKSO8

1
1uF/X 2.2n/6/X7R/50V/K
P(Q_8VCC)max=(12V-8V)*0.2A=800mW

4
3
2
1

4
3
2
1

1
2
3
4

1
2
3
4
GND

1
NTMFS4935N/N/3.2mm/PPAKSO8 NTMFS4935N/N/3.2mm/PPAKSO8 R617
261R/X
R607 1%
261R/X
1%

2
Place across Place across

2
+12V_BUS 12
VDDC_LGATE1_CTR 1 R603 2 VDDC_LGATE_1 LS MOSFET LS MOSFET
0R
603 RC snubber values shown RC snubber values shown

CCSN1

CCSN2
CCSP1

CCSP2
QR604

17 16 15 603

FB_S

FB_S
are for reference only, are for reference only,
12
R623
9 1 +12V_BUS 1 2 VDDC_LGATE_1_1
tuning is required 12 tuning is required
1
VDDC_LGATE_2 2 VDDC_LGATE2_CTR
12
12V Bus power for 12V Gate Drive

11 0R 0R
14
2

1% Route like differential pair Route like differential pair

3

10K/X

R624
R661

12

12
VDDC_LGATE_2_2 1 2

12

12

12
1

0R
Q661 +VDDC
1

SI2304DS 1
R670
0R

BAT54KFILM/X
12 +VDDC
2

Optional D611
2 1
Optional

1
Rdroop
C649 C650 C646 C647 C658 C661 C648 C656 C659 C679
0.1uF 0.015uF 10uF 10uF/X 0.1uF 0.015uF/X 10uF/X 10uF 10uF/X 10uF/X
2

402 402 402 402

1% 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V

2
2

100K/X
C670 R664
10UF R632 C694
GND GND GND GND GND GND GND GND GND GND
0R/X

1
12

12
1

2R686 0R/X
1 VCCDRV
1uF

12
BOOT2
2
16V

OUT

IN

Output MLCC Output MLCC

VDDC_EN 2R685 0R
1 SS_ICOMP
C612

16 12
2

2R684 0R/X
1 VDDC_REFIN
16 12 +VDDC
1

D601
VDDC_POK

Optional
0.47UF
VDDC_LGATE2_CTR
VCCDRV

VDDC_PHASE_2
VCC

BAT54KFILM/X VDDC PWM WHOLE CHIP ENABLE

VDDC_REFIN
VDDC_UGATE2_CTR

VDDC_LGATE1_CTR 12 +VDDC
12 THE RESISTERS SHARE PAD
1

12

C602 VDDC_PHASE_1
12 12
1 2

1
24

23

22

21

20

19

0.47UF
16V + + + +
C641 C642 C643 C644
820uF 820uF 820uF 820uF
PHASE1

PHASE2
LGATE1

VCC

LGATE2
VCCDRV

R634 2.5V 2.5V 2.5V 2.5V

2.2K
6.3 x 9 mm, TH 6.3 x 9 mm, TH 6.3 x 9 mm, TH 6.3 x 9 mm, TH
1%

2
R636

1%
PGD 2

1K/X

12
VDDC_UGATE1_CTR 1 UGATE1 U601 UGATE2 18 1 2 5VCC
12 15 GND GND GND
uP1610PQAG
BOOT1 2 BOOT1 BOOT2 17 Overlap the footprints for MR655 and C655
0R/X
C660 2 1
MR655
2 1 3 5VCC POK 16 C654
R654 5% Output Bulk CAPs
6.3V 1 2
0.0022uF/X 2 1
此電電此此此PWM 150R/X
1uF 4 AGND REFIN 15 50V
C655 +VDDC
0R/X
5VCC
1 2 5 MODE 12
SS/EN 14 SS_ICOMP 1 15NF2
OUT
MR610

25V
1

R610
6 CSP1 FB 13 VDDC_FB
IN
SHARE PAD NS600
2
0R

0R/X
PIN5 PH2 EN PGND1 25 50V 2 1 FB_S
12
220pF/X R658
-HI, PH 2 DISABLE,PH1 ENABLED; PGND2 26 C607 C3 NS_VIA/X
2

-LO, PH 1 AND PH 2 ENABLED. PGND3 27 1 R653 2 2 C653 1

1.87K 2.2NF
28
COMP

R3
CSN1

CSN2

PGND4
CSP2

1
IOUT

RT

R651
GND
10K
1 2 1% VDDC_SV 2 R600 1 VDDC_ASIC_FB +VDDC
7

10

11

12
1 CSN1
CSP1

0R
RFB1
1

603
CSN2

CSP2

R656
1

0R
2 1 Reserve for C601
Loop Measurement 0.1uF/X
R605 R615 R662 C638 6.3V
Rdroop

665R 665R 0R 0.1uF/X GND

1% 1% 1% 6.3V C1 R652
2

2
12.1K
1 C6522 2 1 2 R657 1 5%
2

3.3NF 0R/X 300R

C604 C614 R1 R696
2 1 2 1 R656, R657 SHARE PAD
1

1
16V

16V

C651 1 2
1
56PF
R655 R663 C2
51.1K/X 100K/X
Close to U601 1% 1% Type III Compensation
1

2
0.1uF

0.1uF

6.3V Rdroop option

2

2
1

0.1uF
C605 C615
0.1uF
R604 6.3V R614 +VDDC LOAD
12.1K 12.1K
1%
2

1%
Choosing Different Gate Drive
2

CCSP2
12 5V Gate Drive
Populate R631,R632 and Do Not Populate R630,R670,C660,R661,Q661
CCSN2
12
8V Gate Drive
CCSN1
12 Populate R630, C660, R661,Q661, and Do Not Populate R631,R632,R670

CCSP1
12 12V Gate Drive
Popualte R630,C660,R670, and Do Not Populate R631,R632,R661,Q661

Title
GIGABYTE
Power Supply III: VDDC
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 12 of 20
 +MVDD_Source

+12V_BUS
VDDCI_EN
IN
1

C906 +VDDCI

1
0.15uF/X
16V
2

C915 C916 C917 C919 C933

2

5
6
7
8
Q605 10UF 10UF 4.7uF 4.7uF 0.15uF
BAT54KFILM/X 16V 16V 16V
D901 Type III Compensation

2
13 VDDCI_PHASE
C905
1

Thermal
1 2 R912

Pad
C911
R909
0.1uF
16V
1 2 2 1 2 1 NS900
10NF 8.25K 0R R714,R709
10V share pad
VDDCI_BOOT U901 C912 NS_VIA/X 此Input MLCC電電電電電電PCB T& B，并并并并并并并電
1 BOOT PHASE 8 1 2 C913 Sense Point NTMFS4921N/N/6.95m/PPAKSO8

4
3
2
1
2

100PF 1 R913 2 2 1 VDDCI_UGATE_CTR

50V +VDDCI
這這個MLCC用料此此此PWM R901
13
VDDCI_UGATE_CTR 2 UGATE COMP/EN 7 R914
0R 470PF
16V 13 1 2
0R/X 0R

1 R905 2 3 6 1 2 2 R900 1
OSC FB 603 L901
1

0R 10K 0R VDDCI_PHASE
13 0.8UH/30A/HNC109/F/D
VDDCI_LGATE_CTR 4 5
VDDCI_VCC R911
13 LGATE VCC Reserve for
1

RFB1
Loop Measurement
1

R907
R915 9 GND1 GND4 12 2 1
5.9K 10 GND2 GND3 11 C903
2.2R

9
5
6
7
8

1
0.22uF 805
Q903
2

25V

1
此電電此此此PWM 805
VDDCI_FB
C929 C930
OUT
2

uP1529QSU8 + 10UF/X 10UF/X

+12V_BUS R919 C925 6.3V 6.3V
1R 820uF

2
2.5V

1 2

2
NTMFS4935N/N/3.2mm/PPAKSO8 C908

4
3
2
1
1.5NF
25V

2
VDDCI_LGATE_CTR
R903
13 1 2
0R

+VDDCI

2
C923 C924 C920
0.1uF/X 0.015uF/X 390pF/X
10V 10V 50V

1
Title
GIGABYTE
Power Supply III: VDDCI
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 13 of 20
 +12V_BUS

+MVDD_Source

2
L702
B702 B703 0.47uH
60/1206/6A/S/X60/1206/6A/S/X

1
1

1
C730
C717 C719 C718 C720 +

5
6
7
8
Q701 C715 C716 4.7uF 4.7uF 0.1uF 0.1uF
16V 16V 16V 16V
10UF 10UF 100UF

2
Thermal
Pad
此Input MLCC電電電電電電PCB T& B，并并并并并并并電
NTMFS4921N/N/6.95m/PPAKSO8 +MVDD

4
3
2
1
R701
14
MVDD_UGATE_CTR 1 2 MVDD_UGATE 14 10 +MVDD
0R

L701
MVDD_PHASE 1.0uH
14
+12V_BUS

+12V_BUS
2011.12.20 修修H-L side & Chock
17 16 15 14 12 11 9 1
1

9
5
6
7
8

1
Q703

1
MVDD_EN
C706 IN C723 C724
0.15uF/X + + 10UF/X 10UF/X
16V R719 C726 C729 6.3V 6.3V
2

1R 820uF 820uF/X
+MVDD
2

2
D701 2.5V 2.5V

1 2

2
BAT54KFILM/X
Type III Compensation 14 10 +MVDD
1

14 1 2
C705
MVDD_PHASE MVDD_PHASE
C711 NTMFS4935N/N/3.2mm/PPAKSO8 C708

4
3
2
1
0.1uF
16V
1 2 2 R712 1 2 R7091
1NF
25V
4.7NF 12K 0R R714,R709
NS700

2
10V share pad
U701 NS_VIA/X R703
MVDD_BOOT 1 BOOT PHASE 8 1 2
C712 R713 C713 Sense Point 14
MVDD_LGATE_CTR 1 2 MVDD_LGATE
2

68PF
50V
1 2 2 1 0R

14
MVDD_UGATE_CTR 2 UGATE COMP/EN 7 這這個MLCC用料此此此PWM
R714
820PF
16V
0R/X 0R MVDD_FB_TRACE
R711 +MVDD
R705
1 2 3 OSC FB 6 MVDD_FB 1 2 MVDD_SV 6032 R7001
1

0R 10K 0R 14 10 +MVDD
14 MVDD_LGATE_CTR 4 LGATE VCC 5 Reserve for
1

MVDD_VCC RFB1
Loop Measurement
1

2
R7071
R715 9 GND1 GND4 12 2
5.9K 10 GND2 GND3 11 C703
2.2R
C725 C727 C728
0.22uF 805 0.1uF/X 0.015uF/X 390pF/X
2

25V 10V 10V 50V

uP1529QSU8
603 +12V_BUS OUT
2

1
11 9
14 12
此電電此此此PWM17 16 +12V_BUS

Title
GIGABYTE
Power Supply III: MVDD
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Monday, January 02, 2012 Sheet 14 of 20
 Linear Regulators
LDO #1: Vin = 3.00V to 3.60V (3.3V +/- 9%) Vout = +1.8V +/- 2%; Iout = 1.6A (TBV) RMS MAX

PCB: 50 to 70mm sq. copper area for cooling

Regulators for +5V, +5V_VESA and +5V_VESA2

+3.3V_BUS

18 17 16 15 9 1 +3.3V_BUS

+12V_BUS

17 16 14 12 11 9 1 +12V_BUS
1 R8702
3.6R/X
1 R8712
0R
1 R8722
3.6R/X
1 R8732 100mA
3.6R/X
+5V_VESA

9 +5V_VESA
1 2
MR870 NA
3.3R/X U400 F400
1 2
MR871 1 IN OUT 3 1 2
3.3R/X
1/2W@1210

1
1 2 1.8V WORST-CASE REQUIREMENT
MR872

GND

TAB
1/2W 1% 3.3R/X
C410 C411
1.5W dissipated in resistors 1 2
MR873
1uF MC78M05CDT 1uF

4
Est. Current 16V 6.3V
3.3R/X
Display Config 0603

2
16V

DVI+HDMI+DP 1330mA

1/4W@1206 +5V
+3.3V_BUS
18 17 16 15 9+3.3V_BUS
1
1

+1.8V
MR451
C866 +1.8V
1 20R/X
17 10 9 7
10uF
6.3V
1

+5V
2

R862 R863
10K 10K/X

1
2

LDO1_VIN U681 R865 C865 C862 C861 C864

OUT
+1.8V_LDO_POK 1 8 13K
R5
33pF
50V
10uF
6.3V
10uF/X
6.3V
0.1uF
16V
+1.8V_EN 2 POK GND#8 7 LDO1_FB 1%
DNI
IN

2
3 EN FB 6
4 VIN VOUT 5 LDO1_REFIN R4
CNTL NC
1

1
9
GND#9
C868 R864
1uF 1%
10K
6.3V uP0104PSU8/SOP8/3A
2

2
VOUT = Vref x (1 + R5/R4)

1 R8662
0R/X

+12V_BUS +5V
1

R450
360R/X
2

R451
1 20R 5VCC
IN
BZT52C5V1
D450

Title
GIGABYTE
Power Supply III: Linear Regulators
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 15 of 20
 Power Management - Power Gating and Dynamic Voltage Control Then this will set VDDC to a fixed value.
- Hi-Side Divider R651 is Fixed to 5.11K
- Vo = Vref * (1 + R651 / R650 )
12V_BUS & 3V3_BUS POWER SEQUENCING
VDDC Low Side Divider - Vref = 0.6V

+3.3V_BUS +12V_BUS +12V_BUS

VDDC_FB
IN
17 15 9 1 +3.3V_BUS 15 14 12 11 9 1 +12V_BUS 12 11 9 1 +12V_BUS

1
18 17 16 17 16 15 14

1
+3.3V_BUS R671 R672

2
Node 1
+1.8V_EN 20K/X 20K/X
R857 OUT R678 R676
20K/X 20K/X
+3.3V_BUS

2
2
10K VDD_FB_IN1

2
1

1
R840
R852 +3.3V_BUS R673 VDDC_FB_IN2

3
R850
PSEQ_N1 2 1 1 Q852
20K/X
R650
2.32K 11.3K 5.1K 20K/X
MMBT3904

1
3

1
RFB2
PSEQ_N3 Q606
2

2
1
402
1 Q850 Place close C681 IN
GPIO_15_VID0 1 2N7002E

1
Node 3 MMBT3904 to its CTLR 0.1uF
C846 10V +3.3V_BUS

2
0.1uF/X
R688

2
10V
U680 3.24K
MR673

2
1%

2
1 VCC VID0 8 GPIO_15_VID0
5
16
20K/X

2
3

3
R689
2 GND VID1 7 GPIO_20_VID1
5 16 R674

1
PSEQ_N2 1 Q851 IN
SCL 3 SCL VREF 6 VDDC_REF 1 2 VDDC_REFIN
OUT
20K/X

Node 2 MMBT3904
BI
SDA 4 SDA R1 5 0R
Q607

1
1

1
IN
GPIO_20_VID1 1 2N7002E

2
1

1
R851 uP1801AMT8 C680
1K 0.033uF
R853 R687

2
16V

2
1K 5.49K
2

2
1%
MR674
2

2
20K/X

1
+3.3V_BUS

2
R675

3
20K/X
+12V_BUS

1
Q608

IN
GPIO_30_VID2 1 2N7002E
1

2
+1.8V

2
R832 MR675
+1V_EN 20K/X
5.1K OUT
+3.3V_BUS
2

1
3
R831
1 2 1 Q839
1

5.1K MMBT3904
BACO R677

2
R855

3
1K
20K/X
2

VDDC_EN
OUT Q609

1
+1.8V_LDO_POK R845
IN
2 1 1 Q841 IN
GPIO_29_VID3 1 2N7002E
5.1K MMBT3904
VDDC_EN
OUT
2

2
1

2
3 MR677

3
R876 DNI
IN
CTF_PWROFF_B 1 2 C848
0.1uF 2 R838 1 1 PX_EN R1027 10K 1 20K/X
0R/X 5% 10V Q1 IN Q1014
1

5.1K MMBT3904 MMBT3904

2

1
1

2
R856
2

2
1K/X
C839 R1030
0.1uF/X 10K/X
2

10V
DNI
2

1
PSEQ_N3 MVDD Low Side Divider
R875
1 2 17
MVDD_FB
OUT
0R 5%

1
DNI - Hi-Side Divider RFB1 is Fixed to 10K

R874 - Vo = Vref * (1 + RFB1 / RFB2 )

1 2 +1.8V_EN
- Vref = 0.8V R710
6.65K
0R/X 5%
402

2
RFB2

POWER SEQUENCING CIRCUIT

+1V Low Side Divider

+1V_FB
+12V_BUS OUT
17 16 15 14 12 11 9 1 +12V_BUS

1
- Hi-Side Divider RFB1 is Fixed to 10K
- Vo = Vref * (1 + RFB1 / RFB2 )
MVDD_EN
OUT - Vref = 0.8V R830
16.9K
+3.3V_BUS
2

402

2
RFB2
R843
5.1K

+VDDCI
1

PSEQ_MVDD_EN
R846 +VDDC
DNI
PWR_ENABLE# 2 1 1 Q842
2

5.1K
R841 MMBT3904
2
3

5.1K
B629 +3.3V_BUS
1 2 VDDCI_FB
OUT
1

Q840 60R_6A/X

1
IN
VDDC_POK 1 2
R1693 1 2N7002E VDDCI_EN
OUT

1
1K
B639 R951

2
1 2 R952
120K
R950
2

60R_6A/X 20K

2
1

R847 402
2 1 1 Q843
10K/X

2
1

5.1K RFB2
C841 MMBT3904

3
1uF/X
C840
2

6.3V
0.1uF/X
2

10V
Q955
2

IN
GPIO_7_VDDCI_VID 1 2N7002E

2
2
R953

10K

1
VDDCI Low Side Divider

Title
GIGABYTE
Power Supply III: PWR MGMT & SEQ
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 16 of 20
 For 2-WIRE FAN ONLY +12V_BUS

17 16 15 14 12 11 9 1 +12V_BUS

Fan Control
Mechanical and Thermal Management +12V_BUS
+12V_BUS
+1.8V
U1O 17 16 15 14 12 11 9 1 +12V_BUS
15 10 9 7 +1.8V

1
PART 15 OF 15

1
AJ32 TSVDD DPLUS AF29 GPU_DPLUS
OUT C4008

1
1uF
R4105 16V
1K 0805
C4020 C4004

2
1
1uF AJ33 TSVSS DMINUS AG29 0.0022uF GPU_DMINUS
OUT 16V

2
6.3V 50V

1
R4102

2
3K
+3.3V_BUS +12V_BUS C4106

TSS FDO
1uF

2
16V
15 14 12 11 9 1 +12V_BUS J4001

2
2

2
17
PWM_B 16 1
MMBT3906

1
PFB 1 1 1
NFB 2
R4107 2

1
820R
R4100 Q4102

1
20K/X MMBT3906 HDR_1X2
R4112

3
3

1
5.1K/X DNI
Q4101 R4108

2
R4101
GPIO28_FDO AK32 TS_FDO_ASIC 1 2 TS_FDO 1 Q4100
1M/X
C4104 R4110
BU ONLY

2
DNI 1uF 0R/X
20K D4100

2
16V

3
MMBT3904
DNI BAT54KFILM/X

2
NA R4409 1 Q4501

1
20K/X 2N7002E FANOUT_N
OUT

2
3

2
4
Warning: TS_FDO is not 5V tolerant. MAX sink current 1.65mA R4517
1
R4500 2
20K 1 1 2
20K 1 Q4510 R4113 R4501

IN 5% Q4500 5%
6.8K/X 100K
5%
VDIFF 1 Q4103 Add Copper under pad 4
MMBT3904 MMBT3904 PBSS4350Z (at least 1cm^2)

1
1R4514 2
20K/X

3
1
DNI
If Critical Temperature is reached this will force the fan to run at full 5% C4102
speed while power is removed from GPU & rest of the board. 1uF
6.3V R4106

1
This is an open collector signal. Active level is hard pull down to ground. 1K

2
overlap

2
footprints for

IN
PERST#_BUF 3 D1720 D4101 and
PX_EN MD4101
2 16 17
BAT54S

3
Critial Temperature Fault

2
2R4057 20K 1 PWM_ENB 1 Q4011
MMBT3904

2
1
C4402 R4063

1
100K/X
0.1uF/X 1uF

2
16V

2
C4501
1%

1R4103 2
10K

1
Place close to its CTLR R4111 C4100
1K/X 0.1uF
16V R4109
1% 1M/X

2
CTF_PWROFF_B DNI
CTF2: R4051=20K, R4053 DNI, C4401=0.1UF;
OUT

2
D4500

3
1N4148W
2 1
R4051
CTF_PWROFF 1 Q4010
20K MMBT3904

1
1
DNI

2
1
1 2
R4062 17 CTF_BYPASS
R4053
0R/X 100K/X
C4401
0.1uF

2
16V

2
+3.3V_BUS
18 16 15 9 1 +3.3V_BUS
1

+3.3V_BUS
R4407
20K/X +3.3V_BUS
2

DNI Q4502
2

MMBT3906

1
Q4400 1 CTF2_GAT MMBT3906

8
7
C4500
PX_EN1 R45122 DNI
IN
1 R4502 0.1uF
U4500
3

20K 10K 2 5

PR
Vcc
17 D Q

2
5%
Critial Temperature Fault

2
1

1 C Q 3 1
R4509 2
1M

CL
5%

G
R4404 R4405
2

1
20K 20K
Q4503 C4507
NC7SZ74K8X
R4408 1 R4503
2

4
6

1
MMBT3904
33K/X 0.1uF
R4038 5% DNI 16V
TCRIT 1 2 C4502
1K

IN +12V_BUS
1

2
0R/X 10uF
6.3V
3

PERST#_BUF

2
1
IN
GPIO_19_CTF 1 R4400 4.7K
2 CTF2_RESET 47K
2 R44021 CTF2_TRIP 1 Q4401

1
MMBT3904 R4515
100K
R4516
2

5%
1

20K

3
R4403 C4400 Q4509

3
3 D4400
100K 0.01uF
10V
1

MMBT3904
1 Q4508
2

BAT54S 1uF 2N7002E

2
2

2
2
C4506
PERST#_BUF
IN

SK1

PCB1 For DVI Connector

AMD
PCB

PCB(109-C44557-00)
ASSY-SCREW200 ASSY-SCREW201
ASSY-SCREW202
6090034500G
SCREW

Socket 6090034500G

7020000800G 7020000800G 7020001700G 7121000100G

HS1C HS1D HS1A Rectangular Heatsink 8W
80200515A0G HS1B
Bracket VGA DP DVI
Bracket Components

Bracket 80200515C0G DP DP DVI

80200515C0G 80200515B0G 8020051500G 80200515A0G
BK1 BK2 BK3 BK4

Bracket 8020051500G VGA HDMI DVI BRACKET BRACKET BRACKET BRACKET 17 25 24 32

9 16
18
19
20
21
22
23

26
27
28
29
30
31
10
11
12
13
14
15

80200515B0G
Bracket DP HDMI DVI
1
2
3
4
5
6
7
8

7121000100G
Fansink 7122000100G

7120781200G
For 75W board

Title
GIGABYTE
Power Supply III: Mech_Thermal Management
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 17 of 20
(19) Debug Circuits

JTAG

+3.3V_BUS
U1A
18 17 16 15 9 1 +3.3V_BUS
+3.3V_BUS
PART 1 OF 15

18
TESTEN AD28 TESTEN 9 1 +3.3V_BUS
JTAG_SOCKET_8 18 17 16 15
18
JTAG_TRSTB AM23 JTAG_TRSTB
18
JTAG_TCK AK23 JTAG_TCK 18
JTAG_TDO 7 8

1
JTAG_TDI AN23 JTAG_TDI 5 6
JTAG

18 JTAG_TDI 18
18
JTAG_TDO AM24 JTAG_TDO 18
JTAG_TMS 3 4 R436
18
JTAG_TMS AL24 JTAG_TMS 18
JTAG_TCK 1 2 1K/X
DNI

2
18 TESTEN
J4004
NA

1
+3.3V_BUS
R437
18
JTAG_TRSTB 2 R38 1 +3.3V_BUS
1K
15
9
1
18
17
16
1K

2
1
R39
1K/X
DNI

2
JTAG_TRSTB

engineering board pull high

production board pull down

+3.3V_BUS
LM96163 FOR BACKUP THERMAL CONTROL
18 17 16 15 9 1 +3.3V_BUS

+3.3V_BUS
1

1
18 17 16 15 9 1 +3.3V_BUS
C4003 C4002
100pF/X 1uF/X
50V 6.3V
2

2
1

R4011
10K/X
2

U4001

IN
SCL 1 2
R4001
SCL_R
SMBCLK 10 TCRIT 1 TCRIT
OUT
100R/X

BI
SDA 1 2
R4002
SDA_R
SMBDAT 9 VDD 2
100R/X

TACH 8 3 GPU_DPLUS
D+ IN

OUT
GPIO_17_THERMINT 1 2
R4080
THERMINT
ALERT 7 D- 4 GPU_DMINUS
IN DNI
0R/X

GND6 5 1 2
LM63_PWM TS_FDO
PWN R4081 OUT
33R/X

THMPAD 11

LM96163CISD/X

Title
GIGABYTE
Power Supply III: Debug Circuit
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 18 of 20
 MEMORY CHANNEL A & B

Debug
GDDR5 4pcs 64Mx32 (1GB)

CH A AC Coupling Caps

TMDP-D

DDC2
DisplayPort

HPD4
Connector

JTAG/I2C
GPIO

POWER REGULATORS Overlap

From +12V VGA

OPTIONAL Header

+VDDC RGB Filters

+MVDD

FAN
DDC2

From +12V LINEAR:

ROM
Straps
+5V_VESA, +5V_VESA2

From SMPS: SL TMDS HDMI

TMDP-D AC Coupling Caps Connector

+5V BIOS

From +MVDDQ Linear: 5V_VESA

Thermal

PCIE_VDDC, DPLL_VDDC, DDC6 AUXDDC5

Speed control
DPx_VDD10, SPV10, MEM_VREF
DisplayPort
GPIO17
& temperature
INTERRUPT HPD1 Connector

OPTIONAL
From +3.3V Direct:
sense D+/D-

VDDR3, A2VDD
FAN Temp. Sensing

TS_FDO
Built-in PWM
From 3.3V Linear (1.8V)

Overlap

PCIE_PVDD, PCIE_VDDR, VDDR4,

Dynamic Power Management

DPLL_PVDD, SPV18, MPV18, DL TMDS

VDD1DI, VDD2DI, AVDD, AVDDQ, AC Coupling Caps DVI-I

TMDPEF

DPx_PVDD, DPx_VDD18, VDD_CT,

POWER DELIVERY
TSVDD

DAC1 Connector
RGB Filters

Cedar AUXDDC4

HPD4 5V_VESA

100MHz

XO_IN2
27MHz

XO_IN Clock

Temperature Critical
CTF XTALIN

PCI-Express Xtal
Power Sequencing
Circuit

CAPEVERDE GDDR5 1GB

+3.3V_BUS VGA/DP HDMI/DP dDVI-I
+12V_BUS

PCI-Express Bus

Title
GIGABYTE
Power Supply III: BLOCK DIAGRAM
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 19 of 20
 DATE
TITLE SCHEMATIC NO.

CAPE VERDE PRO GDDR5 64Mx32 dDVI-I+HDMI/DP+DP/VGA

105-C445XX-00

NOTE: REV
THIS SCHEMATIC REPRESENTS THE PCB, IT DOES NOT REPRESENT ANY SPECIFIC SKU.
REVISION HISTORY
FOR STUFFING OPTIONS (COMPONENT VALUES, DNI PLEASE CONSULT THE PRODUCT SPECIFIC BOM.

PLEASE CONTACT AMD REPRESENTATIVE TO OBTAIN LASTEST BOM CLOSEST TO THE APPLICATION DESIRED. P04

SCH PCB
DATE REVISION DESCRIPTION
REV REV

00 00A 2011/07/11 Initial CAPE VERDE schematic,

1.Update bracket DP HDMI DVI to 80200515B0G;

2. Add C4401/C4402
01 00B 2011/08/23 3. wire GPIO15/GPIO20 to I2C DAC

4. remove BIF_VDDC

1. add BACO fan delay circuit;

2. Update 1.8V LDO symbol to GS7103;

02 00C 2011/09/27
3. Remove some debug circuit;

03 00D 2011/11/15 1. update BACO fan delay circuit;

04 00 2011/11/28 1. update CTF to shut off 1.8v;

Title
GIGABYTE
Power Supply III: HISTORY
Size Document Number Rev
Custom
GV-R775D5-1GI 0.1
Date: Tuesday, December 27, 2011 Sheet 20 of 20