Paul A.

Bohn

Prof. Miriam Leeser

ECE U530 Digital Hardware Synthesis

17 October 2006

Project Proposal
Description:
The purpose of this design is to develop a time keeping alarm clock and implement it on
a Spartan-3 FPGA development board.

Plan:
The core design of this project consists of the implementation of a basic digital clock. A
user should be able to set the clock by holding down the clock set button, and
incrementing the appropriate hour/minute buttons. The first phase of this project will be
accelerated by making use of some existing code available at the Xilinx website. The
Xilinx code is attached to this proposal.

More advanced features will be implemented as time permits.

List of features to be implemented: (ordered in increasing complexity)

1. 7-seg display
2. base 60 counter output to 7-seg display
3. 24 hour time roll over
4. Maybe A.M. P.M. time (12 hour roll over)
5. Clock setting functionality
6. Alarm clock features
a. Alarm time set
b. Alarm indicating LED/Sound output
7. special alarm clock feature making use of a random number generator
Inputs and Outputs:
Entity:
entity clock is port (
clk50in : in std_logic ; -- 50 Mhz XTAL
pb_in : in std_logic_vector(3 downto 0); -- 4 pushbuttons
inputs
sw_in : in std_logic_vector(7 downto 0); -- 8 switch inputs
digit_out : out std_logic_vector(3 downto 0); -- digit drivers
led_out : out std_logic_vector(7 downto 0); -- 8 LEDs
seg_out : out std_logic_vector(7 downto 0)); -- segment drivers
end clock ;

Deadlines:

Date Task

October 30 Acquire a firm understanding of Xilinx basic clock code

November 6 Change code to perform 24 hour roll over and display hh::mm time

November 8 Progress Report

November 19 Finish clock setting functionality

November 20 Preliminary Project Report

November 30 Finish alarm setting feature

December 12 Finish alarm indicator (Sound / LED )

December 13 Final Project Report