S. D. M.

College of Engineering and Technology, Dharwad – 580 002

Department of Electronics and Communication Engineering
Internal Assessment-I

Semester: VIII Date: 10/04/2021

Course Code & Title: 15UECE872- GPU Computing Max. Marks: 20
Course Instructor: Mr. Sunil S. Mathad Time: 10:00 to 11.00AM

Note: Q3 is Compulsory answer any one from Q1 and Q2

.
Q1(a) Bring out the fundamental differences in design philosophies of CPU and GPU. (5M)
Q1(b With appropriate example show memory as a limiting factor to parallelism. (5M)
)
OR
Q2(a) Brief about compilation and execution of a CUDA program. (5M)
Q2(b With an example explain CUDA grid organization. (5M)
)

Q3(a) Elaborate upon synchronization and transparent scalability in CUDA GPUs. (5M)
Q3(b Write a CUDA code to add two matrices of the order N; involving kernel (5M)
) definition and launch of kernel from the host code.

Q. No. 1a 1b 2a 2b 3a 3b

CO 1 1,2 2 1,2 1,2 2,3

Approved by IQAC
Ch1

1. What is Heterogeneous parallel computing?

2. Bring out the fundamental differences in design philosophies of CPU and GPU.

3. With a neat sketch explain the architecture of CUDA capable GPU. (state the typical
values such as computation capability, Memory, Memory bandwidth etc)

4. Write a short note on Parallel Programming Languages and Models.

Ch2

1. With a neat sketch fixed function NVIDIA GeForce graphics pipeline.

2. Give an account of separate vertex processor and fragment processor in a programmable

graphics pipeline.

Ch3.

1. Differentiate between task level parallelism and data level parallelism.

2. Brief about compilation and execution of a CUDA program.

3. List and explain any three CUDA APIs for managing device global memory.

4. With an example brief about error handling in CUDA.

5. Write a CUDA code to add two matrices of the order N; involving kernel definition and
launch of kernel from the host code.

Ch4.

1. With an example explain CUDA grid organization.

2. Elaborate upon synchronization and transparent scalability in CUDA GPUs.

Ch5

1. Give an overview of CUDA device Memory model along with CUDA device memory
types.

2. Explain the working of tile matrix multiplication kernel using shared memory along with
code.

3. With appropriate example show memory as a limiting factor to parallelism.

4.