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• Boolean Algebra
• Logic Functions Representation
• Logic Gates
• Logic Functions Minimization
• Combinational Circuits
• Sequential Circuits
Logic Functions
zi = Fi(x0,x1,x2, …) | zi {0,1}, i = 0,1,2, … m-1, xk {0,1}, k = 0,1,2, …n-1
where Fi = logic functions ; xk = input variables; zi = output variables
where Logic 0 = FALSE and Logic 1 = TRUE
Logic function F
x0 Block diagram
x Logic z
1
Circuit
x2
F(x0,x1,x2,x3)
Logic Functions
Logic Inverter
can be represented by
1. truth tables,
Logic function F 2. logic (Boolean) expressions,
3. logic diagrams (schematics) of the logic
xz circuits that implement these functions.
0 1 4. K-maps – later!
1 0 x Time diagrams
(functional simulation)
VHi ≈ +5V =
TRUE = Logic 1
z=x
x U1A VLo ≈ 0V = t
1 2
FALSE = Logic 0 0 10 20 30 40 50[ns]
z z (Ideal) time diagram
7404
1
0 0 10 20 30 40 50 t
[ns]
Realistic Time Diagrams
Approximations of Real Time-Diagrams
x
VHi ≈ +5V =
TRUE = Logic 1
Propagation Delay
VLo ≈ 0V =
t
Logic Inverter FALSE = Logic 0
0 10 20 30 40 50 [ns]
U1A
z
x z 1
1 2
7404 0 t
z=x 0 10 20
td propagation delay
30 40 50 [ns]
x z
0 1
1 0
Realistic Time Diagrams
Approximations of Real Time-Diagrams
x
1
50%
1 7404 2 10% 0
Rise
50%
z=
t
20 30 t 6 40 50 [ns]
x 10 f
0 tr
td rise time fall time
delay
x z
0 1
1 0
Boolean Algebra over {0, 1}
• ,=,+,., ,0,1
• NOT:
Boolean Axioms
Property OR AND
Closeness a + b = c → c ε {0,1} a . b = c → c ε {0,1}
Identity a+0=a a.1=a
0 is identity for OR 1 is identity for AND
Commutative a+b=b+a a.B=b.a
Distributive a+(bc) = (a+b) (a+c) a (b + c) = ab + ac
Complement a+a=1 aa=0
Associative (a + b) + c = a + (b + c) (a b) c = a (b c)
Boolean Theorems
Null + = . =
Theorem OR AND
Absorption +1=1 .0= 0
Idempotency + . = . + =
+ . = + . + = .
Uniting . + . = + . =
Consensus +
. + . + . +.+. .c
Factoring = +( . ) . = a+b.( . )
+ . + . + .
= . +( . ) = + .( + )
De Morgan’s Theorems
– Using . + . + .
identity LHS =
. + ( + ) . + .
– Using distributive LHS =
– Regrouping LHS = . . + . . + . . + .
+ .
.
– Using distributive LHS = + (. . )+ (. . )+ .
. .
RHS
OR rules (identities)
(1) 0+X=X XYZ . .
(3) 1+X=1
X+Y Z (X+Y) (X+Z)
_____________________________________________________________________
(5) X+X=X
(7) X+X=1 0 0 0 0 0
(17) (X)=X 0 0 1 0 0
0 1 0 0 0
(9) X+Y=Y+X 0 1 1 1 1
(11) X+(Y+Z)=(X+Y)+Z
(14) . . 1 0 0 1 1
X + Y Z = (X+Y) (X+Z)
1 0 1 1 1
(15) X+Y=X.Y 1 1 0 1 1
1 1 1 1 1
Proving DeMorgan’s Theorem
aba
baba
a b a . b a + b a +b .
b a b
_______________________________
0 0 1 1 1 1
0 1 0 0 1 1
. 1 0 0 0 1 1
a+b=a b
1 1 0 0 0 0
.
a b=a+b
can be generalized:
x1 x2 xn x1 x2 xn
x1 x2 xn x1 x2 xn
All Logic Functions of Two Variables
x F Map 1st
y row to 23
1 1 1 1
0 1 00 00 10 10 01 01
0 0 0 0 0 1 1 1 1 0 0 0 0
0 1 1 0 0 0 0 1 1 1 1
1
1 0 0 0
1 1 0
1 1 0 0 1 1 0
0
0
1
1
1
1
0
0
0 1 1
11 11 00 11 00 11 00 11 00 11 0 1 0 1 0 1 0 1
0 X Y X xor Y
not Y not X 1 Map last
X and Y
X=Y X nand Y Row to 20
(m0) 0 0 0 0
(m1) 0 0 1 0
(m2) 0 1 0 1
(m3) 0 1 1 1
F (m4) 1 0 0 0
(m5) 1 0 1 1
(m6) 1 1 0 0
(m7) 1 1 1 1
Karnaugh Maps
C
AB C D F
AB CD 00 01 11 10
0 0 1 3 2
() 0 0 0 0 ... 00
1
() 0 0 0 1 ... 4 5 7 6
2
() 0 0 1 0 ... 01
3 B
() 0 0 1 1 ... 11 12 13 15 14
4
read as binary values with A =
() 0 1 0 0 ... A 10 8 9 11 10
5
() 0 1 0 1 ...
6
() 0 1 1 0 ... D
7
() 0 1 1 1 …
8
() 1
9
0 0 0 … The minterms are listed by an
() 1 0 0 1 …
10
( )1 0 1 0 … equivalent decimal number for
11
( )1 0 1 1 … easy reference
12
( )1 1 0 0 …
13
( )1 1 0 1 …
14 1 1 0 …
( )1
(15)1 1 1 1 ...
Karnaugh Maps – 5 Variables
(0) 0 0 0 0 0
a b c d e Y
(1) 0 0 0 0 1
The 2 K-maps are obtain ed from the 2 0 0 0 1 0
()
cd e (7) 0 0 1 1 1
00 0 1 3 2 4 5 7 6 (9) 0 1 0 0 1
01 8 9 11 10 12 13 15 14 (10) 0 1 0 1 0
(11) 0 1 0 1 1
11 24 25 27 26 28 29 31 30 (12) 0 1 1 0 0
16 17 19 18 20 21 23 22 (13) 0 1 1 0 1
10 (14) 0 1 1 1 0
de 00 01 11 10 (15) 0 1 1 1 1
(16) 1 0 0 0 0
cd e 000 001 011 010 100 101 111 110 0 1 3 2 (17) 1 0 0 0 1
ab (18) 1 0 0 1 0
00 0 1 3 2 8 9 11 10
6 7 5 4 c=0 (19)
(20)
1 0 0 1 1
8 9 11 10 24 25 27 26 1 0 1 0 0
14 15 13 12
01 (21) 1 0 1 0 1
11 24 25 27 26 30 31 29 28 16 17 19 18 (22) 1 0 1 1 0
(23) 1 0 1 1 1
10 16 17 19 18 22 23 21 20 (24) 1 1 0 0 0
de 00 01 11 10 (25) 1 1 0 0 1
(26) 1 1 0 1 0
ab (27) 1 1 0 1 1
00 4 5 7 6 (28) 1 1 1 0 0
01 12 13 15 14
c=1 (29)
(30)
1
1
1
1 1
1 0
1 0
1
11 28 29 31 30 (31) 1 1 1 1 1
10 20 21 23 22 (logic) adjacent cells
Karnaugh Maps – 6 Variables
def 100 101 111 110
abc
100 36 37 39 38
def 000 101 44 45 47 46
abc 001
100 32 33 35 34 63 62
def 101 40 41 43 42 55 54
abc 100 001
000 4 5 7 6 59 58
abc def 001 12 13 15 14 51 50
000 001
000 0 1 3 2 31 30
abc 101 40 41 43 42 44 45 47 46
011 24 25 27 26 28 29 31 30
0 3 2 4 5 7 6 63 62
000 1 010 16 17 19 18 20 21 23 22
001 8 9 11 10 12 13 15 14 55 54
100 32 33 35 34 36 37 39 38
011 24 25 27 26 28 29 31 30
101 40 41 43 42 44 45 47 46
010 16 17 19 18 20 21 23 22
111 56 57 59 58 60 61 63 62
110 48 49 51 50 52 53 55 54
27
Logic Minimization
• Manual procedures:
1. Boolean Algebraic manipulation
2. Karnaugh maps (K-maps)
• Automatic procedures for:
a) Finding all Prime Implicants (PI)
b) Finding the minimum cover from the PI’s list
Logic Minimization - Algebraic manipulation
F=ABC+ABC+ABC+ABC
F = (ABC + ABC) + (ABC + ABC)
A B C
F=A(BC+BC)+A(BC+BC)
F=AB(C+C)+AC(B+B)
1 1
.
A B
F F=AB+AC
.
A C
A A A Logic F
B Circuit
C F(A,B,C)
The Uniting Theorem
33
Logic Minimization using K-Maps
A B C F F 2,3,5,7 AC AB ABC 0 1
0 0 0 0 0 00 0 1
()
1 0 0
() 0 0 1 0 B 2 3
2 01
() 0 1 0 1 1 1
3 ABC 00 01 11 10
() 0 1 1 1 0 0 1 11 6 7
4
1 0 0 0 0 0 3 2 0 1
() 1 1* AB
5
() 1 0 1 1 10 04 1 5
1 4 5 7 6 BC
6
1 1 0 0 0 1* 1 0
()
7
() 1 1 1 1 AC PI: AC, BC, A’B
C EPI: AC, A’B
Logic Minimization using K-Maps
F 0,2,5,6,7,8,10,13,14,15
ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD
ABCD
A B C D F Looping a quad of adjacent 1s eliminates the two variables
(0) 0 0 0 0 1 that appears in both direct and complemented form.
(1) 0 0 0 1 0 PI EPI* Non-
(2) 0 0 1 0 1 CD 00 01 11 10
essential PI
(3) 0 0 1 1 0 AB BD
(4) 0 1 0 0 0 00 0 1 3 2
BD
(5) 0 1 0 1 1 1* 0 0 1
4 5 7 6
(6) 0 1 1 0 1 01 CD BC
0 1* 1 1
(7) 0 1 1 1 1 11 12 13 15 14
(8) 1 0 0 0 1 0 1* 1 1 BD
8 9 11 10
(9) 1 0 0 1 0 10 BD CD
(10) 1 0 1 0 1 1* 0 0 1
(11) 1 0 1 1 0 BC
(12) 1 1 0 0 0
CD
(13) 1 1 0 1 1
F = BD + BD + or
(14) 1 1 1 0 1
BC
(15) 1 1 1 1 1
SoP/NAND & PoS/NOR implementation
Remember
DeMorgan’s Theorem Equivalent Gate Symbols
. A
A A B A+B
. =
A B=A+B B B
.
A A+B A A B
. = B
A+B=A B B
A F
A A
Incompletely Specified Logic Functions
(7) 0 1 1 1 1 1 1 1* 0 AD
4 5 7 6 AD
(8) 1 0 0 0 1 01 ABC
0 x 1* 0
(9) 1 0 0 1 0 AD
11 12 13 15 14
(10) 1 0 1 0 x 1* x 0 x
(11) 1 0 1 1 0 8 9 11 10 ABC
10
(12) 1 1 0 0 1 1 0 0 x
(13) 1 1 0 1 x AD BC D
BC D
(14) 1 1 1 0 x ABC
(15) 1 1 1 1 0 Fmin = AD + AD + or
BCD
Incompletely Specified Logic Functions
(0) F F F F F
A B C D F F0F1F2F3F4F5F6F7F8F9F10 11 12 13 14 15 CD 00 01 11 10
0 0 0 01 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(1)
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AB
(2) 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 2
00
(3) 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1* 0
(4)
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 4 5 7 6
(5) 0 1 0 1 x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 x 1* 0
(6) 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 13 15 14
11
(7) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1* x 0 x
(8) 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 9 11 10
10
(9) 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x
(10) 1 0 1 0 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
(11) 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(12) 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ABC
(13) 1 1 0 1 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
(14) 1 1 1 0x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
F13min = AD + AD + or
(15) 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ⊕ BCD
F =A D + ABC
13 or
A’ D’ BCD
B’ B’
C’ C’
A A
D D
Combinational Circuits
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
Equations are modified as follows:
⊕ ⊕ 0 1 1 1 0
Cout = B)·CIN)+ 1 0 0 0 1
((A (A·B)
S= B CIN 1 0 1 1 0
A ⊕ 1 1 0 1 0
1 1 1 1 1
Combinational Circuits Design
Delay Memory
line
Clock