LAB4

All modules are given in LAB #4, except

Basic Computer Block Diagram this controller which has to be designed,
implemented and simulated in Quartus and
256x 8 Memory Data[7..0]
experimentally tested on the Altera platform
Data[7..0]

Address [7..0] CPU

8
Address register (AR) Datapath Control Unit
8 Sequence counter
Program counter (PC) (SC) State Register

SCn+1 =δ(SC,n X)
4

State Decoder (T)

Stop register
8 16
Instruction register IR IR [7..0]
Instruction Decoder
8 DR [7..0]
(lab_controller)
8
Data register (DR) λ(Sn,X)

B Control Register
(Register buffer / bank)
ALU Accumulator (AC) U8
8
S Control commands to
counters , registers , bus
8 Bus
Display Address multiplexer and ALU

select
REGISTER (OUTA) DIP switches
Data[7..0] 8
(addr. to display)
2 Display Data 7-segment display
Display Mem location

controllers 7-segment
REGISTER (OUTD) displays
 Programmer’s Instructions
110

• Basic
View  Lab Computer
4096 (2 12) words
Format
PC Memory reference ( IR6 =0) Opcode Operand Address
Computer
AR of 16 bits 8 15 14 9 8 7 0
256 (2 )
15 8 7 0 IR7 IR6=0 ... IR1 IR0
000 7 0 words of Direct Addressing ( IR7 = 0)
001 PC 8 bits Indirect Addressing ( IR7 = 1)
AR
002 7 0 Register reference ( IR6 =1) Opcode
00 7 ... 0
003
IR7 IR6=1 IR1 IR0
01
004 7 2 1 0
005 02 Memory Reference
…. OpCode
807 FF Instruction Operand Address
Register Ref. Instrc. OpCode
808
809
AC IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0
Mem
I /Reg O p C o d e
80A DR Memory Direct Addr X0 0 0 x x x x x x
80B OUTA Reference Indirect Addr. X2 1 0 x x x x x x

80C OUTD Reg. Ref. Instr. X0 x 1 x x x x x x

…. Visualize in OUTD the contents of the
FFF memory location from address OUTA
Opcode Operand Address
AC Memory-reference instruction format:
15 14 12 11 1 0
DR Direct Addressing ( I =0)
I IR14 IR13 IR12
Indirect Addressing ( I =1)
Opcode Register / IO OpCode
OUTR RR / IO instruction format:
INPR Register reference ( I = 0)
15 14 12 11 1 0
3 I 1 1 1
Input / Output reference ( I =1)
 COMMON BUS SYSTEM

Read L I C
Write
Memory DR
256 x 8 Address LIC ALU
L DIP Switches

IR
7-Segment
PC OUTA LD
LD
AR AC
OUTD
L I C L I C unused
1 2 3 4 5 6 7
0

4 8-bit Common Bus

S0 S1 S2
 Computer
Structure

Control Unit

Z = λ(Sn,X) Comb. Circ. Sn+1 = δ(Sn,X)

X

Buffer Register
LAB #4 Z = λ(S ,X)
n

Sn n+1 n
SC = δ(SC ,X)

Sn
5
SC
Data Path
Sequence Controller
 Symbol Binary codes = hex Description
I=0 (direct addr) I=1(indirect addr)
AND
SUB
00 000001=01 10 000001=81
00 000011=03 10 000011=83
AND AC to memory word
Subtract a memory word from AC
Instructions List & Format
ADD 00 000010=02 10 000010=82 Add a memory word to AC

LDA 00 000100=04 10 000100=84 Load AC from a mm01y location Memory Reference OpCode
Instruction Operand Address
Refe
renc
eMe
mor

STA 00 001000=08 10 001000=88 Store AC to a memory location Register Ref. Instrc. OpCode
BUN 00 010000=10 10 010000=90 Branch unconditionally RTL IR IR IR IR IR IR IR IR
7 6 5 4 3 2 1 0
Increment counter of memory
ISZ 00 100000=20 10 100000=AO location and skip the following ASM#1 I Mem/ O p C o d e
instruction if the incremented Reg
number is 0 Memory Direct Addr X0 0 0 x x x x x x
CLA 01 000001=41 Clear AC
Reference Indirect Addr. X2 1 0 x x x x x x
CMA 01 000010=42 Complement AC Reg. Ref. Instr. X0 x 1 x x x x x x
Arithmetic left shift AC
Refere

ASL 01 000100=44
nceRe
gister

ASR 01 001000=48 Arithmetic right shift AC

INC 01 010000=50 Increment AC

HLT 01 100000=60 Halt. A Stop bit is set to 1, which

prevents PC from being
incremented.
Memory-reference Opcode Operand Address
instruction format: 15 14 9 87 0
IR7 IR6 ... IR1 IR0
Direct Addressing ( IR7 =0) Memory reference ( IR6 =0)
Indirect Addressing ( IR7 =1) Register reference ( IR6 =1)
= · indicates a direct memory-reference instruction; = · · : AND;
= · indicates a register-reference instruction
= · indicates an indirect memory-reference instruction.
: ADD;
There are no input/output instructions: = · · : SUB;
1. The program and data/operands are loaded into the = · · : LDA;
memory when the bit-stream is downloaded to the FPGA. = · : STA;
2. The memory content from an address provided by the DIP
= ·

= · : BUN 6
switches is visualized on the 7-segment display, while the = · : ISZ
program is running.
 RTL SC

ASM#2
0000
Instruction
0001

Cycle
VIZ

0011

0010

0100

RTL (ASM#2)
FETCH

IR6 (0101)
IR6’(0101)
ASM#3
EXECUTION

7
 Instruction Fetch + Viz Cycle RTL (ASM Start

#2) SC←0
SC
- common to all types of instruction RTL AR ← OUTA
0000
T0
VIZ

State Description Notation RTL

ASM#2 0001
T0 Load the address register AR with the contents of OUTA T0: AR <- OUTA
T OUTD ← M[AR] T1
1 Read memory location pointed to by AR to register OUTD T1: OUTD <- M [AR]
0010
T2  Load AR register with the ADDRESS of the opcode of T2: AR <- PC Only when S=0
the current instruction (PC) T2S’: PC <- PC + 1 (System is not in AR←PC T2
 Increment PC (if the program is running, i.e., Stop FF Halt mode) PC ← PC+1
FETCH

0011
S = 0) to point to the address of the next byte to be
read, which can be: IR ← M[AR] T3
o the next instruction, if the current instruction is a 0100
T4
register-reference instruction Only when S=0 Decode
o the 2nd byte of the current instruction, if it is a (System is not in Instruction in IR
memory-reference instruction. Halt mode) YES (register-
T NO(memory IR6=1?
3 Read the instruction’s opcode from memory to IR T3 : IR <-M [AR]
T
4 This state is a delay that allows the opcode to be (nothing) -reference reference
decoded in Control Unit. Instruction)
IR6’(0101)
instruction) IR6 (0101)

T5 If X1  it is a register - reference instruction which will T5X1: exec. Table 3 AR←PC Execute register-
be executed now T5 PC ← PC+1 T5 reference
instruction T5X1 :SC <- 0 Instruction
If X 0 or X 2( memory - reference instruction), T5IR’6 : AR <- PC SC←0
copy PC to AR, i.e, the address of the instruction’s 2nd T6 AR ← M[AR]
EXECUTION

byte goes from PC to AR => now AR contains the

No (Direct Yes ( indirect Addressing)
ADDRESS of
o the operand address if direct addressing, or TsIR’6 S’: PC <- PC + 1 Addressing) IR7=1?
o the address of the operand address if indirect T7 (Do Nothing T7 AR ← M[AR]
addressing
Increment PC if program is running (Stop FF S=0).
X0  X2  IR6 .
Note that

T6 Read from memory location pointed to by AR to AR; the T6IR’6 : AR <- M [AR]
read byte is - the operand address, if direct addressing,
or
-the address of the operand address, if indirect
addressing
T7 If indirect addressing, read the operand address from T7 X 2 : AR  M AR
memory location pointed to by AR
If direct addressing, don’t do anything, as the operand T7X0: (nothing)
8 address is already in AR since T6
T8 & Execute the memory-reference instruction (Table 4). (see Table 4)
after
 Instructions Execution RTL (ASM #2)
Type of Symbol Binary codes = hex Description RTL Notation
Instruction I=0 (direct addressing) I=1(indirect addressing)
AND AC to memory word
AND 00 000001=01 10 000001=81
Memory Add a memory word to AC
ADD 00 000010=02 10 000010=82

Reference SUB 00 000011=03 10 000011=83

(Table 4) Subtract a memory word from AC
Load AC from a mm01y location
LDA 00 000100=04 10 000100=84

Store AC to a memory location cycle not allocated to allow address to stabilize

STA 00 001000=08 10 001000=88

Branch unconditionally
BUN 00 010000=10 10 010000=90
Increment counter of memory location
ISZ 00 100000=20 10 100000=AO

and skip the following instruction if the

incremented number is 0
Clear AC
CLA 01 000001=41

Register Complement AC
CMA 01 000010=42
Arithmetic left shift AC
ASL 01 000100=44
Reference
(Table 3) Arithmetic right shift AC
ASR 01 001000=48
9 Increment AC
INC 01 010000=50
Halt. A Stop bit is set to 1, which
HLT 01 100000=60
prevents PC from being incremented.
Control Signals Generated by CU
ASM#3 Methods for equations’ derivation:
1. Directly from
Memory CPU ALU a) RTL table or ASM#2 chart
b) ASM#4 chart
(M(In, T)) (ALU(In,
T )) 2. By mapping ASM#4 to State Table
1. memwrite 1. ALU_Sel2
CPU registers 2. ALU_Sel1
(R(In, T))
3. ALU_Sel0
1. AR_Load Bus (data mux)
2. PC_Load
(Bus(In,
T))
3. PC_Inc 1. BusSel2
4. DR_Load 2. BusSel1
5. DR_Inc 3. BusSel0
6. IR_Load
7. AC_Clear Control Unit
8. AC_Load ((In, T))
10
9. AC_Inc 1. SC_Clear
Description Notation RTL
Visualization T0: AR ← OUTA
T1: OUTD ← M [AR]
Fetch T2: AR ← PC
T2S’: PC ← PC + 1 Equations Derivation Method 1a
T3: IR ← M [AR]
T4 - delay that allows the opcode to be decoded
If X1: register - reference instruction execute (Table 4)
directly from RTL Table
CLA T5X1 :SC ← 0
T5X1IR0: AC ← 0
CMA
ASL
T5X1IR2: AC ← ashl AC (R(In, T ))
ASR T5X1IR3: AC ← ashr AC
INC T5X1IR4: AC ← AC+ 1
Scan Table and find all the RTL statements
HLT T5X1IR5: S ← 1 in which

AR is loaded:
AR_Load = T0 + T2 + IR6’ T5 + T6IR’6 + T7X2
If indirect (X2)

memory - reference instruction execute (Table 3) PC is loaded:

AND PC_Load = …
ADD
PC is incremented:
SUB
PC_Inc = S’ T2 + S’IR6’ T5 + …
LDA

STA IR is loaded:
IR_Load = T3
BUN

ISZ
(assuming that the next
OUTD is loaded:
instruction is a memory- OUTD_Load = T1 11
reference instruction)
….
 Derivation Method 1b ASM
Equations ASM #2 – RTL   ASM
SC
0000
#4 design SC
0000
RTL
0001
ASM#2 0001
ASM#4
0010
0010
AR_Load,BusSel1
PC_Inc
0011
0011

0100
0100

IR6 (0101)
IR6’(0101) IR6 (0101)
IR6’(0101)

12
 Equations Derivation Method 1b ASM
ASM#2 – RTL specification -> -> ->ASM#4 - design
FETCH
BusSel=110

BusSel=000
AR_load, BusSel=010
INC_PC

BusSel=000

BusSel=010

BusSel=000

13 BusSel=000
 Equations Derivation
(ASM#5) Method 1b directly from BusSel=110

ASM#4 (signals)
BusSel=000
(R(In, T )) AR_load, BusSel=110
PC_Inc
AR_Load = T0 + T2 + IR6’ T5 + …
PC_Load = …
BusSel=000
PC_Inc = S’ T2 + IR6’ T5 + …
IR_Load = T3
OUTD_Load = T1
….
(M(In, T))
Memread = T1 + T3 + T6 IR6 + T7 X2 + BusSel=110
……

(Bus(In, T))
BusSel=000

BusSel2 = T5 IR6’ S’ + …
BusSel1 = = T5 IR6’ S’ + …
BusSel=000
14
BusSel0 = 14
 RTL ASM->State Table->Equations RTL Signals
(ASM#2) λ (ASM#4)
ASM#2 -> ASM#4 -> ASM#5
Present CU Inputs Micro-operation CU Outputs
Equation
State
Derivation Conditions RTL Control
Timing Bus Register
(ASM#5) signal Sel Signals

Method 2a T0 AR <- OUTA 110 AR_Load

T1 OUTD <- M[AR] 000 OUTD_Load

Memread
T2 AR <- PC 010 AR_Load
S PC <- PC+1 PC_Inc
via state table from T3 IR <- M[AR] 000 IR_Load
ASM#4 (signals)
Memread
T4 Delay for IR
decoding
T5 IR6’ AR <- PC 010 AR_Load
PC <- PC+1 PC_Inc

IR6 IR0 AC<-0 (CLA) AC_Clear

IR1 AC<-AC’(CMA)

IR2

IR4 AC_Inc

IR5

T6
T7 IR7
 Equations Derivation
Memory Control Signals (ASM#5) Method 2a
Present CU Inputs Micro-operation CU Outputs
(M(In, T))
State
Register Memwrite = …
Timing Bus
Conditions RTL Control
signal Sel
Signals
T0 AR <- OUTA 110 AR_Load
Memread = T1 + T3 +
T1 OUTD <- M[AR] 000 OUTD_Load

Memread
T2 AR <- PC 010 AR_Load

S PC <- PC+1 PC_Inc

RTL ASM->State Table- >Equations
T3 IR <- M[AR] 000 IR_Load
Memread
T4 Delay for IR decoding ASM#2 -> ASM#4 -> ASM#5
T5 IR6’ AR <- PC 010 AR_Load

PC <- PC+1 PC_Inc

IR6 IR0 AC<-0 (CLA) AC_Clear

IR1 AC<-AC’(CMA)

IR2
IR4 AC_Inc

IR5
T6

T7 IR7
 Equations Derivation
Registers Control Signals (ASM#5) Method 2a
Present CU Inputs Micro-operation CU Outputs
(R(In, T))
State
Timing Bus Register
RTL ASM->State Table-
>Equations
Conditions RTL Control
signal Sel
Signals ASM#2 -> ASM#4 -> ASM#5
T0 AR <- OUTA 110 AR_Load
T1 OUTD <- M[AR] 000 OUTD_Load AR_Load = T0 + T2 + IR6 T5 + ….
Memread PC_Load = …..
T2 AR <- PC 010 AR_Load

S PC <- PC+1 PC_Inc

PC_Inc = S T2 + IR6 T5 +
T3 IR <- M[AR] 000 IR_Load … DR_Load = …..
Memread DR_Inc = ….
T4 Delay for IR decoding
IR_Load = ….
T5 IR6’ AR <- PC 010 AR_Load

PC <- PC+1 PC_Inc

AC_Clear = T5 X1IR0
IR6 IR0 AC<-0 (CLA) AC_Clear
AC_Load = ….
IR1 AC<-AC’(CMA) AC_Inc = ….
IR2 OUTD_Load = T1
IR4 AC_Inc

IR5
T6

T717 IR7
 RTL ASM->State Table-
Equations Derivation (ASM#5) Method >Equations ASM#4 -> ASM#5
ASM#2 ->
2a
State
State Table ->
COMMON BUS SYSTEM

Present CU Inputs Micro-operation CU Outputs

Register CONTROL ( Signals(In,T))

Bus

Timing Conditions RTL Bus Control

signal Sel Signals
Circuit Bus select  (In, T)
which Control Conditions = Bus
T0 AR <- OUTA 110 AR_Load
writes on (In, T) BusSel BusSel BusSel
T1 OUTD <- M[AR] 000 OUTD_Load the bus 2 1 0
Memread T1
T2 AR <- PC 010 AR_Load Memory T3
T IR ’ 0 0 0
6 6 T5 IR6’

S PC <- PC+1 PC_Inc TX

7 2

IR_Load T8 (Y0 + Y1+ Y2+ Y3+ Y6)

T3 IR <- M[AR] 000 Memread AR T
8 5
Y
0 0 1
T4 Delay for IR PC T2 0 1 0
decoding T5 IR6’
T5 IR6’ AR <- PC 010 AR_Load
DR T Y
10 6
0 1 1
PC <- PC+1 PC_Inc (never happens here)
IR 1 0 0
T Y
IR6 IR0 AC<-0 (CLA) AC_Clear AC 9 4 1 0 1
T
IR1 AC<-AC’(CMA)
OUTA 0 1 1 0
not used (indifferent) 1 1 1
IR2

IR4 AC_Inc …
BusSel0 =
IR5
BusSel1 =
T6
T7 IR7
BusSel2 = T9 Y4 + T0
 Equations Derivation
ALU selection control signals (ASM#5) Method 2a
ALU operations table (  ALU(In, T) )
ALU_ ALU_ ALU_
Operation Description RRI
Sel2 Sel1 Sel0 Table 3
S2 S1 S0
0 0 0 AC+DR Addition
0 0 1 AC + DR’+ 1 Subtraction: AC - DR
0 1 0 ashl AC AC arithmetic left shift
0 1 1 ashr AC AC arithmetic right shift
1 0 0 ACDR logic AND
1 0 1 ACDR logic OR
1 1 0 DR DR transfer Symbol RTL Notation MRI
1 1 1 AC’ Complement AC Table 4
ALU_Sel0 = S0 = T9 Y2+ T5 X1 IR3 + AND T8Y0 : DR  M AR
T9Y0:AC ACDR,SC0
… ALU_Sel1 = S1 = …
ADD T8Y1 : DR  M AR
ALU_Sel2 = S2 = … T9Y1:AC ACDR,SC0
SUB T8Y2 : DR  M AR
RTL ASM->State Table-
T9Y2:AC  ACDR,SC 0
>Equations LDA T8Y3 : DR  M AR
ASM#219 -> ASM#4 -> ASM#5 T9Y3 : AC  DR, SC  0
 IR Load

OUTD Load
PC Inc
BusSel2

BusSel1

BusSel0

ALU Sel2
ALU Sel1
ALU Sel0

AR Load
PC Load

DR Load

AC Load

Halt
DR Inc

AC Inc
memwrite

AC Clear

SC Clear
Instruction Phase Timing State Notation RTL micro-op FROM

(Table 2) TO

Display T0 T0 AR<-OUTA 1 1 X AR_Load 1

T1 T1 OUTD<-M[AR] 0 0 0 OUTD_Load Read 1
Fetch opcode T2 T2 AR<-PC 0 1 0 AR_Load 1
T2S' PC<-PC+1 PC_Inc 1
T3 T3 IR<-M[AR] 0 0 0 IR_Load Read 1
T4 T4 Nothing
Exec Reg-Ref instr (IR6=1 - Table 3) IR'7 IR6=X1
5
CLA T T5 X1 IR0 AC<-0 AC_Clear 1
CMA T5 X1 IR1 AC<-AC' 1 0 1 AC_Load 1 1 1 1
ASL T5 X1 IR2 AC<-ashl AC
ASR T5 X1 IR3 AC<-ashr AC
INC T5 X1 IR4 AC<-AC+1
HLT T5 X1 IR5 S<-1
T5 X1 SC<-0
Fetch 2'nd byte of Mem-Ref IR'7 IR'6=X0
instr (IR6=0) IR7 IR'6=X2
If Mem-Ref Instr (IR'6) : addr of T5 IR'6 AR<-PC
instr 2nd byte (of PC) => AR T5 IR'6 S' PC<-PC+1
Fetch instr 2nd byte=addr field = addr of operand T6 T6 IR'6 AR<-M[AR]
(direct addr), or addr of operand's addr (indir)

Do nothing (direct addr) T7 T7 X0 Nothing

7 2
or fetch operand (indirect addr) T X AR<-M[AR]
Exec Mem-Ref instr (IR6=0 - Table 4) IR'6 IR'1 IR0=Y0
IR'6 IR1 IR'0=Y1
IR'6 IR1 IR0=Y2 RTL Table -> State Table ->
Equation Derivation IR'6 IR2=Y3
IR'6 IR3=Y4 Equations
IR'6 IR4=Y5
Method 2b IR'6 IR5=Y6 ASM#2 -> ASM#4 -> ASM#5
AND T8 T8 Y0 DR<-M[AR]
9 0
T Y AC<-AC * DR, SC<-0
8 1
ADD T Y DR<-M[AR]
T9 Y1 AC<-AC + DR, SC<-0
SUB T8 Y2 DR<-M[AR]
T9 Y2 AC<-AC - DR, SC<-0
LDA T8 Y3 DR<-M[AR]
9 3
T Y AC<-DR, SC<-0
STA T9 Y4 M[AR]<-AC, SC<-0
BUN T8 Y5 PC<-AR, SC<-0
ISZ T8 Y6 DR<-M[AR]
T9 Y6 DR<-DR+1
20 T10 Y6 M[AR]<-DR
T11 Y6 if (DR=0 & S=0) then (PC <- PC + 1)
T12 Y6 if (DR=0 & S=0) then (PC <- PC + 1),
SC<-0
 Data Exchange with ISRs

• Use global data

• May need to disable interrupts for critical regions of
code using this data

Input-Output and Interrupt

21
 Data[7..0]
256x 8 Memory
Data[7..0]

Address [7..0] CPU

Datapath Control Unit
Address register (AR ) 8
Sequence counter
(SC) State Register
4
Program counter (PC ) 8
State Decoder (T)
Stop register
IR [7..0] 16
Instruction register (IR ) 8
Instruction Decoder
8
DR [7..0] (lab_controller)
8
Data register (DR )
Control Register
(Register bank)
8

ALU Accumulator (AC) λ(Sn,Xn)

Control commands to
8 counters, registers , bus
multiplexer and ALU
Bus
INPUT Address REGISTER 8
(OUTA ) select
DIP switches
Data[7..0] 8 (addr. to display)

7-segment display I/O

OUTPUT Data REGISTER 7-segment
(OUTD ) controllers displays