Power Supply Design Seminar

Applying SiC and GaN

to high-frequency power

Reproduced from
2016 Texas Instruments Power Supply Design Seminar SEM2200
TI Literature Number: SLUP345
© 2016, 2017 Texas Instruments Incorporated

Power Seminar topics and online power training modules are available at:ti.com/psds
 Applying SiC and GaN
to High-Frequency Power

Rais Miftakhutdinov
John Rice

Texas Instruments – 2016/17 Power Supply Design Seminar 5-1

Agenda
• Introduction to SiC and GaN
• Applications and Benefits
• Driver Considerations
• Switching Performance
• Hard and Soft Switching Examples
• Measurement and Simulation
• Conclusion

Texas Instruments – 2016/17 Power Supply Design Seminar 5-2

Power electronics driving forces

Global Regulations and Industry Initiatives

demand higher efficiency and power
density at a lower cost

$$

Requirements drive markets from Silicon

to SiC and GaN

Texas Instruments – 2016/17 Power Supply Design Seminar 5-3

Physical advantages of GaN and SiC over Si
Physical properties determine power switch
Specific Ron vs Vbreak
performance
Material Si GaN SiC Impact
Lower leakage, higher
Bandgap (Eg), eV 1.1 3.4 3.26
operating temperature
Breakdown Field 200- Higher breakdown
30 300
(Vbr), V/µm <300 voltage for the same die

Electron Mobility
1500 1500 700 On par
(μe), cm2/V·s
Thermal More efficient cooling,
Conductivity, 1.3 >1.5 <3.8 higher operating
W/cmK temperature
Dielectric
11.7 9 9.7 On par
Constant, εr

3.351 102  Vbr 2  Eg 6 8.725  102  Vbr 2  Eg 7.5

Ronspi  ← For Si and SiC Ronspi  ← For GaN
e   r e   r

Texas Instruments – 2016/17 Power Supply Design Seminar 5-4

Commercial SiC transistors landscape
• Key Players: Wolfspeed, Rohm, Infineon, ST Micro, USiC, Micro Semi,
Global Power, GE and more coming
• Voltage and Current Ratings: 400 to 1700 V, 2.6 to 60 A
• Rdson and FoM: 25 to 1000 mΩ, 1400 to 10400 mΩ•nC
• From Yole: $200M Market in 2015, CAGR: 22%
• Texas Instruments supports SiC technology by introducing gate driver ICs
optimized for SiC FETs, like for example UCC2753X family

Texas Instruments – 2016/17 Power Supply Design Seminar 5-5

Commercial GaN transistors landscape
• Key Players: EPC, GaN Systems, Transphorm, Panasonic, Navitas and
more coming
• Voltage and Current Ratings: 30 to 650 V, 15 to 90 A
• Rdson and FoM: 1 to 150 mΩ, 20 to 990 mΩ•nC
• From Yole: $10M Market in 2015, CAGR: 95%
• Texas Instruments entered GaN market by introducing highly integrated
Power Stage products: LMG3410 and LMG5200

Texas Instruments – 2016/17 Power Supply Design Seminar 5-6

Application benefits: WBG versus Si
Si Today WBG Tomorrow
Topo-
Applications Pdens. Cost, Pdens. Cost, Why?
logy Eff. % Eff. %
W/inch3 ₵/W W/inch3 ₵/W

PFC + 92– Bridgeless PFC,

>40 <10 94-96 >55 <8
DC/DC 94.5 >MHz DC/DC
AC-DC Power Supply

Integrate motor
and inverter,
Inverter 93 180 5 >94 >210 3.3
adjustable speed
Motor Drive drive

30% power loss

PFC + reduction, lower
93-94 >50 15 95-96 >70 10 cost of cooling,
DC/DC
EV, HEV Charger high temperature

Texas Instruments – 2016/17 Power Supply Design Seminar 5-7

Other applications that benefit from WBG devices
• Renewable Energy and Smart Grid

o Solar Inverters and Wind Turbines

• Down Hole Drilling

• Avionics and Transportation

• Envelope Tracking and Class D Audio

Texas Instruments – 2016/17 Power Supply Design Seminar 5-8

WBG transistors require new drivers
• RDS(on) over Vgs plots show that optimal drive voltage differs
for various WBG transistors. Fast switching might require negative bias.
Si, GaN Cascode SiC optimal drive: 20 V GaN optimal drive: 5 V
optimal drive: 12 V Negative turn OFF: -5 V

Texas Instruments – 2016/17 Power Supply Design Seminar 5-9

Total gate charge comparison

Si,SuperJ, 650V, 67mΩ SiC, 900V, 65mΩ: GaN, 650V, 55mΩ:

138nC@10V 30 nC @ 15 V 5.8 nC & 6 V

Texas Instruments – 2016/17 Power Supply Design Seminar 5-10

Datasheet drive current Ratings Neglect Parasitics
Example: +4A/-8A rated driver
performance with no parasitics:
∗

Assume: Cgs = 1nF, Vdd = 8V, then: trise = 2ns, tfall = 1ns

Is it possible?

Texas Instruments – 2016/17 Power Supply Design Seminar 5-11

Drive current including parasitic inductances
 Driving WBG FETs has to be fast and
clean
 No large undershoot and overshoot
allowed

Vgs voltage

Drive circuit No Ind. With Ind. V

I sink peak 8A 4.6 A
A
tfall 1 ns 4.5 ns
Vgs undershoot 0V -3V Ig current

Vgs overshoot 0V 1V
Time, ns
Texas Instruments – 2016/17 Power Supply Design Seminar 5-12
High dv/dt issue
• WBG FETs can generate dv/dt transients exceeding 100 V/ns
• High slew rate dv/dt generates Miller turn-on spike at gate
• Split output driver with low RSINK minimizes Miller turn-on spike
• Split drive voltage with negative turn-off bias also helps, but drive losses increase.

VDS
Vin

FET: SiC ON OFF

I(CGD) VGS Of
CGD C3M0900280D
SR MOSFET
800-V Vds rise
COSS
IG RG with 40V/ns
CGS
I(CGS) slew rate.
RSINK 15V turn ON, Vin
-3V
VDSturn
Of OFF split
SRto
rail MOSFET
mitigate 4V
Miller Spike

Texas Instruments – 2016/17 Power Supply Design Seminar 5-13

 Driver isolation options
• Driver isolation provides safety, level shift and noise immunity
• Related insulation can be rated Functional, Basic and Reinforced
Digital Isolator and
Driver and xfrmr Isolated Driver
High Voltage Driver

Implementation
+
Prop. Delay, ns 100 to 150 100 to 250 20 to 50
Area ratio 8:1 2:1 1
Height ratio 10:1 1 1
dV/dt immune Medium Poor Good
Bandwidth 20kHz to 500kHz DC to 1MHz DC to 5MHz
Summary Does not fit WBG Partially fits WBG Best option for WBG

Texas Instruments – 2016/17 Power Supply Design Seminar 5-14

Biasing techniques for WBG FETs:
Limitations of Bootstrap Approach:
• Diode must have low Qrr
• SiC or GaN diode could be used
• Bias voltage is not precise
• Regular Cboot recharge is needed
• Mostly limited to two-level topologies
• Limited dV/dt and bus voltage <600V
Texas Instruments – 2016/17 Power Supply Design Seminar
Biasing using isolated converters:
• Always available
• Can be used with any topology
• Stable, accurate bias voltage
• High dV/dt immunity provided by low Cis
Driver board with
signal and bias isolation
5-15
Layout and drive rules
• Locate driver next to the FET
• Separate noisy grounds as shown
• Locate decoupling capacitor close to VDD and GND
• Use split output drivers to optimize turn ON/OFF
• Use split rail to mitigate Miller turn ON
• Select components with low parasitics
• Minimize high di/dt loops
• Minimize high dv/dt areas
• Use wide traces whenever possible
• Use simulators to extract parasitics
Drive
Signal current Highest noise power
current switch current

Texas Instruments – 2016/17 Power Supply Design Seminar 5-16

Hard and soft switching FOM
General FOM:
Hard Switching:
Soft Switching:
• FOMs do not account for MOSFET rated voltage dependence
• For the same power, if V ↑, then I ↓. This allows higher RDSON ↑
• Impact of Qg, Qgs2, Qgd depends on drive voltage
• Impact of Qoss depends on operating voltage
• Qrr depends on power and remains the same
• k = 0.1 to 0.2, accounts for current increase to achieve soft switching
Use of RDSON and Q normalized to Vds = 30V and Vgs = 12V allows fair
comparison of different technologies in multilevel topologies ↓ ↓
Qgs2 Qgd
30 ↓
12 Qg

2 2 30
12 12
Texas Instruments – 2016/17 Power Supply Design Seminar 5-17
Small signal Coss not relevant for switching losses
Coss(Vds) 
Coss(25V )  25V 

2
• Data Sheet based Coss is measured at 1MHz and <0.5V AC
  40 pF
2.2  Vds  5V 
• Small signal Coss cannot be used for switching losses evaluation
• Large signal Cson is determined by test setup shown here
• Based on this Cson switching losses model is derived

Vs  Is  T 2  Eson(Vds)
Eson(Vds)  Cson(Vds) 
4 Vs 2
Texas Instruments – 2016/17 Power Supply Design Seminar 5-18
Large signal Cson measurements instead of Coss
• Isolated IC driver UCC21520 and battery bias is used to minimize parasitic capacitances
• Waveforms show 800V input switching
Charge current: 400mA/div Phase node: 200V/div Time scale: 20ns/div

Upper Vgate: 5V/div

Texas Instruments – 2016/17 Power Supply Design Seminar 5-19

GaN vs Si FET large signal Cson comparison
10000
Si: SPP11N60CFD:
Equivalent Turn On Switching Capacitance, Cson, pF

600V, 0.44Ω (red line)

 20V  5V 
0.75

Cson(Vs)  1617 pF   
1000  Vs  5V 
GaN: TPH2002PS:
600V, 0.26Ω (blue line)
 20V  5V 
0.47
100 Cson(Vs)  427 pF   

0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400

Vd-s, V
 Vs 5V 
Si SPP11N60CFD
GaN TPH2002PS
Si SPP11N60CFD model
GaN TPH2002PS model

Cson(Vs)  (Vs) 2
Averaged loss per single FET and single switching Ploss(Vs) 
event. Multiply by 4 for full half-bridge loss. 2T
Texas Instruments – 2016/17 Power Supply Design Seminar 5-20
SiC vs Si FET large signal Cson comparison
10000
Si: IPW90R340C3:
Equivalent Turn On Switching Capacitance, Cson, pF

900V, 0.34Ω (red line)

 20V  5V 
0.73

Cson(Vs)  5389 pF   
1000  Vs  5V 
SiC: C3M0280090D:
900V, 0.28Ω (blue line)
 20V  5V 
0.17

Cson(Vs)  396 pF   
 Vs  5V 
100
0 100 200 300 400 500 600 700 800 900

Vd-s, V
Si IPW90R340C3 measured
SiC C3M0280090D measured
Si IPW90R340C3 model

Cson(Vs)  (Vs) 2
SiC C3M0280090D model

Averaged loss per single FET and single switching event. Ploss(Vs) 
Multiply by 4 for full half-bridge loss. 2T
Texas Instruments – 2016/17 Power Supply Design Seminar 5-21
Closer look at nonlinear Coss charge and discharge
Equivalent circuits
Half-Bridge Stage as part of many topologies 1st half-cycle: 2nd half-cycle:
Vs HS - ON, LS - OFF HS - OFF, LS - ON

QHS id Coss(v(t))
Vg-s QHS

Vg-s QLS QLS Coss(v(t))

ic

Charge and discharge loss of nonlinear capacitances are independent on current

waveforms but determined by total charge through FET channel at specified Vs

pRav: Average turn ON Q(T/2): Total charge ic(t), id(t): Arbitrary charge and
loss for half-bridge through FET channel discharge currents
/ /
2∙ ∙ /2 /2
/2

Texas Instruments – 2016/17 Power Supply Design Seminar 5-22

Coss related loss based on spec: SiC C3M0280090D
Coss(Vs) = 20pF@900V from spec Ed(Vs) = 9μJ@900V from spec

Ed(Vs): Energy stored in FET output

capacitance, usually provided in spec, is
derived from Coss as shown below.
During discharge, this energy dissipated
as loss. Spec does not include data to
estimate Coss charging related loss.

Digitizing Integrating Coss over v Integrating v(q) over q

Texas Instruments – 2016/17 Power Supply Design Seminar 5-23

Stored and charge energy of nonlinear Coss
Stored Energy plot Ed(Vs) derived as
Area above v(q) curve and below area above v(q) in the left plot. This plot
red line represents stored energy is usually provided in datasheet

Area below v(q) curve and above

x axis represents charge energy

Total hard switching losses include discharge and

charge losses and proportional to red rectangular area

Texas Instruments – 2016/17 Power Supply Design Seminar 5-24

Buck Power Stage to Compare SiC vs Si FETs

VIN: 800V

UCC21520
C3M0280090D L: 930μH,
vs 40mΩ
IPW90R340C3
VS: 5V
C4D02120E
VLS: 18V Cin Cout Vout:
C3M0280090D
vs 400V, 800W
IPW90R340C3

Texas Instruments – 2016/17 Power Supply Design Seminar 5-25

Major waveforms at 100 kHz and 1 μs fixed dead time
Phase: 200V/div (blue); IL: 0.9A/div on left, 2A/div on right (pink); Low Gate: 20V/div (green);
Upper Gate: 20V/div (red); Time: 2μs/div
ZVS at Pout = 0 W Hard Switching at Pout = 300W

Texas Instruments – 2016/17 Power Supply Design Seminar 5-26

dV/dt Slew Rate at Soft and Hard Switching Conditions
Phase: 200V/div (blue); IL: 0.9A/div on left, 2A/div on right (pink); Low Gate: 20V/div (green);
Upper Gate: 20V/div (red)
Soft Switching dV/dt = 1.5V/ns; Time: 500ns/div Hard Switching dV/dt = 40V/ns; Time: 20ns/div

Texas Instruments – 2016/17 Power Supply Design Seminar 5-27

ZVS and Body Diode Recovery Impact on Efficiency
100

98

96
Efficiency, 800Vin, 400Vout: %

94 Adaptive
92 frequency and
90
dead time
88
Additional losses control can be
because of body implemented
86 ZVS lost at fixed
diode recovery using digital
84 100kHz frequency
controllers like
and 1μs dead time
82
UCD3K family.
80
0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800

Output power, W
C3M0280090D, fixed 100kHz frequency and 1us dead time
C3M0280090D, adaptive frequency and dead time to maintain ZVS

Texas Instruments – 2016/17 Power Supply Design Seminar 5-28

SiC vs Si Ploss in 100-kHz, 800-V to 400-V buck converter
64

Black: Si 900 V, 340 mΩ FET has

60
Ploss, Buck 800Vin to 400Vout, Hard switching vs ZVS: W

56
52 extreme Coss and Body diode
48
44 losses at hard switching
40
36 Red: SiC 900 V, 280 mΩ FET has
32
28
much lower Coss and Body diode
24 losses at hard switching
20
16
12
8
4
SiC (blue) and Si (pink) FETs have
0
0 80 160 240 320 400 480 560 640 720 800
similar conduction losses at Zero-
Ouput power, A Voltage Switching but the drive
C3M0280090D, hard switching at fixed Fsw=100kHz and Td=1us
C3M0280090D, ZVS using adaptive Fsw and Td losses of SiC FET are much lower
IPW90R340C3, hard switching at fixed Fsw=100kHz and Td=1us
IPW90R340C3, ZVS using adaptive Fsw and Td

Texas Instruments – 2016/17 Power Supply Design Seminar 5-29

SiC vs Si drive losses in 800-V to 400-V buck converter
0.8
Drive losses, Buck 800Vin to 400Vout, 100kHz hard switching, Vdr=18V: W

Black: Si FET drive loss at 100 kHz

fixed frequency with 18-V drive rail
0.7

0.6 during hard switching. Output

0.5
power was limited by extreme
losses in power stage.
0.4

0.3

0.2
SiC FET drive losses at similar
0.1 conditions are about 25% of Si FET
0
0 60 120 180 240 300 360 420 480 540 600

Output power, A
C3M0280090D, hard switching at fixed Fsw=100kHz and Td=1us
IPW90R340C3, hard switching at fixed Fsw=100kHz and Td=1us

Texas Instruments – 2016/17 Power Supply Design Seminar 5-30

 Measurement and Simulation

Half-bridge GaN Switch with integrated gate driver

LMG5200

Texas Instruments – 2016/17 Power Supply Design Seminar 5-31

Advancing a GaN design may necessitate
upgrading your bench
• 1GHz+ Scope + High bandwidth
voltage (Single ended and differential)
and current probes

• TEM – Transverse Electromagnetic Cell

• Field probes with small loop area to

isolated high PCB field areas

• Non-inductive, non-capacitive load with

remote sensing
LMG5200 test bench
• Spectrum Analyzer or Mixed Domain
Oscilloscope

Texas Instruments – 2016/17 Power Supply Design Seminar 5-32

80V, 18 mOhm, enhancement-mode GaN switch
(eGaN) half-bridge with integrated driver

LMG5200 Optimized
Functional Block Diagram Package and Layout

Texas Instruments – 2016/17 Power Supply Design Seminar 5-33

Application Circuit:
LMG5200 EVM – 48VDC to 1V at 8 Amps
Layout critical placement
- Input Caps
- Ground isolating resistor

LMG5200

From PWM
Signal Input
Generator DC
Deadtime Input

Output – 1V at 8A

Texas Instruments – 2016/17 Power Supply Design Seminar 5-34

Creating an on-time pulse to convert
48 V to 1 V at 8 A and 500 kHz High Resolution Timer Block
Programming

F28069
USB ControlStick

Texas Instruments – 2016/17 Power Supply Design Seminar 5-35

Oscilloscope & probe time domain considerations

LMG5200 EVM + C2000

F28069 USB ControlStick

Texas Instruments – 2016/17 Power Supply Design Seminar 5-36

Correcting for measurement error
1GHz/5GS/s scope/probe system Root Sum Square Estimate

Duty cycle /on-time estimates

LMG5200 switch node converting 48V to 1V at 500kHz

Texas Instruments – 2016/17 Power Supply Design Seminar 5-37

 Modeling LMG5200 circuit behavior
SPICE circuit simulation and correlation
LMG5200 uses EPC2016, 80V,
18mohm eGaN FETs

*
T 61.47
VSW - Sim
43.85
VSW 26.24
8.62
-9.00
1.15
1.10
Vout 1.05
1.00 Vout - Sim
950.00m
341.59u 342.46u 343.34u 344.21u 345.09u • Scope probe capacitance counts
Time (s)
• Plane capacitance counts
Simulated and Measured Waveforms • Component Parasitics count
shifted to show correlation

Texas Instruments – 2016/17 Power Supply Design Seminar 5-38

LMG5200 far-field radiated emissions
Converting 48 V to 1 V at 10 A, efficiency = 75%
T -30.00
Peak = -53dBm = 54dBuV
-40.00

-50.00
900MHz - Cell Tower
-60.00

dBm
Noise Floor
-70.00

-80.00

-90.00

-100.00
0.00 250.00M 500.00M 750.00M 1.00G
Frequency

Open TEM Cell Setup TEM Cell Measurement

* Noise floor measured with board connected, but not switching

Texas Instruments – 2016/17 Power Supply Design Seminar 5-39

Full-wave 3D EM analysis PCB import and design
workflow in CST Studio Suite

1) Full-wave 3D Simulation

•Broadband analysis of geometry

•passes a model to the circuit

2) Circuit Simulation

•SPICE like circuit simulation

•Transient or AC analysis.

3) Combine Results

•Calculates field and currents in the 3D model

•Considers switching pattern of the circuit simulation

Texas Instruments – 2016/17 Power Supply Design Seminar 5-40

LMG5200 board surface current animation
48VIN, 1 VOUT at 8 A
1MHz
DC
250 (1KHz)
MHz
Current DC Input
current
Current

PGND
and GND

Output – 1V at 8A
connect
point

Texas Instruments – 2016/17 Power Supply Design Seminar 5-41

Closeup on switch area surface current at 1 MHz
VIN -purple
plane layer 2 PGND
Increased
current GND
density and
loop area due
to pgnd/plane
cutouts

These vias void ground and

create a bottleneck for high
frequency return current

PGND
SW

Texas Instruments – 2016/17 Power Supply Design Seminar 5-42

Visualization of input capacitor effectiveness in
CST Studio Suite
C10=10uF
Capacitor effectiveness
determined by
placement, dielectric,
and footprint

Bottom side capacitor

C8=0.1uF C14=1uF

Texas Instruments – 2016/17 Power Supply Design Seminar 5-43

Summary
• Advantages of WBG devices and their impact on Power Electronics
Applications outlined
• Optimal driving technique for WBG FETs and differences versus Si FETs
presented
• Hard and Soft Switching performance of SiC, GaN and Si FETs
demonstrated
• Switching loss evaluation based on very non-linear small signal Coss in
Datasheet versus large signal Cson discussed in detail
• Measurement and Simulation technique applied to WBG devices
thoroughly investigated

Texas Instruments – 2016/17 Power Supply Design Seminar 5-44

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