Microcontroller Systems

(KON 309E)

LECTURE NOTES
(WEEK 2)
STM32 Microcontroller Family (Fundamentals of Power & Clock Control)

1.1. Power Control:

Microcontrollers are not always supplied with an infinite power source (power grid) as in
development boards. Most of the time, these devices operates using rechargeable power
units (batteries); therefore, power management can be crucial in such cases.

In STM32F103 microcontrollers requires 2.0V to 3.6V operating voltage supply (V DD). The
internal 1.8V digital power is supplied via an internal regulator. The following figure
illustrates the power supply overview in STM32F10x microcontrollers.

Figure 1.1: Power supply overview in STM32F10x microcontrollers [1].

 To improve conversion accuracy, the ADC has an independent power supply that can
be filtered separately, and shielded from noise on the PCB. Furthermore, to ensure a
better accuracy on low-voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF+. The voltage on VREF+ may range from 2.0 V to
VDDA (VREF– must already be tied to VSSA).

 To retain the content of the “Backup Registers” when VDD is turned off, the VBAT pin
can be connected to an optional standby voltage supplied by a battery or another
source.
  The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the
main digital supply (VDD) is turned off. Switching to the VBAT supply is controlled by
the power down reset (PDR) circuitry embedded in the reset block.

 The voltage regulator is always enabled after reset. It works in three different modes:
In “Run” mode, the regulator supplies full power to the 1.8 V domain and in “Stop”
mode, the regulator supplies low power to the 1.8 V domain, preserving the contents
of the registers and SRAM, whereas, the regulator is powered off in “Standby” mode.

1.2. Low-Power Modes:

Microcontrollers operate in “Run” mode after system (or power) reset unless another
command is given. However, there exist other operating modes for microcontrollers in order
to save the power used by the device. As stated earlier, since the microcontrollers are
generally used in small-scale systems and energized by batteries, energy efficient operation
is important. Thus, when the CPU is not required to be run, power-saving modes can be
used.

 Sleep mode: In sleep mode, CPU clock is off, whereas, all peripheral units, including
the Cortex-M3 core peripherals such as NVIC, SysTick, etc., are kept running. The WFI
instruction (__WFI(); in Keil) is used to enter sleep mode, and any peripheral
interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake
up the microcontroller from sleep mode.

 Stop mode: In stop mode, all clocks are stopped. The PLL, the HSI and the HSE RC
oscillators are disabled. The voltage regulator can be configured either in normal or
low-power mode. SRAM and register contents are preserved. In the Stop mode, all
I/O pins keep the same state as in the Run mode.

 Stand-By mode: The Standby mode allows achieving the lowest power consumption.
It is based on the Cortex®-M3 deep-sleep mode, with the voltage regulator disabled.
The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the
HSE oscillator are also switched off. SRAM and register contents are lost except for
registers in the Backup domain (BKP) and Standby circuitry.

Note: The backup registers (BKP) are forty two 16-bit registers for storing 84 bytes of user
application data. They are implemented in the backup domain that remains powered on by
VBAT when the VDD power is switched off. They are not reset when the device wakes up from
Standby mode or by a system reset or power reset.

Summary of the low-power modes can be seen from the following figure.
 Figure 1.2: Summary of the low-power modes in STM32F10x microcontrollers [1].

1.3. Power Control Registers:

- The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). The
power control register (PWR_CR) is given as follows in the user manual of STM32F10x series.

Here, PDDS and LPDS bits are important to control the “Stop” and “Standby” modes. Also,
the reset value for this register is given as 0x00000000.

- On the other hand, the power control/status register is also given as below:

Here, EWUP bit is important due to the fact that it determines if the WKUP pin is used for a
general purpose I/O or wake-up from Standby mode (0: GPIO, 1: Wake-up from Standby).
Also, the reset value for this register is also given as 0x00000000.

Examples about the power control will be provided in the next lecture notes since they
require some knowledge about general purpose input outputs (GPIOs), external interrupts
(EXTI), etc.
2.1. Clock Control:

It is known that a clock signal is necessary for the operation of all sequential (logic) circuits.
The central processing unit, peripheral units, memory and registers work with the help of a
properly set clock source. The execution speed in the CPU also depends on the frequency of
clock signal.

Three different clock sources can be used to drive the system clock in STM32F10x devices:

 HSI (High-Speed Internal) Oscillator Clock

The HSI clock signal is generated from an internal 8 MHz RC oscillator and can be
used directly as a system clock or divided by 2 to be used as PLL input. The HSI RC
oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster start-up time than the HSE crystal oscillator;
however, the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
 HSE (High-Speed External) Oscillator Clock:

The high speed external clock signal (HSE) is mostly generated via an external
crystal/ceramic resonator. The 4 to 16 MHz external oscillator has the advantage of
producing a very accurate rate on the main clock.
 PLL (Phase-Locked-Loop) Clock:

The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock
frequency. The PLL configuration (selection of HSI oscillator divided by 2 or HSE
oscillator for PLL input clock, and multiplication factor) must be done before enabling
the PLL. Once the PLL enabled, these parameters cannot be changed.
Furthermore, the devices have two secondary clock sources as given below:

 40 kHz LSI (Low-Speed Internal) RC Clock:

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU).
The clock frequency is around 40 kHz (between 30 kHz and 60 kHz).
 32.768 kHz LSE (Low-Speed External) Crystal:

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has
the advantage providing a low-power but highly accurate clock source to the real-
time clock peripheral (RTC) for clock/calendar or other timing functions

(Please note that each clock source can be switched off when it is not used, to reduce power
consumption)
In the STM32 microcontroller family, the mentioned clock sources are used to feed the
buses introduced in the previous notes. Several prescalers allow the configuration of the
AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. Note
that the maximum frequency of the AHB and APB2 domains is 72 MHz and the maximum
allowed frequency of the APB1 domain is 36 MHz.

2.2. (Reset and) Clock Control Registers:

- The clock control register (RCC_CR) in the STM32F103 user manual is given as follows:

The reset value for this register is given as 0x0000XX83 where X is undefined.

- Clock configuration register (RCC_CFGR), on the other hand, is presented as follows:

The reset value for this register is given as 0x00000000.

- The clock interrupt register (RCC_CIR) is also given as follows:

The reset value for this register is given as 0x00000000.

- APB2 and APB1 peripheral clock enable register (RCC_APB2ENR, RCC_APB1ENR) are one of
the important registers and given as follows, respectively:
RCC_APB2ENR:

RCC_APB1ENR:

References:

[1] URL-1, https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-

stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-
mcus-stmicroelectronics.pdf, STM32F103xx Reference Manual, RM0008, reached in:
24.09.2020.