Data Sheet: LCD Row/column Driver For Dot Matrix Graphic Displays

INTEGRATED CIRCUITS
DATA SHEET
PCF8578
LCD row/column driver for
dot matrix graphic displays
Product specification 2003 Apr 14
Supersedes data of 1998 Sep 08
Philips Semiconductors Product specification

PCF8578
CONTENTS 18 SOLDERING
18.1 Introduction to soldering surface mount
1 FEATURES
packages
2 APPLICATIONS 18.2 Reflow soldering
3 GENERAL DESCRIPTION 18.3 Wave soldering
18.4 Manual soldering
4 ORDERING INFORMATION
18.5 Suitability of surface mount IC packages for
5 BLOCK DIAGRAM wave and reflow soldering methods
6 PINNING 19 DATA SHEET STATUS
7 FUNCTIONAL DESCRIPTION 20 DEFINITIONS
7.1 Mixed mode 21 DISCLAIMERS
7.2 Row mode
22 PURCHASE OF PHILIPS I2C COMPONENTS
7.3 Multiplexed LCD bias generation
7.4 Power-on reset
7.5 Internal clock
7.6 External clock
7.7 Timing generator
7.8 Row/column drivers
7.9 Display mode controller
7.10 Display RAM
7.11 Data pointer
7.12 Subaddress counter
7.13 I2C-bus controller
7.14 Input filters
7.15 RAM access
7.16 Display control
7.17 TEST pin
8 I2C-BUS PROTOCOL
8.1 Command decoder
9 CHARACTERISTICS OF THE I2C-BUS
9.1 Bit transfer
9.2 Start and stop conditions
9.3 System configuration
9.4 Acknowledge
10 LIMITING VALUES
11 HANDLING
12 DC CHARACTERISTICS
13 AC CHARACTERISTICS
14 APPLICATION INFORMATION
15 CHIP DIMENSIONS AND BONDING PAD
LOCATIONS
16 CHIP-ON-GLASS INFORMATION
17 PACKAGE OUTLINES
2003 Apr 14 2

PCF8578
1 FEATURES
• Single chip LCD controller/driver
• Stand-alone or may be used with up to 32 PCF8579s
(40960 dots possible)
• 40 driver outputs, configurable as 32⁄8, 24⁄16, 16⁄24 or
8⁄ rows/columns
32
2 APPLICATIONS
• Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32
• Automotive information systems
• Externally selectable bias configuration, 5 or 6 levels
• Telecommunication systems
• 1280-bit RAM for display data storage and scratch pad
• Point-of-sale terminals
• Display memory bank switching
• Computer terminals
• Auto-incremented data loading across hardware
subaddress boundaries (with PCF8579) • Instrumentation.
• Provides display synchronization for PCF8579
3 GENERAL DESCRIPTION
• On-chip oscillator, requires only 1 external resistor
• Power-on reset blanks display The PCF8578 is a low power CMOS LCD row/column
driver, designed to drive dot matrix graphic displays at
• Logic voltage supply range 2.5 to 6 V
multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device
• Maximum LCD supply voltage 9 V has 40 outputs, of which 24 are programmable,
• Low power consumption configurable as 32⁄8, 24⁄16, 16⁄24 or 8⁄32 rows/columns.
The PCF8578 can function as a stand-alone LCD
• I2C-bus interface
controller/driver for use in small systems, or for larger
• TTL/CMOS compatible systems can be used in conjunction with up to
• Compatible with most microcontrollers 32 PCF8579s for which it has been optimized. Together
• Optimized pinning for single plane wiring in multiple these two devices form a general purpose LCD dot matrix
device applications (with PCF8579) driver chip set, capable of driving displays of up to
40960 dots. The PCF8578 is compatible with most
• Space saving 56-lead plastic mini-pack and 64 pin quad microcontrollers and communicates via a two-line
flat pack bidirectional bus (I2C-bus). Communication overheads are
• Compatible with chip-on-glass technology. minimized by a display RAM with auto-incremented
addressing and display bank switching.
4 ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
PCF8578T VSO56 plastic very small outline package; 56 leads SOT190-1
PCF8578U/2 − chip with bumps in tray −
PCF8578H LQFP64 plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2
2003 Apr 14 3

PCF8578
5 BLOCK DIAGRAM
C39 - C32
R31/C31 - R8/C8
R7 - R0
17 - 56
(29 to 35, 37, 38 to 46
48 to 62, 63, 64, 1 to 6)
VDD 9 (20)
10 (21)
V2
11 (22) (1)
V3 ROW/COLUMN
12 (23) PCF8578
V4 DRIVERS
13 (24)
V5
VLCD 14 (25)
6 (12)
TEST
DISPLAY
MODE OUTPUT
CONTROLLER CONTROLLER
Y DECODER
AND SENSING 32 x 40-BIT DISPLAY
AMPLIFIERS DISPLAY RAM DECODER
X DECODER
(9) 3
SYNC
POWER-ON SUBADDRESS TIMING
RAM DATA POINTER (10) 4
RESET COUNTER GENERATOR
Y X CLK
2 (8) (16) 8
SCL OSC
INPUT I 2 C-BUS COMMAND
1 (7) FILTERS CONTROLLER DECODER OSCILLATOR
SDA R OSC
(14, 15, 17 to 19 (11) 5

VSS
15, 16 26 to 28 36, 47) 7 (13)
MSA842
n.c. n.c. SA0
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
The pin numbers given in parenthesis refer to the LQFP64 package.
Fig.1 Block diagram.
2003 Apr 14 4

PCF8578
6 PINNING
PIN
SYMBOL DESCRIPTION
VSO56 LQFP64
SDA 1 7 I2C-bus serial data input/output
SCL 2 8 I2C-bus serial clock input
SYNC 3 9 cascade synchronization output
CLK 4 10 external clock input/output
VSS 5 11 ground (logic)
TEST 6 12 test pin (connect to VSS)
SA0 7 13 I2C-bus slave address input (bit 0)
OSC 8 16 oscillator input
VDD 9 20 positive supply voltage
V2 to V5 10 to 13 21 to 24 LCD bias voltage inputs
VLCD 14 25 LCD supply voltage
n.c. 15, 16 14, 15, 17 to 19, not connected
26 to 28, 36, 47
C39 to C32 17 to 24 29 to 35, 37 LCD column driver outputs
R31/C31 to R8/C8 25 to 48 38 to 46, 48 to 62 LCD row/column driver outputs
R7 to R0 49 to 56 63, 64, 1 to 6 LCD row driver outputs
2003 Apr 14 5

PCF8578
SDA 1 56 R0
SCL 2 55 R1
SYNC 3 54 R2
CLK 4 53 R3
VSS 5 52 R4
TEST 6 51 R5
SA0 7 50 R6
OSC 8 49 R7
VDD 9 48 R8/C8
V2 10 47 R9/C9
V3 11 46 R10/C10
V4 12 45 R11/C11
V5 13 44 R12/C12
VLCD 14 43 R13/C13
PCF8578T
n.c. 15 42 R14/C14
n.c. 16 41 R15/C15
C39 17 40 R16/C16
C38 18 39 R17/C17
C37 19 38 R18/C18
C36 20 37 R19/C19
C35 21 36 R20/C20
C34 22 35 R21/C21
C33 23 34 R22/C22
C32 24 33 R23/C23
R31/C31 25 32 R24/C24
R30/C30 26 31 R25/C25
R29/C29 27 30 R26/C26
R28/C28 28 29 R27/C27
MSA839
Fig.2 Pin configuration (VSO56).
2003 Apr 14 6

PCF8578
60 R10/C10
59 R11/C11
58 R12/C12
57 R13/C13
56 R14/C14
55 R15/C15
54 R16/C16
53 R17/C17
52 R18/C18
51 R19/C19
50 R20/C20
49 R21/C21
handbook, full pagewidth
62 R8/C8
61 R9/C9
64 R6
63 R7
R5 1 48 R22/C22
R4 2 47 n.c.
R3 3 46 R23/C23
R2 4 45 R24/C24
R1 5 44 R25/C25
R0 6 43 R26/C26
SDA 7 42 R27/C27
SCL 8 41 R28/C28
PCF8578H
SYNC 9 40 R29/C29
CLK 10 39 R30/C30
VSS 11 38 R31/C31
TEST 12 37 C32
SA0 13 36 n.c.
n.c. 14 35 C33
n.c. 15 34 C34
OSC 16 33 C35
n.c. 17
n.c. 18
n.c. 19
VDD 20
V2 21
V3 22
V4 23
V5 24
VLCD 25
n.c. 26
n.c. 27
n.c. 28
C39 29
C38 30
C37 31
C36 32
MBH588
Fig.3 Pin configuration (LQFP64).
2003 Apr 14 7

PCF8578
7 FUNCTIONAL DESCRIPTION Timing signals are derived from the on-chip oscillator,
whose frequency is determined by the value of the resistor
The PCF8578 row/column driver is designed for use in one
connected between OSC and VSS.
of three ways:
• Stand-alone row/column driver for small displays Commands sent on the I2C-bus from the host
(mixed mode) microcontroller set the mode (row or mixed), configuration
(multiplex rate and number of rows and columns) and
• Row/column driver with cascaded PCF8579s control the operation of the device. The device may have
(mixed mode)
one of two slave addresses. The only difference between
• Row driver with cascaded PCF8579s (mixed mode). these slave addresses is the least significant bit, which is
set by the logic level applied to SA0. The PCF8578 and
7.1 Mixed mode PCF8579 also have subaddresses. The subaddress of the
PCF8578 is only defined in mixed mode and is fixed at 0.
In mixed mode, the device functions as both a row and
The RAM may only be accessed in mixed mode and data
column driver. It can be used in small stand-alone
is loaded as described for the PCF8579.
applications, or for larger displays with up to 15 PCF8579s
(31 PCF8579s when two slave addresses are used). Bias levels may be generated by an external potential
See Table 1 for common display configurations. divider with appropriate decoupling capacitors. For large
displays, bias sources with high drive capability should be
7.2 Row mode used. A typical mixed mode system operating with up to
15 PCF8579s is shown in Fig.5 (a stand-alone system
In row mode, the device functions as a row driver with up
would be identical but without the PCF8579s).
to 32 row outputs and provides the clock and
synchronization signals for the PCF8579. Up to 16
PCF8579s can normally be cascaded (32 when two slave
addresses are used).
Table 1 Possible displays configurations
MULTIPLEX MIXED MODE ROW MODE

APPLICATION TYPICAL APPLICATIONS
RATE ROWS COLUMNS ROWS COLUMNS
Stand alone 1:8 8 32 − − small digital or
1 : 16 16 24 − − alphanumerical displays
1 : 24 24 16 − −
1 : 32 32 8 − −
With PCF8579 1:8 8(1) 632(1) 8× 4(2) 640(2) alphanumeric displays and
1 : 16 16(1) 624(1) 16 × 2(2) 640(2) dot matrix graphic displays
1 : 24 24(1) 616(1) 24(2) 640(2)
1 : 32 32(1) 608(1) 24(2) 640(2)
Notes
1. Using 15 PCF8579s.
2. Using 16 PCF8579s.
2003 Apr 14 8

PCF8578
7.3 Multiplexed LCD bias generation 7.4 Power-on reset

The bias levels required to produce maximum contrast At power-on the PCF8578 resets to a defined starting
depend on the multiplex rate and the LCD threshold condition as follows:
voltage (Vth). Vth is typically defined as the RMS voltage at 1. Display blank
which the LCD exhibits 10% contrast. Table 2 shows the
2. 1 : 32 multiplex rate, row mode
optimum voltage bias levels for the PCF8578 as functions
of Vop (Vop = VDD − VLCD), together with the discrimination 3. Start bank, 0 selected
ratios (D) for the different multiplex rates. A practical value 4. Data pointer is set to X, Y address 0, 0
for Vop is obtained by equating Voff(rms) with Vth. Figure 4
5. Character mode
shows the first 4 rows of Table 2 as graphs. Table 3 shows
the relative values of the resistors required in the 6. Subaddress counter is set to 0
configuration of Fig.5 to produce the standard multiplex 7. I2C-bus interface is initialized.
rates.
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
Table 2 Optimum LCD voltages
MULTIPLEX RATE
PARAMETER
1:8 1 : 16 1 : 24 1 : 32
MSA838
1.0
V2 V bias
--------- 0.739 0.800 0.830 0.850
V op Vop V2
0.8
V3
--------- 0.522 0.600 0.661 0.700
V op V3
0.6
V4
--------- 0.478 0.400 0.339 0.300
V op
0.4
V5 V4
--------- 0.261 0.200 0.170 0.150
V op
0.2
V5
V off ( rms )
---------------------- 0.297 0.245 0.214 0.193
V op 0
1:8 1:16 1:24 1:32
V on ( rms ) multiplex rate
--------------------- 0.430 0.316 0.263 0.230
V op
Vbias = V2, V3, V4, V5. See Table 2.
V on ( rms )
D = ---------------------
- 1.447 1.291 1.230 1.196 Fig.4 Vbias/Vop as a function of the multiplex rate.
V off ( rms )
V op
--------- 3.370 4.080 4.680 5.190
V th
Table 3 Multiplex rates and resistor values for Fig.5
MULTIPLEX RATE (n)

RESISTORS
n=8 n = 16, 24, 32
R1 R R
R2 ( n – 2 )R R
R3 ( 3 – n )R ( n – 3 )R
2003 Apr 14 9
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2003 Apr 14
Philips Semiconductors
LCD DISPLAY
n 40 n
rows columns
V DD V DD
40
R1 columns
C
V2
R2
C
V3
V DD V DD A0
HOST R3
MICROCONTROLLER C VLCD VLCD A1 subaddress 1
V4 PCF8578 PCF8579 VSS / V DD
10
VSS VSS A2
SCL
R2 VSS / V DD SA0 A3
SDA C
V5 SDA SCL CLK SYNC V4 V3
R1
C
V
LCD
VSS SA0 VSS / V DD
OSC
VSS VLCD R OSC
SDA SCL CLK SYNC
Product specification
MSA843
PCF8578
Fig.5 Typical mixed mode configuration.

PCF8578
T frame ON
0 1 2 3 4 5 6 7 OFF
VDD
V2
V3
ROW 0 V4
V5
V LCD
1:8
VDD
V2
V3
COLUMN V4
V5
V LCD
SYNC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VDD
V2
V3
ROW 0 V4
V5
V LCD
1:16
VDD
V2
V3
COLUMN V4
V5
V LCD
SYNC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
VDD
V2
V3
ROW 0 V4
V5
V LCD
1:24
VDD
V2
V3
COLUMN V4
V5
V LCD
SYNC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VDD
V2
V3
ROW 0 V4
V5
V LCD
1:32
VDD
V2
V3
COLUMN V4
V5
V LCD
SYNC column
display
MSA841
Fig.6 LCD row/column waveforms.
2003 Apr 14 11

PCF8578
T frame state 1 (OFF)

VDD state 2 (ON)
V2
ROW 1 V3
R1 (t) V4
V5
V LCD
VDD
V2
ROW 2 V3
R2 (t) V4 dot matrix
1:8 multiplex rate
V5
V LCD
VDD
V2
COL 1 V3
C1 (t) V4
V5
V LCD
VDD
V2
COL 2 V3
C2 (t) V4
V5
V LCD
V op
0.261 Vop
V state 1 (t) 0V
0.261 Vop
V op
V op
0.478 Vop
0.261 Vop
V state 2 (t) 0V
0.261 Vop
0.478 Vop
V op MSA840
V state 1 (t) = C1(t) R1(t): general relationship (n = multiplex rate)
Von(rms) 1 8 1 Von(rms) 1 n 1
= = 0.430 =
V op 8 8 ( 8 1) V op n n ( n 1)
V state 2 (t) = C2(t) R2(t): Voff(rms) 2 ( n 1)

=
Voff(rms) 2 ( 8 1)
V op n ( n 1) 2
= = 0.297
V op 8 ( 8 1) 2
Fig.7 LCD drive mode waveforms for 1 : 8 multiplex rate.
2003 Apr 14 12

PCF8578
state 1 (OFF)
T frame
VDD state 2 (ON)
V2
ROW 1 V3
R1 (t) V4
V5
V LCD
VDD
V2
ROW 2 V3
R2 (t) V4
V5
V LCD
VDD
V2
COL 1 V3
C1 (t) V4
V5 dot matrix
V LCD 1:16 multiplex rate
VDD
V2
COL 2 V3
C2 (t) V4
V5
V LCD
V op
0.2 Vop
V state 1 (t) 0V
0.2 Vop
V op
V op
0.6 Vop
0.2 Vop
V state 2 (t) 0V
0.2 Vop
0.6 Vop
V op
MSA836
V state 1 (t) = C1(t) R1(t): general relationship (n = multiplex rate)
Von(rms) 1 16 1 Von(rms) 1 n 1
= = 0.316 =
V op 16 16 ( 16 1 ) V op n n ( n 1)
V state 2 (t) = C2(t) R2(t): Voff(rms)

= 2 ( n 1)
V off(rms) 2 ( 16 1)
V op n ( n 1) 2
= = 0.254
V op 16 ( 16 1 ) 2
Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.
2003 Apr 14 13

PCF8578
7.5 Internal clock 7.6 External clock

The clock signal for the system may be generated by the If an external clock is used, OSC must be connected to
internal oscillator and prescaler. The frequency is VDD and the external clock signal to CLK. Table 4
determined by the value of the resistor ROSC, see Fig.9. summarizes the nominal CLK and SYNC frequencies.
For normal use a value of 330 kΩ is recommended.
The clock signal, for cascaded PCF8579s, is output at 7.7 Timing generator
CLK and has a frequency 1⁄6 (multiplex rate 1 : 8, 1 : 16
The timing generator of the PCF8578 organizes the
and 1 : 32) or 1⁄8 (multiplex rate 1 : 24) of the oscillator
internal data flow of the device and generates the LCD
frequency.
frame synchronization pulse SYNC, whose period is an
integer multiple of the clock period. In cascaded
applications, this signal maintains the correct timing
MSA837
relationship between the PCF8578 and PCF8579s in the
10 3 system.
f OSC
7.8 Row/column drivers
(kHz)
Outputs R0 to R7 and C32 to C39 are fixed as row and
10 2 column drivers respectively. The remaining 24 outputs
R8/C8 to R31/C31 are programmable and may be
configured (in blocks of 8) to be either row or column
drivers. The row select signal is produced sequentially at
10
each output from R0 up to the number defined by the
multiplex rate (see Table 1). In mixed mode the remaining
outputs are configured as columns. In row mode all
programmable outputs (R8/C8 to R31/C31) are defined as
row drivers and the outputs C32 to C39 should be left
1 open-circuit.
10 102 103 104
R OSC (kΩ )
Using a 1 : 16 multiplex rate, two sets of row outputs are
To avoid capacitive coupling, which could adversely affect oscillator driven, thus facilitating split-screen configurations, i.e. a
stability, ROSC should be placed as closely as possible to the OSC row select pulse appears simultaneously at R0 and
pin. If this proves to be a problem, a filtering capacitor may be R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex
connected in parallel to ROSC.
rate of 1 : 8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly
Fig.9 Oscillator frequency as a function of
to the LCD. Unused outputs should be left open-circuit.
external oscillator resistor, ROSC.
In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are
rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32
R0 to R31/C31 are rows.
Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note 1.

OSCILLATOR
FRAME FREQUENCY DIVISION CLOCK FREQUENCY
FREQUENCY MULTIPLEX RATE (n)
fSYNC (Hz) RATIO fCLK (Hz)
fOSC(2) (Hz)
12288 64 1 : 8, 1 : 16, 1 : 32 6 2048
12288 64 1 : 24 8 1536
Notes
1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
2. ROSC = 330 kΩ.
2003 Apr 14 14

PCF8578
7.9 Display mode controller 7.15 RAM access

The configuration of the outputs (row or column) and the RAM operations are only possible when the PCF8578 is
selection of the appropriate driver waveforms are in mixed mode.
controlled by the display mode controller.
In this event its hardware subaddress is internally fixed at
0000 and the hardware subaddresses of any PCF8579
7.10 Display RAM
used in conjunction with the PCF8578 must start at 0001.
The PCF8578 contains a 32 × 40-bit static RAM which
There are three RAM ACCESS modes:
stores the display data. The RAM is divided into 4 banks
of 40 bytes (4 × 8 × 40 bits). During RAM access, data is • Character
transferred to/from the RAM via the I2C-bus. The first • Half-graphic
eight columns of data (0 to 7) cannot be displayed but • Full-graphic.
are available for general data storage and provide
compatibility with the PCF8579. There is a direct These modes are specified by bits G1 to G0 of the RAM
correspondence between X-address and column output ACCESS command. The RAM ACCESS command
number. controls the order in which data is written to or read from
the RAM (see Fig.10).
7.11 Data pointer To store RAM data, the user specifies the location into
The addressing mechanism for the display RAM is which the first byte will be loaded (see Fig.11):
realized using the data pointer. This allows an individual • Device subaddress (specified by the DEVICE SELECT
data byte or a series of data bytes to be written into, or read command)
from, the display RAM, controlled by commands sent on
• RAM X-address (specified by the LOAD X-ADDRESS
the I2C-bus.
command)
7.12 Subaddress counter • RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage takes Subsequent data bytes will be written or read according to
place only when the contents of the subaddress counter the chosen RAM ACCESS mode. Device subaddresses
agree with the hardware subaddress. The hardware are automatically incremented between devices until the
subaddress of the PCF8578, valid in mixed mode only, is last device is reached. If the last device has
fixed at 0000. subaddress 15, further display data transfers will lead to a
wrap-around of the subaddress to 0.
7.13 I2C-bus controller
7.16 Display control
The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs The display is generated by continuously shifting rows of
the conversion of the data input (serial-to-parallel) and the RAM data to the dot matrix LCD via the column outputs.
data output (parallel-to-serial). The PCF8578 acts as an The number of rows scanned depends on the multiplex
I2C-bus slave transmitter/receiver in mixed mode, and as rate set by bits M1 and M0 of the SET MODE command.
a slave receiver in row mode. A slave device cannot The display status (all dots on/off and normal/inverse
control bus communication. video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
7.14 Input filters corresponding to the top of the display is set by bits
To enhance noise immunity in electrically adverse B1 and B0 of the SET START BANK command. This is
environments, RC low-pass filters are provided on the shown in Fig.12. This feature is useful when scrolling in
SDA and SCL lines. alphanumeric applications.
7.17 TEST pin

The TEST pin must be connected to VSS.
2003 Apr 14 15
2003 Apr 14
PCF8578/PCF8579 PCF8579
driver 1 driver 2 driver k
bank 0
bank 1
RAM
4 bytes
bank 2
bank 3
PCF8578/PCF8579 system RAM LSB

40-bits 1 k 16
1 byte 0 1 2 3 4 5 6 7 8 9 10 11
character mode
16
MSB
0 2 4 6 8 10 12 14 16 18 20 22
2 bytes
1 3 5 7 9 11 13 15 17 19 21 23
half-graphic mode
0 4 8 12 16 20 24 28 32 36 40 44
1 5 9 13 17 21 25 29 33 37 41 45
4 bytes
2 6 10 14 18 22 26 30 34 38 42 46
3 7 11 15 19 23 27 31 35 39 43 47
PCF8578
MSA849
RAM data bytes are full-graphic mode
written or read as
indicated above
Fig.10 RAM ACCESS mode.

2003 Apr 14
DEVICE SELECT:
subaddress 12
RAM ACCESS: bank 0
character mode bank 1

bank 1
RAM bank 2
bank 3
LOAD X-ADDRESS: X-address = 8

R/ W
slave address
17
READ S
S 0 1 1 1 1 0 A 1 A DATA A
0
R/W
slave address DEVICE SELECT LOAD X-ADDRESS RAM ACCESS
S
S 0 1 1 1 1 0 A 0 A 1 1 1 0 1 1 0 0 A 1 0 0 0 1 0 0 0 A 0 1 1 1 0 0 0 1 A
0
last command
DATA A DATA A
WRITE
MSA835
PCF8578
Fig.11 Example of commands specifying initial data byte RAM locations.

PCF8578
RAM
bank 0
top of LCD
bank 1
LCD
bank 2
bank 3
MSA851
Fig.12 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.
2003 Apr 14 18

PCF8578
8 I2C-BUS PROTOCOL In READ mode, indicated by setting the read/write bit

HIGH, data bytes may be read from the RAM following the
Two 7-bit slave addresses (0111100 and 0111101) are slave address acknowledgement. After this
reserved for both the PCF8578 and PCF8579. The least acknowledgement the master transmitter becomes a
significant bit of the slave address is set by connecting master receiver and the PCF8578 becomes a slave
input SA0 to either 0 (VSS) or 1 (VDD). Therefore, two types transmitter. The master receiver must acknowledge the
of PCF8578 or PCF8579 can be distinguished on the reception of each byte in turn. The master receiver must
same I2C-bus which allows: signal an end of data to the slave transmitter, by not
1. One PCF8578 to operate with up to 32 PCF8579s on generating an acknowledge on the last byte clocked out of
the same I2C-bus for very large applications the slave. The slave transmitter then leaves the data line
2. The use of two types of LCD multiplex schemes on the HIGH, enabling the master to generate a stop condition
same I2C-bus. (P).
In most applications the PCF8578 will have the same slave Display bytes are written into, or read from, the RAM at the
address as the PCF8579. address specified by the data pointer and subaddress
counter. Both the data pointer and subaddress counter are
The I2C-bus protocol is shown in Fig.13. automatically incremented, enabling a stream of data to be
All communications are initiated with a start condition (S) transferred either to, or from, the intended devices.
from the I2C-bus master, which is followed by the desired
slave address and read/write bit. All devices with this slave In multiple device applications, the hardware subaddress
address acknowledge in parallel. All other devices ignore pins of the PCF8579s (A0 to A3) are connected to VSS or
the bus transfer. VDD to represent the desired hardware subaddress code.
If two or more devices share the same slave address, then
In WRITE mode (indicated by setting the read/write bit each device must be allocated a unique hardware
LOW) one or more commands follow the slave address subaddress.
acknowledgement. The commands are also
acknowledged by all addressed devices on the bus.
The last command must clear the continuation bit C.
After the last command a series of data bytes may follow.
The acknowledgement after each byte is made only by the
(A0, A1, A2 and A3) addressed PCF8579 or PCF8578
with its implicit subaddress 0. After the last data byte
has been acknowledged, the I2C-bus master issues a stop
condition (P).
2003 Apr 14 19

PCF8578
acknowledge by acknowledge
all addressed by A0, A1, A2 and A3
PCF8578s / PCF8579s selected PCF8578s /
R/ W
PCF8579s only
slave address
S
S 0 1 1 1 1 0 A 0 A C COMMAND A DISPLAY DATA A P
0
1 byte n 0 byte(s) n 0 byte(s)

update data pointers
and if necessary,
MSA830 subaddress counter
(a)
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge no acknowledge
slave address slave address from master from master
S S
S 0 1 1 1 1 0 A 0 A C COMMAND A S 0 1 1 1 1 0 A 1 A DATA A DATA 1 P
0 0
n 1 byte n bytes last byte

R/ W R/W
at this moment master
transmitter becomes a update data pointers
master receiver and and if necessary
PCF8578/PCF8579 slave subaddress counter
receiver becomes a
slave transmitter MSA832
(b)
acknowledge by
all addressed acknowledge no acknowledge
PCF8578s / PCF8579s from master from master
slave address
S
S 0 1 1 1 1 0 A 1 A DATA A DATA 1 P
0
MSA831 n bytes last byte

R/ W
update data pointers
and if necessary,
(c) subaddress counter
Fig.13 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string
(WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ
mode).
2003 Apr 14 20

PCF8578
8.1 Command decoder

The command decoder identifies command bytes that MSB LSB
arrive on the I2C-bus. The most-significant bit of a
command is the continuation bit C (see Fig.14). When this C REST OF OPCODE
bit is set, it indicates that the next byte to be transferred will
also be a command. If the bit is reset, it indicates the MSA833
conclusion of the command transfer. Further bytes will be

regarded as display data. Commands are transferred in C = 0; last command.
WRITE mode only. C = 1; commands continue.
The five commands available to the PCF8578 are defined Fig.14 General information of command byte.
in Tables 5 and 6.
Table 5 Summary of commands

COMMAND OPCODE(1) DESCRIPTION
SET MODE C 1 0 D D D D D multiplex rate, display status, system type
SET START BANK C 1 1 1 1 1 D D defines bank at top of LCD
DEVICE SELECT C 1 1 0 D D D D defines device subaddress
RAM ACCESS C 1 1 1 D D D D graphic mode, bank select (D D D D ≥ 12 is not
allowed; see SET START BANK opcode)
LOAD X-ADDRESS C 0 D D D D D D 0 to 39
Note
1. C = command continuation bit. D = may be a logic 1 or 0.
2003 Apr 14 21

PCF8578
Table 6 Definition of PCF8578/PCF8579 commands

COMMAND OPCODE OPTIONS DESCRIPTION
SET MODE C 1 0 T E1 E0 M1 M0 see Table 7 defines LCD drive mode
see Table 8 defines display status
see Table 9 defines system type
SET START BANK C 1 1 1 1 1 B1 B0 see Table 10 defines pointer to RAM bank
corresponding to the top of the LCD;
useful for scrolling, pseudo-motion and
background preparation of new display
DEVICE SELECT C 1 1 0 A3 A2 A1 A0 see Table 11 four bits of immediate data, bits
A0 to A3, are transferred to the
subaddress counter to define one of
sixteen hardware subaddresses
RAM ACCESS C 1 1 1 G1 G0 Y1 Y0 see Table 12 defines the auto-increment behaviour of
the address for RAM access
see Table 13 two bits of immediate data, bits Y0 to
Y1, are transferred to the X-address
pointer to define one of forty display
RAM columns
LOAD X-ADDRESS C 0 X5 X4 X3 X2 X1 X0 see Table 14 six bits of immediate data, bits
X0 to X5, are transferred to the
X-address pointer to define one of forty
display RAM columns
2003 Apr 14 22

PCF8578
Table 7 Set mode option 1 Table 11 Device select option 1

BITS DESCRIPTION BITS
LCD DRIVE MODE
M1 M0 Decimal value 0 to 15 A3 A2 A1 A0
1:8 MUX (8 rows) 0 1
Table 12 RAM access option 1
1 : 16 MUX (16 rows) 1 0
1 : 24 MUX (24 rows) 1 1 BITS
RAM ACCESS MODE
1 : 32 MUX (32 rows) 0 0 G1 G0
Character 0 0
Table 8 Set mode option 2
Half-graphic 0 1
BITS Full-graphic 1 0
DISPLAY STATUS
E1 E0 Not allowed (note 1) 1 1
Blank 0 0 Note
Normal 0 1 1. See opcode for SET START BANK in Table 6.
All segments on 1 0
Inverse video 1 1 Table 13 Device select option 1
DESCRIPTION BITS
Table 9 Set mode option 3
Decimal value 0 to 3 Y1 Y0
SYSTEM TYPE BIT T
PCF8578 row only 0 Table 14 Device select option 1
PCF8578 mixed mode 1 DESCRIPTION BITS
Decimal value 0 to 39 X5 X4 X3 X2 X1 X0
Table 10 Set start bank option 1
BITS
START BANK POINTER
B1 B0
Bank 0 0 0
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1
2003 Apr 14 23

PCF8578
9 CHARACTERISTICS OF THE I2C-BUS 9.4 Acknowledge
The I2C-bus is for bidirectional, two-line communication The number of data bytes transferred between the start
between different ICs or modules. The two lines are a and stop conditions from transmitter to receiver is
serial data line (SDA) and a serial clock line (SCL) which unlimited. Each data byte of eight bits is followed by one
must be connected to a positive supply via a pull-up acknowledge bit. The acknowledge bit is a HIGH level put
resistor. Data transfer may be initiated only when the bus on the bus by the transmitter, whereas the master
is not busy. generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
9.1 Bit transfer acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
One data bit is transferred during each clock pulse. of each byte that has been clocked out of the slave
The data on the SDA line must remain stable during the transmitter. The device that acknowledges must pull down
HIGH period of the clock pulse as changes in the data line the SDA line during the acknowledge clock pulse, so that
at this moment will be interpreted as control signals. the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
9.2 Start and stop conditions must be taken into consideration). A master receiver must
Both data and clock lines remain HIGH when the bus is not signal the end of a data transmission to the transmitter by
busy. A HIGH-to-LOW transition of the data line, while the not generating an acknowledge on the last byte that has
clock is HIGH, is defined as the START condition (S). been clocked out of the slave. In this event the transmitter
A LOW-to-HIGH transition of the data line while the clock must leave the data line HIGH to enable the master to
is HIGH, is defined as the STOP condition (P). generate a stop condition.
9.3 System configuration

A device transmitting a message is a 'transmitter', a device
receiving a message is the 'receiver'. The device that
controls the message flow is the 'master' and the devices
which are controlled by the master are the 'slaves'.
SDA
SCL
data line change

stable; of data
data valid allowed MBA607
Fig.15 Bit transfer.
2003 Apr 14 24

PCF8578
SDA SDA
SCL SCL
S P
START condition STOP condition

MBA608
Fig.16 Definition of start and stop condition.
SDA
SCL
MASTER SLAVE MASTER

SLAVE MASTER
TRANSMITTER / TRANSMITTER / TRANSMITTER /
RECEIVER TRANSMITTER
RECEIVER RECEIVER RECEIVER
MBA605
Fig.17 System configuration.
handbook, full pagewidth START clock pulse for

condition acknowledgement
SCL FROM
1 2 8 9
MASTER
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER MBA606 - 1
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig.18 Acknowledgement on the I2C-bus.
2003 Apr 14 25

PCF8578
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER MIN. MAX. UNIT
VDD supply voltage −0.5 +8.0 V
VLCD LCD supply voltage VDD − 11 VDD V
VI1 input voltage SDA, SCL, CLK, TEST, SA0 and OSC VSS − 0.5 VDD + 0.5 V
VI2 input voltage V2 to V5 VLCD − 0.5 VDD + 0.5 V
Vo1 output voltage SYNC and CLK VSS − 0.5 VDD + 0.5 V
Vo2 output voltage R0 to R7, R8/C8 to R31/C31 and C32 to C39 VLCD − 0.5 VDD + 0.5 V
II DC input current −10 +10 mA
IO DC output current −10 +10 mA
IDD, ISS, ILCD VDD, VSS or VLCD current −50 +50 mA
Ptot total power dissipation per package − 400 mW
Po power dissipation per output − 100 mW
Tstg storage temperature −65 +150 °C
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ).
2003 Apr 14 26

PCF8578
12 DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies
VDD supply voltage 2.5 − 6.0 V
VLCD LCD supply voltage VDD − 9 − VDD − 3.5 V
IDD1 supply current external clock fCLK = 2 kHz; note 1 − 6 15 µA
IDD2 supply current internal clock ROSC = 330 kΩ − 20 50 µA
VPOR power-on reset level note 2 0.8 1.3 1.8 V
Logic
VIL LOW level input voltage VSS − 0.3VDD V
VIH HIGH level input voltage 0.7VDD − VDD V
IOL1 LOW level output current at SYNC VOL = 1 V; VDD = 5 V 1 − − mA
and CLK
IOH1 HIGH level output current at SYNC VOH = 4 V; VDD = 5 V − − −1 mA
and CLK
IOL2 LOW level output current at SDA VOL = 0.4 V; VDD = 5 V 3 − − mA
IL1 leakage current at SDA, SCL, SYNC, Vi = VDD or VSS − − +1 mA
CLK, TEST and SA0
IL2 leakage current at OSC Vi = VDD − − +1 µA
Ci input capacitance at SCL and SDA note 3 − − 5 pF
LCD outputs
IL3 leakage current at V2 to V5 Vi = VDD or VLCD −2 − +2 µA
VDC DC component of LCD drivers − ±20 − mV
R0 to R7, R8/C8 to R31/C31 and
C32 to C39
RROW output resistance R0 to R7 and row mode; note 4 − 1.5 3 kΩ
R8/C8 to R31/C31
RCOL output resistance R8/C8 to R31/C31 column mode; note 4 − 3 6 kΩ
and C32 to C39
Notes
1. Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50% duty factor.
2. Resets all logic when VDD < VPOR.
3. Periodically sampled; not 100% tested.
4. Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input
(V2 to V5, VDD and VLCD) when the specified current flows through one output under the following conditions
(see Table 2):
a) Vop = VDD − VLCD = 9 V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2 − VLCD ≥ 6.65 V; V5 − VLCD ≤ 2.35 V; ILOAD = 150 µA.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; ILOAD = 100 µA.
2003 Apr 14 27

PCF8578
13 AC CHARACTERISTICS
All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 to 6 V;
VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

fCLK1 clock frequency at multiplex rates of 1 : 8, ROSC = 330 kΩ; VDD = 6 V 1.2 2.1 3.3 kHz
1 : 16 and 1 : 32
fCLK2 clock frequency at multiplex rates of ROSC = 330 kΩ; VDD = 6 V 0.9 1.6 2.5 kHz
1 : 24
tPSYNC SYNC propagation delay − − 500 ns
tPLCD driver delays VDD − VLCD = 9 V; − − 100 µs
with test loads
I2C-bus
fSCL SCL clock frequency − − 100 kHz
tSW tolerable spike width on bus − − 100 ns
tBUF bus free time 4.7 − − µs
tSU;STA start condition set-up time repeated start codes only 4.7 − − µs
tHD;STA start condition hold time 4.0 4.0 − µs
tLOW SCL LOW time 4.7 − − µs
tHIGH SCL HIGH time 4.0 − − µs
tr SCL and SDA rise time − − 1 µs
tf SCL and SDA fall time − − 0.3 µs
tSU;DAT data set-up time 250 − − ns
tHD;DAT data hold time 0 − − ns
tSU;STO stop condition set-up time 4.0 − − µs
handbook, full pagewidth 3.3 kΩ 1.5 kΩ

SYNC, CLK 0.5 VDD SDA VDD
MSA829
C39 to C32, 1 nF
R31/C31 to R8/C8
and R7 to R0
Fig.19 AC test loads.
2003 Apr 14 28

PCF8578
1/ f CLK
0.7 VDD
CLK
0.3 V DD
0.7 VDD
SYNC
0.3 V DD
t PSYNC t PSYNC
0.5 V
C39 to C32,
R31/C31 to R8/C8 (V DD V LCD = 9 V)
and R7 to R0
0.5 V
t PLCD MSA834
Fig.20 Driver timing waveforms.
handbook, full pagewidth
SDA
t BUF t LOW tf
SCL
t tr t HD;DAT t SU;DAT
HD;STA t HIGH
SDA
t SU;STA
MGA728 t SU;STO
Fig.21 I2C-bus timing waveforms.
2003 Apr 14 29
2003 Apr 14
14
APPLICATION INFORMATION
LCD DISPLAY
R0 R1 R2 R3 R4 R5 R6 R7 R8/ R9/ R10/ R11/ R12/ R13/ R14/ R15/ R16/ R17/ R18/ R19/ R20/ R21/ R22/ R23/ R24/ R25/ R26/ R27/
C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27
PCF8578
30
VSS SA0 R31/ R30/ R29/ R28/

SDA SCL SYNC CLK TEST OSC V DD V2 V3 V4 V5 VLCD n.c. n.c. C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28
R OSC
MSA844
PCF8578
Fig.22 Stand-alone application using 8 rows and 32 columns.
2003 Apr 14
PCF8578: Segment Driver
a Application
R0
f
g b
e one line of 24 digits 7 segment
c
one line of 12 digits star-burst
R7 d dp (mux 1:16)
LCD Total: 384 segments
R8
R15
12
1
(Using 1:16 mux, the first C16 C17 C39
,,
character data must be
loaded in bank 0 and 1
starting at byte number 16)
a LSB
,,,
,,, ,,,,
,,
31
0 16 17 39 b
Bank f
g
,,,, ,,
0 c
e
d
1 dp
MSB
AM
DISPLAY
R
RAM
EE
PCF8578 (1)
ALTERNATE DISPLAY BANK 2
FR
ALTERNATE DISPLAY BANK

3 MLB423
1-byte
PCF8578
(1) Can be used for creating blinking characters.
Fig.23 Segment driver application for up to 384 segments.

2003 Apr 14
V DD
V DD
R 32 1:32 multiplex rate
C
LCD DISPLAY 32 x 40 x k dots (k 16)
V2 rows (20480 dots max.)
C R
V3
(4 2 3)R 8
C
V4 PCF8578 40 40 40
unused columns
(ROW MODE) columns subaddress 0 columns subaddress 1 columns subaddress k 1
C R
V5
V DD V DD A0 V DD V DD A0 V DD V DD A0
C R SA0 VSS
VLCD A1 A1 A1
VLCD 1 VLCD 2 VLCD k
V3 PCF8579 A2 V3 PCF8579 A2 V3 PCF8579 A2
32
VLCD
VSS OSC
V4 A3 V4 A3 V4 A3
VSS SDA SCL CLK SYNC R OSC VSS SYNC CLK SCL SDA SA0 VSS SYNC CLK SCL SDA SA0 VSS SYNC CLK SCL SDA SA0
VSS VSS VSS VSS VSS VSS VSS
V DD
SCL
SDA
MSA845
PCF8578
Fig.24 Typical LCD driver system with 1 : 32 multiplex rate.
2003 Apr 14
V DD VSS V DD VSS V DD VSS
SA0 SDA SCL CLK SYNC VSS SA0 SDA SCL CLK SYNC VSS SA0 SDA SCL CLK SYNC VSS
A3 V3 A3 V3 A3 V3
A2 k V4 A2 2 V4 A2 1 V4
PCF8579 PCF8579 PCF8579
A1 V LCD A1 VLCD A1 VLCD
A0 V DD V DD A0 V DD V DD A0 V DD V DD
subaddress k 1 40 subaddress 1 40 subaddress 0 40

columns columns columns
V DD
16 1:16 multiplex rate

V DD LCD DISPLAY 16 x 40 x k dots (k 16)
R rows (10240 dots max.)
C
33
V2
C R 16 x 40 x k dots (k 16)
rows (10240 dots max.)
V3
C R
8 40 40 40
V4 PCF8578
C R unused columns
V5
C R SA0
VSS / V DD
V LCD A1 A1 A1
VLCD
VSS OSC
V4 A3 V4 A3 V4 A3
V DD
SCL
SDA
MSA847
PCF8578
Fig.25 Split screen application with 1 : 16 multiplex rate for improved contrast.
2003 Apr 14
V DD VSS V DD VSS V DD VSS
SA0 SDA SCL CLK SYNC VSS SA0 SDA SCL CLK SYNC VSS SA0 SDA SCL CLK SYNC VSS
A3 V3 A3 V3 A3 V3
A2 k V4 A2 2 V4 A2 1 V4
PCF8579 PCF8579 PCF8579
A1 V LCD A1 VLCD A1 VLCD
A0 V DD V DD A0 V DD V DD A0 V DD V DD
subaddress k 1 40 subaddress 1 40 subaddress 0 40

columns columns columns
V DD
1:32 multiplex rate

V DD LCD DISPLAY 32 x 40 x k dots (k 16)
R (20480 dots max.)
34
C 32
V2
C R (4 2 3)R 32 x 40 x k dots (k 16)
rows (20480 dots max.)
V3
C
8 40 40 40
V4 PCF8578
C R unused columns
V5
C R SA0
VSS / V DD
V LCD A1 A1 A1
VLCD
VSS OSC
V4 A3 V4 A3 V4 A3
V DD
SCL
SDA
MSA846
PCF8578
Fig.26 Split screen application with 1 : 32 multiplex rate.
2003 Apr 14
VSS
SCL V DD
SDA V
LCD
R0
R OSC
(4 2 3)R
R R R R
n.c.
n.c.
LCD DISPLAY
PCF8578
35
R31/C31
C0 C27 C28 C39 C0 C27 C28 C39
PCF8579
n. PCF8579
n.
c.
c.
to other
PCF8579s
PCF8578
MSA852
Fig.27 Example of single plane wiring, single screen with 1 : 32 multiplex rate (PCF8578 in row driver mode).

PCF8578
15 CHIP DIMENSIONS AND BONDING PAD LOCATIONS
SYNC
TEST
SDA
CLK
VSS
SCL
SA0
R0
R1
R2
R3
R4
7 6 5 4 3 2 1 54 53 52 51 50
49 R5
OSC 8
48 R6
47 R7
46 R8/C8
VDD 9 45 R9/C9
V2 10
V3 11
44 R10/C10
V4 12
43 R11/C11
V5 13
42 R12/C12
4.88 VLCD 14 0
mm 41 x
R13/C13
0
40 R14/C14
39 R15/C15
38 R16/C16
37 R17/C17
C39 36 R18/C18
15 PCF8578
C38 35 R19/C19
16
34 R20/C20
C37 17
C36 18 33 R21/C21
C35 19 32 R22/C22
20 21 22 23 24 25 26 27 28 29 30 31
R31/C31
R30/C30
R29/C29
R28/C28
R27/C27
R25/C25
R24/C24
R23/C23
C34
C33
C32
R26/C26
3.06 mm MBH589
Chip area: 14.93 mm2.

Bonding pad dimensions: 120 µm × 120 µm.
The numbers given in the small squares refer to the pad numbers.
Fig.28 Bonding pad locations.
2003 Apr 14 36

PCF8578
Table 15 Bonding pad locations (dimensions in µm); all x/y coordinates are referenced to centre of chip, see Fig.28
PINS
PAD NUMBER SYMBOL x y
VSO56 LQFP64
1 SDA 174 2241 1 7
2 SCL −30 2241 2 8
3 SYNC −234 2241 3 9
4 CLK −468 2241 4 10
5 VSS −726 2241 5 11
6 TEST −1014 2241 6 12
7 SA0 −1308 2241 7 13
8 OSC −1308 1917 8 16
9 VDD −1308 1113 9 20
10 V2 −1308 873 10 21
11 V3 −1308 663 11 22
12 V4 −1308 459 12 23
13 V5 −1308 255 13 24
14 VLCD −1308 51 14 25
15 C39 −1308 −1149 17 29
16 C38 −1308 −1353 18 30
17 C37 −1308 −1557 19 31
18 C36 −1308 −1773 20 32
19 C35 −1308 −1995 21 33
20 C34 −1308 −2241 22 34
21 C33 −1014 −2241 23 35
22 C32 −726 −2241 24 37
23 R31/C31 −468 −2241 25 38
24 R30/C30 −234 −2241 26 39
25 R29/C29 −30 −2241 27 40
26 R28/C28 174 −2241 28 41
27 R27/C27 468 −2241 29 42
28 R26/C26 672 −2241 30 43
29 R25/C25 876 −2241 31 44
30 R24/C24 1080 −2241 32 45
31 R23/C23 1308 −2241 33 46
32 R22/C22 1308 −1977 34 48
33 R21/C21 1308 −1731 35 49
34 R20/C20 1308 −1515 36 50
35 R19/C19 1308 −1305 37 51
36 R18/C18 1308 −1101 38 52
37 R17/C17 1308 −897 39 53
38 R16/C16 1308 −693 40 54
2003 Apr 14 37

PCF8578
PINS
PAD NUMBER SYMBOL x y
VSO56 LQFP64
39 R15/C15 1308 −489 41 55
40 R14/C14 1308 −285 42 56
41 R13/C13 1308 −81 43 57
42 R12/C12 1308 123 44 58
43 R11/C11 1308 351 45 59
44 R10/C10 1308 603 46 60
45 R9/C9 1308 1101 47 61
46 R8/C8 1308 1305 48 62
47 R7 1308 1515 49 63
48 R6 1308 1731 50 64
49 R5 1308 1977 51 1
50 R4 1308 2241 52 2
51 R3 1080 2241 53 3
52 R2 876 2241 54 4
53 R1 672 2241 55 5
54 R0 468 2241 56 6
− n.c. − − 15, 16 14, 15, 17 to 19,
26 to 28, 36, 47
2003 Apr 14 38
2003 Apr 14
16 CHIP-ON-GLASS INFORMATION
VDD VDD
V3
V4
VLCD
VSS
CLK
SYNC
SCL
SDA
SC
0
SA
O
R
SC
O
TE
ST
VS
A3
S
D
V
C
A2
LK
V 2
SY
A1
V3
3
C
SC
A0
SA
L
4
V
0
V4
SD
TE
V 5
A
ST
D
VS
VLCD
LC
S
R
C
0
D
LK
VSS
D
R
V
SY
1
R
c.
CLK
SC
2
n.
L
SD
SYNC
3
V
A
C
V 4
SCL
D
0
LC
C
1
SDA
39
C
38
C
39
39
C
38
C
37
C
PCF8578
PCF8579
R0 to R31
C0 C1 C2
LCD
DISPLAY
PCF8578
MSA850
If inputs SA0 and A0 to A3 are left unconnected they are internally pulled to VDD.
Fig.29 Typical chip-on-glass application (viewed from the underside of the chip).

PCF8578
17 PACKAGE OUTLINES
VSO56: plastic very small outline package; 56 leads SOT190-1
D E A
X
y
HE v M A
56 29
Q
A2 A
A1 (A 3)
pin 1 index θ
Lp
L
detail X
1 28
w M
e bp
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.
0.3 3.0 0.42 0.22 21.65 11.1 15.8 1.6 1.45 0.90
mm 3.3 0.25 0.75 2.25 0.2 0.1 0.1 o
0.1 2.8 0.30 0.14 21.35 11.0 15.2 1.4 1.30 0.55 7
0.012 0.12 0.017 0.0087 0.85 0.44 0.62 0.063 0.057 0.035 0o
inches 0.13 0.01 0.0295 0.089 0.008 0.004 0.004
0.004 0.11 0.012 0.0055 0.84 0.43 0.60 0.055 0.051 0.022
Notes
1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
97-08-11
SOT190-1
03-02-19
2003 Apr 14 40

PCF8578
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2
c
y
48 33
49 32 ZE
e
E HE A
A2
(A 3)
A1
wM
θ
bp Lp
pin 1 index L
64 17
1 16 detail X
ZD v M A
e wM
bp
D B
HD v M B
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1) θ
o
1.6 0.20 1.45 0.27 0.18 10.1 10.1 12.15 12.15 0.75 1.45 1.45 7
mm 0.25 0.5 1 0.2 0.12 0.1
0.05 1.35 0.17 0.12 9.9 9.9 11.85 11.85 0.45 1.05 1.05 0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
00-01-19
SOT314-2 136E10 MS-026
03-02-25
2003 Apr 14 41

PCF8578
18 SOLDERING If wave soldering is used the following conditions must be

observed for optimal results:
18.1 Introduction to soldering surface mount
packages • Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
This text gives a very brief insight to a complex technology. smooth laminar wave.
A more in-depth account of soldering ICs can be found in
• For packages with leads on two sides and a pitch (e):
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011). – larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
There is no soldering method that is ideal for all surface transport direction of the printed-circuit board;
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch – smaller than 1.27 mm, the footprint longitudinal axis
SMDs. In these situations reflow soldering is must be parallel to the transport direction of the
recommended. printed-circuit board.
The footprint must incorporate solder thieves at the
18.2 Reflow soldering downstream end.
Reflow soldering requires solder paste (a suspension of • For packages with leads on four sides, the footprint must
fine solder particles, flux and binding agent) to be applied be placed at a 45° angle to the transport direction of the
to the printed-circuit board by screen printing, stencilling or printed-circuit board. The footprint must incorporate
pressure-syringe dispensing before package placement. solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example, During placement and before soldering, the package must
convection or convection/infrared heating in a conveyor be fixed with a droplet of adhesive. The adhesive can be
type oven. Throughput times (preheating, soldering and applied by screen printing, pin transfer or syringe
cooling) vary between 100 and 200 seconds depending dispensing. The package can be soldered after the
on heating method. adhesive is cured.
Typical reflow peak temperatures range from Typical dwell time is 4 seconds at 250 °C.
215 to 250 °C. The top-surface temperature of the A mildly-activated flux will eliminate the need for removal
packages should preferably be kept: of corrosive residues in most applications.
• below 220 °C for all the BGA packages and packages
18.4 Manual soldering
with a thickness ≥ 2.5mm and packages with a
thickness <2.5 mm and a volume ≥350 mm3 so called Fix the component by first soldering two
thick/large packages diagonally-opposite end leads. Use a low voltage (24 V or
• below 235 °C for packages with a thickness <2.5 mm less) soldering iron applied to the flat part of the lead.
and a volume <350 mm3 so called small/thin packages. Contact time must be limited to 10 seconds at up to
300 °C.
18.3 Wave soldering When using a dedicated tool, all other leads can be
Conventional single wave soldering is not recommended soldered in one operation within 2 to 5 seconds between
for surface mount devices (SMDs) or printed-circuit boards 270 and 320 °C.
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 Apr 14 42

PCF8578
18.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, not suitable(3) suitable
HTSSOP, HVQFN, HVSON, SMS
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO, VSSOP not recommended(6) suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Apr 14 43

PCF8578
19 DATA SHEET STATUS
DATA SHEET PRODUCT

LEVEL DEFINITION
STATUS(1) STATUS(2)(3)
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
20 DEFINITIONS 21 DISCLAIMERS
Short-form specification  The data in a short-form Life support applications  These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition  Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes  Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes in the products -
Characteristics sections of the specification is not implied. including circuits, standard cells, and/or software -
Exposure to limiting values for extended periods may described or contained herein in order to improve design
affect device reliability. and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information  Applications that are
communicated via a Customer Product/Process Change
described herein for any of these products are for
Notification (CPCN). Philips Semiconductors assumes no
illustrative purposes only. Philips Semiconductors make
responsibility or liability for the use of any of these
no representation or warranty that such applications will be
products, conveys no licence or title under any patent,
suitable for the specified use without further testing or
copyright, or mask work right to these products, and
modification.
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2003 Apr 14 44

PCF8578
22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 Apr 14 45

PCF8578
NOTES
2003 Apr 14 46

PCF8578
NOTES
2003 Apr 14 47
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003 SCA75

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 403512/05/pp48 Date of release: 2003 Apr 14 Document order number: 9397 750 11026

Data Sheet: LCD Row/column Driver For Dot Matrix Graphic Displays

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Data Sheet: LCD Row/column Driver For Dot Matrix Graphic Displays

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INTEGRATED CIRCUITS

LCD row/column driver for

LCD row/column driver for

LCD row/column driver for

(14, 15, 17 to 19 (11) 5

Fig.1 Block diagram.

LCD row/column driver for

LCD row/column driver for

Fig.2 Pin configuration (VSO56).

LCD row/column driver for

Fig.3 Pin configuration (LQFP64).

LCD row/column driver for

Table 1 Possible displays configurations

MULTIPLEX MIXED MODE ROW MODE

LCD row/column driver for

7.3 Multiplexed LCD bias generation 7.4 Power-on reset

Table 3 Multiplex rates and resistor values for Fig.5

MULTIPLEX RATE (n)

LCD row/column driver for

Fig.6 LCD row/column waveforms.

LCD row/column driver for

T frame state 1 (OFF)

V state 1 (t) = C1(t) R1(t): general relationship (n = multiplex rate)

V state 2 (t) = C2(t) R2(t): Voff(rms) 2 ( n 1)

Fig.7 LCD drive mode waveforms for 1 : 8 multiplex rate.

LCD row/column driver for

V state 1 (t) = C1(t) R1(t): general relationship (n = multiplex rate)

V state 2 (t) = C2(t) R2(t): Voff(rms)

Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.

LCD row/column driver for

7.5 Internal clock 7.6 External clock

Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note 1.

LCD row/column driver for

7.9 Display mode controller 7.15 RAM access

7.17 TEST pin

driver 1 driver 2 driver k

PCF8578/PCF8579 system RAM LSB

Fig.10 RAM ACCESS mode.

RAM ACCESS: bank 0

character mode bank 1

LOAD X-ADDRESS: X-address = 8

LCD row/column driver for

LCD row/column driver for

8 I2C-BUS PROTOCOL In READ mode, indicated by setting the read/write bit

LCD row/column driver for

1 byte n 0 byte(s) n 0 byte(s)

n 1 byte n bytes last byte

MSA831 n bytes last byte

LCD row/column driver for

8.1 Command decoder

conclusion of the command transfer. Further bytes will be

Table 5 Summary of commands

LCD row/column driver for

Table 6 Definition of PCF8578/PCF8579 commands

LCD row/column driver for

Table 7 Set mode option 1 Table 11 Device select option 1

LCD row/column driver for

9 CHARACTERISTICS OF THE I2C-BUS 9.4 Acknowledge

9.3 System configuration

data line change

Fig.15 Bit transfer.

LCD row/column driver for

START condition STOP condition