Received: 23 March 2020

DOI: 10.1049/ote2.12029
- -Revised: 30 October 2020

O R I G I N A L R E S E A R C H PA P E R
Accepted: 24 November 2020

- IET Optoelectronics

Implementation of all‐optical Toffoli gate by 2D Si–air photonic

crystal

Paromita De1 | Sapana Ranwa1 | Sourangshu Mukhopadhyay2

1
Department of Electronics and Communication
Engineering, National Institute of Technology,
Durgapur, West Bengal, India
2
Department of Physics, University of Burdwan,
Burdwan, West Bengal, India
Correspondence
Paromita De, Department of Electronics and
Communication Engineering, National Institute of
Technology, Durgapur, West Bengal 713209, India.
Email: paromitade2014@gmail.com
Funding information
University Grants Commission (Government of
India); Department of Physics, The University of
Burdwan
Abstract
The quantum Toffoli gate is one of the essential reversible universal logic gates widely
used for optical data processing. Herein, a new scheme of developing all‐optical Toffoli
gate using a two‐dimensional silicon–air photonic crystal is proposed. For the realization
of the Toffoli gate, the principles of constructive and destructive interference of light are
used. The Toffoli gate comprises two‐input–three‐output‐based optical AND gate, and a
two‐input–one‐output optical XOR gate. Two Y junction power splitters have been used
at the two inputs of the AND gate. The operating wavelength of the proposed Toffoli
gate is 1550 nm along with the wafer size of 50 µm � 50 µm. The performance of the
Toffoli gate has been analysed and simulated by the plane‐wave expansion method and
finite‐difference time‐domain method. The response time and contrast ratios are also
obtained from the simulation. The proposed Toffoli gate is intensity encoded with no
non‐linear material within the crystal which shows significant improvement over other
proposals.

1 | INTRODUCTION
All‐optical logic gates take a significant role in various
emerging technologies such as optical networks, optical signal
analysis, and high‐speed signal processing and networks [1]. In
optical signal processing, high‐speed data transfer and capacity
are two critical requirements for the development of the
communication system [2, 3]. Therefore, all‐optical logic gates
become one of the vital aspects of the implementation of
signal processing and networks. Realisation of all‐optical logic
gates can be achieved via various techniques such as photonic
crystals (PCs) [4–7], ring resonators [8–10], semiconductor
optical amplifiers, and so on [11].
The PC‐based logic gates have unique properties such as
high speed, simplified design, low power losses, better
confinement, and compactness. In two‐dimensional (2D) PC,
materials with different refractive indices have been placed side
by side which gives a change in refractive index in two di-
rections (X and Z) and remain constant in other direction (Y).
PCs are periodic array dielectrics that allow control over the
flow of light. Defects created in the PCs disturb the periodicity
of the crystal and enable the localisation of light. The crystals
also exhibit photonic band gaps (PBG) where specific wave-
lengths of light are prohibited from propagating within the
crystal [12–14]. Implementations of various quantum gates
using optical switches, such as Fredkin gate, Quantum Square
Root Not gate, Pauli X Y Z, etc., have already been proposed
[15–18]. PCs have also been used to implement all‐optical
logic, as well as many other optical devices necessary for op-
tical processing applications [19–22]. The Toffoli gate is one of
the most important universal reversible logic gates [23–27].
The reversibility of the Toffoli gate has been implemented in
various ways [28–31]. A method of integrating the key quan-
tum circuits with existing technology platforms to harness any
multi‐level information is demonstrated [32]. It is demon-
strated experimentally to reduce the number of controlled
operations on the physical platforms that can be applicable to
linear optics [33]. For a linear optical quantum gate using
Mach Zhender interferometer, a study on the tomographic
characterisation has been done [34]. An implementation of the
Toffoli gate using a Kerr material has been proposed where the
second‐order non‐linearity of the material exploits the princi-
ple of the changing refractive index depending on the intensity
of light [35]. The all‐optical Toffoli logic using the MZI‐SOA

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- DE ET AL.

in symmetric configuration with an extinction ratio of 18.57 dB

and Q factor of 38.10 dB used the cross‐gain modulation and
cross‐phase modulation phenomenon to get the changes in the
carrier density and refractive index of the material [11].
Quantum gates with quantum dots using single‐sided optical
microcavities have also been proposed, which use the giant
optical Faraday rotation technique induced by a single electron
spin [36]. All‐optical Toffoli gates using coupled‐resonator
optical waveguides (CROWs) have been reported that
generate a strong non‐linear interaction that helps the imple-
mentation of a single‐ and two‐qubit quantum gates [37].
Herein, the all‐optical Toffoli gate was designed and
simulated. The designed Toffoli gate has been implemented
using a 2D PC composed of silicon (Si) rods in the air. FIGURE 1 Schematic layout of the Toffoli gate
All‐optical Toffoli gate has been based on light interference
effect and gives low power consumption. The performance of T A B L E 1 Truth table of the Toffoli gate (where L indicates the
the Toffoli gate has been analysed and simulated by the presence of light (logic state 1) and N indicates no light (logic state 0))
plane‐wave expansion method (PWE) and the finite‐difference Input Output logic
AND gate XOR
time‐domain (FDTD) method. The proposed gate uses no
(I1) (I2) (I3) (I1· I2) (I1· I2)⊕I3 O1 O2 O3
non‐linear material within the crystal.
0(N) 0(N) 0(N) 0(N) 0(N) 0(N) 0(N) 0(N)

0(N) 1(L) 0(N) 0(N) 0(N) 0(N) 1(L) 0(N)

2 | DESIGN OF THE ALL‐OPTICAL 1(L) 0(N) 0(N) 0(N) 0(N) 1(L) 0(N) 0(N)
TOFFOLI GATE
1(L) 1(L) 0(N) 1(L) 1(L) 1(L) 1(L) 1(L)
All‐optical Toffoli gate using a 2D PC comprising silicon rods 0(N) 0(N) 1(L) 0(N) 1(L) 0(N) 0(N) 1(L)
in the air has been implemented. It is a three‐qubit gate with
0(N) 1(L) 1(L) 0(N) 1(L) 0(N) 1(L) 1(L)
three inputs and three outputs. Toffoli gate has two control
bits, and a third bit as the target signal. When both the control 1(L) 0(N) 1(L) 0(N) 1(L) 1(L) 0(N) 1(L)
bits are in the logic state ‘1’, the target bit changes or com- 1(L) 1(L) 1(L) 1(L) 0(N) 1(L) 1(L) 0(N)
plements favouring a NOT operation. It is observed that when
both the inputs (I1 and I2) takes the logic state ‘1’, the third
input (I3) is complemented at the output [23–25]. It is an the inputs of I1 and I2. Many researchers have reported the
interference‐based logic operation; if there is constructive concept of schematic layout of Toffoli gates with the help of
interference of light, the output has been taken as ON state AND gate and XOR gate work [28, 29]. The output of the AND
that shows the logic state ‘1’ for the normalised intensity of gate is treated as an input to the XOR operation. Outputs O1 and
0.35 or above. For output OFF state, that is, for the logic state O2 are simply taken from the inputs I1 and I2, respectively. The
‘0’ will occur due to destructive interference of input light with output of the AND (I1, I2) is XOR‐ed with the input I3 to obtain
normalised intensity below 0.25. For intensity‐based logic, the output O3.The truth table for the implementation of the
contrast ratio CR (10 log PP10 ) is defined as the logarithmic ratio Toffoli logic is given in Table 1.
of ON (P1) to OFF (P0) output power where P1 and P0 are The novelty of the current proposal is to develop a Toffoli
output power levels corresponding to the logic ‘1’ and logic ‘0’. gate that is very small in size (50 µm � 50 µm) PC wafer
It is better to have a high contrast ratio or ON to OFF ratio. operated at 1550 nm wavelength without non‐linear element
Destructive and constructive interferences between the inputs within the crystal.
signals provide low‐ and high‐output power levels corre- The use of the PC ensures that the implementation of the
sponding to the logic ‘0’ and the logic ‘1’ [4]. Therefore, Toffoli gate in a minimal system volume with very low light
reducing the output power level (P0) further increases the CR. intensity. As the gate inputs and outputs are intensity encoded,
This CR can be controlled by the proper change of the silicon conditional and sequential gate systems can also be organised.
rod dimensions in the interference points in the crystal.
Being intensity‐based logic, it has the advantage of the stage‐
by‐stage cascading with proper fan‐out. An AND gate and an 3 | SILICON–AIR TWO‐DIMENSIONAL
XOR gate have been cascaded to get the Toffoli logic [25]. The PHOTONIC CRYSTAL
principle of constructive and destructive interferences of light
has been used to design the AND XOR logic [4]. The symmetric The designed 2D silicon–air PC has a wafer dimension of 50
layout for the proposed Toffoli logic is shown in Figure 1. Here µm � 50 µm with 43 � 35 silicon rods in a square lattice.The
we have three inputs marked as I1, I2, and I3 and three outputs lattice constant of the crystal is 670 nm and the refractive index
marked as O1, O2, and O3 and two Y junction power splitters at of the silicon is 3.49. The r/a of the silicon rods is 0.2 where r
DE ET AL.
FIGURE 2 Band gap of designed crystal
FIGURE 3 Layout of Y junction power splitter
is the radius of the rods and a is the lattice constant. The
band gap of the unperturbed lattice for TE polarisation is
shown in Figure 2 which exists for the value from 0.348693 to
0.449631. The corresponding wavelength to the band gap is
1490–1921 nm. The wavelength used for the simulation of the
Toffoli gate is 1550 nm.
4 | IMPLEMENTATION OF TOFFOLI
GATE
For its implementation, two power splitters (PS), PC‐based
AND gate, and XOR gate are essential [4, 20].
4.1 | Power splitter
The layout of a Y branch PS (Figure 3) is designed with an
input port and two output ports. Three rows of the silicon rods
have been removed to create line defects to design the Y
branch PS. The input signal at the input port is divided into
two channels, which gives the output of the power splitter at
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FIGURE 4 Performance of the power splitter
Port A and Port B. There are 21 � 21 silicon rods with r/a 0.2
and lattice constant 670 nm.
The performance of the designed Y junction PS can be
seen in Figure 4. The normalised output at Port A is 0.45 and
at port B is 0.45 at the wavelength of 1550 nm. Two PSs of the
same design and performance have been used in the proposed
Toffoli gate.
4.2 | Design of AND gate
The all‐optical AND gate has been designed with two input
ports and three output ports. In the layout of the AND gate
shown in Figure 5, where two PSs have been used, one each
for the two inputs (I1 and I2). There are three outputs (O1, O2,
and O3). The outputs, O1 and O2 correspond to the inputs I1
and I2, respectively, and the output O3 is from the AND
operation of I1 and I2. The gate is implemented with silicon–air
2D PCs.
The waveguides have been created in the crystal with the
help of line defects by removing an entire row of the silicon
rods [12]. The 1550‐nm‐wavelength light wave can propagate
142
- DE
FIGURE 5 Layout of AND gate
through this waveguide. If there are no extra rods, the intensity
of the light wave at the output port should be the same as the
input port for a two‐port waveguide. In case of the AND gate,
at the junction, there are two sets of rods r1 and r2. The r/a
ratios of r1 and r2 are 0.05 and 0.02, respectively. The nor-
malised intensity available at the output port can be adjusted
with these extra rods. The transmission to the output port can
be increased or decreased by reducing or enlarging the radius
of the rods, respectively. In case there are no extra rods, the
intensity of the light wave at the output port should be the
same as the input port [4, 12–14]. So, in this case, these are
reflector rods which help in optimising the transmission and
achieve a better contrast ratio.
Line defects have been created to design the PS and the
output ports of the AND gate. The design of the AND gate is
shown in Figure 6. The AND gate is at the T junction of the
three arms of the two inputs and the output port (O3). These
rods have been inserted to control the transmission of the light
towards the output ports. The proposed design of the rods in
the AND gate is optimising the transmission for logic ‘0’ and
achieve a high contrast (ON–OFF) ratio. The path length of
both the inputs (I1 and I2) is the same, and hence at the T
junction, constructive interference takes place. With only one
input present (I1 = 1 and I2 = 0), because of the presence of
the rods r1 and r2, it gives transmission at the output O3
corresponding to the logic level ‘0’. With both the inputs
present (I1 = I2 = 1), the strength of the signal at the output
port corresponds to the logic level ‘1’ (Table 2) due to the
constructive interference at the T junction (Figure 6). The
performance of the designed AND gate is shown in Table 2.
When both input I1 = I2 = 0, the transmission is low, and
the gate assumes at a logic state ‘0’. With only one input
available (I1 = 1 and I2 = 0), the output transmission (O3) is in
ET AL.
FIGURE 6 Design of AND gate
the logic state ‘0’. With both the inputs in the ON state
(I1 = I2 = 1), the output port O3 will receive 0.69 normalised
intensity due to constructive interference, which depicts the
logic state ‘1’. The contrast ratio for AND gate is 4.9 dB.
There are also outputs O1 and O2 that have one‐to‐one
mapping with inputs I1 and I2, having the CR of 7.6 dB.
The simulation result for the AND gate is shown in
Figure 7. With input I1 in the ON state and I2 OFF, it is seen
that there is no output at O2 (Figure 7a). The transmission at
output O1 (Figure 7a) is sufficiently high to be in the logic state
‘1’. The AND gate output port O3 (I1·I2), and the intensity at
the output is low corresponding to the logic state ‘0’. Similarly,
with only I2 = 1, I1 = 0 input, there is output available at O2
(logic state ‘1’). For the outputs O1and O3, the transmission at
the output is low corresponding to the logic state ‘0', which is
also shown in Table 3. With both the inputs I1 and I2 available,
as shown in Figure 7c, the outputs O1, O2, and O3 are in the
logic state ‘1’. The transmission at the output O3 is sufficiently
high due to the constructive interference at the T junction and
assumption at the logic state ‘1’.
4.3 | Design of XOR gate
The layout of the XOR gate is shown in Figure 8. Port A and
Port B are considered as the input port, and Port 3 is
considered as the output port. At the junction of each inputs,
there are three rods r3 with ratio r/a = 0.04. These rods help to
control the transmission of the light towards the output so as
to achieve an optimised design for a high CR. The XOR gate is
based on the principle of destructive interference.
With phase difference and path differences (2n + 1)π and
(2n + 1) λ/2, respectively (where λ is the free space wavelength
of the light and n is a +ve integer), the destructive interference
occurs.When both inputs are in the same phase initially,
the phase of one of the inputs can be varied by using a
phase shifter or by the variation of length of the arms (input
DE ET AL.
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TABLE 2 Performance of the designed AND gate

Input Output
CR (dB) Output
I1 I2 O1 O2 for O1 and O2 transmission (O3) Logic (I1·I2) CR (dB) for O3
0 0 0 0 7.6 0 0 4.9
0 1 0 0.45 0.22 0
1 0 0.47 0 0.22 0
1 1 0.47 0.45 0.69 1

FIGURE 8 Layout and design of XOR gate

when both the inputs are available, there is negligible trans-

FIGURE 7 Simulation result of AND gate
to the junction of XOR gate). In this simulation, two arms of
the XOR gate have different arm lengths, which introduced
path difference for input signals. The proposed XOR
gate designed with a lattice constant of 670 nm for the
designed crystal and the light wavelength of 1550 nm for the
simulation. So, the ratio of wavelength to the lattice constant
(a) is = 2.313.
When both the inputs are at the same phase, introducing a
path difference in the order of n2 a; 3n 2 a; 2 a; …, it gives
5n
destructive interference at the junction. In this XOR design,
the arm length of both inputs is taken 8a and 13.7835a (8a +
2 a), correspondingly. For the XOR gate, one arm is 8 � a
5n
� �
path length and the other arm is 8a þ 5n 2 a which is
13.7835a or 14a path length. It will introduce a phase differ-
ence of 180° between the two input arms. The performance of
the designed XOR gate is shown in Table 3. It is observed that
mission at the output. When only one input is present, either
input A or input B, only then the normalised transmission at
the output port achieves the logic state ‘1’. The contrast ratio
of the designed XOR gate is 7.6 dB. The simulation result of
the XOR gate is shown in Figure 9.
Figure 9a shows simulation results corresponding to the
inputs A and B equal to 1; there is destructive interference at
the junction and negligible transmission available at the output
(logic state ‘0’). With only one input present (A for Figure 9b
and B for Figure 9c), there is sufficient transmission at the
output port shown at the logic state ‘1’.
4.4 | Design of all‐optical Toffoli gate
The proposed Toffoli gate is an all‐optical reversible logic
with three inputs and three outputs. All the inputs are
assumed to have the same phase at the input, which is only
possible if they are drawn from the same source. The sche-
matic layout to implement the Toffoli logic gate operation is
already stated in Figure 1. There are two PSs, an AND gate
and an XOR gate have been used for the implementation of
the Toffoli gate. The design and layout of the Toffoli gate are
shown in Figure 10. The proposed Toffoli gate has three
inputs (I1, I2, and I3) and three outputs (O1, O2, and O3)
along with two junctions J1 and J2. The outputs O1 and O2
have one‐to‐one mapping with I1 and I2. For the third output
O3, the AND‐ed output of I1 and I2 is XOR‐ed with the
input I3, the operations of which takes place at junctions J1
144
- DE
Output
Input A Input B transmission (Pout/Pin) Output logic
0 0 0 0
0 1 0.7 1
1 0 0.7 1
1 1 0.12 0
FIGURE 9 Simulation result of XOR gate
and J2, respectively. Line defects have been used to design the
waveguides in Figure 10.
The detailed design of the proposed Toffoli gate is shown
in Figure 11. The designed J1 junction for inputs I1 and I2 is
having three r1 rods (ratio r/a = 0.04) that have been opti-
mised for the best performance of the Toffoli operation, and
these rods control the light towards the output and also
control the transmission to the junction J1. The AND
operation of I1 and I2 takes place at JI. The path lengths for
the inputs I1 and I2 are the same length of 48a from the
input port to the output port O3 and for I3, the path length
is 31a from the input to the output port O3. Therefore, when
both I1 and I2 are present at J1, it shows constructive
interference. The junction J2 operation shows results corre-
sponding to the XOR gate and destructive interference oc-
curs at this junction. Here the AND‐ed output of I1 and I2
(I1·I2) is XOR‐ed with I3. For the input arm of I3, there are
rods r4 of ratio r/a 0.05. The other input to the XOR gate
has rods r1 at the junction J2. There rods direct light towards
the output and also control transmission. Reflection rods r1
at junction J2 of ratio r/a0.04 are used. These rods help in
reducing reflections at the junction. The arms of junction J2
have different path lengths so that the inputs become in
different phases, and destructive interference takes place at
this junction (Table 4, Figure 10). If both the inputs are of
the same amplitude and opposite phase, then complete
ET AL.
T A B L E 3 Performance of the XOR gate
designed for the Toffoli gate
Output CR (dB)
7.6
FIGURE 10 Designed layout of Toffoli gate
destructive interference happens. If either of the input is
having a different amplitude or the phase is not opposite or
in both situations, then there will be some transmission (apart
from some destructive interference of I3 with I1 and I2) at
the output of the XOR gates.
In a Toffoli gate, there are three inputs and three outputs,
two of the bits as the control bit and the third bit as the
target bit. When both these control bits are present, then
the target bit complements. When both the control bits are
present (I1 = I2 = ON), and I3 is OFF, then due to the
constructive interference of I1 and I2 at junction J1, the
output at O3 has sufficient transmission to be in the logic
state ‘1’. When I3 is ON and both the control bits I1 = I2 =
ON, then at junction J2 (Figure 10), destructive interference
takes place; therefore, the transmission intensity at the output
O3 is very less and goes to the logic state ‘0’. The outputs O1
and O2 have one‐to‐one correspondence with inputs I1 and
I2, which are obtained from PS1 and PS2, as shown in
Figure 10. The transmission intensity at O1 and O2 is suffi-
cient to be at the logic state ‘1’ and is obtained when the
inputs I1 and I2 are ON, respectively. The CR for Port O3 is
5.2 dB, and for Ports O1 and O2 are 8.7 dB. The perfor-
mance of the Toffoli gate is given in Table 4.
DE ET AL.
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FIGURE 11 Design of the Toffoli gate

TABLE 4 Truth table of the simulated result of the Toffoli gate

Output
transmission
Input power ðPPoutin Þ Output logic
AND logic XOR logic Contrast ratio Contrast ratio
Input 1 (I1) Input 2 (I2) Input 3 (I3) (I1· I2) (I1· I2) ⊕ I3 O1 O2 O3 O1 O2 O3 (CR) for O1 and O2 (CR) for O3
0 0 0 0 0 0 0 0 0 0 0 8.7dB 5.2dB

0 1 0 0 0 0 0.45 0.12 0 1 0
1 0 0 0 0 0.46 0 0.11 1 0 0
1 1 0 1 1 0.46 0.45 0.37 1 1 1
0 0 1 0 1 0 0 0.55 0 0 1
0 1 1 0 1 0 0.45 0.39 0 1 1
1 0 1 0 1 0.45 0 0.41 1 0 1
1 1 1 1 0 0.46 0.45 0.09 1 1 0

FIGURE 12 Simulation result of the Toffoli

gates
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FIGURE 13 (a) Path length versus.phase change. (b) Phase change of the propagating wave with respect to λ/a for the propagation of the 1550‐nm light
wave
FIGURE 14 Time‐domain response of the Toffoli gate
To implement the Toffoli gate, we have selected the rod
dimensions and the r/a ratio in such a way that the
constructive and destructive interferences occur at the
proper places of the junctions to execute the overall Toffoli
operation.
The simulation result of theToffoli gate in Figure 12 shows
the different logic states of outputs for the various input states.
With only I3 in ON state (Figure 12a), the output O3 has
sufficient transmission at the output (Table 4) and it will be in
the ON state.
When I1 and I3 are in the ON state (Figure 12b), there is
output at O1 and O3. The output O2 is in the logic state ‘0’. The
transmission of I1 from junction J1 is very less (Table 2), whereas
I3 has sufficient transmission intensity (Table 4), so the output
O3 has sufficient transmission to be in the logic state 1. With two
inputs I1 and I2 in the ON state and I3 OFF state, then outputs
O1 and O2 are in the logic state ‘1’. The inputs I1 and I2 undergo
AND operation, and due to constructive interference at J1
ET AL.
FIGURE 15 Time‐evolving curve of the Toffoli gate
junction, transmission intensity of the output O3 goes to the
logic state ‘1’ as shown in Figure 12d. With all the three inputs in
the ON state, there is output only at O1 and O2. The output O3 is
complemented as in junction J2 as destructive interference oc-
curs between I3 and the AND operated output of I1 and I2
(Figure 12c). Hence transmission intensity at output O3 is less
(Table 4), which confirms the logic state.
In Figure 13a,b, the graphs show the variation of the phase
of the 1550‐nm light wave propagating in the crystal lattice of
the lattice constant 670 nm. For every 2.313 � a distance of
the lattice, there is a phase variation of 2π.
The time‐domain response of the gate is shown in
Figure 14. The time‐domain response of the Toffoli gate has
been obtained at the output port. Response time and bit rate of
the proposed Toffoli gate have been calculated from the time‐
evolving curve as shown in Figure 15. The response time and
bit rate of the input signal for the designed Toffoli gate are
0.5333 ps and 1.85 Tbps, respectively.
DE ET AL.
5 | CONCLUSION
Quantum logic systems are fundamental structures for quantum
computing. The proposed Toffoli gate is an implementation
using a 2D photonic silicon–air crystal and it is an all‐optical
universal reversible gate that has much importance in revers-
ible optical processing. The implementation is simple, compact,
and no non‐linear material has been used for the switching
purposes. The wafer size of 50 µm � 50 µm is enough for its
implementation. The wavelength used for the simulated results
is 1550 nm which is widely used in the C band. The Toffoli gate
operates on the principle of constructive and destructive in-
terferences of light with all the inputs initially in the same phase
and drawn from a single source of light. The logic is an intensity‐
based operation and hence can be cascaded with proper fan‐out.
The simulated result shows the response time of 0.533 ps with
the bit rate of 1.85 Tbps (much higher than previous reported
work), along with the gate CR of 8.7 and 5.2 dB. In the realisation
of the whole scheme, a two‐input and three‐output AND gate
with CR 7.6 and 4.9 dB is also demonstrated. The Toffoli gate
can be integrated with optical and photonic nano cavities. In a
bulk wafer, such quantum logic gates can be developed by
cascading. The present system is designed for a wavelength of
1550 nm.
ACKN OW LE DG E ME N T
The authors acknowledge the Centre for Advanced Studies
(CAS) programme funded by University Grants Commission
(Government of India), Department of Physics, The University
of Burdwan, for the partial financial support to conduct the
research.
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