Novel Approach for Search Engine

Yoichi Sato, Kanji Otsuka, Kaoru Kobayashi*, Toshiyuki Kouchi*, Minoru Uwai*, Masato Nishizawa*
Meisei University, Collaborative Research Center
2-1-1 Hodokubo, Hino-shi, Tokyo 191-8506 Japan
Nagase & Co., Ltd
otsuka@gad.meisei-u.ac.jp

ABSTRACT
This is well known that IoT needs intelligent search engines to
manage big data processing. We have been developing such issues
with novel algorithms.
CAM (Contents Addressable Memory) conducts high speed
searching with high power consumption which is not productive. The
LUT (Look Up Table) algorithm with certain software is one type of
method that is utilized to save power and commonly found in today..
However there is possibility of a reduced search speed it using the
sequential software method. The method used in our study produces
high speed searching with low power due to the address-to-data
search algorithm on LUT when compared with the regular data-to-
address step. This reversal approach has considered historically.
However address collisions occur prolifically and could not be a
zero-based probability. In the study of our algorithm developed a
zero-based probability process which is accomplished by key data
division and only division data searching steps resulted in high speed
and low power output.
COMPARISON OF CAM AND AXONERVE
OPERATION STEPS
Almost all current methods for data searching have been in
data bits coincidence processing. The searching method for
CAM is the typical approach as shown in Figure 2. In one
instance, the matched address that is accessed by activation of
all of the memory generates the search key data-01101 inputs
to the search line driver, whereby all the vertical data lines are
hit by it at the same time. The address lines are hit by the all
data lines and then a coincident line is activated only.
Connecting the sense amp drives the right address to encoder.
Finally the right address (i.e. 01) is produces the outputs for
the search data of 01101.

INTRODUCTION
IoT manages larger and more complex databases. Find data
quickly in a large database can be very difficult and time-
consumption. Smarter search engine will look to find information
quickly with high speed and low power output. One of highest search
engine is CAM (Contents Addressable Memory)[1][2][3] but ti is well
known for its high power consumption due to the need for
simultaneous activity in the entire memory mat as shown in Figure 1
above. Search engine software based nowadays is in the LUT
algorism; however, there is growing dissatisfaction with LUT’s
processing speed. An novel approach developed by our group was
utilized successfully that was named as “AxonerveTM ” with high
speed and low power output as shown in Figure 1 below. That can be FIGURE 2. CAM O PERATION FEATURE IN CASE OF
seen one entry address activations enough for the search. 5BITS DATA

Simultaneous activation of all memory requires great deal of

power compared to conventional memory access operation as shown
in Figure 2 right-below which requires single memory activation.

As mentioned before, CAM and software based LUT algorithms

are data-to-address step and address-to-data step as counter algorithm
has not been commercialized yet due to the made prolifically
collisions with many discussion[4][5]. Our approach as Axonerve has
been developing successfully on the address-to-data step with smart
idea that includes “don’t care” concept. This searching process will
be mention as shown in Figure 3 for write and Figure 4 for lead.

Specific registered data group is shown in the upper-right table

which includes data address (DA) and decimal figures. The binary
data is divided into 6 segments with two bits each. The middle two
FIGURE 1. GLANCE OF SEARCH ACTIVATION FEATURE tables are for search memory mats. The first word write step is

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 represented by the color green the middle-upper table. The DA=00’s
data shifts to Register Address (RA) of 10 at the first segment as the
00 of DA that is the write operation. In the same manner, the 10, 10,
00, 11 are allocated as the like. It should be noted that the allocation
figures are DA=00 and is an important concept for the algorithm. In
other word, RA is just the two divided data.
There would be found that all the collision occurs with some of
the probability in one RA. In this occasion, the extraction can be not.
The probability is figured out principally in our study as shown in
Figure 5 and 6.
Figure 5 indicates the probabilities of each function in write,
collision and empty entries which can make over entries because of
empty segment existence. When the number of entries is the same of
RA number that is the ratio of 1 on the horizontal axis, all the
collision probability is conducted to the 0.26 in a normalized
segment. Figure 6 shows all of the collision probability that relates
the number of segment power of the 0.26. If large database is
managed in actual, over 10 segments would be operated that is
negligible probability for all the collision in random database. The
address for IPv4 and IPv6 often deviates from random data. The
deviation data should be treated to the dispersion figures of the key
entry data that we already developed successfully.

FIGURE 3. WRITE ALGORITHM OF AAXONERVE ON AN

EXAMPLE
The 2nd to 4th data is written on the same mat as the middle-lower
table. In the 2 nd row of data represented by the color orange the first
segment of two bits RA11 can be written as 01 but the second
segment of the two bits 10 is a collision. Then this segment function
changes to “don’t care” which means the blind subsequent ignore
represented by the red color. The same manner of the step follows all
the collisions that mean 5 segments signed red color. The 3 rd to 4th
steps also the same operation is done for all of the data registered as
shown by the middle-below table. We can see many collisions (red
color) remarkably.
FIGURE 4. T HE ALGORISM HOW TO SEARCH DATA
Below table is the confirmation memory that copies the registered
memory table itself.

Figure 4 indicates how to operate the search using the registered

search memory mat. If we want to search the data of 2697 that is 10
10 10 00 10 11 in binary code, the searching step can be done. Refer
to upper-left table which shows black allows in each binary of the
segments. Then RA=10 line is picking up as shown in upper-right
colored line. Significant information is drawn from the 00 from the
three segments. After that we would know possibly as the DA=00
excepted the three “don’t care” segments. So the confirmation is
completed as represented by the upper-right of the second row green
binaries without unmatched figures. Finally we can extract the
DA=00.

Another two examples are shown in middle-left and below-left

tables. On 3779 searching case, only one segment can be valid-
DA=01. However, right data address i.e. DA=01 is extracted here.
On the 1504 searching case, the emptied segments introduce the FIGURE 5. EACH P ROBABILITY IN WRITE COLLISION
DA=11 information which does not match. Tthe 1504 shows no data AND EMPTY ENTRIES
in the database.

COLLISION PROBABILITY ON AXONERVE

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FIGURE 6. ALL C OLLISION PROBABILITY IN R ANDOM
PERFORMANCE COMPARISON WITH AXONERVE AND
CAM
As search speed analytical comparison between Axonerve and
CAM is shown in Figure 7 that is the same machine cycle. However
Axonerve reached higher clock speed than CAM. That is why
Axonerve architecture is used by all conventional SRAM (Static
Random Access Memory) circuits and compared to larger specific
designed CAM circuits.
Composition of conventional SRAM circuits of Axonerve is
saving the chip area as shown in Figure 8 and compares with CAM
when the design meets the same conditions.
FIGURE 7. MACHINE CYCLE OF AXONERVE AND CAM
FIGURE 8. CHIP AREA C OMPARISON
IEEE XPLORE CATALOG NUMBERS: CFP1659B-ART ISBN: 978-1-5090-4769-7
T ABLE 1. POWER COMPARISON DESIGN IN KEY DATA LENGTH 144BITS AND
4 K ENTRIES
Power comparison of specific design trial is done in case of 144
bit length on key data and 4k word entries is shown in Table 1 which
result to one order magnitude saving power in Axonerve.
CONCLUSION
The purpose of this study is only to introduce the content of how
to produce high speed and low power results. This is validated by
one segment matting enough and even other segment collisions all
which is very novel architecture. No one has been managed by the
similar approach that is huge collisions ignore as “don’t care” idea.
In conclusion we found major performance areas:
(1) Realization of low power compared with CAM
one as inversed relation of entry numbers that is the
address-to-data step.
(2) Receiving higher speed searching than even
CAM.
(3) Easier circuit design with conventional SRAM
with smaller size.
Axonerve has been already marketed now as Nagase & Co.’s IP
with many improvements.
REFERENCES
[1] Robert M. Colomb, [2]Kostas Pagiamtzis, Ali Sheikholeslami,
Content-Addressable Memory (CAM) Circuits and
Architectures: A Tutorial and Survey, IEEE SOLID-STATE
CIRCUITS, VOL. 41, NO. 3, MARCH 2006
[3] Kostas Pagiamtzis, Ali Sheikholeslami, Using Cache to
Reduce Power in Content-Addressable Memories (CAMs),
IEEE 2005 CUSTOM INTEGRATED CIRCUITS
CONFERENCE, 2005
[4] David Anthony New, Gus Yeung, Martin Jay Kinkade, David
John Willingham, US7606108 B2, registered 7. Nov. 2007
[5] Paul C. van Oorschot, Michael J. Wiener, Parallel Collision
Search with Application to Hash Functions and Discrete
Logarithms, www.certainkey.com/dnet/acmccs94.pdf, August
17,1994
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 ACKNOWREGEMENT
IVery much appreciate the D-Clue members to support for
supporting during development of Axonerve.

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