Electronics Projects

Vol. 22
 EFY Books & Publications
FOR YOU
EFY is a reputed information house, specialising in electronics and information technology
magazines. It also publishes directories and books on several topics. Its current publications are:
(A) CONSTRUCTION PROJECTS
1. Electronics Projects, Vol. 1: A compilation of selected construction projects and circuit ideas Rs 120
published in Electronics For You magazines during 1979 and 1980.
2. Electronics Projects, Vol. 2 to 19 (English version): Yearly compilations (1981 to 1998) of Rs 120 (each)
interesting and useful construction projects and circuit ideas published in Electronics For You.
3. Electronics Projects, Vol. 20, 21 and 22 (with CD): Yearly compilations (1999 to 2001). Rs 150 (each)
4. Electronics Projects, Vol. 16 (fgUnh laLdj.k): Yearly compilations (1995) of interesting and Rs 95
useful construction projects and circuit ideas published in Electronics For You.
(B) OTHER BOOKS
1. Learn to Use Microprocessors (with loppy): By K. Padmanabhan and S. Ananthi (fourth enlarged edition). Rs 180
An EFY publication with loppy disk. Extremely useful for the study of 8-bit processors at minimum expense.
2. ABC of Amateur Radio and Citizen Band: Authored by Rajesh Verma, VU2RVM, it deals Rs 75
exhaustively with the subject—giving a lot of practical information, besides theory.
3. Batteries: By D.Venkatasubbiah. Describes the ins and outs of almost all types of batteries used Rs 60
in electronic appliances.
(C) DIRECTORIES
1. EFY Annual Guide: Includes Directory of Indian manufacturing and distributing units, Buyers’ Guide and Rs 300 (with CD)
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2. ‘i.t.’ Directory: First comprehensive directory on IT industry covering hardware, software, telecom, Rs 250 (with CD)
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on key industry trends through its regular assortment of Market Surveys and other important information.
5. ePower: Published every alternate month for the electronic-power industry, primarily consists of all electronic Rs 50
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those catering to it.
6. BenefIT: A technology magazine for businessmen explaining how they can beneit from IT. Rs 20

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ELECTRONICS
PROJECTS
VOL. 22

EFY Enterprises Pvt Ltd

D-87/1 Okhla Industrial Area, Phase-1
New Delhi 110020
 © EFY Enterprises Pvt Ltd.
First Published in this Edition, December 2006

All rights reserved. No part of this book may be reproduced in any

form without the written permission of the publishers.

ISBN 81-88152-17-X

Published by Ramesh Chopra for EFY Enterprises Pvt Ltd,

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Typeset at EFY Enterprises Pvt Ltd and
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 FOREWORD
This volume of Electronics Projects is the twenty second in the
series published by EFY Enterprises Pvt Ltd. It is a compilation
of 21 construction projects and 66 circuit ideas published in
‘Electronics For You’ magazine during 2001.

We are also including a CD with this volume, which not only con-
tains the datasheets of major components used in construction proj-
ects but also the software source code and related files pertaining
to various projects. This will enable a reader to copy these files
directly to his PC and compile/run the program as necessary, without
having to prepare them again using the keyboard. In addition, the CD
carries useful software, tutorials and other goodies (refer ‘contents’
in CD).

In keeping with the past trend, all relevant modifications, corrections

and additions sent by the readers and authors have been incorporated in
the articles. Queries from readers along with the replies from authors/
EFY have also been published towards the end of relevant articles. It
is a sincere endeavour on our part to make each project as error-free
and comprehensive as possible. However, EFY cannot resume any
responsibility if readers are unable to make a circuit successfully, for
whatever reason.

This collection of a large number of tested circuit ideas and

construction projects in a handy volume would provide all classes
of electronics enthusiasts—be they students, teachers, hobbyists or
professionals—with a valuable source of electronic circuits, which
can be fabricated using readily-available and reasonably-priced
components. These circuits could either be used independently or in
combination with other circuits, described in this and other volumes.
We are sure that this volume, like its predecessors, will generate tre-
mendous interest among its readers.
 CONTENTS

Section A: Construction Projects

1. Build Your Own Pentium III PC ................................................................................. 3

2. Automatic Room Light Controller.............................................................................. 17
3. Intelligent Water Level Controller .............................................................................. 21
4. A Unique Liquid Level Indicator ................................................................................ 25
5. Interface Your Printer with 8085 Microprocessor ...................................................... 28
6. Morse Processor.......................................................................................................... 33
7. Access-Control System ............................................................................................... 42
8. Telephone Line-Interfaced Generic Switching System .............................................. 46
9. Programmable Melody Generator .............................................................................. 55
10. Auto Control for 3-Phase Motors ............................................................................... 66
11. Telephone Remote Control ......................................................................................... 72
12. Microcontroller-Based School Timer ......................................................................... 75
13. Digital Capacitance-cum-Frequency Meter ................................................................ 80
14. Fluid-Level Controller with Indicator......................................................................... 84
15. MGMA—A Mighty Gadget with Multiple Applications ........................................... 87
16. Trafic and Street Light Controller ............................................................................. 91
17. Lead-Acid Battery Charger with Active Power Control ............................................. 98
18. Amplitude Measurement of Sub-Microsecond Pulses................................................ 101
19. Automatic Submersible Pump Controller ................................................................... 104
20. Transistor Curve Tracer .............................................................................................. 107
21. Tripping Sequence Recorder-cum-Indicator............................................................... 113

Section B: Circuit Ideas

1. Electronic Starter for Single-Phase Motors ................................................................ 119

2. Modem ‘On/Off’ Indicator ......................................................................................... 120
3. Touch-Select Audio Source ........................................................................................ 121
4. Precision Attenuator with Digital Control .................................................................. 121
5. Precision Ampliier with Digital Control .................................................................... 122
6. Random Number Generator Based Game .................................................................. 123
7. 9-Line Telephone Sharer ............................................................................................. 124
8. Electronic Card Lock System ..................................................................................... 126
9. Pulsed Operation of a CW Laser Diode...................................................................... 127
10. Generation of 1-Sec. Pulses Spaced 5-Sec. Apart ...................................................... 128
11. High-/Low-Voltage Cutout with Timer....................................................................... 129
12. Automatic Heat Detector ............................................................................................ 130
13. Musical ‘Touch’ Bell................................................................................................... 131
14. Non-Contact Liquid-Level Controller ........................................................................ 131
15. High-Power Bicycle Horn .......................................................................................... 133
16. AC Mains Phase-Sequence Indicator ......................................................................... 133
17. Luxurious Toilet/Bathroom Facility ........................................................................... 135
18. EEPROM W27C512 (Winbond) Eraser ..................................................................... 136
19. Intelligent Electronic Lock ......................................................................................... 137
20. Stable 455KHz BFO for SSB Reception .................................................................... 139
21. Auto Shut-off for Cassette Players and Ampliiers ..................................................... 139
22. House Security System ............................................................................................... 141
23. Simple Water-Level Indicator-cum-Alarm ................................................................. 142
24. Precision Inductance and Capacitance Meter ............................................................. 142
25. Under-/Over-Voltage Beep for Manual Stabiliser ...................................................... 144
26. Ultra-Sensitive Solidstate Clap Switch ....................................................................... 145
27. 15-Step Digital Power Supply .................................................................................... 145
28. Microphone for Computer .......................................................................................... 147
29. Versatile Zener Diode Tester....................................................................................... 147
30. DTMF Proximity Detector.......................................................................................... 149
31. Stepper Motor Control ................................................................................................ 149
32. Low-Cost Intercom ..................................................................................................... 150
33. High-Power Car Battery Eliminator ........................................................................... 151
34. Automatic Plant Irrigator ............................................................................................ 152
35. Simple Telephone Ring Tone Generator ..................................................................... 152
36. Dual-Input High-Fidelity Audio Mixer....................................................................... 153
37. Unipolar/Bipolar Triangular and Bipolar Square Wave Generator............................. 154
38. Anti-Theft Security for Car Audios ............................................................................ 155
39. PC-Based Dial Clock-cum-Electronic Roulette ......................................................... 156
40. Long-Range Cordless Burglar Alarm ......................................................................... 157
41. Water-Level Controller ............................................................................................... 158
42. Invisible Broken Wire Detector .................................................................................. 160
43. PC-Based Multi-Mode Light Chaser .......................................................................... 161
44. Fuse Status Indicators for Power-Supplies ................................................................. 163
45. A Hierarchical Priority Encoder ................................................................................. 164
46. Digital Mains Voltage Indicator .................................................................................. 165
47. Electronic Dice ........................................................................................................... 166
48. Light-Operated Organ ................................................................................................. 168
49. Stereo Tape Head Preampliier for PC Sound Card .................................................... 168
50. Heart Beat Monitor ..................................................................................................... 169
51. Digital Fan Regulator.................................................................................................. 170
52. Running Lights and Running Holes............................................................................ 171
53. A Simple Transistor Tester .......................................................................................... 172
54. 12V, 3A Power Supply ................................................................................................ 172
55. Speller Effect Sign Display......................................................................................... 173
56. Darkroom Timer ......................................................................................................... 174
57. Active Shortwave Antenna ......................................................................................... 174
58. Long-Range Target Shooter ........................................................................................ 175
59. Power Supply for Walkie-Talkies ............................................................................... 176
60. High-Performance Interruption Detector .................................................................... 177
61. Digital Relay Tester for RAX and MAX .................................................................... 178
62. Fastest Finger First Indicator ...................................................................................... 179
63. Decorative Signboard ................................................................................................. 180
64. Condenser Mic Audio Ampliier ................................................................................. 181
65. Smoke Alarm .............................................................................................................. 182
66. Overload Protector with Reset Button ........................................................................ 183
 SECTION A:
CONSTRUCTION PROJECTS
Page = 1
 BUILD YOUR OWN
PENTIUM III PC
K.C. BHASIN AND NEERAJ KUNDRA

T
he procedure presented here there must be some slack after these ence between them.
would enable you to assemble are installed and connected.) This will The motherboard contains sensitive
your own multimedia personal improve the cooling and reduce the components, which can be easily dam-
computer. It is assumed that you have a chances of electromagnetic interfer- aged by static electricity. Therefore the
fundamental knowledge of how a PC func- motherboard should remain
tions and some basics of electronics. By in its original antistatic
way of tools you only need Philips-head envelope until it is required
and at-blade screwdrivers. A simple mul- for installation. When it is
timeter is the only test equipment that taken out from the enve-
you would ever require during assembly, lope, it should be immedi-
for AC and DC voltage measurement. ately placed on a suitable
All the parts needed to assemble grounded conductive sur-
this multimedia PC with processor face. The motherboard itself
speed of 700 MHz are listed under Parts should be held from edges
List. The cost of parts may vary from and the person taking it
dealer to dealer and also with time.
It is suggested to source these items
from authorised dealers who would meet
their warranty obligations. We have also
mentioned the brand names of the parts
that we used during assembly of the basic
unit. It is, however, not necessary to use
identical makes, except, of course, the
main processor and the motherboard,
based on identical chipset mentioned later
in this article.

Precautions
Before starting the actual assembly of
the PC system, the following precautions
would help you to avoid any mishap dur-
ing the assembly process:
While the motherboard has to
be fitted at a fixed place inside the
PC cabinet, the locations of add-on
cards (as and when used) and the
drives (hard disk drive, floppy disk
drive, and CD-ROM drive) within
the drives’ bay of the cabinet can be
changed within certain limits. But it
is better to place them far away from
each other. (Of course, the length of
the cable provided for interconnec-
tions to the motherboard or add-on
cards has to be taken into account, as Fig. 1: Block diagram of motherboard employing 810E chipset

ELECTRONICS PROJECTS Vol. 22 3

 would be some differences between any two
Key Features of Motherboard Using Intel 810/810E Chipset makes of the motherboard.
Processor Start the assembly only after going
Full support for the Intel Pentium III and Celeron processors using PGA370 socket.
Supports 66MHz and 100MHz bus speed including all PGA370. through this article at least once. Only
Supports 133MHz bus speed (810E chipset version only). when you feel at ease, start the assembly
VRM 8.2 (Voltage Regulator Modules) On-board of your machine as per the guidelines
Flexible motherboard design with on-board VRM 8.2, easy to upgrade with future proces- included in this article and the applicable
sors. user’s manuals.
System Memory Never try to insert a card in PC slots
A total of two 168-pin DIMM sockets (3.3V SDRAM types). or try to plug/unplug a connector with
Memory size up to 512MB.
Supports SDRAM at 66/100 (PC100) MHz. power supply to the PC ‘on’.
Supports symmetrical and asymmetrical DRAM addressing. Ensure that the mains 3-pin socket
Banks of different DRAM types and depths can be mixed. or the socket on your stabiliser/UPS that
System BIOS you would be using for connection to the
4-Mbit Intel Firmware hub (with security feature). SMPS of the computer and/or the monitor
PnP, APM, ATAPI, and Windows 95/98.
is correctly wired with ‘live’ line on your
Full support of ACPI & DMI.
Auto-detects and supports LBA hard disks with capacities over 8.4 GB. right hand side. To nd out which line is
Easily upgradable by end-user. live (phase) and which one is neutral, use
On-board I/O your multimeter in 250V AC or higher
Supports two PCI-enhanced IDEs PIO mode 3, mode 4, and ultra DMA 33/66 channels (optional range. The live line will show full voltage
ultra DMA 66 cable). Twin headers for four IDE devices including IDE HDDs and CDROMs. w.r.t. neutral pin and nearly the same
One ECP/EPP parallel port (via a header).
Two 16550A UART parallel port (via a header). voltage w.r.t. the ground pin, while the
One oppy port. Supports two FDDs of 360KB, 720KB, 1.2MB, 1.44MB, or 2.88MB (via a neutral pin (w.r.t. ground pin) would/
header). should show very little voltage (less than
Four USB ports (via a header, optional). 10V AC). Else, the mains wiring has a
PS/2 mouse port (via a header, optional).
AT keyboard port (factory option for PS/2 type).
problem that needs to be set right.
Infrared (IrDA) support. Don t drop any screw or other
Plug-and-play conducting material on your PC’s moth-
Supports plug-and-play speci cation 1.1. erboard as that might cause shorting of
Plug-and-play for DOS, Windows 3.X, Windows 95, as well as Windows 98. pins/tracks and consequent damage when
Fully steerable PCI interrupts. you switch it ‘on’.
On-board VGA Make sure that you have a large, at
Hardware motion compensation for S/W MPEG2 decode (DVD).
3-D hyper pipelined architecture.
surface area to work on. That will reduce
Full 2-D hardware acceleration. the chances of small screws etc falling and
3-D graphics visual enhancements. getting lost.
Dynamic display memory (DDM) or optional 4MB display cache (810DC100 or 810E chipset While screwing components on to
version only).
the chassis, do not use excessive force
Resolution up to 1,600x1,200.
Win 95 vxd, Win 98/NT5 mini-port drivers support. as that may damage the screws or their
VGA port (via a header). grooves/holes.
On-board AC97 Sound
Integrated AC97 controller with standard AC97 CODEC.
Direct Sound and Sound Blaster compatible. Pentium III technology
Full-duplex 16-bit record and playback.
PnP and APM 1.2 support. Some points to be noted about the Pen-
Win 95, 98, and NT drivers ready. tium III processor being used here are:
Line-in, line-out, mic-in and MIDI/game port. Intel’s Pentium III processors sup-
Power Management port various clock speeds from 450MHz
Supports SMM, APM and ACPI. to 933 MHz. The one meant for desktop
Break switch for instant suspend/resume on system operations. version goes up to 1.13 GHz. (We are us-
Energy star ‘Green PC’-compliant.
WAKE-ON-LAN (WOL) header support. ing here a 700MHz version.)
External modem ring-in wake-up support. Integrates P6 dynamic execution
Expansion Slots architecture and a dual independent bus
One audio modem riser (AMR). (DIB) architecture.
Four PCI bus master slots (ver 2.1 compliant). Has a multi transaction system
bus.
out should wear an antistatic wrist for DIMMS and cards. Incorporates Intel’s MMX media
strap that is properly grounded. In If you are using a motherboard dif- enhancement technology.
the absence of a proper wrist strap, ferent from the one mentioned in the parts Supports Internet streaming
you may make one on your own using list, modify the guidelines mentioned here single-instruction multiple data (SIMD)
a peeled off multi-strand copper cable as per the directions given in the user’s extensions.
and ground it properly. Similar han- manual (which is supplied with the moth- Compared to Pentium II, it has 70
dling precautions are also required erboard you may be using), since there new instructions, enabling advanced 3-D

4 ELECTRONICS PROJECTS Vol. 22

 imaging, streaming audio and video, and
speech recognition.
Has a 32k (16k for instructions and
another 16k for data) as primary (level 1)
non-blocking cache for rapid access to most
heavily used data. In addition, it has 512k
uni ed, non-blocking (level 2) cache or
256k advanced transfer cache integrated
on die, which runs at the core frequency
of the processor with very low memory
access time.

The motherboard
While the processor is the most important
part of the motherboard, the motherboard
itself is the most important part of the com-
puter system. Together with the chipset, it
forms the brain of your computer.
The modern motherboards do away
with the large number of controller chips
and cards that were used in the older XT
and AT versions, such as clock generator,
bus controller, timer/counter, monitor/
printer adopter, FDD and HDD control-
lers, multi-I/O or super IDE controller
card, and DMA controller. All the func-
tions performed by these controllers/cards
(and others) are now performed by just
two or three chips and that too at much
higher speed.
The motherboard based on Intel’s
810/810E chipset (being used in the
Fig. 2: PC Partner motherboard layout diagram
present system) combines the advan-
tage of a multimedia (full-screen, full-
TABLE I motion video with realistic graphics)
and enhanced Internet performance at
JP1, JP2—System Bus Frequency
a budget price. With this motherboard,
JP1 JP2 CPU Clock Speed
one does not need separate sound,
1 Open 1 Open 133MHz (100MHz CPU run at 133MHz Front Side Bus) video, or graphics enhancement cards.
1 Open 1 1-2 100MHz (66MHz CPU run at 100MHz Front Side Bus) A block diagram of a motherboard
1 Close* 1 1-2* Auto* employing 810E chipset is shown in
Fig. 1.
JP15 - BIOS (Firm Ware Hub) Key features. The main features
Boot Block Protect JP4 - CMOS Clear of the PC Partner motherboard used
JP15 Function JP4 Function in this project are shown in the accom-
panying box. A layout diagram showing
1 Close* Unlocked* 1 1-2* Normal
the relative position of the jumpers,
1 Open Locked 1 2-3 CMOS Clear
connectors, major components, PCI
slots, and DIMM and CPU sockets is
JP34 - On Board Crystal PCI Sound (Optional) JP29 - Keyboard Power On Select shown in Fig. 2.
JP34 Function JP29 Function Jumper settings. Positions of vari-
1 1-2* Powered by +5V* ous jumpers within the motherboard are
1 1-2* PCI Sound Enable*
1 2-3 Powered by +5V Standby shown in Fig. 3. The jumper settings for
1 2-3 PCI Sound Disable (Allows Keyboard Power On) enabling various functions are shown in
Table I. Default settings are shown with
* Default settings
JP35, JP36 - On Board AC97 Codec Sound an asterisk mark. (Note. Leave all these
# P= jumpers in their default setting posi-
JP35 JP36 Function
Primary AMR, tions for the present project. The proces-
1 1-2* 1 2-3* (S)# AC97 Sound Enable*
S = Secondary AMR sor speed setting is to be done through
1 2-3 1 1-2 (P)# AC97 Sound Disable
CMOS setup as indicated later.)

ELECTRONICS PROJECTS Vol. 22 5

 manual with 3-year lim-
ited warranty. Similarly, en-
sure that the 64MB SDRAM
DIMM bears the label (such
as PC100) to indicate that it
is compatible with 100MHz
system bus speed.
Checking cabinet and
its accessories. The AT
Fig. 3: Jumper positions within motherboard mini tower PC cabinet
measures approx.180mm (width) x
330mm (height) x 360mm (depth). The
drive bays comprise two 133.35mm
(5.25-inch) exposed, one 89mm (3.5-inch)
exposed, and two 89mm (3.5-inch) inter-
nal bays.
It has 200W SMPS of VESTA make
pre-installed (+5V @16A, +12V @6A, -5V
@0.5A, and 12V @0.5A). LEDs with 2-pin
SIP connectors are provided for power ‘on’
(green and white twisted wires), HDD
(orange and white twisted wires) activity
indication, and to reset push switch (blue
and white twisted wires), which are re-
quired to be connected to the appropriate
pin pairs (Berg type) on the motherboard.
(Please refer Fig. 2 to spot the correspond-
ing connectors near JP34/JP4, but for the

Fig. 4: Power on/off switch wiring

Hardware installation
and checkout
Verifying components. First, carry out
a physical check of all the items as per
the parts list to ensure that there are no
apparent de ciencies and no signs of any
physical damage, and the parts are correct
as indicated by the labels on the items/pack-
ages. For example, the Pentium processor
pack should comprise Pentium III proces-
sor labeled 700MHz/100MHz system bus,
fan/heat-sink assembly, and installation
A wires and 4-pin connector), to go into
(a)
(b) A monitor used with the PC. At this stage,
Fig. 5: Installation of Pentium III processor in PGA 370 socket
Fig. 6: DIMM installation
time being, leave them alone.) An 8-ohm,
0.5W speaker (with black and red twisted
corresponding 4-pin speaker connector
on motherboard, also forms part of the
cabinet.
Checking SMPS. The control con-
sole on the cabinet also has a DPDT
push-button switch to switch on the
mains (230V AC) to SMPS of the compu-
ter and a parallel-wired 3-pin AC socket
(c) on SMPS for connecting AC power to the
slide the shielded connectors of the four
power supply wires of the SMPS into the
corresponding connectors on the DPDT
(d) switch as per the diagram provided on
the SMPS case (top side). The same is
reproduced in Fig. 4. The white and
black wires have a return path via blue
and brown wires, respectively, when the
power supply switch is flipped ‘on’. Con-
nect the 3-pin power cord provided with
the cabinet to the socket at the back
of SMPS and plug 3-pin plug into the

6 ELECTRONICS PROJECTS Vol. 22

 PARTS LIST female power TABLE IV
connectors with
Item Description Make Parallel-Port Connector CN6
projection in the
AT cabinet with SMPS, power cord, Pin Signal Name Pin Signal Name
power switch, reset switch, speaker, middle. If these
LEDs, complete with connectors and are held such 1 Strobe- 14 AFD
installation hardware packet. IMIL, Chen- that all black 2 Data bit 0 15 Error
nai wires are adja- 3 Data bit 1 16 INIT
Motherboard with Intel’s 810 4 Data bit 2 17 SLCTIN
cent to each oth-
chipset PC Partner, USA along with 5 Data bit 3 18 GND
er, this forms a 6 Data bit 4 19 GND
user s manual, CD (containing
drivers for onboard devices) and 12-pin AT power 7 Data bit 5 20 GND
headers for motherboard connectors. supply connec- 8 Data bit 6 21 GND
* (refer check-list) PC Partner tor with orange 9 Data bit 7 22 GND
Pentium PIII-700 Processor Intel wire (carrying 10 ACK 23 GND
64MB (PC 100)SDRAM (168-pin DIMM) Alpha 11 Busy 24 GND
HDD (hard disk drive) Seagate
power good sig-
12 PE 25 GND
FDD ( oppy disk drive) 3.5 Sony nal) emanating 13 SLCT 26 GND
CD-ROM drive 52X with audio cable Samsung from pin 1.
Keyboard Logitech The volt-
Mouse(3-button) Logitech ages on various TABLE V
Colour Monitor 14 LG COM1/COM2–Serial Connectors CN4*, CN5*
USB connector bracket with 2 headers - pins of this joint
12-pin connector Pin Signal Name Pin Signal Name
*list of connectors/brackets forming part of motherboard.
with their colour 1 DCD 6 DSR
Header (connectors with cables) for HDD (40-pin twin) - one 2 SIN 7 RTS
Header for FDD (34-pin twin) - one codes are shown
3 SOUT 8 CTS
Header for PS/2 mouse - one in Table II. 4 DTR 9 RI
Port bracket set with headers for: Check the cor- 5 GND 10 NC
(a) VGA (15-pin D connector ending into 16-pin FRC and rectness of these *These connectors are for the serial port
parallel port (25-pin D ending into 26-pin FRC) - one
(b) Com1 and Com2 (two 9-pin D ending into 10-pin FRC) - two
voltages within bracket. Both connectors have the same pin-
the range as outs.
(c) Onboard AC97 sound codec (line-in, line-out, mic-in and
MIDI/game port ending into 26-pin FRC) - one given in Table
(red wire)] meant for various drives are
II. Then switch
also correct.
socket of the mains supply or the UPS, off the power
Motherboard tment. The chassis
as appropriate. supply and take out the 3-pin plug
on which motherboard is to be mounted
Switch on the SMPS. The fan blower from the mains socket. If the AT power
can be easily removed from the PC
inside the SMPS should start running, connector voltages are correct, you
cabinet. Unscrew it and gently slide it
indicating availability of +12V supply to can safely assume that voltages in all
out from the main casing. Lay it atly
the fan. Now verify all DC outputs of the other power connectors [4-pin Molex,
on the antistatic workbench (properly
SMPS as follows. carrying +12V (yellow wire) followed
grounded conductive surface). Mark the
There are two distinct 6-pin Molex by two black wires (ground) and +5V
side facing the keyboard connecter cutout
TABLE II on the chassis.
At Power Connector Pin Voltages All motherboards have standard
Pin Voltage Range Wire Pin Voltage Range Wire mounting holes. The hardware supplied
Colour Colour comprises plastic and metallic mother-
1 *P. G. 4.5V (min) Orange 7 Ground - Black board retaining fasteners/screw-holders.
2 +5V +5%/-4% Red 8 Ground - Black Metal-type screw-holders are better as
3 +12V +5%/-4% Yellow 9 -5V +10%/-8% White these have better strength and also these
4 -12V +10%/-9% Blue 10 +5V +5%/-4% Red ground the motherboard to the chassis.
5 Ground - Black 11 +5V +5%/-4% Red
6 Ground - Black 12 +5V +5%/-4% Red You may use four metallic screw-holders
*P. G. = Power good signal which is +5V (delayed, 100ms 500ms).
for the four corner holes in the mother-
board, while the plastic fasteners may be
used for the middle
TABLE III
holes of the mother-
VGA–VGA Out Connector CN34*
board.
Pin Signal Name Pin Signal Name
Before attempting
1 Red signal 9 NC tment of the mother-
2 Green signal 10 GND
3 Blue signal 11 NC board, align it on the
4 NC 12 Display data channel data chassis such that the
5 GND 13 Horizontal sync keyboard connector
6 GND 14 Vertical sync on the motherboard
7 GND 15 Display data channel clock
8 GND
is towards the side
*This connector is for the VGA display port. Connect a marked earlier for
VGA or higher resolution display monitor to it. this purpose. Now

ELECTRONICS PROJECTS Vol. 22 7

 TABLE VI TABLE IX
Audio & Game Port Pin Header CN341* Floppy Connector Pin De nitions (JP26)
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin Function Pin Function

1 VCC 8 GND 15 NC 22 MIC-in 1 GND 2 FDHDIN

2 VCC 9 XTD 16 VCC 23 NC 3 GND 4 Reserved
3 SWC 10 GND 17 Line-out 24 GND 5 Key 6 FDEDIN
4 SWA 11 SWB 18 Line-out 25 Line-in 7 GND 8 Index-
5 XTC 12 XTB 19 GND 26 Line-in 9 GND 10 Morot enable
6 XTA 13 MSIN 20 GND 11 GND 12 Drive select B-
7 MSOUT 14 SWD 21 MIC-in 13 GND 14 Drive select A-
15 GND 16 Motor enable
*This header is for the audio port bracket. It connects audio ports-stereo line-out, stereo line-in 17 GND 18 DIR-
and microphone—and a game port (for a joystick or MIDI device) to your system. 19 GND 20 STEP-
21 GND 22 Write data-
fit all the screw- TABLE VIII 23 GND 24 Write gate-
TABLE VII 25 GND 26 Track 00-
holders/fasteners,
CN7: USB Port IDE Connector Pin De nitions (J18, J19) 27 GND 28 Write protect-
as discussed above,
Pin Assignment Pin Function Pin Function 29 GND 30 Read data-
on the chassis, oppo-
1 VCC 1 Reset IDE 2 GND 31 GND 32 Side 1 select-
site the holes on the 33 GND 34 Diskette
2 GND 3 Host data 7 4 Host data 8
motherboard, using
3 USBP1- 5 Host data 6 6 Host data 9
4 USBP0+ Philips screws pro- 7 Host data 5 8 Host data 10 TABLE X
5 USBP1+ vided in the hard- 9 Host data 4 10 Host data 11 PS/2 Mouse Connector*
6 USBP0- ware packet. Align 11 Host data 3 12 Host data 12
7 GND Pin Description Pin Description
the motherboard 13 Host data 2 14 Host data 13
8 VCC 15 Host data 1 16 Host data 14 1 Mouse data 2 NC
above the fasteners
17 Host data 0 18 Host data 15 3 Ground 4 +5V
and push it down,
19 GND 20 Key 5 Mouse clock 6 NC
so that the self-retaining heads of plastic 21 DRQ3 22 GND *This connector is for the optional PS/2 mouse
fasteners pop out from the respective 23 I/O Write- 24 GND port bracket.
holes. For the metallic screw-holders, use 25 I/O Read- 26 GND
Philips screws to secure the motherboard 27 IOCHRDY 28 BALE notches at the bottom edge of DIMM with
to the chassis rmly without using exces- 29 DACK3- 30 GND the corresponding keys in the socket.
sive force. 31 IRQ14 32 IOCS16- 3. Push the DIMM vertically down,
33 Addr 1 34 GND inserting its bottom edge into the socket.
Pentium processor mounting (re-
35 Addr 0 36 Addr 2
fer Fig. 5). The processor is to be tted 4. Once seated properly, push DIMM
37 Chip select 0 38 Chip select 1-
into the PGA370 (pin grid array with 39 Activity 40 GND down from the top edge until the retainer
370-pin recesses) socket, which is a ZIF clips snap into place and the DIMM is
(zero insertion force) socket. Take out screwdriver tip to do this, but be careful rmly held into its position.
the processor and its heat sink tted with that screwdriver does not slip and dam- Cable set installation. While the
cooling fan and heat sink retainer clip D . age the tracks on the motherboard [refer motherboard chassis is still not replaced
Now proceed as follows: Fig. 5(d)]. into the case, you could install one of the
1. Lift handle A to its vertical posi- 6. Connect the 3-pin fan connector to ends of all the cables originating from the
tion [refer Fig. 5(a)]. the corresponding connector CN17 marked motherboard. The installation of cables,
2. Align the processor pins with the ‘CPU Fan’ on the motherboard. which originated from SMPS and the con-
socket holes and insert the processor into DIMM installation (Fig. 6). There trol panel of the case (LEDs, reset switch,
its socket [refer Fig. 5(b)]. are two 168-pin SDRAM DIMM sockets and the speaker), would be completed
3. With the processor in its socket, on the motherboard with socket 1 marked after the motherboard chassis is screwed
lower handle A and bring it to its closed ‘1’ and socket 2 left unmarked. The back into the PC case.
(horizontal) position [refer Fig. 5(c)]. two sockets can together accept 512MB The cables to be connected to the
4. Orient the heat sink (with fan on SDRAM (i.e. up to 256 MB each). We FRC-type male connectors/headers on the
top) such that the depression on one side propose to install a single 64MB DIMM, motherboard are listed below, and the pin
of the heat sink matches the correspond- which is quite adequate for current type assignments are shown in the referred
ing projection on PGA370 socket, and of applications. It can be inserted into any tables. On the motherboard, normally,
place it (along with fan) over the proces- of the two sockets and the same will be only start pin 1 is indicated. In an FRC
sor [refer Fig. 5(c)]. automatically suitably con gured during connector, all odd number pins are in one
5. On the PGA370 socket, there are setup. Remove the DIMM from its anti- row while even number pins are in the
two small projections on opposite sides, static envelope, holding it by its edges. opposite row; pin 2 is opposite pin 1, pin 4
in which the heat sink clip has to be Proceed as follows: is opposite pin 3, and so on.
inserted. While it is fairly easy to insert 1. Using ngertips, push the retainer Pin 1 on the mating FRC female con-
one side, it is rather tricky to insert the clips on either side of the DIMM socket nector can be identi ed by an arrow mark
left-out side as it needs to be pulled down slightly away from the socket. over it. Ribbon cable wire going into pin
with considerable force to engage it into 2. Position the DIMM to be installed 1 is of red (sometimes blue) colour. Some
the projection. You may use the at above the socket, aligning the two small of the FRC connector pairs have a notch

8 ELECTRONICS PROJECTS Vol. 22

 to floppy drive (DS1 in
Fig.7).
Let us configure the
HDD as primary master
and CD-ROM drive as
primary slave using a sin-
gle cable emanating from
CN1 (IDE-1 header) on the
Fig. 7: Floppy drive cable for connecting up to two FDDs motherboard (refer Fig. 8).
(We could alternatively con gure CD-
ROM drive as secondary master and
connect it directly to CN2 (IDE-2 con-
nector) in motherboard, using another
40-pin cable/connector.)
The jumper on HDD should be used
to short pins 7 and 8 on the jumper block
at the rear of HDD (refer Fig. 9). Simi-
larly, there is a jumper block at the rear
of CD-ROM drive with the pairs of pins
marked as CS (cable select), SL (slave),
and MA (master). Ensure that jumper
is used in the middle to select the slave
mode for CD-ROM. The cable connection
Fig. 8: Connection of HDD and CD-ROM drive arrangement for HDD and CD-ROM is
using IDE-1 header shown in Fig. 8.
Before installation of drives, note
and the corresponding projection, which down pin-1 orientation/position of the
serves as a key so that they can go only 34-/40-pin interface cable connectors on
the correct way. The cables used for the the drives.
drives have an additional connector in The CD-ROM drive may be installed
the middle (for slave in case of HDD and in the topmost position for 13.33cm
drive B in case of FDD, which will be ex- (5.25-inch) drive, after pushing out the
plained later). Using the tips given here, plastic piece (used for protection) cover-
you can install the motherboard end of ing the cutout in this drive s bay. Align
the following cables: it from the front side of the case to en-
16-pin VGA connector CN34 (refer sure that it is ush with the cabinet s
Table III). external surface. Using four Philips
26-pin parallel-port connector CN6 screws (6-32 UNC) secure it in proper
(refer Table IV). horizontal position. The screws should
10-pin serial/com ports 1 and 2, CN4 not be allowed to go more than 3.5 mm
and CN5 (refer Table V). into the threaded holes.
26-pin sound cable connector CN31 Suitable cutout also exists in the drive
(refer Table VI). bay for installing the 8.9cm (3.5-inch)
8-pin USB connector CN7 (refer oppy drive. Before tting, ensure that
Table VII). drive door in the front opens downward
40-pin IDE-1 connector for HDD/CD- (hinged towards top). For installing oppy
ROM drive CN1 (refer Table VIII). drive follow the same procedure as used
34-pin FDD connector CN3 (refer for xing CD-ROM drive.
Table IX).
6-pin PS/2 mouse connector CN8
(refer Table X).
Installation of drives in drive’s
bay. Before proceeding with the physical
installation of CD-ROM drive, hard disk
drive, and oppy drive in the drive s bay,
you have to plan their con guration. We
propose to use only one oppy drive. This
drive will be con gured as oppy drive
A . The 34-pin oppy drive cable end with
twisted wires, emanating from CN3 on
the motherboard, needs to be connected
The HDD can now be installed at the
lowest closed (without any cutout in front)
position in the drive bay. Secure it like the
other drives using four Philips screws.
Completing the hardware in-
stallation. After having completed the
installation of drives and the cable set
of the motherboard, install back the as-
sembled motherboard chassis (complete
with its cable/connector set) into the PC
cabinet and then complete the cabling
as follows.
You may start with AT power supply
connectors. By now you are familiar with
two 6-pin Molex connectors from SMPS
used for powering the motherboard (re-
fer paragraph under heading ‘Checking
SMPS’ in Part I). Take connecter with
orange wire (PG signal) rst and align it
over pin 1 of PW1 connector on mother-
board. Projections on Molex connector of
SMPS would engage into corresponding
holes in PW1 connector. Once you have
engaged the connector in this fashion,
make it vertical and then simply slide it
down. It will snap into its position. (Be
careful not to bend the pins and ensure
that you have not engaged the wrong
pins.) Similarly, insert the other 6-pin
Molex connector in the adjacent pins of
AT power connector. On installation, all
black coloured wires will be adjacent to
each other.
Some of the connectors originating
from the motherboard (e.g. COM1, COM2,
and VGA connectors) can be secured into
the cutouts provided on the case below the
SMPS. Thus secure the D connectors for
COM1, COM2, and VGA into the respec-
tive cutouts using Philips screws. This
saves the precious space inside the PC
case and gives it an ethical look.
For accommodating the panel/bracket
for 25-pin D connector of parallel port and
PS/2 mouse as well as audio panel/bracket,
remove two of the cutouts from the rear
of the case by just forcing them out with
hands, and secure these brackets in the
vacant positions using Philips
screws.
Now you may terminate
the connectors originating from
control panel on the cabinet at
the motherboard. Connect the
loudspeaker connector to CN14,
power-on LED connector to
CN12, HDD LED connector to
CN13, and reset switch connector
to CN11. (Correct orientation
can be ensured by matching
the pin connected to coloured
ELECTRONICS PROJECTS Vol. 22 9
(not white) wire to go into pin 1 of the
connectors in motherboard.)
Now connect the 40-pin middle con-
nector (in the ribbon cable) originating
Fig. 9: Back-panel connector details of HDD
and CD-ROM drives
SCREENSHOTS CMOS SETUP MENUS


10 ELECTRONICS PROJECTS Vol. 22
from CN1 in the motherboard to CD-ROM
drive and its end connector to HDD, ensur-
ing that pin 1 of connector pairs correctly
match. (Projection/slot in the middle of
connectors will help you in proper orien-
tation of the connectors, unless you try
to force it in with wrong orientation.)
Follow it up by connecting the 34-pin
oppy drive end-connector (at the end of
twisted cable) to the interface connector
of oppy drive. This header originates
from CN3 on the motherboard.
The 4-pin Molex-type power supply
connectors now remain to be connected
to the drives. Ensure that rounded
shoulder on the female connectors mate
correctly with the corresponding male
power connectors on CD-ROM drive and
HDD. In all cases you will observe
that yellow wire (+12V) pin faces
the PC case cover.
For FDD, use the 4-pin mini
power supply connector. This con-
nector, if inserted properly, will
lock itself into position. To take
out this connector, you should
press the retaining lever with
your ngertip. Connect one of the
4-pin connectors—CN24 or CN33
or CN32—to analogue audio out-
put connector on CD-ROM drive,
Continued
TABLE XI
Pin Assignment Internal Audio
Connector Internal Audio Connector
CN25 : AUX-IN
Pin Assignment
1 AUX-L
2 GND
3 GND
4 AUX-R
CN24 : CD-IN
Pin Assignment
1 CD-L
2 GND
3 GND
4 CD-R
CN33 : CD-IN
Pin Assignment
1 CD-R
2 GND
3 CD-L
4 GND
CN32 : CD-IN
Pin Assignment
1 GND
2 CD-L
3 GND
4 CD-R
after correctly matching the ground pin ‘G’
marked over the analogue audio connec-
tor on CD-ROM drive (refer Fig. 10) and
those of CN24 or CN33 or CN32 as given
in Table XI.
If you have followed all the tips reli-
giously, your hardware assembly is com-
plete on closing the cover of the cabinet
using four to six Philips screws. But before
you do that, have a look again to ensure
that no loose wires are hanging around.
After closing the cover, you may connect
the keyboard cable to the keyboard con-
nector, mouse cable to COM1 connector,
and amplified speakers’ banana-type
stereo jack into the line-out plug on the
audio bracket.
Now that hardware assembly part of
the basic unit is over, installation of other
cards, such as LAN card (for networking),
internal modem card (for Internet access),
and TV tuner card, into the PCI slots,
using the software drivers supplied with
them, can be attempted subsequently.
Creating a startup disk
Eventually you will be using Windows
operating system (say, Windows 98), and
for that you should be having Microsoft
Windows 98 installation CD. Use some
other PC having Windows 98 operating
system to create a ‘startup disk’. The idea
is to have all important les, including
system les, Fdisk.exe, and Format.com
les, in hand, so that you may proceed
with hardware partitioning and format-
ting of hard disk once you switch on your
newly assembled PC for the rst time.
To make a startup disk, get a new
formatted 8.9cm (3.5-inch) oppy. On the


working computer, click ‘start button’,
select settings, double click on icon ‘add/
remove programs’, select ‘startup disk’,
insert formatted oppy in oppy drive, and
click over the ‘create disk’ button seen on
monitor’s screen.
The program would prompt you for
insertion of original Windows 98 CD in
CD-ROM drive. Insert the same and click
on OK button. Even if you do not have
the original CD, but have all programs
in Win98 directory in ‘C:’ drive, you can
give the proper path and the appropriate


programs will be copied to the startup
oppy disk.

CMOS setup
Switch on the newly assembled PC. It
performs power-on-self-test (POST). Dur-
ing POST you will nd Num Lock , Caps
Lock , and Scroll Lock LEDs ashing. A
single short beep during POST indicates
that motherboard is OK .
Certain messages will keep appearing
on the screen of your monitor, including
Press Del to enter CMOS setup . When
this message appears, press Del key to
enter setup. The CMOS Setup Utility

screen appears on monitor screen (refer
screenshot 1). There are seven items on
the left, which can be selected using ar-
row keys on your keyboard. On the right,
it shows certain options that are quite
obvious and can be interactively executed
when required.
Select the first item on the left,
Standard CMOS Features , and press
enter to see its screen (refer screenshot 2).
Use arrow keys to move between the items
and Page Up or Page Down key to edit
or select the options. You may correct the
date, including year and century, and the
time to their current values.

You would notice from screenshot
2 that during power up, the BIOS has
identi ed the primary master (Seagate s
10GB hard disk ST310211A), 52X Sam-
sung s CD-ROM Drive SC-15, floppy
drives, video, and RAM address range
(including its breakdown). This
latest Award BIOS 1984-2000 does
not contain Auto Detect Hard Disk
as a separate utility in the CMOS
setup options.
To select any other screen/setup
utility option, press ‘Esc’, select
the next item from setup utility
menu, and press ‘Enter’. The next
screenshot (screen shot 3) pertains
to Advanced BIOS Features . Here
you may edit and change the rst,
Continued
second, and third boot devices to read
CD-ROM, HDD-0, and floppy, respec-
tively. This will enable you to boot/run
the computer from CD-ROM (if you have
a Windows installation), CD, HDD (after
formatting and transferring the system
les), or oppy drive (using the startup
oppy created earlier), in that priority.
Press ‘Esc’ to come back to the open-
ing screen. For the time being, skip
utilities/screens 4 through 7 with their
default values. Select the last “Fre-
quency/Voltage Control menu item. Edit
‘CPU clock/spread spectrum’ item to read
100MHz/On . Thereafter press Esc and
select ‘Save and Exit Setup’ or F10 key,
and then ‘Y’ and ‘Enter’ for saving the
edited BIOS selections.

ELECTRONICS PROJECTS Vol. 22 11

 HDD partitioning and
formatting
Assuming that you have Windows 98
installation CD in CD-ROM drive, the


PC will boot from the CD and start the
Windows 98 setup program. Press function
key ‘F3’ to come out of the setup program
and come to the prompt D:\Win98> . Type
‘Fdisk’ and press ‘Enter’ for starting with
the partitioning of HDD. (Note. We could
have used the start up oppy in Drive
A instead of inserting Windows CD in
CD-ROM drive and come to A:\> prompt
for running the Fdisk program from A
drive, if desired.)
On pressing Enter key, the following
FDISK main menu appears:
Current xed disk drive: 1


Choose one of the following:
1. Create DOS partition or logical DOS drive
2. Set active partition
3. Delete partition or logical DOS
drive
4. Display partition information
Enter choice: [ ]
Press Esc to exit FDISK
Enter choice 1 above and press ‘Enter’
key. The next menu on page 2 appears as
follows:
1. Create primary DOS partition?
2. Create extended DOS partition?
3. Create logical DOS partition?

Type ‘1’ and press ‘Enter’ key. The
program veri es integrity of the disk and
then displays.
Do you wish to use max. size for a
primary DOS partition and make it ac-
tive. Y/N?
Type ‘N’ and press ‘Enter’. (Because,
we propose to create two DOS partitions
of equal size.) Once again the program
veri es integrity of the disk and prompts
you to enter/specify partition in megabytes
or percentage of disk space. Type 50%
and press ‘Enter’. The program complies.
Now press ‘Esc’ key to return to the main
FDISK menu.
Now enter choice 2. (The primary DOS
partition created earlier becomes active.)
The program will ask you to enter the
number of partitions. As it is currently 1
on ‘C’ drive, therefore type ‘1’ and press
‘Enter’.
Again press Esc . (Do not press Esc
key more than once, else it will come out
of FDISK.) Again you are led to main
FDISK menu.
Enter choice 1. You will come to menu
on page 2. Now enter choice 2 to create
extended DOS partition. The program

will again verify the integrity of the disk
and show availability of 50% of the disk
space for extended DOS partition. Type
50% for extended DOS partition and press
‘Enter’.
Again press Esc (only once). The pro-
gram will ask you to specify the disk space
for logical drive. Simply press ‘Enter’ and
then press ‘Esc’ to come back to the main
FDISK menu. Choose option 4 to display
the information. After looking at the parti-
tion information that it has been correctly
done, press ‘Esc’ to come out. Press keys
CTRL+ALT+DEL or RESET button for
settings to take effect. The PC will boot
from CD-ROM drive as per settings done
in the CMOS setup. On booting you will
again come to the setup part of Windows
98 program. Hence to come out of it, press
F3. Now your drives are designated as
under:
C: First partition on hard disk
D: Extended partition on hard disk
E: CD-ROM drive
Now you will be able to access CD-
ROM drive by typing E: . After the prompt
E:\> , type Format C:/S/U/V and press
‘Enter’. (Here ‘C:’ refers to drive to be for-
matted, ‘S’ to system (transfer of system
les to C drive during formatting), U to
unconditional, and V to veri cation.) Af-
ter formatting ‘C’ drive, you will come back
to the prompt E:\Win98> . Type setup
and press ‘Enter’ to install Windows 98
on ‘C’ drive.
As the program is interactive, keep
answering the questions logically. Choose
‘typical’ while selecting the Windows ver-

12 ELECTRONICS PROJECTS Vol. 22

sion. Various messages like ‘enter compu-
ter name’, workgroup, etc keep appearing,
which you may reply suitably. Against
‘date/time zone’ selection, choose India.
Computer will show the Agreement
format that you are bound to accept.
Hence click on the appropriate button.
Before proceeding with the Windows
installation, the program prompts you for
entering the key number of Windows 98
product, which accompanies each original
copy. You must type the key number ac-
curately. It will then copy the Windows
98 les to C drive in Win98 directory.
This will obviate use of Windows CD
for creating a startup le, whenever
required.
To format drive D , double click on
My Computer icon, click the right button
on drive D:, choose Format , and in For-
mat D: menu box, choose full and click
on Start button. After completion of the
formatting of D drive, it is accessible for
read/write operations. This completes par-
titioning and formatting of the hard disk.
Loading
motherboard drivers
On-board VGA display driver. When
the PC is running, insert the motherboard
driver CD that came with the motherboard
(PCPartner driver s CD, in our case) into
CD-ROM drive. Select drive E , select In-
tel Chipset Products , 810, VGA , Win9X,
and Graphics, in that order, and double
click on its ‘Setup.exe’ icon and follow the
instructions on screen. After nishing,
shut down the PC as per Windows shut-
down procedure and restart to allow the
drivers to take effect.
On-board AC97 Codec sound
driver. Click on ‘Start’ button, select set-
tings, select control panel, double click on
System icon, click on Device Manager ,
go to Other Devices , double click on PCI
multimedia , select PCI Audio , click on
Remove button (since compatible soft-
ware drivers have not yet been installed to
avoid con icts), and then click on refresh
button.
Go back to control panel and, click
on Add new H/W . A wizard guides you
through rest of the process, and in due
course, a message “Found new hardware
PCI multimedia audio, display, sound
video appears. The program asks if you
have disk (drivers). Click the ‘Browse’
button, select E:, ‘Intel Chipset Products’,
810 , AC97 Sound, CS4299, Win98, in that
order, and run ‘Setup’.
During the setup, when the
program prompts you for selec-
tion of device, choose ‘Crystal
Audio Codec and click OK .
Again during the course of driver
installation for Crystal Audio
Codec, the program will prompt
you for location of Windows 98
files, which you may browse
and point towards C:\Win98
directory or towards Windows
CD as E:\Win98 and click OK
button. After nishing, you may
verify, via Device Manager (refer
preceding para) by clicking on
‘Sound, Video and Game control-
ler icon, that Crystal Audio Co-
dec as also Crystal Audio Codec
with Game Device appear under
it. (A sound icon will concurrently
appear on the bottom line of your
desktop.)
Intel Firmware Hub
con guration. In Device Man-
ager under Other Devices , an below.
Unknown Device would still appear. This APM. APM caters to the PC to enter
concerns ‘Intel’s Firmware Hub’. To correct an energy-saving standby mode. BIOS
this problem, again go to 810 subdirectory enables APM by default. It can be initiated
on the CD, double click on INF_install , in the following ways:
and then on ‘Setup.exe’ within that sub- 1. By specifying time-out period in
directory. A message Found New Device BIOS setup program.
Intel Firmware Hub appears on the 2. By connecting a hardware suspend/
screen. This device will be automatically resume switch to CN10 on the mother-
con gured when you follow the instruc- board.
tions appearing on the screen properly. To 3. From ‘Suspend’ menu item in Win-
con rm that there are no unknown devices dows.
now, open Device Manager and check all ACPI. ACPI provides direct control
the items under Other Devices . to the operating system over the power
With installation of drivers for on- management as well as plug-‘n’-play func-
board devices, hardware and software tions. Features include:
configuration of your multimedia PC 1. Power management control of
is complete. Other secondary functions individual devices, add-on cards, video
such as power management functions— display, and HDD.
APM (advanced power management) or 2. Methods for achieving less than
ACPI (advanced configuration and power 30W operation in ‘Power-on Suspend
management interface)—can be incorpo- Sleeping State’ and less than 5W in ‘Sus-
rated later through pend to Disk Sleeping State .
CMOS Power Man- 3. A soft-off feature to power off the
agement Setup’ fa- PC.
cility. Similarly, 4. Support for multiple wake-up events
you can install for the PC to resume normal operation.
Ethernet card for 5. Support for front-panel power and
LAN and modem ‘sleep’ mode switch.
card for the Inter- Ethernet card for LAN. Ethernet
net, fax, and e-mail cards capable of running at 10Mbps to
accessibility via 100Mbps, of different makes such as
telecom lines. A Intel, Real Tek, Mercury and Dax, as
brief information Ethernet PCI adapter are available in
on these additional the market.
functions is given Each card comes with a bracket, driver
ELECTRONICS PROJECTS Vol. 22 13
diskette, and user manual. The bracket
would have an LED and RJ-45 jack.
This jack is used for running a twisted-
pair unshielded cable (max. length 100
metres) between the card and the hub/
concentrator (10Base-T or 100Base-Tx)
to which other computer s LAN cards are
similarly connected. Once the cable is
connected to the hub, the LED on Ether-
net card would light up. Before installing,
remove a cutout opposite the PCI slot to
make space for the bracket of Ethernet
card. When you install the card, the
Readers’ comments:
Q1. The authors have shown irresponsi-
bility by planning to install a Pentium III
processor on a PGA 370 socket meant for
a Celeron or lower processor.
Adarsh Soodan
Through e-mail
Q2. The article is really interesting and
useful. Please clarify the following techni-
cal terms:
1. PS/2 mouse connector
2. Energy Star, Green PC
3. Audio modem riser (AMR)
R. Sreerekha Hareendran
Kollam, Kerala
Q3. I request the authors to clear the fol-
lowing doubts.
1. Is there any single and reliable
dealer in Chennai, Bangalore or Kerala
from where I can procure all the com-
ponents.
2. Is the PC available in kit form?
3. Instead of a 35.5 cm (14-inch) colour
monitor, can I use a 43.2 cm (17-inch) col-
our monitor with this PC, without making
any alterations. Further, is there any 43.2
cm LCD, colour monitor available for this
PC. In that case what are all the altera-
tions required to be made?
A. Venugopalan Unny
Palakkad
Q4. Please clarify:
1. What is the difference between a
boot disk and a start-up disk?
2. How can I increase the HDD capac-
ity to 20 GB? Further, how can I partition
HDD into four sections (logical drives) and
CD-ROM drive as the fth drive?
3. De ne primary master/slave and
secondary master/slave.
4. How can I con gure HDD as second-
ary master and CD-ROM drive as second-
ary slave?
5. Provide a few tips for attaching a
CD-writer and also a DVD drive to the
system.
T. K. Hareendran, Kadakkal
14 ELECTRONICS PROJECTS Vol. 22
power to the PC should be ‘off’.
When you switch ‘on’ the computer,
it automatically detects its presence
and ‘New Hardware Wizard’ appears
on the screen to guide you through the
installation process. It asks for location
of the drivers. The driver s oppy can be
inserted in A drive and path can be in-
dicated. You can then proceed further, as
per instructions appearing on the screen,
to complete its installation.
Modem. 56kbps PnP (plug-‘n’-play
compatible) and Windows 95/98 compat-
Q5. I have successfully assembled the
PC as per the given procedure using a
128MB RAM instead of a 64MB RAM.
Please answer the following regarding
this project:
1. How should I proceed to partition
my hard disk into four logical drives?
2. The booting speed of my PC is lower
than that of my colleague’s PC that uses
500MHz Celeron processor and 64MB
RAM. Why so?
3. What is the difference between AMI
BIOS and AWARD BIOS?
Narla Sankar
Through e-mail
Q6. Following the guidelines in the article,
I have successfully assembled my PC using
altogether a different processor (500MHz
AMD K6-2) and a different motherboard
(Tomato with SIS 530 Chipset) with
Award BIOS. All is well except that dur-
ing the rst switching, it ashes CMOS
checksum error and CMOS battery
failed . The former message Checksum
error does not appear on restarting the
PC. Is this problem due to wrong orienta-
tion of BIOS chip?
Vinod D. Buchia
Gandhidham
Authors, K.C. Bhasin and Neeraj Kun-
dra, state:
A1. We have not only planned but
also installed the Intel’s Pentium III
processor in PGA 370 socket, and the
system is up and running superbly at
EFY ever since.
In fact, Fig. 5 showing its installation
in PGA 370 socket is from Intel Pentium
III processor installation notes which ac-
company the Intel Pentium III processor.
So the remarks made by the reader are
totally unwarranted.
A2. 1. PS/2-compatible keyboard and
mouse connector are miniature 6-pin
DIN connectors unlike the PCAT 5-pin
keyboard and 9-/25-pin (comport) connec-
tor for the mouse. The pin signals are: 1.
ible internal modem cards are available
from different manufacturers for instal-
lation in any of the PCI slots. The modem
card will have a telephone line jack for
connection of telephone line from wall
socket, a parallel phone jack for connect-
ing a telephone set, and Mic and speaker
jacks for external mic and speakers for use
with voicemail and speakerphone facili-
ties, respectively.
For installing the drivers, the pro-
cedure would be similar to that used for
installation of the Ethernet card. ฀
Data; 2. N/C (not connected); 3. Ground;
4. Vcc; 5. Clock; and 6. N/C.
2. Label Energy Star is awarded by
Environmental Protection Agency (EPA),
USA, for products which meet its speci -
cations. It was introduced in 1992. Green
PC is Energy Star program developed
by EPA for minimising unnecessary en-
ergy consumption and release of harmful
chemicals during production, especially
chloro uorocarbons (CFCs) that cause
depletion of ozone layer.
3. The AMR (audio modem riser) card
is a new modular speci cation that inte-
grates the audio/modem functions on the
motherboard by assigning the analogue
I/O functions to a riser card. Integration
of the audio/modem function enhances
system capabilities while reducing costs.
The AMR interface is based on an AC-link
that is compliant with Intel audio codec
97 version 2.1 speci cation. It supports
data, fax, and voice modes. The pin details
of its 46-pin edge connector are given in
Table I.
The general features of the card in-
clude:
Transmission protocols supported
(ITU-T V.90 and K56 ex, V.34, V.32is,
V.22bis, V.21, Bell 212A, and Bell 103)
Maximum download speed of 56,000
bps
Virtual COM Port throughput
460.8 kbps
Call progress monitor
On-/off-hook control
DTMF detection and generation
Distinctive ring for data, fax, and
voice
Call ID support (optional)
We will try to publish troubleshoot-
ing procedures for the PC, in EFY, very
soon.
A3. 1. We have not carried out a mar-
ket survey of the cities/states mentioned
by you and as such we cannot provide you
any related information.
 system les, a few other utilities such
2. For complete kit or parts, you may will be creating three logical partitions in
contact EFY associates, M/s IT Solutions
as Chkdsk.exe, Fdisk.exe, and Scandisk. the extended DOS partition of 50 per cent
(India) Pvt Ltd for quotations at itsolu-
exe to help you optimise and maintain drive space. Thus in the rst line seen on
tions@pcbonanza.com. the system. page 49 of February issue, type 33% for
3. One can connect any VGA/SVGA 2. To increase the HDD s capacity to the leftover disk space instead of pressing
compatible colour monitor or LCD monitor
20 GB, you can simply replace the exist- ‘Enter’. You will observe from the screen
ing HDD with either a higher-capacity
to this PC. For example, LG Electronics' that drive D: has been created.
38.4 cm LCD monitor 500 LC (Windows (20GB) HDD or use an additional HDD in Press ‘Esc’ to return to the menu on
one of the two IDE channels (primary or
95 plug-n-play compatible) can be directly page 1 and repeat the procedure for cre-
connected. secondary, connected to IDE1 and IDE2 ating the next drive, with the exception
A4. 1. A bootable disk is one that
connectors, respectively, on the moth- of typing 50% of the leftover drive space.
contains the basic system les, namely,erboard) with each channel capable of For creating the last drive, follow the pro-
the two hidden les (IO.SYS and MSDOS. supporting two devices (anyone as master cedure given in the starting paragraph on
SYS) and command.com le. These les and the other as slave). page 49 (February) in toto.
provide I/O resources for application The names ‘master’ and ‘slave’ have You would thus create all the required
programs as well as an environment to no sanctity in real terms. For con gur- drives of required capacities. Note that if
execute programs and interact with theing a drive as master and the other as you install two HDDs in place of a single
operating system. slave, the position of jumpers at the rear HDD, then drive letter D: is automati-
You can make a oppy bootable by just
on each HDD device should conform to cally kept reserved by the DOS for the
adding the system les. To do this, usethe settings for jumper block in Fig. 2 primary drive in the next HDD, and in
Windows Explorer, select 3½ oppy, and above. The setting at serial No. 3 is not that case your four drives on the rst HDD
right-click on ‘+’ sign on its left. Now from
applicable to the newer PCs that are all will be named C:, E:, F:, and G:. The last
compatible with ATA (advanced technol-
the pull-down menu, select ‘format’. Select drive name after partitioning of the next
copy system les only and click on itsogy attachment) packet interface. The HDD will be assigned to the CD-ROM
start button to copy the above-mentioned
fourth setting (cable select) is meant drive. In the case of two physical HDDs,
les to make the oppy bootable. for computers that use CSEL option for the page 1 of menu in ‘Fdisk’ will show an
If you desire to view hidden les in
master and slave device by selecting or additional choice 5. Change current xed
the disk, click ‘view’ on the menu bar of
deselecting pin 28 of the interface bus, by disk drive’.
Windows Explorer and select ‘view’ in the
jumpering pins 5 and 6. 3. The two devices connected to IDE1
folders option. Then under hidden les , One can use the IDE HDD auto connector (refer the motherboard in Fig.
select show all les and click apply . You
detect’ option from the main menu for 2 of the article) are termed ‘primary’
can now see all les including hidden les
auto-detection of HDD parameters. In and those associated with IDE2 connec-
on the disk. most cases, the BIOS will auto-detect the tor ‘secondary’. Master and slave will be
A start-up disk on the other handHDD(s). If it does not, select the User con gured as per the shorting link s posi-
has, in addition to the above-mentioned
option to manually enter the drive’s pa- tions. It is a normal practice to con gure
rameters by referring the drive at extreme connector as master
TABLE I to its documentation and the one connected to middle connec-
AMR Connector Pin De nitions (AMR) that gives the values for tor as slave. (You can also con gure them
Pin Signal Pin Signal cylinders, heads, and so vice-versa.)
number number on. The mode should be 4. The shorting link in jumper block
B1 Audio mute# A1 Audio_PWRDN set to LBA (logical block of CD-ROM drive (Fig. 9) will need to
B2 GND A2 Mono_phone addressing). short pins marked SL . For HDD, fol-
B3 Mono_out_/PC_beep A3
B4 A4 The procedure for low the guidance given in the preceding
B5 A5 creating one active paragraph. Both the devices should be
B6 Primary_DN# A6 GND (bootable) primary par- connected to the cable terminating on
B7 -12V A7 +5V dual/+5V SB tition (drive C:) and one IDE2 connector.
B8 GND A8 USB_OC#
B9 +12V A9 GND
extended DOS partition 5. Attaching a CD-R (CD-recorder/
B10 GND A10 USB+ (drive D:) has already burner/r-drive). There are various ver-
B11 +5VD A11 USB- been covered in the sions. Some can be attached externally
(Key) (Key) article. Assume that we while the others can be installed like a
(Key) (Key) want a primary parti- CD-ROM itself inside the PC. Some will
B12 GND A12 GND
B13 A13 S/P-DIF_IN tion of 50 per cent and be IDE-compatible and can be con gured
B14 A14 GND three extended DOS using IDE cable referred above. Some ver-
B15 +3.3VD A15 +3.3V dual/3.3V SB partitions of equal size sions will be SCSI compatible (for higher
B16 GND A16 GND of the leftover disk space speed), but for that you will need an extra
B17 AC97_SDATA_OUT A17 AC97_SYNC
B18 AC97_RESET# A18 GND
for drives D:, E:, and SCSI adapter card in one of the vacant
B19 AC97_SDATA_IN3 A19 AC97_SDATA_IN1 F:, respectively. (Note. PCI slots. The latest ones are USB (uni-
B20 GND A20 GND Drive letter G: will be versal serial bus) port-compatible. (The
B21 AC97_SDATA_IN2 A21 AC97_SDATA_IN0 automatically assigned USB port is available on your Pentium
B22 GND A22 GND to CDROM drive in the motherboard.) Some external recorders
B23 AC97_MSTRCLK+RST A23 AC97_BITCLK
process.) In effect, we can be connected via the printer port.

ELECTRONICS PROJECTS Vol. 22 15

 The newer models can write as well as
read, and as such they can also function
as CD-ROM drives. Some of the record-
ing software accompanying these writers
would also have a veri cation feature
called ‘pre-mastering’ for comparing the
recorded data against source le. Neces-
sary documentation including software
drivers for installation, con guration, and
utilities will accompany the CD-R. Going
through this literature, you can buy the
CD-R that suits you the best.
Attaching a DVD to the system. The
minimum system requirements for in-
stalling a DVD in the same place where
CD-ROM goes include Pentium with bus
speed of 133 MHz (supported by 810E
chipset) or better (200 MHz is required
for maintaining 30 frames/second rate),
Windows 95 or later version (Windows 98
has in-built DVD support), 16MB/32MB
RAM, graphics resolution of 800x600 pix-
els with 16-bit colour, and sound blaster-
compatible card. You also need to install
an MPEGII decoder card in a spare PCI
slot for decompression of video and audio.
(Software-based MPEG decoders are com-
paratively much slower.)
While a CD can store around
650MB/700MB, a single-sided DVD can
store 4.7 to 9 GB and a double-sided DVD
up to 18 GB. (A double-sided DVD needs
to be ipped to read the second side as
existing drives can read from a single
side only.) The DVD kit would comprise
ATAPI/EIDE-compatible controller (SCSI-
compatible are also available in the mar-
ket), an MPEGII decoder card, cables, and
software including sample titles. Consider-
ing an ATAPI/EIDE-compatible controller,
con gure DVD drive as primary slave by
placing the shorting link across SL pins
on its jumper block at the rear in the same
fashion as described above.
Read your DVD installation manual
carefully, since there are various ways to
cable together the DVD drive, MPEG card,
existing sound card, and existing CD-ROM
drive (if any). You should follow the docu-
mentation for audio and video connections.
However, here is a typical approach:
Connect the internal audio cable from
the rear of the DVD drive to the rst
audio-in connector on the MPEG card. If
you nd an internal audio cable from your
existing CD-ROM drive fastened to your
sound card, disconnect that cable from
the sound card and plug it into the MPEG
card’s secondary audio-in connector.
Next connect an audio cable from the
audio-out connector on the MPEG card to
16 ELECTRONICS PROJECTS Vol. 22
1.
2.
3.
4.
Fig. 2: Settings for jumper block
the sound card’s internal audio-in con-
nector. Remove the monitor connector
from your graphics card and plug it into
the appropriate connector on the rear of
your MPEG card. Find the VGA loop-back
cable included in your DVD kit. Attach
its one end to your graphics card and
the other to the input connector on your
MPEG card.
If you want to use a TV monitor with
your DVD drive, link the video-out connec-
tor on your MPEG board to the monitor’s
video-in connector. Now proceed to install
the drivers and DVD software. Power up
your PC. Windows will detect the MPEG
board and ask you for a driver. Insert the
driver oppy from your DVD kit and click
OK . You may need to restart your PC
before proceeding.
A5. 1. The rst question has already
been answered above.
2. The slow booting operation in PC
may be attributable to some other reason
rather than the processor. The booting
process in the PC involves a number of
steps. Some of the probable reasons and
the suggested remedies are given below:
The power good (PG) signal may
not be building fast to its speci ed value
(4.5Vmin). For that, you need to check
your PCs SMPS. The speci ed power rat-
ing of the power supply to support Intel’s
810 chipset is 145 watts for a typical
con guration.
In the CMOS setup utility (refer
screenshot 4), edit the eld against Sys-
tem BIOS Cacheable and Video BIOS
Cacheable’ to read ‘Enabled’ in place of
Disabled .
Ensure that 3.3V SDRAM sticks
(DIMMs) used by you are 100MHz-
compatible.
Ensure rm connections from moth-
erboard to all peripherals. Improper con-
nections can result in BIOS taking time
in identifying them/their settings during
POST operations. As time-out margins
are fairly long, a lot of time could get
wasted that way.
Reload command.com le to make
sure that it is not corrupt. Also check for
presence/removal of any virus using Nor-
ton or other anti-virus program.
We suggest you to refer the BIOS
FAQs posted by Pheonix at www.
pheonix.com/platform/awardbios.html’
before coming to any conclusion.
3. AMI (American Megatrends Inc.)
and AWARD (AWARD Softwares, which
merged with Pheonix Technologies Ltd
in Sept.1998) are the two renowned BIOS
suppliers. There are a few other suppliers
also in the eld (e.g. Microid Research
Inc., Chips & Technologies, etc). At the
user’s level, one does not directly interface
with the BIOS, except via the CMOS set-
up options that are more or less similar,
irrespective of the BIOS supplier. BIOS
is chipset-/hardware-speci c. Hence it will
generally differ from one motherboard
manufacturer to another. Even the same
manufacturer may upgrade his BIOS by
some hardware modi cations to make it
compatible with the new hardware. Only
options can be changed via the CMOS
set-up utility.
A6. The BIOS chip orientation is
correct, else you would not even see the
initial setup screen or any message.
Battery-backed CMOS chip orientation is
also correct if your system time is chang-
ing correctly, since battery-backed CMOS
chip is used for retaining the system
set-up data as well as the RTC (real-time
clock) data.
It seems that either your battery-
backed CMOS chip is faulty or some of its
pins are not making proper contact with
the base and hence its integrity is not get-
ting veri ed during POST. Check if this
CMOS chip has popped up from its base
or any of its pins are bent and rectify the
same. Else, try changing this IC. There
could also be a track discontinuity problem
on your motherboard.
Check proper setting of jumpers, es-
pecially the CPU core voltage selection.
For AMD K6-2, this voltage setting is
2.2V. This can be achieved by shorting
pins 7-8 of JP5, while leaving all oth-
ers open, in your Tomato motherboard.
Shorting is achieved by moving the link
to 1-2 and opening is achieved by mov-
ing the link over 2-3. This information
may be included in the user manual of
your motherboard. Else, you may get it
from http://www.zida.com/js_t530b.htm .
 AUTOMATIC ROOM LIGHT
CONTROLLER
REJO G. PAREKKATTU PARTS LIST
Semiconductors:
IC1, IC2, IC3 - NE555, timer
IC4 - 74LS192, up/down decade
BCD output of the counter, at any time,

U
sually, when we enter our room counter
in darkness, we nd it dif cult represents the number of persons inside IC5 - 74LS85, 4-bit magnitude
to locate the wall-mounted switch- the room. The output of the up/down comparator)
board to switch ‘on’ the light. For a counter is decoded by 7-segment decoder/ IC6 - 7447, BCD to 7-segment
decoder/driver
stranger, it is tougher still as he has no driver and displayed on 7-sement display.IC7 - MCT2E, opto-coupler
knowledge of the correct switch to be Simultaneously, the output of counter is IC8 - 7805, +5V regulator
turned on. Here is a reliable circuit that compared by 4-bit magnitude compara- IC9(N1-N4) - 74LS00, quad 2-input
takes over the task of switching ‘on’ and tor. NAND gate
IC10(N5-N10) - 74LS14, hex schmitt
switching ‘off’ of the light(s) automatically The output of comparator remains inverter gate
when somebody enters or leaves the room high as long as BCD output of counter is T1, T2 - BC548, npn transistor
during darkness. This circuit has the fol- greater than zero. A logic gate is used to
T3 - SL100, npn transistor
lowing salient features: D1-D3
initiate energisation of a relay to switch - IN4001, recti er diode
IRLED1, IRLED2 - Infrared LED
It turns on the room light whenever ‘on’ the light when comparator output is
Resistors (all ¼-watt, ±5% carbon, unless
a person enters the room, provided that high and it is dark outside.
stated otherwise):
the room light is insuf cient. If more than R1 - 3.3-kilo-ohm
one person enters the room, say, one after R2 - 10-kilo-ohm
the other, the light remains ‘on’. The circuit R3 - 100-ohm
R4, R5, R21 - 1.2-kilo-ohm
The light turns ‘off’ only when the The detailed section-wise description of
R6, R7, R12 - 33-kilo-ohm
room is vacant, or, in other words, when the circuit shown in Fig. 2 is as follows:
R8, R9 - 180-kilo-ohm
all the persons who entered the room IR transmitter. The IR transmitter R10, R11 - 1-kilo-ohm
have left. R13-R19
circuit consists of an astable multivibra- - 470-ohm
R20 - 100-kilo-ohm
A 7-segment display shows the tor built around NE555 timer IC1. The
VR1 - 10-kilo-ohm preset
number of persons currently inside the output of IC1 at pin 3 is a rectangular
Capacitors:
room. waveform of around 36kHz frequency. C1 - 0.001µF, ceramic disk
The circuit is resistant to noise and This output is used to drive two IR LEDs,C2, C3, C4 - 0.01µF, ceramic disk
errors since the detection is based on in- which transmit modulated IR light at C5, C6 - 4.7µF, 16V electrolytic
frared light beams. 36kHz frequency. Modulating frequency C7, C8 - 10µF, 16V electrolytic
C9 - 1µF, 16V electrolytic
The circuit uses commonly available of 36 kHz is used because the IR receiver
Miscellaneous:
components and is easy to build and test. modules used in this circuit respond to IR
M1, M2 - IR sensor modules
The functional block diagram of the signals modulated at 36kHz frequency. DS1 - LT542 (common anode
circuit is shown in Fig.1. It comprises The multivibrator frequency can be cor- display)
36kHz IR transmitter, two IR detector RL1
rectly adjusted with the help of preset VR1 - 12V, 200 ohm, 2 C/O.
LDR1 - LDR (Dark resistance > 120
modules, two monostable multivibrators, (10 kilo-ohm). Resistor R3 is a current kilo-ohm)
up/down-counter, 4-bit magnitude com- limiting resistor that keeps the IR LEDs,L1 - 230V, 100W electric bulb
parator, 7-segment decoder display, light current within the required range. - 12V power supply
sensor, and relay driver. IR detector modules. The IR de- - Printed circuit board
- IC sockets
Two pairs of IR transceivers are em- tector modules used in the circuit are
ployed in order to detect whether the
person is entering or leaving the room.
When a person enters the room, IR
detector 1 gets triggered, followed by
triggering of IR detector 2. Conversely,
when a person leaves the room, IR
detector 2 gets triggered, followed by
triggering of IR detector 1.
A priority detector circuit deter-
mines which of the two detectors is
triggered rst and then activates an
up/down counter accordingly. The Fig. 1: Block diagram of automatic room light controller

ELECTRONICS PROJECTS Vol. 22 17

 Fig. 3: Timing waveforms

commonly available in or leaves the room, the infrared light

the market. These have beams are interrupted one-by-one and the
three terminals for Vcc output of each IR sensor module, in turn,
(+5V, here), ground, and goes high, which results in conduction of
the output signal, re- associated transistors T1 and T2. Which
spectively. In the normal transistor will turn on rst depends on
state, the output pin whether the person is entering or leaving
(pin 3) of this detector the room.
remains at high state, In the circuit, two NE555 timer ICs
and when an IR light (IC2 and IC3) wired as monostable multi-
of correct modulating vibrators are used. The pulse width of the
frequency is detected, output waveform (on time) for these mul-
its output pin goes low. tivibrators is xed at about 0.9 seconds
The pin configuration by suitably selecting the values for the
of the IR modules may timing capacitors C5 and C6 in conjunc-
vary from one manufac- tion with their associated resistors R8 and
turer to the other. (Pin R9. These monostable multivibrators get
con guration of module triggered when their trigger input pins
TSOP 1136 for 36 kHz (pin 2) go low. Thus the multivibrators are
used by EFY is shown in triggered only when the IR light beams
Fig. 2.) (Articles based are interrupted. Although the output
Fig. 2: Schematic diagram of automatic room light controller

on the IR sensor module pulse width of both the multivibrators is

have been published in approximately the same, there is, how-
Nov. 2000 (also in Elec- ever, a phase difference corresponding to
tronics Projects Vol. 21) the elapsed time between the successive
and some other previous interruptions of the IR beams. Refer to
issues of EFY. Readers the waveforms shown in timing diagram
may refer the same for of Fig. 3.
more information about Priority-detector logic circuit. The
the module.) priority detector circuit uses three NAND
Since the IR trans- gates, ve inverter gates, and two differen-
mitter in this circuit is tiators. The timing diagram given in Fig.
continuously ‘on’, emit- 3 helps in understanding as to how the
ting IR light, in the nor- priority-detector circuit detects a person
mal condition, the output going out of the room.
pins of both IR modules At rst the outputs from the mon-
will be at low state. ostable multivibrators are NANDed
Therefore transistors T1 by gate N1 and its polarity is inverted
and T2 will remain cut- again by gate N7. At the same time, the
off. When a person enters outputs of monostable IC3 and IC2 get

18 ELECTRONICS PROJECTS Vol. 22

differentiated by the capacitor-resistor
combinations of C7-R10 and C8-R11,
respectively. Each differentiated output
is passed via Schmitt inverter pairs of
N5-N6 and N10-N9 to convert the differ-
entiated pulses into rectangular pulses.
The rectangular pulses obtained at the
output of gates N6 and N9 are again
NANDed with the output of gate N7 in
NAND gates N2 and N3, respectively.
Fig. 4: Actual-size, single-sided PCB layout for the circuit
Fig. 5: Component layout for PCB
The rectangular pulse at pin 4 of NAND
gate N2 ends before the output of gate
N7 goes high and hence the output of
NAND gate N2 stays high, while both
inputs to NAND gate N3 are simultane-
ously high for the duration of rectangu-
lar output of gate N9. As a result, the
output of gate N3 applied to countdown
clock pin 4 of IC4 causes the counter to
count down on its trailing edge (low-to-
high transition) and the output count
goes down by one count.
Similarly, when a person enters
the room, pin 4 of counter IC4 remains
high, while its pin 5 (count up) gets a
low-going pulse resulting into counter
output advancing by one count. Values
of capacitors C7 and C8 and resistors
R10 and R11 can be varied for optimum
performance.
Up/down counter. Up/down decade
counter 74LS192 (IC4) is used as the
counter. When the power is turned ‘on’,
its outputs Q0 through Q3 are in the
low state. Whenever a person enters the
room, a low-going pulse is applied at its
count-up pin 5, while its count-down
pin 4 is held at logic 1 and its output
count advances by one. Similarly, when
the person leaves the room, a similar
pulse is applied at its countdown input
(pin 4) while its countup pin 5 is held at
logic 1 and its output decreases by one.
Thus the 4-bit output always represents
the number of persons still inside the
room. The output of the decade counter
is connected to 7-segment decoder/driver
IC6 (7447) that displays the number on
common-anode 7-segment LED display
(LT542).
Magnitude comparator. The output
of the up/down counter is also applied to
4-bit magnitude comparator that acts
as zero detector, i.e. it detects whether
the number of persons inside the room
is greater than zero or not. The 4-bit
output of the decade counter is always
compared with a reference 4-bit number
(0000), and if a match occurs, the output
at pin 5 (P>Q) of the comparator goes
low to represent an ‘empty room’ condi-
tion. In all other cases (when the number
of persons in the room is greater than
zero), P>Q output will be at high state.
This output is given as one of the inputs
to NAND gate N4 (followed by inverter
gate N8). Thus, as long as the room is
not empty, one of the inputs to N4 gate
will be high.
The second condition for the light to
get switched on is yet to be satis ed.
Whether there is suf cient light in the
room or not is checked by the light sensor
circuit.
Light sensor. The light sensor is
wired around the opto-coupler MCT2E.
The resistance of the LDR depends upon
the amount of light in the room. An LDR
with resistance below 5 kilo-ohm in nor-
mal light and more than 120k resistance
in darkness is required. When there is
ELECTRONICS PROJECTS Vol. 22 19

Fig. 6: Proposed layout of IR transmitter
and receiver pairs
suf cient ambient light, the transistor
inside the opto-coupler is turned ‘on’ and
the input of NAND gate (pin 3) is driven
to low state. Thus the output of NAND
gate remains at high state and that of in-
verter gate N8 at low. However, when the
light is insuf cient, the resistance of the
LDR increases, turning off the transistor
inside the opto-coupler. The sensitivity
can be controlled by adding a high-valued
variable resistance (about 680k) across
the LDR.
When both conditions are satis ed
20 ELECTRONICS PROJECTS Vol. 22
(that is one or more persons are inside
the room and the ambient light is insuf -
cient), the output of NAND gate goes low
and that of inverter gate N8 goes ‘high’ to
turn on transistor T3, thereby energising
relay RL1. A 230V, 100W electric bulb is
connected via the relay to the AC mains.
Once the relay gets energised, the LDR is
effectively removed from the circuit (since
the LDR is connected to the N/C contact of
the two pole relay) to prevent the icker-
ing of the lamp with changing resistance
of the LDR.
Assembly and testing
The full circuit, with the exception of the
IR transmitter, can be assembled on a
single general-purpose PCB. However,
an actual-size, single-sided PCB for the
circuit in Fig. 2 is shown in Fig. 4. The
component layout for the PCB is shown
in Fig. 5.
The receiver-transmitter pairs are
placed about a metre apart as shown in
Fig. 6. The distance between the two sen-
sors (receiver modules) is about 40 cm.
A steel pipe of 5mm diameter and 3cm
length can be placed in front of the IR
module in order to improve its directiv-
ity. After assembling the circuit, adjust
preset VR1 (10k) until pin 3 of both the IR
sensor modules go high (5V). If the circuit
still does not function properly, adjust the
distance between the sensors. The metal
cabinets of the IR modules must be con-
nected to ground.
Note that the circuit works with a
regulated +5V supply, except the power
supply to the relay coil. The circuit has
no off-time memory, and so its working is
interrupted during power failure.
Another disadvantage is that the cir-
cuit can count only up to 9. But it is quite
unusual to have more than nine people in
a normal living room.
Take care about the IR sensor module
pin connections. It may be damaged if con-
nected wrongly.
฀
 INTELLIGENT
WATER LEVEL CONTROLLER
I
n coming years, the drinking water
is going to be one of the scarce com-
modities. This would partly be at-
tributable to our mismanagement of
water supply and its wastage. In normal
households, where pumps are used to ll convenient to go up frequently and see It can check the ground tank (sump
the overhead tanks (OHT), it is usually
observed that people switch on the pump
and forget to switch it off even when the
Fig. 1: Circuit diagram of water level controller
SADHAN CHANDRA DAS
tank has become full. As a result, water ler circuit presented here. It has the fol-
keeps over owing until the household lowing features:
people notice the over ow and switch It can automatically switch on the
the pump off. As the OHT, in general, is pump when the tank is empty and switch
kept on the topmost oor, it is not quite it off when the tank becomes full.
the water level in the OHT. tank) water level from which the water is
This problem can be solved by using pumped into the overhead tank (OHT).
the intelligent digital liquid level control- If the sump tank water level is below the
ELECTRONICS PROJECTS Vol. 22 21
 low and the display shows decimal digit
0. In this way the display circuit works
to show decimal digits 0 through 4, cor-
responding to the level of the water, as
de ned by the position of the sensors at
different heights. Here the resistors R9
through R12 and R19 through R21 have
been used for passive pull-down.
Controller circuit. The controller
circuit is built around three quad 2-input
NOR ICs (IC3 through IC5) to switch
the pump motor on or off when certain
conditions are ful lled. The conditions
to be met for switching-on/running of the
pump are:
Fig. 2: Power supply 1. The mains supply should be within
certain ‘low’ and ‘high’ cut-off limits (say
Digital display between 200V AC and 250V AC).
circuit (refer Fig. 1.) 2. The water level in the sump (ground
This circuit comprises a tank) is above certain optimum level (2'
quad 2-input XOR gate in Fig. 1).
IC1 (CD4030) for sum 3. Water in the overhead tank (OHT)
outputs, decimal to BCD is below the minimum level.
code converter using Once all the above-mentioned three
diode matrix of diodes conditions are satis ed, the pump motor
D3 through D7, a BCD would start running. The corresponding
to 7-segment decoder/ logic level at point A will be low (point B
driver IC2 (74LS47), will also be low automatically—not being
Fig. 3: Construction details of probes for mineral water and common-anode type in touch with the liquid), point C will also
7-segment dis- be low and point D will be high.
play LTS 542R. Once running, the pump will continue
When only to run even when the water rises above
the tip of sensor the minimum level in the OHT (i.e. when
probe (cathode) point A subsequently goes high), provided
No. 1 is in touch the rst condition is still fully satis ed
with the water, and the water level in the sump has not
the voltage at fallen below that of sensor 1'. It will stop
pin 3 of IC1 be- only when either the maximum speci ed
comes logic high level in the OHT has been reached or the
(i.e. +5V), and water level in the sump has fallen below
hence voltage at sensor 1' position.
line No. 1 (L-1) Here the NOR gate pairs of N2 and
also becomes N3, and N6 and N7, form NOR-latches.
high. Now due When the ground tank (sump) water level
Fig. 4: Construction details of probes for non-conducting liquids
to conduction of is above the de ned level 2', the voltage
diode D3, the BCD code at pin 11 of gate N6 is low. So diode D12
0001 (Q3 Q2 Q1 Q0) is cannot conduct. Also, if the mains voltage
predetermined level, the unit switches off
generated and converted to equivalent is within acceptable limits of 200-250V,
the pump to protect the pump from dry-
7-segment code by IC2 (74LS47) to dis- the voltage at output pin 3 of gate N12 is
run, even though the overhead tank may
play the decimal digit ‘1’. high and the voltage at collector of tran-
be completely empty.
Similarly, when the tips of the both sistor T2 is low. Diodes D8 and D11 are
It includes under- and over-voltage
sensors 1 and 2 are in touch with water, thus cut off. So the voltage at input pin
cutout to switch off the pump if the voltage
the voltage at pin 3 becomes logic low 8 of gate N4 is pulled down to logic low
is not within speci ed low (200V) and high
(0V) while the voltages at pin 4 and line level by passive pull-down resistor R18
(250V) limits.
2 (L-2) become logic high (i.e. +5V). Now (56 kilo-ohm).
It includes a circuit for digital dis-
due to conduction of diode D6, the cor- Now if overhead tank is empty, i.e.
play of the overhead tank level to indicate
responding BCD code 0010 is generated
water levels 0 through 4 as per positions water level is below level 1, voltage states
and decimal digit 2 is displayed on the at input pins 1 of gate N2, and pins 12
of the tips of the sensors inside the over-
7-segment display. and 13 of gate N1, are pulled down to
head tank.
When the tank is completely empty, logic low by passive pull-down resistors
The sensors used in this project have
the outputs of all XOR gates of IC1 are R13 and R14 respectively. Hence volt-
a lifetime of more than ve years.

22 ELECTRONICS PROJECTS Vol. 22

 PARTS LIST
Semiconductors:
IC1 - CD4030 quad 2-input XOR
gate
IC2 - 74LS47 BCD to 7-segment
decoder/driver
IC3-IC5 - CD4001 quad 2-input NOR
gate
IC6 - LM7812 regulator 12-volt
IC7 - LM7805 regulator 5-volt
T1-T2 - SL100 npn transistor
D1-D15,
D17-D20 - 1N4001 recti er diode
D16 - Red LED
DIS1 - LTS542R 7-segment common
anode display
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1-R8 - 33-kilo-ohm
R9-R18 - 56-kilo-ohm
R19-R21 - 1.5-kilo-ohm
R22, R24 - 2.2-kilo-ohm
R23 - 1.2-kilo-ohm
R25 - 1-kilo-ohm
Fig. 5: Actual-size, single-sided PCB for water level controller R26, R27 - 220-kilo-ohm
R28-R34 - 330-ohm
VR1, VR2 - 100-kilo-ohm preset
Capacitors:
C1-C4, C7 - 0.01µF ceramic disc
C5 - 470µF, 35V DC electrolytic
C6 - 2200µF, 35V DC electrolytic
C8,C9 - 10µF, 25V DC electrolytic
Miscellaneous:
RL1 - 12V, 200-ohm 2 C/O relay
X1 - 230V AC primary to
(a) 0-15V, 750 mA, and
(b) 0-12V, 100 mA secondary
transformer
S1 - Push-to-on button
S2 - On/Off switch
- IC sockets
- Heat sinks for regulator ICs
- SS304, 5mm dia. stainless
steel rod for anode and 3mm
dia. for all cathodes - of ap-
propriate length
- Multi-core feed wire

10 go low. Transistor T1 is cut off and the

relay is kept disabled, even though the
Fig. 6: Component layout for the PCB overhead tank is fully empty. The relay
will be enabled only when the water level
ages at output pin 11 of gate N1 and pin 1 of gate N2 goes high. Already, the in the sump tank is above level 2'.
input pin 5 of gate N3 become logic high voltage levels at pin 11 of gate N1 and When the ground tank water level is
to force the output at pin 4 of gate N3 to input pin 5 of gate N3 are low. So the volt- above level 2' but the line voltage is out of
be latched low. This logic level will not ages at output pin 4 of gate N3 and input range, gate N12 output pin 3 goes low to
change until voltages at input pins 5 and pin 9 of gate N4 become logic high to turn cut off transistor T2, making diode D11
6 of gate N3 become low (0V) and voltage the output pin 10 of gate 4 to logic low level. conduct. In this state the output of gate
at pin 1 of gate N2 goes high (+5V). Since Thus relay RL1 is de-energised, to switch N6 and the output of gate N2 become logic
both inputs of gate N4 are low, hence its the pump off. low. Although diode D12 does not conduct,
output at pin 10 goes logic high to drive When line voltage is within the speci- diode D11 conducts and the output of gate
transistor T1 into conduction. Relay RL1 ed limits and ground water level goes N4 goes low to cut off transistor T1. This
is thus energised and the pump motor is below the de ned level 1', the voltage at disables relay RL1 and the pump remains
switched ‘on’. output pin 11 of gate N6 becomes logic off, even though the overhead tank is com-
The water level of the overhead tank high to make diode D12 conduct. As a pletely empty.
starts rising. When the water level reaches result, the voltage at pin 8 of gate N4 Here two cathode sensors for sensing
the tip of the topmost sensor 5, voltage at becomes logic high to make its output pin ground tank water level have been used

ELECTRONICS PROJECTS Vol. 22 23

instead of one, to provide some hysteresis One of its terminals is grounded while its rain water does not come in contact with
in the system. When ground water level other terminal, marked ‘G’, is connected the soldered joints. One has to use ortho-
is below level 1', the output of gate N6 to point G of high/low cutout circuit in phosphoric acid or zinc-chloride to make a
becomes logic high (5V). When water level Fig. 1. The other secondary rated at 15V, soldered joint between stainless steel and
is above level 2', the output of gate N6 is 750 mA is used for deriving the regulated conducting part of the exible feed wire.
logic low (0V). If the water level is in be- DC supplies required for operation of the The distance between the anode and
tween levels 1' and 2', there is no change circuit. the cathodes should not be more than 60
of state at output of gate N6, i.e. output Construction of sensors (Fig. 3). cm. Arrangement should be made in such a
remains at the last/previous state. The highlight of the circuit are its elec- way that no electrode touches the other.
Power supply (Fig. 2). The power trodes (Fig. 3) used for mineral/conductive The circuit can also be used for non-
supply circuit consists of step-down water, which are made of stainless steel conductive liquids such as pure distilled
transformer X1 (having two secondaries (grade SS-304) rods. These electrodes have water by using oats in conjunction with
with ratings of 12V, 100 mA and 15V, a life span of more than ve years. Anode micro switches, as shown in Fig. 4. This
750 mA), a bridge recti er (using four is a rod of 5 mm diameter and each of the arrangement can be used for distilled wa-
1N4001 diodes), a capacitor of 2200 µF for cathodes is of 3 mm diameter, as shown ter plants, research laboratories, and for
ltering purpose, regulator IC 7812 for in the gure. other nonconductive liquid level sensing
feeding the anode probes as well as relay The cathodes and the anode should be applications.
RL1, and regulator IC 7805 for feeding long enough so that their soldered termi- An actual-size, single-sided PCB for
regulated +5V supply to all digital ICs, nals are not in contact with water, even the circuits in Figs 1 and 2 is shown in Fig.
LEDs, and 7-segment display. The 12V when the tank is full. The joints should be 5, and the component layout is shown in
secondary is used for sampling the mains. covered with insulation in such a way that Fig. 6. ฀

24 ELECTRONICS PROJECTS Vol. 22

 A UNIQUE
LIQUID LEVEL INDICATOR
SADHAN CHANDRA DAS

A
separate alternative circuit of a and the power
unique liquid level indicator supply circuit
to provide a display in terms of in Fig. 2 inde-
the percentage of full-scale level in OHT pendantly.
is shown in Fig. 7. It can either be used The latter
to replace the digital display circuit configuration
included in Fig. 1 (by simply connecting can be used
the 10% and 100% sensor probes of Fig. 7, when you do
additionally, to points marked ‘A’ and ‘B’ not desire to
respectively in Fig. 1, apart from connec- have auto-
tion of +5V and +12V supplies and ground matic control
points) or it can be used in conjunction for switching
with an audio alarm unit shown in Fig. 8 the pump mo- Fig. 8: Audio alarm unit

Fig. 7: Unique liquid level indicator

ELECTRONICS PROJECTS Vol. 22 25

 Display circuit. The
basic elements of the cir-
cuit, as shown in Fig.
7, comprise three quad
2-input XOR gates (IC1
through IC3) to get only the
sum outputs, a hardwired
decimal-to-BCD converter
(using diodes D1 through
D16), and a 74LS47 BCD-
to-7-segment decoder/driv-
er (IC4). When the tip of
sensor-1 is in touch with
the water, the line (L-1)
connected to pin 3 of IC1
(CD 4030) goes to logic 1
state (+5V).
When the tips of sen-
sors 1 and 2 both touch the
water, pin 3 of IC1 goes to
logic 0 (0V), while line L-2
connected to pin 4 of IC1
becomes high (+5V). Thus
Fig. 9: Actual-size, single-sided PCB for the unique liquid level indicator
which one of the lines (L-1
through L-10) will be at
logic 1 would depend on
which last sensor (counted
from bottom of the tank) is
in touch with the water. If
the tank is totally empty,
all the lines, L-1 through
L-10, would be at logic 0.
T h e s e l i n e s ( L - 1
through L-10) represent the
decimal numbers 1 through
10. If line L-1 is at logic 1,
BCD code 0001 is gener-
ated due to conduction of
diode D9 only. Similarly, if
line L-3 is at logic 1, BCD
code 0011 is generated due
to conduction of diodes D6
and D16.
The voltages, corre-
sponding to their BCD
codes, are fed to the in-
puts of IC 74LS47 (7-seg-
Fig. 10: Component layout for the above PCB ment decoder/driver) to
drive 7-segment display DIS2. When
tor on and off but need only to be warned (Fig. 8) is tapped from line-1 and line-10 line L-10 is high, display DIS3 is driven
when water reaches 100% and also when representing 10% and 100% levels respec- by transistor T1 (SL100) for decimal
its level drops to 10% so that you may tively in Fig. 7. number 1.
manually switch the pump motor on or off, If, in place of displaying the liquid lev- Since all the time the unit place digit
as the case may be. el in percentage, one wants to display only of the percentage display is 0, the cath-
This level indicator can show the dis- the digits 0 through 10, then 7-segment odes of corresponding segments of DIS1
crete levels in percentage from 0 to 100% display DIS1 and LEDs (LED1 through have been permanently connected to
with 10% resolution. An audio alarm LED4) for % symbol can be removed. This 0V (ground) through current-limiting
circuit has been incorporated to generate circuit can be used for premises which resistors of 330 ohms each. In this way
audio alarm when the tank level reaches have overhead tanks and the water supply the circuit displays 0 to 100 per cent
100% and also when the level drops to is provided by municipalities or corpora- of liquid level with 10 per cent resolution.
10%. The input to the audio alarm circuit tions etc. One may or may not use diode D1. In

26 ELECTRONICS PROJECTS Vol. 22

 PARTS LIST Readers’ comments: done for resistors R19, R20, and R21.
Semiconductors: Q1. I have noticed, when the water level The anode voltage should be +12V to
IC1-IC3 - CD 4030 quad 2-input X-OR reaches the probe No 4, the C' segment +15V, which may or may not be regulated.
gate LED of DIS 2 (LT542) does not glow. You may also follow the modi cations
IC4 - 74LS47 BCD to 7-segment The same is the case even when the shown in Fig. 1 (component numbers
decoder/driver
IC5 - UM66 melody generator
water level reaches probe No. 5 and shown for Intelligent Water-Level Control-
DIS1-DIS3 - LTS 542 common anode probe No 6. Kindly suggest the correc- ler) to correctively display the water-level.
7-segment display tive actions. It is due to the fact that the output of
T1, T3, T4 - SL100 npn transistor M. Raja the CMOS ICs (4030) are loaded by 1.5k
T2 - BC 108 npn transistor Bangalore resistors.
D1-D16,
D21, D22 - 1N4001 recti er diode Q2. I have constructed the circuit which EFY: The circuit works satisfactorily with-
ZD1 - 3.1 volt zener diode is working perfectly. Instead of eleven out resistors R2 to R5.
LED1-LED4 - Red LED roads, I want to use a stainless-steel A2. Sensors using a stainless steel hollow
Resistors (all ¼-watt, ±5% carbon, unless hollow pipe that is sealed at one end pipe cannot be used in this circuit. Imag-
stated otherwise): and contains ten normally-open type ine the oat is in between 5th and 6th
R1 - 3.3-kilo-ohm
R2-R5 - 1.5-kilo-ohm
R6-R24 - 330-ohm
R25-R34 - 56-kilo-ohm
R35-R44 - 33-kilo-ohm
R45 - 100-kilo-ohm
R46 - 2.7-kilo-ohm
R47, R48 - 680-ohm
Capacitor:
C1 - 100µF, 25V electrolytic
Miscellaneous:
LS - 8-ohms speaker 7.5 cm dia
- SS 304, 5 mm dia and 3mm
dia stainless steel rods of
appropriate length for anode
and cathodes respectively.
- Multi-core feed wire

this circuit the resistors of 56-kilo-ohm

are connected across the inputs of XOR
gates and ground, while resistors from
R2 to R5 have been used for passive pull-
down action.
Audio alarm unit. Fig. 8 shows
the circuit for audio alarm. The base of Fig. 1: Modification to level controller
transistor T2 (BC108) is connected to the
terminals of lines L-10 and L-1 via diodes magnetic reed switches on the inside reed micro switches, then no switch will be
D21 and D22 respectively and a common and one floating magnet on the outside closed and the display will show only 0,
resistor of 100-kilo-ohm. as the sensor. Could you suggest me the although the water level is in between 5th
When water touches the topmost sen- changes required in the circuit if this and 6th sensors. Moreover, the number
sor probe, transistor T2 conducts and tran- type of sensor is used? of wires from the reed switches remains
sistor T3 is cut off. As a result 3.1V devel- J.P. Thakkar the same.
oped across zener ZD1 becomes available Through e-mail Nowadays for non-conductive liq-
across pins 1 and 2 of melody generator The author, Sadhan Chandra Das, uid, coaxial or parallel-plate type ca-
IC7 (UM66). The ampli ed musical alarm replies: pacitors are used with a suitable circuit
is heard from the speaker. A1. Check IC1, IC2, and IC3 (4030), that employs a frequency-to-voltage
When the tank is neither 100% full and the continuity of the wires con- converter and displays the level of non-
nor it is above 10% (but less than 20%), nected to the sensors. If you find these conductive liquid. But for conductive
transistor T2 cuts off while transistor T3 alright, replace resistors R2 through R5 liquid like water, it is not advisable be-
is saturated to make the voltage across by 5.6k in the circuit before you switch cause due to electrolysis the sensors get
pins 1 and 2 of IC7 at almost 0V, and on the power. If you wish to construct damaged soon. The value of resistors R2
hence no sound is produced by the unit. the circuit Intelligent Water Level through R5 is 1.5k. Use 4.7k or 5.6k re-
A separate parts list and actual-size Controller' published in February issue sistors instead to avoid loading effect of
PCB layout as well as component layout of EFY, the same replacement may be ICs 4030. ฀
(Figs 9 and 10 respectively) are included
after integrating the power supply of Fig. 2
with liquid level indicator circuit of Fig. 7
and audio alarm unit of Fig. 8. ฀

ELECTRONICS PROJECTS Vol. 22 27

 INTERFACE YOUR PRINTER
WITH 8085 MICROPROCESSOR
SHAILA GHANTI

I
t is very convenient to interface a croprocessor know that its buffer is full,
TABLE 1
printer to print 8085 programs. Here and it cannot accept any more characters Pin Assignments of Centronics
a simple hardware interface circuit until it prints out some of the already Interface Connector
with its driver software is described that stored characters. A common standard for Pin No. Signal Direction
would enable student to take printout of interfacing with parallel printers is the 2 Data bit 0 (D0) In
the 8085 programs in hexadecimal codes Centronics interface. 3 Data bit 1 (D1) In
along with their memory locations in the 4 Data bit 2 (D2) In
5 Data bit 3 (D3) In
format: XXXX DD, where XXXX is the 4-bit 6 Data bit 4 (D4) In
hexadecimal address and DD is 2-bit hexa- Centronics interface 7 Data bit 5 (D5) In
decimal data. Centronics printers usually have a 36-pin 8 Data bit 6 (D6) In
For most types of printers, the data to interface connector. The pin assignments 9 Data bit 7 (D0) In
1 Strobe (STR) In
be printed is sent to the printer as of the signi cant pins of Centronics inter-
14 Auto Feed (AF) In
face connector, used in this project, are 36 Device Select (DSL) In
given in Table 1. 31 Initialise (INIT) In
Fig. 1 shows the timing waveforms 11 Busy (BSY) Out
for transferring data characters to 13 Select (SEL) Out
32 Error (ERR) Out
the printer using the basic handshake 12 Paper end (PE) Out
signals. Assuming that the printer has 19 to
been initialised, rst check the busy 30, 33 Ground —
signal pin to see if the printer is ready
to receive data. If this signal is low (not which is used for connecting 8255 to the
Fig. 1: Timing diagram busy), send an ASCII code on the eight printer, should normally have a 26-pin FRC
parallel data lines. After at least 0.5 µs, connector to meet with the corresponding
assert the STROBE connector on the kit, and the other end
signal low to tell the should have a 36-pin male Centronics con-
printer that a char- nector to go into the corresponding connec-
acter has been sent. tor on the printer.
The strobe signal Port A of 8255 is used for transferring
going low causes the the data to the printer. Port B is used for
printer to assert its checking the status signals coming from
Busy signal high. Af- the printer. Port C is used for sending the
Fig. 2: System's block diagram
ter a minimum time control signals required to activate the
ASCII characters on eight parallel of 0.5 µs the strobe signal can be raised printer. The interface signals between
lines. The printer receives the characters high again. Note that the data must be 8255 and the printer should be connected
to be printed and stores them in an inter- held valid on the data lines for at least 0.5 as show in Table 1.
nal buffer. When the printer detects a car- µs after the strobe signal is made high. (EFY Lab note. The maximum cur-
riage return (odH), it prints out the rst When the printer is ready to receive the rent that an 8255 output pin can source
row of characters from the printer buffer. next character, the BUSY signal will be and sink is limited to 400 µA and 2.5 mA,
When the printer detects a second car- low. The process continues. respectively. To enhance this capability,
riage return, it prints out the second row The 8085 microprocessor is interfaced open-collector hex buffers/drivers 7407
of characters. The process continues until to the printer through 8255 program- shown in Fig. 3 were used for all output
the desired characters are printed. mable peripheral
Transfer of ASCII codes from the interface device as TABLE II
microprocessor to a printer needs to be shown in the block Port B of 8255—(Input) Status Signals
done on a handshake basis because the diagram (Fig.2) and Cent. Pin no b2 32 13 11
microprocessor can send characters much the detailed inter- Signal PE ERR SEL BSY Comments
faster than the printer can print them. face diagram (Fig.3). Data B3 B2 BI B0
The printer must in some way let the mi- One end of the cable, 0 1 1 0 =06H (status OK)

28 ELECTRONICS PROJECTS Vol. 22

 signal (DSL*)
to select the
printer. Read
the status to
nd out wheth-
er the printer
is selected
and the Busy
signal is low.
Now send the
ASCII charac-
ter to print
the character,
followed by
the STROBE*
pulse for 0.5
µs. The proc-
ess continues
Fig. 4: Actual-size, single-sided PCB for the
till the end of printer interface circuit
the program.
The end of the
program is in-
dicated using
RST1 (CFH).
The start-
ing location of
the program
to be printed
should be
stored in D
and E regis-
ters. The eight
MSBs and
eight LSBs of
memory loca-
tion should
be stored in
Fig. 3: Schematic diagram of the printer interface circuit D register and Fig. 5: Component layout for the PCB
E register, re-
port pins. For input port pins, there is no spectively. The complete software PARTS LIST
danger of overloading, and hence these program is given with comments as Semiconductors:
pins were connected directly from the necessary. ICI, IC2 - 7407 hex buffer/driver (open
printer to the kit.) (EFY Lab note. The original program collector type)
Resistors (all ¼-watt, ±5% carbon, unless stated
was tried many times, but we did not suc- otherwise):
Printer driver program ceed. Finally, the program was extensively R1-R12 - 1-Kilo-ohm (or use one-/two-
modi ed and successfully run using Epson resistor networks
overview 9-pin printer. The program, along with Miscellaneous: - Centronics connector and
During initialisation, some memory loca- cable
Tables II and III showing the status and
tions are kept aside to
store the ASCII equiva- Table III
Port B of 8255—(Input) Status Signals
lent of the characters that
Cent pin no NU 14 31 1 NU 36 NU NU
are to be printed. This is Signal AF INIT STR DSL Comments
followed by con guration Data C7 C6 C5 C4 C3 C2 C1 C0
(initialisation) of 8255 by X 0 1 1 X 0 X X =30H
sending the mode con- X 0 0 1 X 0 X X =10H Printer
long delay initialisation
trol world to its control X 0 1 1 X 0 X X =30H
register. To initialise
the printer rst send ini- X 0 0 1 X 0 X X =20H
tialisation (INIT*) pulse Short delay strobe
X 0 1 1 X 0 X X =30H
for a few microseconds.
Then send the select NU=Not Used

ELECTRONICS PROJECTS Vol. 22 29

 8085 ASSEMBLY LANGUAGE LISTING
Memory Instructions Code Comments Memory Instructions Code Comments
Location Location
7110 LXI H, 7000 21 7156 4F the status of printer
7111 00 7157 71
7112 70 7158 MVI B, 04 06 Else counter of 4 is initialised in B
7113 LXI D2A20 11 Initialise memory locations to Store 7159 04 register to print 4 digits of memory
ASCII codes of the program. 715A CALL 7220 CD address (use subroutine to transfer
7114 20 715B 20 data to printer in polling mode).
7115 2A 715C 72
7116 MOV A, H 7C To get the ASCII codes of address 715D INX H 23 Get next memory location
7117 CALL 70FC CD of memory location of the program to 715E DCR B 05 check whether 4 characters are
7118 FC be printed using the subroutine. 715F JNZ 715A C2 transferred.
7119 71 7160 5A
711A MOV A, H 7C 7161 71
711B CALL7100 CD 7162 MVI A, 20 3E send to (20) blank space to printer
711C 00 7163 20
711D 71 7164 OUT 08 D3
711E MOV A,L 7D 7165 08
711F CALL 70FC CD 7166 MVI A, 09 3E to generate STROBE pulse to printer
7120 FC 7167 09
7121 70 7168 OUT 0B D3
7122 MOV A, L 7D 7169 0B
7123 CALL 7100 CD 716A MVI A, O8 3E
7124 00 716B 08
7125 71 716C OUT 0B D3
7126 MOV A, M 7E To get the ASCII codes of the 716D 0B
7127 CALL 70FC CD contents of the program to be 716E MVI C, 02 0E Counter of 2 is initialised in C regis-
7128 FC printed using the subroutine. ter
7129 70 716F 02 to print 2 codes.
712A MOV A, M 7E 7170 CALL 7220 CD Use subroutine to transfer data.
712B CALL 7100 CD 7171 20 in polling mode.
712C 00 7172 72
712D 71 7173 INX H 23 Get next memory location.
712E INX H 23 Increment pointer to mem. location 7174 DCR C 0D Check whether 4 characters are
712F MOV A, M 7E Move contents of mem, into acc. 7175 JNZ 7170 C2 transferred.
7130 CPI CF FE Whether it is end of the program. 7176 70
7131 CF 7177 71
7132 JNZ 7116 C2 If not, start executing from 7116 7178 MVIA, 0A 3E send LF code to printer
7133 16 7179 0A
7134 71 717A OUT 08 D3
7135 MVIA, 43 3E If it is end of the program, 717B 08
7136 43 transfer the code for CF. 717C MVIA, 0D 3E send CR code to printer
7137 STAX D 12 717D 0D
7138 INX D 13 717E OUT 08 D3
7139 MVI A, 46 3E 717F 08
713A 46 7180 MVIA, 09 3E
713B STAX D 12 7181 09
713C DCX D 1B 7182 OUT 0B D3
713D LXI H 2A20 21 Initialise mem. Pointer to block 7183 0B
713E 20 (2A20) where ASCII code of charac- 7184 MVIA, 08 3E
713F 2A ters to be printed are stored. 7185 08
7140 MVI A, 82 3E Initialise 8255 7186 OUT 0B D3
7141 82 7187 MOV A,E 7B Check wheter the full program
7142 OUT 0B D3 Write control word in control register 7188 XRA L Ad code are transferred to printer
7143 0B of 8255 7189 JNZ 7158 C2 If not, continue to transfer next
7144 MVI A, 0B 3E Reset printer. 718A 58 codes.
7145 0B 718B 71
7146 OUT 0B D3 718C MOV A,D 7A
7147 0B 718D XRA H AC
7148 CALL 7200 CD Delay for a few microseconds. 718E JNZ 7158 C2 Else, stop executing the program
7149 00 718F 58
714A 72 7190 71
714B MVI A, 05 3E Send SELECT signal. 7191 RST 1 CF
714C 05
714D OUT 0B D3 Subroutine for converting hexadecimal to ASCII codes
714E 0B 70FC RRC OF Rotate right 4 times to get 4 MSB.
714F IN 09 DB Read the status of printer to nd 70FD RRC OF
7150 09 out whether the printer is selected. 70FE RRC OF
7151 ANI 02 E6 70FF RRC OF
7152 02 7100 ANI OF E6 Mask 4 LSBs
7153 CPI 02 FE 7101 OF
7154 02 7102 CPI 0A FE Compare with 0A
7155 JNZ 714F C2 IF printer is not selected, again read 7103 0A

30 ELECTRONICS PROJECTS Vol. 22

 8085 ASSEMBLY LANGUAGE LISTING
Memory Instructions Code Comments Memory Instructions Code Comments
Location Location
7104 JC 7109 DC If it is less than 0A, 722D MOV A,M 7E Get the ASCII code from memory
7105 C6 722E OUT 08 D3 locations, send the data to printer to
7106 70 722F 08 print.
7107 ADI 07 C6 Add 07 to data 7230 MVI A,08 3E Send the strobe pulse with min
7108 07 7231 08 0.5µ duration.
7109 ADI 30 C6 Else add 30H to data to convert data 7232 OUT 0B D3
710A 30 into ASCII code. 7233 0B
710B STAX D 12 7234 MVI A,09 3E
710C INX D 13 7235 09
710D RET C9 7236 OUT 0B D3
7237 0B
Subroutine to transfer data in polling mode: 7238 MVI A,O8 3E
7220 MVI A 09 3E To generate the STROBE signal. 7239 08
7221 09 723A OUT 0B D3
7222 OUT 0B D3 723B 0B
7223 0B 723C RET C9
7224 IN 09 DB Find whether the printer is not Busy
7225 09 Subroutine for delay:
7226 ANI 01 E6 7200 MVI C, FF 0E Load C register with data FF.
7227 01 7201 FF
7228 CPI 00 FE 7202 DCR C 0D Decrement the contents of C reg.
7229 00 7203 JNZ 7202 C2 if the contents of C is not zero, goto
722A JNZ 7224 C2 7204 02 7202.
722B 24 7205 72
722C 72 7206 RET C9

MODIFIED PROGRAM USED BY EFY

Addr. Hex code Label Mnemonics Remarks Addr. Hex code Label Mnemonics Remarks
9000 310095 LXI SP, 9500H ;Initialise stack pointer 9047 3E02 VI A,02H ;ASCII code for start of text
9003 11209D LXI D,9D20H ;Store location where 9049 D308 UT 08H
9006 EB XCHG ;data to be printed starts 904B CD5092 ALL 9250H ;Call status
;into register pair DE 904E CD7092 ALL 9270H ; Call strobe
9007 11209A LXI D, 9A20H ;Location where ASCII 9051 0604 X4: MVI B,04H ;Counter of 4 for printing
;stored 9053 CD249 X2: CALL 9224H ;four digits of addresses
900A 7C X1 MOV A,H 9056 23 INX H ;of memory location
900B CDFC90 CALL 90FCH 9057 05 DCR B
900E 7C MOV A,H 9058 C25390 JNZ X2
900F CD0091 CALL 9100H 905B 3E20 MVI A,20H ;Send blank space to printer
9012 7D MOV A,L 905D D308 OUT 08H
9013 CDFC90 CALL 90FCH 905F CD5092 CALL 9250H ;Call status
9016 7D OV A,L 9062 CD7092 CALL 9270H ; Call strobe
9017 CD0091 CALL 9100H 9065 0602 VI B, 02H ;Counter of 2 for printing
901A 7E MOV A,M ;Convert data to be 9067 CD2492 X3: CALL 9224H ;two digits of data
901B CDFC90 ALL 90FCH ;printed into ASCII 906A 23 INX H
901E 7E MOV A,M 906B 05 CR B
90IF CD0091 CALL 9100H 906C C26790 JNZ X3
9022 23 INX H 906F CD9092 CALL 9290H ;Call LFCR
9023 7E MOV A,M 9072 7B MOV A,E ;Check whether all data
9024 FECF CPI CFH ;End of data? 9073 AD XRA L ;has been transfered for
9026 C20A90 JNZ X1 ;printing
9029 3E43 VI A,43H ;ASCII code of C 9074 C25190 JNZ X4
902B 12 STAX D 9077 7A MOV A,D
902C 13 NX D 9078 AC XRA H
902D 3E46 MVI A,46H ;ASCII code of F 9079 C25190 JNZ X4
902F 12 TAX D 907C 3E03 MVI A,03H ;ASCII code for end of text
9030 1B CX D 907E D308 OUT 08H
9031 21209A XI H,9A20H ;Initialise mem. Pointer 9080 CD5092 CALL 9250H ;Call status
;to start of ASCII codes 9083 CD7092 CALL 9270H ; Call strobe
9034 3E82 VI A,82H ;Initialise 8255 9086 3E04 MVIA,04H ;ASCII code for end of
9036 D30B UT 0BH 9088 D308 OUT 08H ;transmission
9038 3E30 VI A,30H ;Initialise Printer 908A CD5092 CALL 9250H ;Call status
903A D30A UT 0AH 908B CD 7092 CALL 9270H ; Call strobe
903C 3E10 VI A,10H 9090 76 HLT
903E D30A UT 0AH
9040 CD0092 ALL 9200H ;Call delay ;Subroutine for converting hex to ASCII
9043 3E30 VI A,30H 90FC 0F RRC ;Rotate four times to get MSB
9045 D30A UT 0AH 90FD OF RRC

ELECTRONICS PROJECTS Vol. 22 31

Addr. Hex code Label Mnemonics Remarks Addr. Hex code Label Mnemonics Remarks

90FE OF RRC 925B CA6692 JZ X11

90FF OF RRC 925E 0D DCR C
9100 E60F ANI 0FH ;Mask four bits of LSB 925F C25392 JNZ X8
9102 FE0A PI 0AH 9262 05 DCR B
9104 DA0991 C X5 9263 C25192 JNZ X9
9107 C607 DI 07H 9266 C1 X11: POP B
9109 C630 X5: ADI 30H 9267 C9 RET
910B 12 STAX D
910C 13 INX D ;Strobe subroutine
910D C9 RET 9270 3E20 MVI A,20H
9272 D30A OUT 0AH
;Output Subroutine 9274 C5 PUSH B
9224 7E MOV A,M ;Output one byte of data 9275 0EFF MVI C,FFH
9225 D308 OUT 08H 9277 0D X10: DCR C
9227 CD5092 CALL 9250H ;Call status 9278 C27792 JNZ X10
922A CD7092 CALL 9270H ;Call strobe 927B C1 POP B
922D C9 RET 927C 3E30 MVI A,30H
927E D30A OUT 0AH
;Delay subroutine 9280 C9 RET
9200 C5 PUSH B
9201 06FF MVI B,FFH ;Line feed and Carriage return Subroutine
9203 0EFF X7: MVI C,FFH 9290 3E20 MVI A,20H ;ASCII code for space
9205 0D X6: DCR C 9292 D308 OUT 08H
9206 C20592 JNZ X6 9294 CD5092 CALL 9250H ;Call status
9209 05 DCR B 9297 CD 7092 CALL 9270H ;Call strobe
920A C20392 JNZ X7 929A 3E0A MVI A,0AH ;ASCII Code for Line feed
920D C1 POP B 929C D308 OUT 08H
920E C9 RET 929E CD5092 CALL 9250H ;Call status
92A1 CD7092 CALL 9270H ;Call strobe
;Status subroutine 92A4 3E0D MVI A,0DH ;ASCII code for Carriage
9250 C5 PUSH B ;Return
9251 06FF X9: MVI B,FFH 92A6 D308 OUT 08H
9253 0EFF XS: MVI C,FFH 92A8 CD5092 CALL 9250H ;Call status
9255 DB09 IN 09H ;In port B 92AB CD 7092 CALL 9270 H ;Call strobe
9257 E60F ANI 0FH ;Compare with 06H 92AE C9 RET
9259 FE06 CPI 06H

control signals that have been used in
program implementation, is included for
the bene t of readers, who may try both
the programs, if desired.)
Address map of devices used:
RAM locations used: 9000H to 92AEH
(70FCH onwards used by author)
PORT A (output): 08H
PORT B (input): 09H
PORT C (output): 0AH
Control word register: 0BH
Important memory location:
Stack pointer initialised: 9500H
Data to be printed is stored at: 9D20H
onward ASCII conversion of data to be
printed starts at 9A20H. Data to end with
CFH as the last byte.
The actual-size, single-sided PCB lay-
out of the printer interface circuit and the
component layout are shown in Figs 4 and
5, respectively. ฀

32 ELECTRONICS PROJECTS Vol. 22

 MORSE PROCESSOR
JUNOMON ABRAHAM

Mo
rse code, introduced by Samuel been used, which relieves the micro- 7-segment display pattern employed
Morse, is still used universally processor from scanning the keyboard for different characters is shown in
even though better modes of and display. Here, 25 keys, includ- Table I.
communication are now available Follow- ing SHIFT and CTRL keys, and six Two hardware interrupts, RST5.5
ing are the main reasons for its preference 7-segment common cathode character and RST6.5, are used for reading the key
over other means of communication. displays are used. Though 7-segment entries. These are driven by the IRQ line
1. It enables communication with displays are not suitable for alpha- from the keyboard/display interface IC
distant stations, using low-power trans- numeric characters, these have been 8279.
mitters. used here with some compromise for A buffer (IC8) is connected at the
2. It avoids the problem of regional reducing the overall cost. (Note: The display output of 8279 to drive the
accents and pronunciation. use of dot-matrix LCD display avoids 7-segment displays. The encoded scan
3. It has the ability to override noise the dif culty in displaying characters lines (SL2-SL0) are decoded by an octal
as it occupies only a fraction of the in 7-segment format. One can go for a decoder 74LS138 (IC9), whose outputs
bandwidth microcontroller design, if needed.) The drive the common cathode of displays
required for via transistor switches. The keys are
a radio te- TABLE II wired in such a way that those can be
lephony sig- Address Distribution represented by the seven higher order
nal. Device Address rate of the keyboard data.
The cir- EPROM 0000 to 03FF Morse signals in the form of sound are
cuit presented RAM 1000 to 17FF converted to microprocessor-compatible
here converts 8279: signals. The arrangement comprises con-
Command Port 21
text into the Data Port 20
denser microphone, preamplifier, and
correspond- retriggerable monostable multivibrator
ing Morse
code, and vice
versa. The
high light of
this circuit is
that is can in-
terpret Morse
signals avail-
able in the
form of sound
from ham
radio or any
other source.
It is very use-
ful for not
only learning
but also for transmission and reception of
Morse code. It can nd application in ham
radio, telegraphy, etc.

Hardware
The circuit is con gured around the
basic 8085 microprocessor. For simplify-
ing the overall design, a programmable
keyboard/display interface 8279 chip has

ELECTRONICS PROJECTS Vol. 22 33

 PARTS LIST and also acts as a stack. One can en- rmware is divided into the following
Semiconductors: ter/store a maximum of approximately modules: (a) booting, (b) keyboard, (c)
IC1 - 8085A microprocessor 1,750 characters in the RAM. This is transmit, (d) receive, (e) play, and (f)
IC2 - 74LS373 octal D-type latches adequate for normal applications. lookup table.
IC3 - 6116 RAM (2 kB)
IC4 - 27C32 EPROM (4 kB) In case one needs to store lengthy The logic of the program can be gener-
IC5 - 8279 keyboard/display decoder text, one should use a larger capac- ally understood from the Assembly lan-
IC6, IC9 - 74LS138 3-bit binary ity RAM. Battery backup may be guage listing given in Appendix A. A brief
decoder used for avoiding loss of data due to description of each module is, however
IC7 - 74LS123 retriggerable monosta-
power failure. The low-level address/ given below:
ble multivibrator
IC8 - 74LS244 octal bus driver data lines of 8085 are demultiplexed (a) Booting: The section initializes
IC10 - 7805 +5 volt regulator using an octal transparent latch stack pointer 8279 and the interrupts. It
T1 - BC548 npn transistor IC 74LS373. also xes defaults speed for Morse code.
T2 - BC549 npn transistor The address bits A12 and A13 are de- It is the rst module executed when you
T3-T8 - BC558 pnp transistor
Dl - 1N4148 switching diode coded by IC6 to generate chip select (CS) switch on the power supply.
LED1 - LED signals to various ICs. The address map of (b) Keyboard: When a key is
DIS1-DIS6- LTS543 common-cath- devices is indicated in Table II. pressed, IRQ pin of 8279 interrupts
ode 8085. The ISR (interrupt service rou-
display
tine) reads the keyboard data and, if
Resistors (all ¼ watt, ±5% carbon, unless Firmware needed, does some manipulations. It also
stated otherwise) The software driver routines for the cir- displays the entered characters in the
Rl - 68-kilo-ohm
R2 - 3.3-kilo-ohm cuit, along with their Assembly language 7-segment display. (Table III has been
R3 - 2.2-kilo-ohm code, are listed in Appendix A. Basically, included by EFY for ready reference by
R4 - 5.6-kilo-ohm the following functions are performed by the readers to know the hex data gen-
R5 - 1-mega-ohm
R6 - 15-kilo-ohm the software program: erated by 8279 when any key is either
R7, R8 - 1-kilo-ohm 1. Initialisation of the peripherals. pressed alone or in combination with
R9-R16 - 68-ohm 2. Reading the depressed key data and SHIFT or CTRL key.)
R17-R22 - 220-ohm
R23 - 180-ohm its storage in RAM. (c) Transmit. This module converts
VR1 - 2.2-kilo-ohm preset 3. Writing data into the display RAM each character in the RAM to its corre-
VR2 - 100-ohm preset
in 8279. sponding Morse code signals which are
Capacitors:
C1 - 2.2uF, 16V electrolytic
4. Generation of Morse code. output through the SOD line. The speed
C2, C4, C6 - 0.luF ceramic disc 5. Recognition of Morse code from its of transmission or words per minute de-
C3 - 10uF, 16V electrolytic sound. pends on the value entered in the setup
C5 - 0.001uF ceramic disc
C7 - 10pF ceramic disc 6. Giving proper messages at appropri- menu.
Miscellaneous: ate time. (d) Receive. The acquisition of
PZ1 - Piezo buzzer Since Morse code is a time-dependent Morse code is done by checking the
MIC - Condenser microphone code, the program contains many jump presence of sound with time. The
S1-S26 - Tactile switches for instructions. The program has been module continuously monitors the SID
keyboard
XTAL - 6.144 MHz crystal make interactive and user-friendly. The pin of 8085 microprocessor, where the

74LS123 (IC7). The out-

put of IC7 drives SID pin Table IV
Lookup Table
of 8085 and it is in ‘high’
logic state when a sound Chr/word Address Hexcode Chr/word Address Hexcode Chr/word Address Hexcode
is detected by the micro- 0 0300 3FAA0E00 J 034C IE A9 03 00 . 03B4 80 99 39 00
phone. The sensitivity of 1 0304 06 A9 0E 00 K 0350 70 E6 00 00 , 03B8 04 5A 3A 00
2 0308 5BA5OEOO L 0354 38 59 03 00 ; 03BC 84 66 36 00
the ampli er can be ad- 3 030C 4F95 0E00 M 0358 55 3A 00 00 ? 03C0 D3 A5 35 00
justed by preset VR2. 4 0310 66 55 0E 00 035C 46 - 03C4 08 56 39 00
The converted Morse 5 0314 6D55 0D00 03C8 00 3F 00 00
code drives a piezo buzzer 6 0318 7D 56 0D 00 N 0380 54 36 00 00 EOM* 03CC OF 99 0D 00
7 031C 07 5A0D00 O 0384 5C EA 00 00 WAIT* 03D0 7E 59 0D 00
via a transistor connected
8 0320 7F 6A 0D 00 P 0388 73 69 03 00 BT* 03D4 49 56 0E 00
at the SOD line of 8085 9 0324 6F AA 0D 00 Q 038C 67 9A 03 00 SK* 03D8 4F 95 39 00
microprocessor. Intensity A 0328 77 39 00 00 R 0390 50 D9 00 00 SELECt 03DC 6D 79 38 79
of the sound can be con- B 032C 7C 56 03 00 S 0394 6D D5 00 00 03E0 39 78 78 50
trolled by potentiometer C 0330 39 66 03 00 T 0398 78 0E 00 00 trAnst 03E4 77 54 6D 78
D 0334 5E D6 00 00 U 039C 3E E5 00 00 M oVEr 03E8 55 00 5C 2A
VR1. E 0338 79 0D 00 00 V 03A0 2A 95 03 00 rECEIE 03EC 79 50 50 79
The firmware is F 033C 7165 03 00 W 03A4 6A E9 00 00 03F0 39 79 30 79
stored in 27C32 (4k G 0340 3D DA 00 00 X 03A8 52 96 03 00 SEtup 03F4 6D 79 78 3E
EPROM—only 1 kB H 0344 76 55 03 00 Y 03AC 6E A6 03 00 03F8 73 00 00 00
I 0348 30 35 00 00 Z 03B0 4B 5A 03 00 03FC 00 00 00 00
is needed for the pro-
gram). RAM 6116 stores *Notes: 1. EOM=End of message= 3 2. WAIT= 8
the keyboard entries 3. BT=Sentence separation= 3 4. SK=End of work= 3

34 ELECTRONICS PROJECTS Vol. 22

ELECTRONICS PROJECTS Vol. 22 35
sound-converted logic level (depending
on whether the sound is present or not)
is available. It compares this logic level

Size 215×100 mm
with a pre xed time value and accord-
ingly decides whether the sound was
due to dot or dash. Moreover, it displays
characters corresponding to the entered
Morse code.
(e) Display. This module displays
characters in the moving display format
as per the entered message. The speed
of movement is xed to approximately
three characters per second.
(f) Lookup table (Table IV). This
is a block of data, which contains the
7-segment data for every character
and the data needed for Morse code
generation or reception. Each character
takes four EPROM locations. The rst
location indicates the 7-segment data,
while the second and third locations
hold the Morse data code. The fourth
location is unused. (EFY Note. We
have included Table IV showing the
hex data generated by depression of
any key alone or in combination with
SHIFT or CTRL keys, for ready refer-
ence by the readers.)

Control-key functions
Before going to the operating procedure,
we have to know the functions of key as-
sociated with CTRL key.
CTRL+SETUP (8EH). The default
speed is initialized for approximately
5 words/minute. If you want to change
this setting, you can do so by using this
control key combination. When you press
this combination k, the message ‘SEtUP’
is displayed. Here you can enter any
one of the characters ranging from ‘1’
through ‘9’ and ‘A’ through ‘K’ to change
the speed. Note that the minimum speed
is associated with ‘K’ and the maximum
with ‘1’.
CTRL+CLEAR (98H). It clears the
RAM content.
CTRL+PLAY (84). CTRL+PLAY is
used for displaying the RAM content in
moving format. You can interrupt any
process by pressing any control key that
has no function.
CTRL+CONT (86). It is used for
continuing the play operation if it were
interrupted.

Operating procedure
1. Switch on the power supply. A message Fig. 2: Actual-size, single sided PCB for the Morse processor

36 ELECTRONICS PROJECTS Vol. 22

 APPENDIX ‘A’: 8085 ASSEMBLY LANGUAGE PROGRAM LISTING
Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments
Booting 0077 3A5017 LDA 175OH The following CNTL
0000 31FF17 LXI SP.17FFH 007A B7 ORAA key functions are only for
Initialise stack pointer TRANSMIT mode
0003 3E10 MVIA.10H 007B CA8000 JZ 0080H Checking whether we were
Initialise 8279 in the TRANSMIT mode
0005 D321 OUT 21H 007E FB El
0007 3E40 MVI A.40H 007F 76 HLT
0009 D321 OUT 21H 0080 F1 POPPSW Getting key closure data
000B 3E0D MVI A.0DH which is stored in stack
000D 30 SIM 0081 FE92 CPI92H Checking CNTL+<—key
Activating RST6.5 0083 C28900 JNZ 0089H
000E 325017 STA 1750H 0086 2B DCXH Shifting the characters
Updating mode and position 0087 2B DCXH right by one place
data 0088 C9 RET
0011 211D00 LXI H.001DH 0089 FE90 CPI90H Checking CNTL+ßkey
0014 225117 SHLD 1751H 008B C8 RZ Shifting the characters by
0017 21246C LXIH.6C24H Fixing one place
default setup 008C FE80 CPI80H Checking CNTL+TABR key
001A 227017 SHLD 1770H 008E C29600 JNZ 0096H
001D 11DC03 LXI D.03DCH 0091 110500 LXID.0005H Shifting the characters left
0020 CDE000 CALL DISPLAY Display ‘SELECt’ by six places
0023 FB El 0094 19 DAD D
0024 76 HLT Halt 0095 C9 RET
0096 FE82 CPI 82H Checking CNTL+TABL key
RST 5.5 0098 C2A000 JNZ 00A0H
002C C3F700 JMP 00F7H Go to ISR of RST5.5 009B 11F9FF LXI D.,FFF9H Shifting the characters right
by six places
RST 6.5
009E 19 DAD D
0034 DB20 IN 20H Reading keyboard data from
009F C9 RET
IC 8279
00A0 FE88 CPI88H Checking CNTL+ START
0036 F5 PUSHPSW Store it in the stack
key
0037 FE8A CPI8AH Checking CNTL+ RECEIVE
00A2 CA1001 JZ TRANSMIT
key
00A5 FE96 CPI 96H Checking CNTL+DEL key
0039 CA0002 JZ RECEIVE
00A7 C2BA00 JNZ 00BAH
003C FE8C CPI8CH Checking CNTL+
00AA E5 PUSH H
TRANSMIT key
00AB 46 MOV B,M Delete one character in the
003E CA8001 JZ KEYBOARD
left most position of the display
0041 FE84 CPI 84H Checking CNTL+PLAY key
00AC 2B DCX H
0043 CAD001 JZ PLAY
00AD 70 MOV M,B
0046 FE86 CPI 86H Checking CNTL+
00AE 23 INX H
CONTINUE key
00AF 23 INX H
0048 CAD501 JZ 01D5H
00B0 7C MOVA.H
004B FE98 CPI98H
00B1 FE17 CPI 17H
Checking CNTL+ CLEAR
00B3 DAAB00 JC 00ABH
kev
00B6 El POPH
004D C26000 JNZ 0060H
00B7 2B DCX H
0050 210010 LXIH.1000H Clearing the RAM
00B8 2B DCX H
0053 36C8 MVI M.C8H
00B9 C9 RET
0055 23 INXH
00BA FE94 CPI 94H Checking CNTL+INS key
0056 7C MOV A, H
00BC C2D100 JNZ 00D1H
0057 FE17 CPI 17H
00BF 2B DCX H Inserting a space for adding
0059 DA5300 JC 0053H
character
005C 2A5117 LHLD 1751H Return to mode from 00C0 E5 PUSH H
005F E9 PCHL where clearing action is 00C1 46 MOVB.M
called 00C2 36C8 MVI M.C8H
0060 FE8E CPI8EH Checking CNTL+ SETUP 00C4 23 INX H
key 00C5 7E MOV A,M
0062 C27700 JNZ 0077H 00C6 70 MOV M,B
0065 3E0E MVIA.0EH Activating RST5.5 00C7 47 MOV B,A
0067 30 SIM 00C8 7C MOVA.H
0068 11F403 LXI D.03F4H 00C9 FE17 CPI 17H
006B CDE000 CALL DISPLAY Display the message ‘SEtUP’ 00CB DAC400 JC 00C4H
006E FB El 00CE E1 POPH
006F 76 HLT 00CF 2B DCX H
0070 3E0D MV1A.0DH Activating RST6.5 00D0 C9 RET
0072 30 SIM 00D1 FE7F CPI7FH Checking whether key data
0073 2A5117 LHLD 1751H is valid character
0076 E9 PCHL Return to mode from where 00D3 D2CF00 JNC 00CFH
setup action is called 00D6 07 RLC

ELECTRONICS PROJECTS Vol. 22 37

Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments

00D7 77 MOVM,A Enter it into the RAM 0156 217017 LXI H.1770H
00D8 C9 RET Return 0159 46 MOVB.M
015A CD7001 CALL DELAY1 Waiting
DISPLAY SUBROUTINE:
015D 05 DCRB
00E0 0E06 DISPLAY: MVI C,06H Display six characters taken
015E C25A01 JNZ015AH
from lookup table
0161 Fl POPPSW
00E2 1A LDAX D Lookup table is pointed to
0162 0F RRC
by DE -reg pair
0163 0F RRC
00E3 D320 OUT 20H
0164 0D DCRC
00E5 13 INX D
0165 C22501 JNZ 0125H
00E6 OD DCR C
0168 C32101 JMP 0121H
00E7 C2E200 JNZ 00E2H
00EA CDCOO1 CALL DELAY2 Wait for some time
DELAY1 SUBROUTINE:
00ED CDC001 CALL DELAY2
0170 E5 DELAY1: PUSH H Executing these instructions
00F0 C9 RET Return
require approximately
0171 21CF01 LXIH.01CFH 3 msec
VECTOR RST 5.5
0174 2B DCXH
00F7 DB20 IN 20H Reading key closure data
0175 7C MOVA.H
from 8279
0176 B5 ORAL
00F9 E63F ANI3FH
0177 C27401 JNZ0174H
00FB 07 RLC
017A E1 POPH
00FC 327017 STA 1770H Storing clot value
017B C9 RET
00FF 47 MOV B,A
0100 80 ADD B
KEYBOARD SUBROUTINE:
0101 80 ADDB
0180 AF KEYBOARD: XRAA Updating mode and positing
0102 327117 STA 1771H Storing dash value
data
0105 C9 RET Return
0181 325017 STA 1750H
0184 218001 LXIH.0180H
TRANSMIT SUBROUTINE:
0187 225117 SHLD 1751H
0110 31FF17 TRANSMIT: LXI SP.17FFH
018A 11E203 LXI D.03E2H Displaying message
0113 7C MOVA.H
018D CDE000 CALL DISPLAY ‘trAnSf for indicating the
0114 FE17 CPI17H Checking end of mem.
TRANSMIT mode
0116 D2B301 JNC 01B3H
0190 31FF17 LXI SP.17FFH
0119 1603 MVID.03H
0193 210610 LXIH.1006H Entering keyboard data to
011B 5E MOVE.M
the RAM
011C 1A LDAX D
0196 11FBFF LXI D.FFFBH
011D D320 OUT20H Display character in the
0199 19 DADD
RAM
019A 0E06 MVI C.06H
011F F3 DI
019C 1603 MVID.03H
0120 E5 PUSHH
019E 5E MOV E,M
0121 0EO4 MV1C.04H Morse code generation
019F 1A LDAX D
0123 13 INXD
01A0 D320 OUT20H
0124 1A LDAX D
01A2 23 INX H
0125 F5 PUSHPSW
01A3 0D DCRC
0126 217017 LXIH.1770H
01A4 C29E01 JNZ 019EH
0129 E603 ANI 03H
01A7 7C MOVA.H
012B FE01 CPI01H
01A8 FE17 CPI17H Checking end of mem.
012D CA4801 JZ 0148H
01AA DAB301 JC 01B3H
0130 23 INXH
01AD 11E803 LXI D.03E8H
0131 FE02 CPI02H
01B0 CDE000 CALL DISPLAY If mem. is over display
0133 CA4801 JZ 0148H
‘MoVEr’
0136 FE03 CPI 03H
01B3 FB El
0138 CA5901 JZ0159H
01B4 76 HLT
013B Fl POPPSW
01B5 C39601 JMP 0196H
013C El POPH
0131 FB El
DELAY2 SUBROUTINE:
013E 7E MOVA.M
01C0 0E9F DELAY2: MVIC.9FH Wait approximately
013F 23 INXH
400 msec
0140 FECC CPICCH Checking end of message
01C2 CD7001 CALL DELAY1
character’]’
01C5 0D DCRC
0142 C21001 JNZ0110H
01C6 C2C201 JNZ 01C2H
0145 C3B301 JMP01B3H
01C9 C9 RET
0148 3ECD MVIA,CDH Setting SOD line
014A 30 SIM
PLAY SUBROUTINE:
014B 46 MOVB.M
01D0 1603 PLAY: MVI D.03H
014C CD7001 CALLDELAY1 Waiting
01D2 210510 LXI H.1005H
014F 05 DCRB
01D5 F3 DI
0150 C24C01 JNZ 014CH
01D6 23 INXH
0153 3E4D MVIA.4DH Resetting SOD line
01D7 7C MOVA.H
0155 30 SIM

38 ELECTRONICS PROJECTS Vol. 22

Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments

01D8 FE17 CPI 17H Checking end of mem. 0258 OF RRC

01DA D2EB01 JNC 01EBH 0259 OF RRC
025A B2 ORA D
01DD 5E MOVE.M 025B 4F MOVC,A
01DE 1A LDAX D 025C ID DCR E
01DF D320 OUT20H Displaying data in RAM 025D C22902 JNZ 0229H
0260 El POP H
01E1 CDC001 CALLDELAY2 Wait for some time 0261 71 MOVM.C
01E4 FB El 0262 23 INX H
01E5 7E MOVA.M 0263 C32302 JMP 0223H
0266 79 MOVA.C
01E6 FECC CPICCH Checking end of mem. 0267 OF RRC
symbol’]’ 0268 OF RRC
01E8 C2D501 JNZ 01D5H 0269 F6C0 ORIC0H
026B ID DCR E
01EB C3B301 JMP01B3H Go to keyboard module 026C CA7402 JZ 0274H
026F OF RRC
RECEIVE SUBROUTINE: 0270 OF RRC
0271 C36B02 JMP 026BH
0200 3EFF RECEIVE: MVIA.FFH Updating mode and position 0274 El POP H
data 0275 77 MOV M,A
0202 325017 STA 1750H 0276 0638 MVI B.38H
Comparing obtained
0205 210002 LXI H,0200H 0278 21FD02 LXI H.02FDH moree
0208 225117 SHLD 1751H code data with
020B 11EE03 LXI D.03EEH lookup data
027B 3A8017 LDA 1780H
020E CDE000 CALL DISPLAY Display message ‘rECEIE’ 027E 23 INXH
0211 11FA03 LXI D.03FAH 027F 23 INXH
0214 CDE000 CALL DISPLAY Clear the display 0280 23 INX H
0281 23 INXH
0217 FB El 0282 05 DCR B
0218 110510 LXI D.1005H Morse code aquisition 0283 C29102 JNZ 0291H If given
021B 13 INXD morse code is
invalid, display V
021C D5 PUSH D 0286 FE04 CPI 04H
021D 218117 LXIH.1781H 0288 DA1D02 JC 021DH
0220 3600 MVI M.00H 028B 215C03 LXI H.035CH
028E C39F02 JMP 029FH
0222 2B DCX H 0291 BE CMPM
0223 E5 PUSH H 0292 C27B02 JNZ 027BH
0224 0E00 MVI C,00H 0295 3A8117 LDA 1781H
0298 23 INXH
0226 1E04 MVI E.04H 0299 BE CMP M
0228 61 MOVH.C 029A 2B DCX H
0229 0600 MVI B.00H 029B C27B02 JNZ 027BH
022B CD7001 CALL DELAY1 029E 2B DCX H
029F Dl POPD
022E 04 INR B 02A0 7A MOV A,D
022F 20 RIM 02A1 FE17 CPI 17H
Reading the SID pin Checking end of mem.
02A3 D2D102 JNC 02D1H
0230 07 RLC 02A6 7E MOVA.M
0231 DA2B02 JC 022BH 02A7 D320 OUT 20H Display
0234 24 INR H the character
02A9 7D MOV A,L Store
0235 3A7117 LDA 1771H data, corresponding
0238 BC CMPH 02AA 12 STAXD to
Checking for the space displayed character, in
the RAM
between characters 02AB 0600 MVI B,00H
0239 DA6602 JC 0266H 02AD 217017 LXI H.1770H
023C 78 MOV A,B 02B0 7E MOVA.M
02B1 07 RLC
023D FE02 CPI02H 02B2 23 INX H
023F DA2902 JC 0229H 02B3 86 ADD M
0242 2600 MVI H.00H 02B4 D2B802 JNC 02B8H
02B7 04 INRB
0244 1640 MVI D,40H 02B8 4F MOV C,A
0246 3A7117 LDA 1771H 02B9 0B DCX B
0249 OF RRC 02BA CD7001 CALL DELAY1
02BD 20 RIM
024A B8 CMPB 02BE 07 RLC
Checking for dot and dash 02BF DA1B02 JC 021BH Check
024B D25702 JNC 0257H for space between
02C2 78 MOVA.B words
024E 7A MOV A,D 02C3 B1 ORAC
024F 07 RLC 02C4 C2B902 JNZ 02B9H
0250 57 MOV DA 02C7 AF XRAA
02C8 D320 OUT 20H Giving
0251 00 NOP space in display
0252 00 NOP 02CA 13 INX D
0253 00 NOP 02CB 3EC8 MVI A,C8H
02CD 12 STAX D Store
0254 00 NOP the apace data in the
0255 00 NOP RAM
0256 00 NOP 02CE C31B02 JMP021BH Repeat
the process
0257 79 MOVA.C 02D1 76 HLT Halt
Constructing morse code
data

ELECTRONICS PROJECTS Vol. 22 39

‘SELECt’ will be displayed. By depressing
the appropriate key, you can select any
one of the following modes: (a) transmit,
(b) receive, (c) setup, (d) play, (e) continue,
and (f) clear.
2. Press CTRL+TRANSMIT keys
for entering into the transmit mode.
A message ‘trAnSt’ appears for a sec-
ond, after which you can enter your
message.
3. At the end of the message you have
to enter ‘]’ symbol (by pressing SHIFT+]
keys, i.e. 66H) for invoking the micro-
processor.
4. By the use of arrow key ( or 
or by TAB (TAB R or TAB L) keys, set
the location in the message at which the
transmission is to start. If you want to
transmit the message from beginning
depress CTRL+TRANSMIT keys again
for getting into the rst character.
5. Press CTRL+START keys for get-
ting Morse code of the message.
6. You can go to any other mode by
selecting the correspond mode before n-
ishing the transmission or later.
7. For entering into the receive
mode, press the CTRL+RECEIVE keys.
You will see the ‘rECEIE’ message for
one second.
8. Generate Morse code using a buzzer,
voice, or some other source (such as ham
radio and recorded tape).
9. The acceptance of sound will
be indicated by LED1 for duration of
‘Dit’/’Dash’. If LED does not light, adjust
the gain of the ampli er using potmeter
VR2.
10. The converted data can be replayed
by pressing the CTRL+PLAY keys.
Note. 1. The clear and setup control
keys can be used, at any time, if needed.

Construction
PCB designed particularly for this
circuit (as given in Fig. 2, with compo-
nent layout shown in Fig. 3) is needed
for making this circuit. IC bases are
preferred for xing the ICs. For con-
tinuous operation, provide a heat
sink for the regulator IC. Since this is
based on time comparison, it is neces-
sary to use the correct frequency crystal
(6.144 MHz).
Fig. 3: Component layout for the PCB

Readers’ comments: Going through the software, we found an anomalies in the software.
Q1. In the software part of this project error at the address 003CH, after which Sidharth M. Modi
some steps are missing, due to which the processor doesn’t jump to the transmit Mumbai
the processor is not functioning properly. mode and hangs up. Please correct the Q2. The project ‘Morse Processor’ pub-

40 ELECTRONICS PROJECTS Vol. 22

lished in March issue correctly outputs in
the initial stages but displays the message
‘transt’ on going to the transmit mode.
After this when I press any key, it doesn’t
take the input and doesn’t display the
same in the 7-segment display. As a corol-
lary, it’s also not giving the corresponding
Morse code.
Sunil Kumar B.
Through e-mail
Q3. How can I interface CRT display
with 8085 microprocessor? Also provide
me the complete circuit along with the IC
numbers.
Anwar Ali, Hyderabad
The author, Junomon Abraham, re-
plies:
A1. The rmware is correct and the
same was duly tested at EFY. “You need
not doubt the code at location 003CH,
where it checks for the Ctrl+Transmit
key. From here, it goes to the keyboard
routine and feeds the message to the
RAM. The actual conversion process
starts when we press Ctrl+Start key,
during which the processor goes to the
transmit routine.
A2. Make sure that you have loaded
the look-up table (Table IV) in the
EPROM and that the entered program
is absolutely correct. If the same condi-
tions still persist, the problem is with
your hardware.
A3. It is possible to add a CRT control-
ler to 8085 by changing the rmware. You
can use the easily available 6845 CRT
controller. The article based on this IC
was published in the book Learn to Use
Microprocessors by K. Padmanabhan pub-
lished by EFY. The project ‘Video Display
Add-On Board for the 8085 Kit’ based on
9364 chip was published as a technical
article on page 21 in EFY’s Aug. ’83 issue.
The same is also reproduced in Chapter XI
of the above titled book.
ELECTRONICS PROJECTS Vol. 22 41
 ACCESS-CONTROL SYSTEM
BHASKAR BANERJEE

T
he easy-to-construct access control If any one or more of the six consecu- IC4). Each CD4508 contains two complete-
(code lock) circuit presented here tive keyboard-entered digits do not con- ly independent 4-bit data latches having a
incorporates the following unique form to the predetermined code, an alarm common power supply. The 6-digit code is
features: generator sounds the alarm to indicate stored in these latches.
(a) Many people can use the same sys- wrong code. If the result of nal compari- The 4-bit data bus originating from
tem with their own unique 6-digit code. son of all the six digits is correct, a mono the output of IC1 is connected to data
(b) A single-digit system code has been multivibrator, serving as lock driver for
PARTS LIST
included, which is common to all users of opening/closing a lock, gets activated for
the system. It can be easily changed with a xed preset duration. Semiconductors:
IC1 - 74C922 16-key encoder
the help of DIP switches. The detailed description of individual IC2-IC4 - CD4508 dual 4-bit latch
units, as shown in Fig. 2, is as follows: IC5 - CD4017 decade counter
Keyboard and keyboard encoder. IC6 - 27C32 EPROM
Description The keyboard consists of 16 push-to-on IC7-IC9 - CD4063 4-bit magnitude
comparator
The block diagram of the system shown type keys in a 4x4 matrix format. It can be IC10 - CD4528 dual retriggerable
in Fig. 1 provides an overall view of its made using data switches or one can use monostable
composition and working. A 16-digit key- membrane-type keyboard at some extra IC11 - NE555 timer
pad is used for sequentially entering six cost. The keys should be numbered in Hex IC12 - CD4069 Hex inverter
Hex numbers, which are decoded by the as shown in the gure. T1-T4 - BC547 npn transistor
T5 - SL100 npn transistor
keyboard encoder into their equivalent The encoder is built around 74C922 T6 - 2P4M SCR
binary numbers and stored in separate (IC1), which is a 16-key keyboard encoder. D1, D2, D4 - 1N4148 switching diode
data latches in binary form. It generates a 4-bit binary number corre- D3 - 1N4007 recti er diode
The rst three Hex numbers are used sponding to the key pressed; for example, LED1-LED3 - Red LED
LED4 - Green LED
as an address for an EPROM, which shorting pin 1 (R1) with pin 11 (C1) gener-
stores a predetermined code at pre xed ates the binary equivalent of digit ‘0’. Resistors (¼-watt ±5% carbon, unless stated
otherwise)
addresses allocated to separate users or Whenever a key is pressed, the signal R1, R3, R4,
used for separate purposes. The code data generated by this encoder IC is available R15, - 10-kilo-ohm
output from EPROM (one byte/two nibbles) as logic ‘high’ output at pin 12 and is used R2, R5, R8,
at a speci ed address is compared with to activate a piezo-buzzer (PZ1) via tran- R21, R22 - 4.7-kilo-ohm
R6 - 18-kilo-ohm
the next two keyboard entries in two 4-bit sistor T1 (BC547). The continuous tone of R7 - 10-mega-ohm
comparators that are cascaded together. PZ1 indicates that a key is pressed. The R9 - 2.2-mega-ohm
The resultant outputs of these two key-pressed signal is also used to store R10, R11,
comparators are connected to the next data in the latches. R17-R20 - 1-kilo-ohm
comparator stage, in which the last The output from pin 12 is connected to R12-R14 - 470-ohm
R16 - 47-kilo-ohm
keyboard digit (i.e. sixth Hex digit) is pin 13 of IC5 (CD4017 counter) for clock- R23 - 47-ohm
compared with the system code selected ing at its trailing edge. On each clocking, Capacitors:
by DIP switch. counter IC5 advances by one count and C1, C7, C8,
thereby stores C12 - 0.1µF ceramic disc
data in separate C2 - 2.2µF, 25V electrolytic
C3, C5, C6,
data latches one
C9, C10 - 22µF, 25V electrolytic
after the other. C4, C13 - 47µF, 25V electrolytic
IC1 also holds C11 - 470µF, 25V electrolytic
the last number Miscellaneous:
at its output S1 - Push-to-on switch
pins. S2 - Push-to-off switch
- 4x4 keyboard matrix
Data latch-
PZ1 - Continuous tone-type piezo-
es. There are buzzer
six data latches RL1 - 9V, 200-ohm, 1 C/O relay
formed from S3 - 4-way DIP switch
three CD4508 - Regulated 5V power supply
etc
Fig. 1: Block diagram of the access-control system ICs (IC2 through

42 ELECTRONICS PROJECTS Vol. 22

 43
ELECTRONICS PROJECTS Vol. 22
Fig. 2: Schematic diagram of access-control system

Fig. 3: Actual-size, single-sided PCB layout for access-control system
input pins of all the six latches in parallel.
For example, pin 17 (QA) of IC1 is con-
nected to the corresponding pins 4 and 16
of all the latches as the LSB of 4-bit binary
output from IC1. Initially, pin 3 of IC5
provides a high output to ‘clear’ and ‘store’
pins 1 and 2 of IC2A, thereby clearing its
4-bit register.
When a key is pressed, the equivalent
binary code is present at data input pins
of all the latches. On releasing the key,
pin 12 of IC1 changes its state from ‘high’
to ‘low’, thereby generating the required
clock pulse for IC5. This clocking makes
pins 3 and 2 of IC5 low and high, respec-
tively, causing the binary data correspond-
ing to the rst Hex digit keyboard entry ent locations (addresses) in the EPROM
44 ELECTRONICS PROJECTS Vol. 22
to be stored and available at the output
of IC2A.
Similarly, when the second key is
pressed, new data is stored in IC2B with-
out affecting the previously stored data in
IC2A. The outputs from rst three data The outputs from IC9 are available only
latches are connected to address pins of
EPROM 27C32 (IC6). The outputs from
fourth and fth data latches are connected erator is built around a 555 timer (IC11).
to two 4-bit magnitude comparators IC7
and IC8 (CD4063), and the output from
sixth data latch is connected to a similar
4-bit magnitude comparator IC9 for fur-
ther processing.
The memory. All 8-bit codes, except
the 4-bit system code, are stored at differ-
(IC6). Out of the six Hex digits, rst ve
digits are used as personalised code, and
out of these ve digits, the rst three are
used to form an address for EPROM.
The leftmost digit of the code is the
MSD (most signi cant digit) and the third
digit from left is the LSD (least signi -
cant digit) of the 12-bit wide address for
IC6. The fourth and fth digits from left
are to be the same as the data stored in
IC6 (beforehand) at that particular ad-
dress. Thus, when a code is entered via
the keyboard, the fourth and fth digits
are compared with the data stored at the
address formed by the rst three digits.
(The EPROM can be programmed with
the help of ‘Manual EPROM Programmer’,
and may be replaced by an EEPROM for
better reliability.)
Code comparator. There are three
4-bit comparators (IC7 through IC9)
used in the circuit, which are cascaded
together to form a 12-bit comparator.
Comparators IC7 and IC8 compare the
8-bit data output of EPROM with the cor-
responding fourth and fth digits entered
via the keyboard and stored in latches
IC3B and IC4A.
While IC7 compares the upper 4-bit
output of IC6 with the contents of IC3B
(i.e. the fourth digit from left), IC8 com-
pares the lower 4-bit output of IC6 with
the contents of IC4A (i.e. the fth digit
from left). Similarly, IC9 compares the
last digit (i.e. the contents of IC4B) with
the code entered/formed by 4-way DIP
switch S3 (marked A through D), which is
referred to here as the system code. This
system code digit can be changed from
time to time.
The result of the comparison by the
three comparators is nally available from
IC9. If the entered code matches with the
stored data, pin 6 of IC9 goes high, indi-
cating a correct code. Otherwise, either of
pins 5 and 7 goes high depending upon the
magnitude of the data. Pins 5 and 7 are
connected together via diodes D1 and D2
and used as the trigger for alarm circuit.
after entering the last digit.
Alarm generator. The alarm gen-
The logic ‘high’ output from pin 5 or pin 7
of IC9 triggers the SCR and applies Vcc
supply to IC 555 to make it oscillate. The
output from pin 3 of IC11 is used to drive
transistor T2 (BC547) to generate a long-
duration alarm tone from PZ1.
A common buzzer is used for key-press
audio indicator and alarm generator to

Fig. 4: Component layout for the PCB
keep the cost low. The output from pin 3
of timer also drives LED2, which ashes code is entered, pin 6 of IC9 becomes high
at the output frequency of the astable
oscillator.
Readers’ comments:
Q1. The construction project is very inter-
esting and useful. However, how memory
dump is to be programmed in EPROM
IC6 is not given. Though different people
would like to program different codes, at
least one example should have been given
to illustrate this.
MMV and lock driver. When a valid
and triggers monostable multivibrator
CD4528 (IC10) via transistor T3. On trig-
Praveen Shanker, Haridwar
A1. EFY: Though programming of
EPROM is well explained by the author,
here is an example of coding. Let us say
address of the EPROM where a speci c close DIP switches B, C, D, and leave A
code is stored is 41A (Hex). It is equiv-
atent to 0100 0001 1010, which is used as
address All through AO of the EPROM.
gering, pin 6 of IC10 becomes high and
remains in that state for a predeter-
mined time period. The output at pin 6
of IC10 drives transistor T5 (SL100) to
operate relay RL1. When the system is
locked, red LED1 glows, and when it is
unlocked, green LED4 glows.
The other half of IC10 is used to keep
the keyboard activated for a predeter-
mined time. The keyboard is activated
by pressing switch S1. This feature im-
proves the security of the system.
Construction
Data input/output pins are to be con-
nected with utmost care because im-
proper connection will force the system
to work unpredictably. Also, care should
be taken while using IC1, as it is quite
costly. The points marked Vcc should be
connected to the power supply directly.
The system can be built on a general-
purpose PCB or a veroboard. A single-
sided PCB layout for the circuit is, how-
ever, shown in Fig. 3, with its component
layout shown in Fig. 4.
Operation
Initially, when IC1 is disabled by IC10,
no code can be entered. To activate the
keyboard, press switch S1 momentar-
ily. This will activate the keyboard for
a predetermined time. The code should
be entered within this time. Using the
4-way DIP switch S3, the system code
can be changed at any time for extra
security.
If wrong code is entered, the buzzer
sounds alarm and the red LED starts
ashing. In this case, you can reset the
circuit by a momentary depression of
switch S2. It is to be noted that no dis-
play unit is used, to keep the code secret.
But if you still prefer to have one, the
same could be included.
฀
Now assume data stored is B5 (Hex), i.e.
1110 0101 at the above mentioned ad-
dresses. Let the system code be E (Hex),
i.e. 1010. For getting this system code
open (in S3).Thus access code=41A B5E
(Hex) or MSB.......................LSB 0100
0001 1010 1011 0101 1110 (Binary).
ELECTRONICS PROJECTS Vol. 22 45
TELEPHONE LINE-INTERFACED
GENERIC SWITCHING SYSTEM
AJAY SUBRAMANIAN AND NAYANTARA BHATNAGAR
Q uite a few projects using DTMF-
to-BCD decoder ASIC MT 8870/
KT 3170 have appeared in EFY
during the past few years. The project
presented here also uses the same ASIC,
but it is used here as part of a circuit in
which a fairly advanced switching logic
with adequate foolproo ng and authenti-
cation is implemented. The major features
of this circuit are:
Programmable password protection
over a public network
Foolproof mechanisms for events
such as time-out delays, incorrect pass-
word, and power-on initialisation
Expandable design
The primary objective of this circuit is
to make a fairly low-cost device for control-
ling up to a hundred household switches
remotely over any public/private telephone
network.
Description
The block diagram of the system is shown
in Fig. 1. It consists of the following three
units:
1. The interface and control unit
2. The authentication unit
3. The main device selection and
switching circuit
The interface and control unit provides
control signals and BCD data to the other
two units. It handles interfacing with
Fig. 1: Block diagram of telephone line-interfaced generic switching system
46 ELECTRONICS PROJECTS Vol. 22
the telephone line and also generates
control signals for hanging up (HUP) and
a universal reset pulse, which is used by
the authentication circuit for its opera-
tion. Its design may be altered to achieve
connectivity to another network, which is
capable of providing certain control and
data signal sequences.
The authentication unit stores four
presettable digits of code data and
compares the same against the 4-digit
DTMF code sent via the telephone lines
before the time-out occurs. If the 4-digit
code is found valid, the authentication
unit issues an authorisation signal to
the main device selection and switching
unit. However if an incorrect password
is entered, the device terminates the
call by returning to the off-hook condi-
tion.
The fth DTMF digit determines the When a call arrives, a 75-80V AC ring
address of the group to be selected, while
the sixth digit determines the device
number that is to be selected within that
group. The selected device can be switched
on or switched off by a momentary depres-
sion of the telephone keypad switches
marked * (code1011 binary) and # (code
1100 binary), respectively. Thus you can
select any one of the hundred devices,
divided into ten groups, to be switched on/
off, as desired—one at a time.
The interface and control unit
(Fig. 2). This unit performs the following
functions:
Detects an incoming call. Counts
up to a programmable number of rings
and then simulates handset off-cradle
condition.
Once off-hook, it must decode DTMF
signals on the telephone line within a
xed time and generate appropriate BCD
data and StD pulse for indicating a valid
data condition. The positive edge of this
StD pulse is used for subsequent opera-
tions.
Generates a universal Reset signal
that includes a time-out and a power-on-
reset. This Reset signal is an active low
pulse of programmable duration.
Generates a hang-up (HUP) signal
on expiry of the time-out and uses this
signal internally to take the device off-
line.
signal is available on the lines. This ring
signal is coupled to optocoupler Opto-1
(MCT2E) via DC blocking capacitor C1
and current-limiting resistor R1. LED1
serves as a ring indicator and as an anti-
parallel diode to the in-built LED of the
optocoupler for working with AC ring
signal. The output of optocoupler triggers
timer IC1, which is con gured as a mon-
ostable retriggerable ip- op to provide a
pulse output to be used as a clock for dec-
ade counter IC2 (CD4017) with decoded
outputs.
Fig. 2: Circuit diagram of the interface and control unit
The pulse-width of monostable should
be slightly greater than 0.6 second to
ensure that the pulse does not terminate
during the 0.2-second pause between a
pair of ring signals of 0.4-second duration.
Thus the monostable produces one pulse
for each ring (in fact, a pair), which clocks
CD4017 counter.
IC2 will freeze after counting a
pre-programmed number of rings. This
number is determined by its output pin
which is tied to its pin 13. In Fig. 2 pin
9 (O8 output) is shorted to pin 13. Thus
count of IC2 is frozen at the beginning of
the eighth ring.
The rst pulse from IC1 also triggers In case the call is answered from the
the rst stage of monostable multivibra-
tor 74123 (IC5), which causes the Reset
output to go high. As a result, CD4017
(IC2) is enabled (which was otherwise
reset, when no ring signal was present).
Also, the authentication circuit is ena-
bled to receive BCD data and control sig-
nals, as and when generated by MT8870
(IC4).
If the preset count is reached and
the call has not been answered yet (local
telephone handset still on cradle), the
counter (IC2) is frozen and D ip- op whenever fresh data is latched onto its
(IC3A) is set. This activates relay RL1
that places a 220-ohm load across the
lines to simulate handset off-cradle con-
dition and also enables MT8870 (IC4)
by applying a ‘low’ at its inhibit (active
high) pin 5. This causes the ring signal,
in turn, to be taken off the telephone
lines (by telephone exchange) and es-
tablish a connection (analogous to the
maturity of a call). The circuit is now
ready to receive signals from the remote-
end telephone.
local telephone before the preset count of
IC2 is reached, the ring ceases as the local
telephone is in off-hook condition. Since
there is no other way of re-triggering IC5,
a time-out eventually occurs and the de-
vice reinitialises all units automatically.
The device is also protected against acti-
vation by dialing from a parallel phone
instrument, since the ring signal is neces-
sary to power up the ASIC MT8870 (after
a pre-programmed number of rings).
MT8870 (IC4) generates an StD pulse
outputs. This signal is used as a ‘data
valid’ gate wherever appropriate. Also,
when a key is pressed, an ESt (Early
steering) pulse is generated at its pin 16,
which lasts till the key is pressed. This
ESt pulse is used for clocking IC12B in
the authentication and control unit and
retriggering monostable multivibrator
74123 (IC5), extending the duration of
Reset pulse. This ensures that the circuit
will operate as long as the user presses
keys within preset time intervals, or else
a time-out is decreed and the device is
reset.
The resetting process includes hang-
up (HUP) state, clearing the authenti-
cation circuit status, and consequently
deactivating the main switching circuit,
thus restoring the device to its initial
state. (The ip- ops, which control de-
vices in the main device selection and
switching unit, are allowed to retain
their states.)
ELECTRONICS PROJECTS Vol. 22 47

If the time-out period expires, the
Reset pulse falls and the falling edge
is used to trigger the second stage of
monostable multivibrator 74123 (IC5).
The complemented output 2Q of the
second stage of IC5 is a HUP (hang-up)
signal that clears relay driver flip-flop
74LS74 (IC3A), thus causing the device
48 ELECTRONICS PROJECTS Vol. 22
to hang up, and inhibit IC4. It resets
CD4017 (IC2) counter that counts the
number of rings. Also, as a Reset pulse
goes low, it resets the authorisation
circuit.
The additional circuitry around the
input of IC4 protects inbuilt op-amp input
terminals within the chip.
The power-on-reset
circuit comprises resistor
R5 and capacitor C10. It
resets the device when
power to the circuit is
switched on. Since it is low
for some time after power
is switched on, it resets the
ip- op (IC3A) and decade
counter CD4017 (IC2). Fig.
4 shows the relative tim-
ing waveforms pertaining
to this unit.
LED2 through LED5
are used to show the BCD
output for the DTMF code
received over the telephone
lines (decoded after relay
RL1 has energised).
The authentication
unit (Fig. 3). This circuit
receives BCD data and
StD control signal initially.
It outputs authorisation
(Auth) signal only when
the correct security code
has been entered. Control
pulses can reach the ‘main
switching unit’ only when
this signal is low (implying
that authentication of the
four digit code sent over the
telephone lines has been
veri ed).
Note that when a
wrong code is received,
IC9A clocks IC9B and a
low is latched by IC9B. As
Fig. 3: The authentication unit circuit diagram
a result the Q2 output of
IC9B goes high and satu-
rates transistor T2 in the
interface and control unit
and thereby shunts ca-
pacitor C10 to ground, thus
simulating a power-on-reset
condition. As a consequence
CLR signal (at output of
IC6A) is activated and
the line interface circuit is
initialised. Also, since the
monoshot IC5 is cleared,
Reset goes low (active) and
resets the authentication
unit also. When the Au-
thentication unit is initialised, IC9A and
9B are set, which causes Q2 output of IC9
to be reset, and thus transistor T2 is cut off
again. Capacitor C10 now charges through
resistor R5 as it did when the circuit was
initially switched on.
The Reset signal is initially low. As

Fig. 4: Signal waveforms of the interface and control unit
Fig. 5: Method of programming code using
DIP switches
a result, this circuit is in its initialised
state, wherein IC13 (CD4017) is reset and
ICs 9A and 9B (7474) are set (i.e. their Q
outputs are high and Q outputs are low).
Also, IC12A has its CLR pin low and it
is in reset state with its Q pin low. As
stated earlier, the Auth signal is initially
high.
The password consisting of four 4-bit
words is applied at the input pins D0-0
through D0-3 to D3-0 through D3-3 of
74LS244 ICs 15 and 14 respectively as
shown in Fig. 3. These words may be
programmed using thumbwheel switches
or arrays of DIP switches with pull-down
resistors as shown in Fig. 5.
As soon as the device establishes
a call (i.e. relay RL1 energises after a
preprogrammed number of rings), the
authentication unit (and not the main
device selection and control unit) is ac-
tivated due to a high Reset pulse that is
generated as soon as the ring arrives and
also on every pressing of a key due to (ESt)
signal from IC4 via OR gate (IC7A), which
triggers IC5.
Now the caller is expected to enter
the 4-digit password sequence from the
remote telephone set in DTMF mode.
Initially, only the rst word (nibble) of When the user presses all four keys
the array of tri-state buffer drivers (ICs
74LS244) is enabled by O0 output of IC13
(CD4017). As a result, the rst 4-bit ip- op is never clocked. At the end of
programmed word is applied to the ‘P’
inputs of 4-bit comparator IC 74LS85
(IC8). LED7 through LED10 indicate the
preset data present at ‘P’ inputs of the
comparator. The other 4-bit ‘Q’ inputs
for comparison are obtained from the
BCD output decoded by IC4 upon press-
ing a DTMF telephone key at the remote
end. This comparator result is available
at pin 6 of IC8 before the arrival of StD
pulse.
On the arrival of StD pulse, the output
of the comparator is latched into D ip-
op (IC9A). Initially, both ip- ops (IC9A low. This enables IC13 (CD4017) again
and 9B) are set, as explained earlier. So
the CLK input of the second ip- op time, the high ‘Preset’ signal at both the
(IC9B) is low.
If at any instant, a low is latched into
the rst ip- op IC9A (as a result of a When the code is not entered within
failed match between the preset code and
the code entered via the remote telephone
set), the second ip- op (IC9B) is clocked, circuit again goes back to its initial state
and it latches a low at its Q output. This
resets decade counter IC13 via inverter
IC11F. The Q2 output of IC9B is nor-
mally low. But when a wrong password is
entered, this output goes high. As a result,
transistor T2 (2N2222) of the interface
and control unit, grounds the power-on-
reset capacitor C10, as stated earlier.
Thus the unauthorized call is terminated
when the CLR signal (from the output of
IC6A) is activated. As a result, IC2 and
IC3A are reset (asynchronously) and the
off cradle simulation circuit is deactivated.
Also since the Reset signal is low, all other
units are initialised. This feature ensures
that a denial-of-service attack (wherein
unauthorised agents engage the system
and thus prevent authorised users from
using it) is discouraged.
However, if correct codes are entered,
each time when a StD pulse arrives, it
clocks CD4017 (IC13) counter so that
the next word is applied at the input of
the comparator. The result of the current
comparison (high) is latched into the rst (IC16) and two inverter gates (IC17B and
D ip- op (IC9A). 17C) of 7404, has been used to discrimi-
in the correct sequence, the rst ip- op
always latches a high and the second
the sequence, when the last digit is com-
pared and the result is latched, O4 out-
put of CD4017 (IC13) goes high, and as
a result, IC12A is clocked and latches
a ‘high’ at its Q output and the input to
inverter gate IC11E and D2 pin of ip-
op IC12B goes high. Simultaneously, sig-
nal at the output of gate IC11E goes low.
This low signal at pin 12 of IC10D AND
gate disables the gate from accepting any
further StD pulses. So the authentication
unit is bypassed and subsequent BCD
data and StD pulses are transmitted to
the main switching unit. The ESt pulse
associated with fth BCD data, latches
the high signal at D2 input of IC12 to
its Q2 output, while its Q2 output (Auth)
goes low to activate the main device se-
lection and switching unit at the start of
fth code.
When the Reset signal goes high,
the output of inverter gate IC11F goes
by taking its MR pin low. At the same
ip- ops (IC9A and IC9B) keeps them
enabled.
preset period, the Reset signal goes low
on expiry of the time-out period, the
by taking the preset pin on the ip- ops
(IC9A and 9B) low and MR pin of CD4017
(IC13) high. Simultaneously, IC12A is
cleared (its Q output goes low). As a
result, Auth output goes high and the
main device selection and switching
circuit is initialised and deactivated.
Since the initialised state is maintained
as long as the Reset signal is low, any
possibility of noise triggering is elimi-
nated.
Main device selection and switch-
ing unit (Fig. 6). This circuit receives
StD control signal after a successful au-
thentication of the four-digit code by the
authentication unit. The AUTH and its
inverse AUTH signals available on code
authentication are used in this circuit for
enabling various chips such as IC23 and
IC24 (74LS195), IC25 (CD4017), IC27
through IC29 (74LS154), and StD gate
IC19C (7408).
A combinational logic circuit, compris-
ing three 3-input NOR gates inside 7427
nate between an address (numeric digit)
and a switching signal (‘*’ for ‘on’ and ‘#’
for ‘off’). DTMF digit switches 1 through 9
and 0 (0 on the telephone keypad stands
for decimal 10 and the decoded output
ELECTRONICS PROJECTS Vol. 22 49
from MT8870 is the equivalent binary
number 1010) generate a logic-1, R_EN
(register enable) signal, while keys
marked ‘*’ and ‘#’ generate a logic-1,
S_EN (switching enable) signal. Thus
this combinational logic differentiates
between register enable (R_EN) and
device switching enable (S_EN) signals.
The R_EN and S_EN outputs for various
key depressions of the telephone keypad
are shown in Truth Table.
The combinational logic circuit is fol-
lowed by the RCLK and SCLK generation
circuitry comprising ICs 18, 19, 25, and
26, which allows the following functions
to be performed:
After AUTH signal at Q (pin 8 of
IC12B in Fig. 3) goes low (active), one
can select a group and a device within the
selected group by next two DTMF switch
depressions on the telephone keypad,
while a third key depression of ‘*’ or ‘#’
results into switching ‘on’ or ‘off’ of the
desired device.
Multiple devices can be switched on/
off one after the other, once authorisation
signal AUTH becomes active (low) without
a system reset.
The system can be reset after or
before switching ‘on’/‘off’ of the desired
device with the help of remote telephone
keypad. This feature can also be used for
avoiding switching on/off of a device if
the user perceives that he has selected a
wrong device.
When R_EN signal is logic 1, IC25
(CD4017) is clocked at the leading edge
of StD pulse, while one of the 74LS195
registers (IC23 or IC24, as enabled by
one of the Q outputs of IC25) is latched
at the trailing edge of the delayed Std
pulse (RCLK) as indicated by the direc-
tion of arrow on RCLK pulse in Fig.
6. The resistor-capacitor combinations
R26-C11 and R25-C12 wired around
Schmitt inverter gates A through D of
IC26 (7414) provide the necessary delay
for reliable latching of the data in IC23
and IC24. Resistors R27 and R28 across
capacitors C11 and C12, respectively,
serve as bleeders for discharging the
respective capacitors.
When S_EN signal is logic 1, clocking
of 7474 D ip- ops via active 74LS125 disabled.
gates occurs corresponding to the leading
edge of Std (SCLK) pulses, while the trail-
ing edge resets IC25 via capacitor C14, to
enable receiving of fresh group and device
selection data.
Group selection. When any of DTMF
numeric keys 1 through 9 and 0 on the
50 ELECTRONICS PROJECTS Vol. 22
remote telephone keypad is depressed im- PARTS LIST
mediately after AUTH signal goes active Semiconductors:
low, R_EN signal goes to logic 1 (while IC1 - NE555 timer
S_EN is logic 0). As a result, Std pulse IC2, IC13, IC25 - CD4017 decade counter
IC3, IC9, IC12,
passing through NAND gates IC18B and
IC21, IC22 - 7474 dual D ip- ops
IC18C clocks IC25 with its leading edge. IC4 - MT8870 DTMF decoder
IC25 is in reset condition before code au- IC5 - 74123 dual retriggerable
thentication due to ‘high’ AUTH signal, monostable multivibrator
and its Q0 (pin 3) is ‘high’. On clocking, IC6 - 7411 triple 3-input AND
gates
shifting of ‘high’ state from Q0 to Q1 IC7 - 7432 quad OR gates
(pin 2) enables AND gate IC19B, while IC8 - 74LS85 4-bit magnitude
AND gate IC19 is still disabled. Thus the comparator
trailing edge of RCLK passes through IC10, IC19 - 7408 quad 2-input AND
gates
IC19B to latch the MT8870-decoded data
IC11, IC17 - 7404 hex inverters
corresponding to the mentioned numeric IC14, IC15 - 74LS244 octal buffers/line
key depression, which is available at the drivers
input of group select register IC24, at its IC16 - 7427 triple 3-input gates
output. This is the group select address. IC18 - 7400 quad 2-input NAND
gates
The group select address is applied IC20 - 74125 quad bus buffers
to the address lines of 4-line-to-16-line IC23, IC24 - 74195 4-bit parallel access
decoder IC29 (group selector). In the shift registers
normal telephone keypad, we use only IC26 - 7414 hex Schmitt invert-
ers
ten numeric keys (1 through 9 and 0)
IC27-IC29 - 74LS154 4-line to 16-line
and hence only ten outputs (Y1 through decoders
Y10) are available from IC29. The other Opto-1 - MCT2E opto-coupler
six outputs Y0 and Y11 through Y15 are T1,T2 - 2N2222 npn transistor
not used. Thus we can select any of the D1,D2 - 1N4001 recti er diode
D3, D4 - 1N4148 switching diode
groups 1 through 10 via outputs marked ZD1, ZD2 - Zener diode 5.1V
Y1 through Y10 of IC29. LED1-LED10 - Red LEDs
The output corresponding to the ad- Resistors (1/4W ± 5% carbon, unless speci ed
dress present at IC29’s input pins goes otherwise)
low (active). This low (active) output R1, R2, R5, R29 - 10-kilo-ohm
R3, R12, R30 - 100-kilo-ohm
selects/enables another IC 74LS154 R4 - 220-ohm
representing the corresponding group. R6-R9 - 51-kilo-ohm
R10 - 39-kilo-ohm
(Please note that this is only a demo ver- R11 - 56-kilo-ohm
sion circuit, wherein only two groups, out R13 - 330-kilo-ohm
of ten possible groups, can be accessed R14-R18 - 1.2-kilo-ohm
R19 - 20-kilo-ohm
using IC27 and IC28. Pin 19 of IC27 and R20, R27, R28 - 1-mega-ohm
IC28 can be connected to any of the group R21-R24,
select pins Y1 through Y10 of IC29, as R31-R34 - 470-ohm
R25,R26 - 1-kilo-ohm
desired. Once connected, the specific R31-R34 - 4.7-kilo-ohm
group numbers will get allocated to IC27 Capacitors:
and IC28.) C1 - 0.47µF, 160V polyester
Device selection within the se- C2,C4-C6 - 0.01µF ceramic disc
C3, C9, C13 - 10µF, 16V electrolytic
lected group. The next DTMF number C7, C8, C14 - 0.1µF ceramic disc
key depression (i.e. the sixth after C10 - 100µF, 16V electrolytic
energisation of relay RL1 or the second C11, C12 - 47µF, 16V electrolytic
Miscellaneous:
after the 4-digit authentication code)
Xtal - 3.57946MHz quartz crys-
causes shifting of ‘high’ on pin 2 (Q1) of tal
IC25 to pin 4 (Q2) in synchronism with RL1 - Relay 6V, 100-ohm, 1 C/O
the leading edge of StD pulse clocking - 5V, 1A regulated power
supply
IC25. As a result, AND gate IC19A - Berg stick/FRC connectors
is enabled while AND gate IC19B is - Ribbon cable etc.
The trailing edge of delayed StD
pulse (RCLK) causes the data corre- parallel. However, since only one group
sponding to the mentioned numeric key IC is in selected condition (as explained
to be latched at the output of device earlier), the device control output cor-
select register IC23. This device select responding to the device select address
address is applied to address input pins present at the active group input is
of all group ICs (IC27 and IC28, here) in pulled low. This active low output is used
 51
ELECTRONICS PROJECTS Vol. 22
Fig. 6: Main device selection and switching unit

Fig. 7: Actual-size, single-sided PCB for the circuits in Figs 2 and 3
Fig. 8: Actual-size, single-sided PCB for the circuit in Fig. 6
52 ELECTRONICS PROJECTS Vol. 22
as the control signal for a corresponding
tri-state gate of 74LS125 (IC20).
We have shown only four gates, out
of possible 100, in this circuit. The output
pins of tri-state gates are connected to
the clock inputs of the corresponding ‘D’
ip- ops (only four out of possible 100 are
shown). The clock pins of IC21 and IC22
have been pulled high to avoid any noise
triggering when tri-state buffers are in
high-impedance state.
Switching the selected device.
Only one device corresponding to
the digit in the registers—IC24 for
group address and IC23 for device
address—is enabled to be affected by
the signal (‘*’ or ‘#’) as the seventh (or
the third after authentication) code.
On pressing DTMF keypad switch ‘*’
or ‘#’, the selected device is switched
on or switched off depending on the
key pressed. D0 bit of the decoded
switching signals ‘*’ and ‘#’ is applied
to data pins of all 7474 ip- ops in
parallel. Only the data corresponding
to the selected device gets clocked via
the corresponding tri-state gate of
74LS125.
The Q2 output of IC25 is still high
when SCLK is generated and, as a result,
AND gate IC18D is enabled to allow ap-
plication of SCLK to all 74LS125 gates
on depression of either ‘*’ or ‘#’ on the
remote keypad. Switching takes place at
the trailing edge of SCLK pulse, while the
trailing edge of SCLK pulse causes reset-
ting of IC25, thereby creating conditions
that were unavailable just before the pre-
vious group selection. Subsequently, you
can select any other (or the same) group
and any other (or the same) device. You
can switch on or off the selected device by
following the same procedure.
Switching on or off refers to Q output
of the corresponding D ip- op (7474)
going high or low, respectively. You may
suitably use the ip- op outputs to ener-
gise a relay or re a triac or control the
corresponding device/devices.
If you press any number key (1
through 9 or 0) instead of ‘*’ or ‘#’ key
on the DTMF keypad, IC25 will receive
a clock pulse via AND gates IC18B and
IC18C, and the ‘high’ state will shift from
Q2 to Q3 (pin 7 of IC25). Since Q3 output
is coupled to the base of transistor T2 via
diode D4, it will result into a system reset.
A system reset implies that you have to
redial the local telephone number from
remote telephone. When relay RL1 again
energises, redial the four-digit authentica-

Fig. 9: Component layout for PCB-1
Fig. 10: Component layout for PCB-2
tion code, followed by group select, device
select, and switch on (*) or switch off (#)
codes, as explained earlier.
Thus, after dialing two digits iden-
tifying the group and the device within
that group, if we press a third numeric
digit instead of ‘*’ or ‘#’ on the remote
telephone keypad, a system reset can be
achieved remotely. This feature can also
be utilised to bypass switching operation
if the user realises that he has selected a
wrong group/device.
Operation summary. The entire op-
eration can be summarised as below:
Using the remote telephone keypad,
dial the local number of the telephone to
which the circuit is connected.
If the local handset is lifted before
the programmed number of rings, a nor-
mal conversation can be ensured.
If the handset is not lifted before
the programmed number of rings, wait
for simulated off-hook status of the local
telephone handset (indicating energisation
of relay RL1).
Now dial the four digits of the
preset authentication code in a proper
sequence from the remote keypad within
the preset duration. A system reset
will occur in case the 4-digit code is not
dialed within the preset duration or
the code used is wrong, which causes
de-energisation of the relay and creates
conditions similar to on-hook state of
the local telephone handset. So you will
have to repeat all steps from the begin-
ning.
If the 4-digit authentication code
matches the preset code, you can dial the
next two digits identifying the group and
the device within that group selected for
the purpose of switching on or off (or even
as a dummy operation for the purpose of
forcing a system reset).
Dialing ‘*’ from the remote tel-
ephone keypad will result into switching
on of the selected device, while dialing
‘#’ will result into switching off of the
selected device. (Dialing any number, 1
through 9 or 0, causes a system reset.
Relay RL1 will be de-energised, and you
will have to restart from the initial step.)
You can proceed with the same procedure
to switch on/off the next selected device.
The procedure can be repeated for any
number of devices (one-at-a-time) with-
out affecting the status of non-selected
devices.
Testing. It is recommended that the
circuit be built in stages, verifying proper
operation at each stage. The main switch-
ELECTRONICS PROJECTS Vol. 22 53
 Truth Table for Device Selection and Switching at various points. The ring pulse generator and decade
Keypad Decoded data input Switch and register The authentication counter, CD4017, comes next. Finally,
Key from MT8870 enable outputs circuit is also self- interface connections between the various
No. D3 D2 D1 D0 S_EN R_EN contained and may circuits should be made after verifying
1 0 0 0 1 0 1 be assembled and the proper functioning of each circuit in
2 0 0 1 0 0 1 debugged independ- isolation.
3 0 0 1 1 0 1 ently. A single-sided PCB for the circuits
4 0 1 0 0 0 1
5 0 1 0 1 0 1 However, care in Figs 2 and 3, is shown in Fig. 7, while
6 0 1 1 0 0 1 must be taken while another single-sided PCB for the circuit in
7 0 1 1 1 0 1 assembling the inter- Fig. 6 is shown in Fig. 8. The component
8 1 0 0 0 0 1 face and control unit. layouts for both the PCBs are given in
9 1 0 0 1 0 1
The ASIC must be Figs 9 and 10, respectively. Suitable con-
0(10) 1 0 1 0 0 1
* (11) 1 0 1 1 1 0 assembled first and nectors are provided to enable isolation
#(12) 1 1 0 0 1 0 tested for proper op- and joining of individual circuits using
eration and output jumpers/connectors, for easy testing and
ing circuit may be assembled conven- levels, followed by rigging and testing of fault analysis during assembly.
tionally, with logic operation tested monostable multivibrators in the 74123. ฀

Readers’ comments:
We have the following queries regarding
the project:
1. The interface and control section. In
IC2 (CD4017), where would be pins 3, 2,
4, 7, 10, 1, 5, 9, 6, 11, and 12 connected?
Also show the connections of available pin
11 (RST) in IC5 (74123).
2. The authentication section. Show
the connections of pins 1, 5, 6, 9, 10, 11,
and 12 in IC13 (CD4017).
3. The selection and switching unit.
(a) Pins 2 to 11 (Y1 to Y10) of IC27
(74LS154) and IC28 (74LS154) are
connected in parallel. Pins 2 and 11 of
IC27 are connected to pins 1 and 4 of
IC20 (74LS125), respectively, and pins
2 and 11 of IC28 are connected to pins
10 and 13 of IC20 (74LS125), respec-
tively. Pins 2 to 11 (Y1 to Y10) of IC29
(74LS154) are connected to the normal tel-
ephone keypad. Are all these connections
correct?
(b) After entering IC16 (7427), four
data lines D0 through D3 go to IC23
(74LS195) and thereafter IC24 (74LS195)
and then go out as shown in the PCB
layout. Please explain which data goes in
IC16 and where does it output in IC24. Are
these connections related to PCB1?
Ranjit Singh
Amravati
EFY: 1. The interface and control section. number in the selected group are not
Only one of the ten outputs of IC2 decade connected in parallel and only their
counter needs to be connected to its pin address (input) pins are connected in
13 [and pin 3 of IC3(A)] to freeze IC2 parallel, which are controlled by device-
and create a condition simulating lifting select outputs from IC23. However, the
of handset after waiting for a few rings. selection of a group is dependent on IC29,
This is well explained in the article. The which, in turn, is controlled by group-
maximum number of rings can be nine, to select IC24.
avoid false ring condition on the line. Output connections Y1 and Y10 from
RST and Reset outputs are not going IC27 pertain to device Nos. 1 and 10,
to part II and have been used via IC6(A) respectively, of group 1, while connec-
in part I itself. The ags just indicate the tions Y1 and Y10 from IC28 pertain to
label of these signals. device Nos. 1 and 10, respectively, of
2. The authentication section. The group 10. Each device is controlled via
mentioned output pins of IC13, excluding 74LS125 gate in conjunction with one
pin 10, are not used/connected. Pin 10 is ip- op from 7474 IC. In the circuit only
Q3 and is used as clock for IC12(A). two groups (1 and 10), with two devices
3. The selection and switching unit. (1 and 10) from each group, have been
(a) The rst four digits dialled from the shown instead of all the ten groups and
remote telephone keypad are used for a hundred (ten per group) devices. You
matching the authentication code. After should be able to correlate as to which
authentication, the fth digit selects the 74LS125 (IC20) gate and 7474 section
group. If the fth digit is 1 then IC27 (IC21 and IC22 pair) select which device
(group 1) will be selected, and if the fth out of which group.
digit is ‘0’ (code 1010 or ten decimal) then (b) Data lines D0 through D3 are com-
IC28 (group 10) will be selected. The sixth ing from IC4 and go into pins labelled D0
dialled digit selects the device inside the through D3 of IC8, IC16, IC17, IC23, and
selected group. The seventh dialled digit IC24, respectively. They are thus related
(‘*’ for ‘on’ or ‘#’ for ‘off’) of the selected to PCB1.
device or ‘0 through 9’ for circuit reset can The AUTH signal is correctly con-
be used as desired. nected to IC27, IC28, and IC29 in Fig. 7
The output pins re ecting the device and there is no ambiguity.

54 ELECTRONICS PROJECTS Vol. 22

 PROGRAMMABLE
MELODY GENERATOR
A
number of melody generator cir-
cuits based on chips like UM3481,
UM3482, UM34815A, UM66, etc
have appeared in EFY. All these UMC
chips contain preprogrammed masked
ROM and are not eld-programmable as
such.
Here is the detailed design of a typical
melody generator circuit using different
types of memories, including EPROM,
RAM, and ROM (hard-wired).
As soon as the power is switched on
to UMXX series melody generators, a
tune is heard, which stops after a while.
When a switch on the melody generator is
pressed, the second tune is heard. If the
chip is capable of producing twelve tunes,
each successive depression of the switch
results in a new tune being played. After
the twelfth tune has been played, the next
depression of the switch causes the rst
tune to repeat, and so on. The circuit pre-
sented here can be programmed exactly
the same way.
Basics of music
Generally, an electronic organ or piano
is played with both hands. Now imagine
playing a 32-key organ with a single
nger. In that case, only one key can
be pressed at a time and hence only one
note can be heard. Considering that the
time taken by the nger to move from one
Fig. 1: Block diagram of EPROM-/RAM-based melody generator
VYJESH M.V.
key to another is very short, the required
notes can be played properly and hence
the tune can be heard. The notes can also
have breaks in between. This feature can
be explained by considering ve notes
written in the following two ways:
1. SA RE GA MA PA
2. SA---RE GA---MA PA
In the rst case the notes are continu-
ous. In the second case there are breaks
(no sound), indicated by ‘—’ for a stipulat-
ed amount of time, in between SA and RE
as well as GA and MA. Each of the circuits
explained in this project incorporates the
break (no sound) feature.
You should make sure that you have
access to a musician before attempting
any of the circuits. In addition, you would
need a computer and a frequency meter
or a digital multimeter. The computer is
required to test the tunes, i.e. to make
sure that the given notes match the tune
of a given song.
A brief on music from the software
article ‘Generation of Indian Classical
Music on a Microprocessor’ by Prof. V.V.
Athani, published in April ’94 issue of
EFY, is as follows:
“Taking into account only one elec-
tronic organ (piano), the number of notes
in music are only seven—SA RE GA MA
PA DHA NI. But these basic notes are
divided into three octaves (refer Fig. 4),
where each octave also has notes called
half notes. So each octave has twelve
notes. On a piano keyboard, black keys
in between white keys produce the av-
erage frequency of adjacent keys. For
example, ‘SA’ has a frequency of 595
Hz and ‘RE’ has a frequency of 668 Hz.
When a black key in between them is
pressed, a frequency of 631.5 Hz is pro-
duced. These black keys are called half-
note keys.”
Here we have selected a total of 28
notes, including all notes from the middle
octave, eleven notes from upper octave,
and a few from the lower octave. All the
28 notes with their respective frequencies
are given in Table I.
Software and testing
of notes
Before moving to the software program,
let us see how the notes for a tune can
be obtained. Give your musician the
song for which you need notes. Write those
notes in terms of SA RE GA etc, making
sure that all the notes of the tune lie with-
in the range of the 28 notes given in Table
I. No sound in between the notes, includ-
ing its duration, as also the duration of
each particular note, should be taken into
account. For example, if in a tune the time
period of a note SA is 500 ms and that of
RE 1500 ms, the two notes can be written
as SA RE RE RE. Similarly, no sound in
between can be written
as SA RE-RE-SA.
The notes so ob-
tained have to be con-
verted into data char-
acters. This can be done
directly by using Table I;
for example, SA-RE RE
GA---MA can be written
as C-E E G---H.
Execute the program
ELECTRONICS PROJECTS Vol. 22 55
 (refer Appendix ‘A’ for
the source code of the
program) and enter the
delay value (say, 300).
Now enter the rst line
of the tune and press
‘Enter’ key. The tune can
be heard. This tune can
be repeated by pressing
‘R’. If this tune needs to
be changed, or a new tune
is to be entered, press any
key. In this way all the
lines in a tune are tested
line by line. After testing
all the lines, enter all
the lines of the tune once
again and recheck the
tunes until you are satis-
ed. Press E to quit the
program. Now convert the
tunes (data characters) to
hexadecimal values using
Table I. These hexadeci-
mal values are to be en-
tered into EPROM/RAM
at consecutive locations to
get the tune.

EPROM-/RAM-
based melody
generator
Since most parts of the
circuits for EPROM- and
RAM-based melody gen-
erators are similar, the
main circuits for both
versions have been inte-
grated in Fig. 2. Relevant
changes have been de-
Fig. 2: Main circuit of EPROM-/RAM-based melody generator

scribed appropriately.
The common block
diagram for EPROM-
and RAM-based melody
generators is shown in
Fig. 1. A low-frequency
oscillator followed by a
binary counter is used to
generate the addresses for
EPROM/RAM.
In the case of EPROM,
the preprogrammed data
output is directly coupled
to two 1-of-16 decoders
(one for upper nibble and
the other for lower nibble
of data).
However, in RAM
based-circuit, a keyboard

56 ELECTRONICS PROJECTS Vol. 22


Fig. 3: Tone oscillator
Fig. 4: Piano keyboard
is deployed at the time of writing the
data at speci ed locations (addresses)
into the RAM. Thereafter the keyboard
is detached and data output pins are
connected to two 1-of-16 decoders, as in
EPROM-based circuit. Only 28 outputs
(out of 32 outputs) of the two decoders,
with each representing a unique note, are
used in conjunction with individual pre-
sets to control the oscillator’s frequency
and thus the resulting sound from the
loudspeaker
state (all outputs zero).
The binary outputs of
IC2 serve as the ad-
dress for memory loca-
tions in the EPROM,
where the data for the
notes is stored. For the
EPROM version, the
pins of connector K2(F)
are to be kept shorted to
the corresponding pins
of connector K3(M). Suf-
xes F and M within
parentheses indicate
female and male connec-
tors, respectively.
Data bits of the
lower nibble (D0
through D3) are con-
nected from EPROM
to the address pins of
1-of-16 decoder IC4
(CD4514) and those of
the higher nibble (D4
through D7) to the ad-
dress pins of another 1-of-16 decoder IC5
(CD4514).
The ‘Hex value’ column in Table I
indicates that either the lower nibble
or the upper nibble, or both nibbles, of
stored hex data in memory will always
be zero. It means that at least one of the
two CD4514 (IC4 and IC5) will have
binary 0000 at its address input. The Q0
output of these ICs is not used for gen-
erating any note. The hex data 00 (i.e.
0000 0000) is, in fact, used for no sound.
Similarly, hex values 01 (0000 0001) and
10 (0001 0000) are used for ‘Reset’ and
‘Stop-clock’ functions.
The remaining 14 outputs from each
of the two CD4514 (IC4 and IC5) are
used together for generating one of the
28 notes corresponding to the hex data
stored and the output from a speci c
memory location. The Q2 to Q15 outputs
of IC4 and IC5 are connected via diodes
D101 (and preset VR101) through diode
D128 (and preset VR 128), respectively,
to the tone oscillator circuit built around
timer NE555 (IC101), as shown in Fig. 3.
(EFY lab note. The numbering of diodes
and other components of this circuit has
been done for convenience.)
IC101 is wired with presets to form
an oscillator. At any time, only one of
diodes D101 to D128, depending on the
current note selected via EPROM’s ad-
dressed location, will be forward biased
and its corresponding preset will form
part of the oscillator circuit. Each preset
is adjusted to a value (refer Table I) to
obtain the frequency corresponding to
the selected note.
No sound (00 hex). Breaks are

EPROM-based circuit
In Fig. 2, NE555 timer (IC1) is wired in
astable mode, which provides clock pulses
for the 12-stage binary counter CD4040
(IC2). In the EPROM ver-
sion, jumper J1 is used to
permanently short pin 3
of IC1 and pin 10 of IC2,
while there is no need
to operate push-to-on
switches S2 and S3 and
you can leave them open
(i.e. in off state).
An 8-bit, 4k EPROM
2732 is used for IC3.
Since its pin 21 is address
A11, switch S6 is to be
kept in position ‘a’ to con-
nect it to O11 output of
Fig. 5: Flow IC2. When clock pulses
chart of door- are fed to IC2, it starts
bell counting up from its reset Fig. 6: Actual-size single-sided PCB-1 layout for circuit of Fig. 2

ELECTRONICS PROJECTS Vol. 22 57

 necessary PARTS LIST
in between (Common to EPROM, RAM and ROM)
the notes Semiconductors:
to make a IC101 - NE555 timer
tune sound IC201 - 7805 +5V regulator
perfect. The D101-D128 - 1N4007 recti er diode
D201-D204 - 1N4001 recti er diode
break period,
Resistors (¼-watt ±5% carbon, unless other-
termed as wise stated)
‘no sound,’ is R101 - 5-kilo-ohm
obtained by VR101-VR128 - Refer Table I
outputting VR129 - 10-kilo-ohm preset
hex value Capacitors:
00 from the C101 - 0.1µF ceramic disc
EPROM. C102 - 0.22µF ceramic disc
C103 - 10µF, 12V electrolytic
During this
C201 - 100µF, 25V electrolytic
input to the C202 - 1000µF, 16V electrolytic
two 1-of-16 Miscellaneous:
decoder ICs LS101 - 8-ohm, 4W loudspeaker
(IC4 and X201 - 230V AC primary to 0-6V,
IC5), the Q0 500mA sec. transformer
outputs of (for EPROM and ROM)
both decoder Semiconductors:
ICs go high. IC1 - NE555 timer
Since IC2 - CD4040 counter
IC3 - (1) 2732 EPROM
Q0 outputs - (2) 6116 RAM
are not con- IC4, IC5 - CD4514 1-of-16 decoder
nected to the IC6 - CD4011 quad NAND
tone oscilla- gate
T1-T8 - BC547 npn transistor
tor circuit
D1-D64 - 1N4007 recti er diode
(or anywhere LED1-LED20 - Red LED
else), no note Resistors (¼-watt ±5% carbon, unless other-
or sound is wise stated)
Fig. 7: Actual-size single-sided PCB-2 layout for circuit of Figs 3 and 11
R1, R7 - 10-kilo-ohm
R2 - 22-kilo-ohm
R3, R8 - 470-ohm
R4 - 1-mega-ohm
R5, R9-R16 - 1-kilo-ohm
R6 - 2.2-kilo-ohm
R17, R18 - 100-ohm
R19 - 330-ohm
VR1 - 100-kilo-ohm preset
Capacitors:
C1 - 22µF, 12V electrolytic
C2 - 0.1µF ceramic disc
C3 - 0.01µF ceramic disc
C4 - 0.22µF ceramic disc
Miscellaneous:
S1 - Push-to-off switch
S2-S5 - Push-to-on switch
S6 - SPDT switch
J1, J2 - Jumper
K1-K5 - Connectors

produced for hex value 00, and there is

only time elapse. ‘No sound’ code is used
as break between the notes.
Reset (01 hex). When the data output
of EPROM corresponds to 01 (hex), Q1
output of IC4 goes high. Since Q1 output
of IC4 is connected to MR (master reset)
pin 11 of counter IC2 via resistor-capacitor
network R2-C3, IC2 is reset when data 01
Fig. 8: Component layout for PCB-1 hex appears at the output of EPROM.
Stop-clock signal (10 hex). When
58 ELECTRONICS PROJECTS Vol. 22
 breaks/‘no open, there is no
sound’ peri- effect.
ods) for the Similarly, when
fir st tu n e binary data corre-
฀
are stored, sponding to note SA
a stop-clock (05 hex) is output
data (10 hex) by the EPROM, Q5
is stored at of IC4 and Q0 of
the end of IC5 go high. The Q5
tune-1 that output of IC4 brings
stops after into circuit the cor-
the first responding preset
tune. Now tuned to the frequen-
฀
on pressing cy of SA (1190 Hz).
push-to-off The Q0 output of IC5
switch S1 has no effect, as Q0
momentar- is open. In this way
ily, the clock both the ICs (IC4 Fig. 12: Flow chart
advances and IC5) function in of car-reverse horn
to start the accordance with data
second tune at their inputs to pro-
(tune-2). duce the corresponding notes.
Thus each Power supply. The circuit shown in
tune is made Fig. 11 is used to obtain the regulated 5V
to end with DC using IC 7805.
10 hex code The actual-size, single-sided PCB
for stop sig- layouts for the circuits of Figs 2 and 3
nal. When (common for EPROM and RAM versions
all tunes of of the melody generator) are shown in
the doorbell Figs 6 (PCB-1) and 7 (PCB-2), respec-
are exhaust- tively. The component layouts for PCBs of
ed, the last Figs 6 and 7 are shown in Figs 8 and 9, re-
Fig. 9: Component layout for PCB-2
stop-clock data is followed by a reset data spectively. The power supply circuit (Fig.
(01 hex), so that one goes to the start of 11) has also been integrated in PCB-2.
the data output of EPROM corresponds tune-1 (on reset), and the cycle repeats. This circuit can be used as a door-
to 10 (hex), Q1 output of IC5 goes high, For instance, the hexadecimal value bell, or even as a car-reverse horn. The
which after inversion of ‘SA’ is 70H (refer Table I) or binary ow chart for car-reverse horn is shown
by NAND gate N1 is ap- 0111 0000, which means that binary in Fig. 12. The necessary connections
plied to pin 4 of IC1 via data at the input of IC4 and IC5 is 0000 are shown in Fig. 13. When the circuit
normally-closed contacts and 0111, respectively. As a result, only is used as a car-reverse horn, data ows
of push-to-off switch S1. Q7 output of IC5 goes high. This output from the next address location to where
As a result, IC1 stops os- brings the associated preset resistor it stopped earlier.
cillating and producing tuned to the frequency of SA (595 Hz)
clock pulses. The active into the oscillator circuit. Simultaneously,
‘high’ Q1 output of IC5 data 0000 at the input pins of IC4 causes Preset adjustment
is therefore referred to its Q0 pin to go high. But since Q0 is left Connections to join the two PCBs should
as stop-clock signal in be made only after the adjustment of pre-
this circuit. Pushing sets on PCB-2 using any of the following
switch S1 at this stage three procedures:
removes logic ‘high’ in- Using frequency
put from NAND gate N1 meter. Assemble all the
and the clock oscillator components of PCB-2.
starts oscillating. Connect a probe to the
The ow chart for Vcc using a crocodile
a doorbell given in Fig. clip at the other end.
5 shows the order in Switch on the 5V power
which the data is en- supply and connect the
tered/read. First, the output from the tone
data pertaining to the Fig. 10: Flow oscillator on the PCB
rst tune is stored. Once chart for re- to the frequency me-
all the notes (including adjustment Fig. 11: Power supply ter. Now connect the
probe to the anode
ELECTRONICS PROJECTS Vol. 22 59
 choose the main notes in the mid- adjusting the
dle octave. Connect the probe to the variable resis-
respective diode of SA and tell the tors to lower
musician to adjust the variable resistor values in the
to the frequency of SA. Now connect table may be
the probe to the respective diode of RE very tedious.
and adjust the variable resistor to the Any method
frequency of RE, and so on. After ad- may be used to
Fig. 13: Wiring connections for car-reverse horn justing main notes, adjust half notes. adjust all the
(In Table I, music notes shown in small variable resis-
of diode D101 and adjust preset resis- letters are half notes.) This method will tors. But after
tor VR101 for 446 Hz (refer Table I). be successful only if the musician is well playing a tune,
In this way all the variable resistors trained in music. it may be felt
are adjusted one by one by connecting Using digital multimeter. First, that the tune
+5V from the probe to the corresponding assemble only preset resistors VR101 doesn’t sound
diodes. through VR128. Now adjust the variable proper, even if
With the help of a musician. You resistors to their respective values (shown it sounded right
can seek the help of a musician if you in column 6 of Table I) using a digital with computer.
don’t have access to a frequency meter or multimeter. Use the variable resistors The reason can Fig. 14: LED indicator
a digital multimeter. Connect the output with maximum value as given in column be that the re- circuit
from the tone oscillator to the speaker 7 of Table I. You can also use the values sistors were not
and switch on the power supply. First, shown in the circuit diagram of Fig. 3, but properly tuned or it may be due to
minute imperfections in output voltages
from IC4 and IC5. These imperfections
TABLE I
can be overcome by readjusting the resis-
Music Frequency Data Hex Variable Variable Maximum
note of music character value resistor resistor value of tors by the method given below.
note (preset) in-circuit variable The imperfections can only be ad-
(Hz) number value (ohm) resistor justed when data from the EPROM is
Lower octave heard. But, the notes of a tune will not
PA฀ 446 1 20 VR101 8274 10k
be in an increasing frequency sequence.
dha฀ 472 2 30 VR102 7740 10k The sequence should be PA , dha , ----- to
฀ ฀
฀ ฀
DHA฀ 500 3 40 VR103 7230 10k ----- DHA , ni . To do this, include at least
ni฀ 530 A 50 VR104 6744 10k two sets of sequence data from Table I
NI฀ 561 B 60 VR105 6288 10k with 2-3 bytes of gap in between succes-
Middle octave sive sequences, after all the tunes, as
SA 595 C 70 VR106 5850 10k shown in the owchart of Fig. 10. This
re 630 D 80 VR107 5445 10k method of readjustment is used only to
RE 668 E 90 VR108 5055 10k prevent disconnection of PCB of Fig. 7
ga 707 F A0 VR109 4698 5k from PCB of Fig. 6 and tuning the resis-
GA 749 G B0 VR110 4356 5k tors again and again.
MA 794 H C0 VR111 4029 5k Remove jumpers J1 and J2. Switch
ma 841 I D0 VR112 3726 5k
on the power supply. Press switch S4
PA 891 J E0 VR113 3438 5k
dha 944 K F0 VR114 3165 5k
to provide clock pulses for IC2. Say, if
DHA 1000 L 02 VR115 2910 5k the EPROM contains 10 tunes, after the
ni 1062 M 03 VR116 2655 5k tenth tune release S4. Now keep pressing
NI 1120 N 04 VR117 2445 5k S2 momentarily until the rst note of the
Upper octave sequence (PA ) sounds. Now connect the
฀

SA฀ 1190 O 05 VR118 2220 5k frequency meter at the speaker terminals

re฀ 1260 P 06 VR119 2016 5k (disconnect speaker if necessary) and ad-
RE฀ 1335 Q 07 VR120 1824 2k just VR101 if the value of the frequency
ga฀ 1414 R 08 VR121 1644 2k meter reading is not consistent with the
GA฀ 1498 S 09 VR122 1473 2k value in the Table I. Press S2 again to
MA฀ 1588 T 0A VR123 1308 2k adjust VR102, and so on. After the read-
ma฀ 1682 U 0B VR124 1158 2k justment process insert jumpers J1 and
PA฀ 1782 V 0C VR125 1014 2k
J2 and press S3 to reset IC2.
dha฀ 1888 W 0D VR126 876 1k
DHA฀ 2002 X 0E VR127 747 1k
ni฀ 2122 Y 0F VR128 624 1k
RAM-based circuit
no sound — — 00 — — —
Reset  01
The only difference between the EPROM-
Stop-clock  10
and RAM-based circuits is the use of
RAM chip in place of EPROM and a key-

60 ELECTRONICS PROJECTS Vol. 22

Fig. 15: Keyboard and probe for programming RAM

board for programming the RAM in
RAM-based circuits. Besides, an LED
panel is used for displaying the selected
RAM address.
Switch S2 is used to manually provide
clock pulses to IC2. Similarly, switch S3
is used to manually reset IC2 before and
after programming. Both switches (S2 and
S3) are integrated into Fig. 2. The connec-
tor K1 in between IC2 and IC3 is used
to connect to K5(M) connecter along
with the associated LEDs as shown in
Fig. 14. EPROM 2732 (IC3) is replaced
with an 8-bit, 2k SRAM (6116). Pin 21
of 6116 is WE (write enable – active low).
Switch S6 is to be kept in position ‘b’ while
working with RAM.
At the time of writing (programming)
data into the RAM, there is no connection
between connectors K2(F) and K3(M).
Also, jumper J1 is removed. To program
the RAM, K4(M) is to be mated with
K2(F). After programming is over, K2(F)
is connected to K3(M).
IC6 (CD4011) contains four NAND
gates, of which NAND gate N1 is used for
stop-clock signals. It functions in the same
manner as in an EPROM-based circuit.
The inputs of N1 are shorted and connected
to the ground via resistor R7. So the output
of N1 becomes high, which keeps IC1 oscil-
lating.
After a stop-clock (active ‘high’) sig-
nal appears at the input of NAND gate
N1, its output goes low. When switch S1
is pressed, the output of N1 goes high
and IC1 starts oscillating again. Gates
N2 and N3 are used to provide read and
write logic for RAM. In read condition,
the output of N3 is at logic 0 because its
inputs are at logic 1. Pressing of switch
S5 provides ‘write’ condition, since the

Appendix ‘A’
#include <stdio.h> } case’F’:sound(707); break;
#include <dos.h> } break; case’S’:sound(1498);
#include <stdlib.h> void play(char *str,int d) case’G’:sound(749); break;
#include <conio.h> { break; case’T’:sound(1588);
#include <ctype.h> int i=0; case’H’:sound(794); break;
void play(char *str,int d); while(str[i]!=’\0') break; case’U’:sound(1682);
void main() { case’I’:sound(841); break;
{ switch(str[i]) break; case’V’:sound(1782);
int f,d=200; { case’J’:sound(891); break;
char ch1[180],ch2; case’1':sound(446); break; case’W’:sound(1888);
clrscr(); break; case’K’:sound(944); break;
printf(“\n Enter delay value:”); case’2':sound(472); break; case’X’:sound(2002);
scanf(“%d”,&d); break; case’L’:sound(1000); break;
while(1) case’3':sound(500); break; case’Y’:sound(2122);
{ break; case’M’:sound(1062); break;
printf(“\n enter tune :”); case’A’:sound(530); break; case’-’:nosound();
scanf(“%s”,&ch1); break; case’N’:sound(1120); break;
play(ch1,d); case’B’:sound(561); break; }
a:ch2=getch(); break; case’O’:sound(1190); delay(d);
if (tolower(ch2)==’r’) case’C’:sound(595); break; i++;
{ play(ch1,d); break; case’P’:sound(1260); }
goto a; case’D’:sound(630); break; nosound();
} break; case’Q’:sound(1335); }
if (tolower(ch2)==’e’) case’E’:sound(668); break;
exit(0); break; case’R’:sound(1414);

ELECTRONICS PROJECTS Vol. 22 61

 tor K4(M) should
be connected to
K2(F) during pro-
gramming. The
circles shown with
the corresponding
hex values are
Fig. 16: Block diagram of ROM-based melody generator simple metallic
contacts (or tabs)
output of gate N3 is at logic 1 and that of that avoid the use of a large number of
gate N2 at logic 0. switches. To enter the hex data, the probe
LED connector. A separate male connec- is touched to the corresponding metallic
tor K5(M) is fabricated with LEDs as shown in contact tab.
Fig. 14. This connector should be connected to The keyboard can be easily wired us-
K1(F). The LEDs indicate addresses of memory ing a general-purpose board. To test the
locations of RAM. Glowing of LED1 through keyboard after wiring, connect point ‘A’ to
LED11 together means that last RAM loca- the ground via a 100-ohm resistor (R18)
tion is being addressed. (We are using a 2kB as shown in Fig. 15. Now touch each and
RAM.) every tab one by one using the metallic
Keyboard. The circuit diagram of key- probe and verify that the data shown by
board is shown in Fig. 15. Male connec- the LEDs (LED13 through LED20) is
Fig. 17: Schematic diagram of ROM-based melody generator
62 ELECTRONICS PROJECTS Vol. 22
consistent with the hex value shown on
the tab/circle. After checking, disconnect
resistor R18.
Connector K3 should be soldered to
the PCB by using a ribbon cable of ad-
equate length, so that it could be easily
connected to K2(F) after programming.
The outputs from IC4 and IC5 go to
preset-array part of the tone oscillator.
Wiring is done similar to that in an
EPROM version.
Programming. Connect LED con-
nector K5(M) to K1(F) and keyboard
connector K4(M) to K2(F). Press switch
S3 momentarily to reset IC2. No LED
glows on the LED connector, indicating
the initial address as zero. Now touch the
tab marked ‘00’ with the probe. Press S5
momentarily and lift the probe. Glowing
of no LED on the keyboard indicates that
‘00’ is entered in the initial memory loca-
tion. (It is good to enter 00 in the rst
memory location.)
Now get the hex dump values of the
tunes. Press switch S2 to go to the next
memory location, indicated by LED1 (cor-
responding to address line A0), on the LED
connector strip. Touch the appropriate tab
with the probe to enter the corresponding
hexadecimal value at memory location 1.
Press switch S5 and lift the probe. The
data entered into memory location 1 is
shown by keyboard LEDs in binary form.
Hex data values (refer Table I) are
such that any of the four LEDs cor-
responding to either D0 through D3
bits or D4 through D7 bits would glow
to show the data entered. So it is easy
to identify whether the data entered is
correct or not. If necessary, make a table
of binary data along with corresponding
hex values.
After entering all the tunes, discon-
nect keyboard from K2(F) and connect
K3(M) to K2(F). Now connect external
jumper J1 as shown in the circuit dia-
gram.
Switch S4 across jumper J1 termi-
nals is not necessary but it may prove
useful if any readjustment of variable
resistors is needed (as in the case of
EPROM), or for checking each and every
tune one by one.
The programming steps are summa-
rised as below:
1. Press switch S3.
2. Touch tab 00 with the probe.
3. Press and release switch S5.
4. Lift the probe. Fig. 18: Actual-size, single-sided PCB layout for the circuit
5. Press S2 to go to the next memory
location.
the circuit of a ROM-based programmable
6. Repeat from step 2 onwards for the
PARTS LIST melody generator is totally a new one.
next hex value programming.
The ROM, as stated earlier, is home-built
Semiconductors: 7. After last data is entered, press
using discrete components, which can be
IC1 - NE555 timer S3.
used for storage of 100 bits (100 notes).
IC2, IC3 - CD4017 decade counter 8. Keep S4 pressed to check all the
IC4, IC5 - CD4069 hex inverters The block diagram of the ROM-based
tunes that have been entered.
T1-T10 - BC547 npn transistor melody generator is shown in Fig. 16.
9. Connect jumper J1 if all tunes are
T11-T110 - BC558 pnp transistor Note that the last block comprising
entered.
variable resistor array is identical to that
Resistors (¼-watt ±5% carbon, unless other- The data table (Table I), writing of
wise stated) used in EPROM/RAM version (refer Fig. 3
musical notes, conversion of notes to hex
in Part I of the article). The power-supply
R1 - 10-kilo-ohm values, preset-array alignment, and ow
R2 - 100-kilo-ohm circuit shown in Fig. 11 can also be used
charts for door-bell and car-reverse tune
R3 - 680-ohm for ROM-based melody generator. Thus
are also applicable for the RAM version.
R4 - 1-mega-ohm PCB and component layouts shown in Figs
Now we shall study a programmable
R5 - 1-kilo-ohm 7 and 9 can be used without any modi ca-
R6 - 68-ohm melody generator using home-brewed
tion in this system.
ROM.
Capacitors:
There were only a few differences be-
C1 - 2.2µF, 12V electrolytic
C2, C3 - 0.01µ ceramic disc
tween the circuits of RAM- and EPROM- ROM-based circuit
based programmable melody generators
Miscellaneous: The circuit diagram of ROM-based mel-
and as such we could integrate the com-
S1 - Push-to-off switch ody generator is shown in Fig. 17. Here
mon portion of the two circuits into a
timer NE 555 (IC1) is wired as an astable
single schematic/PCB design. However,

ELECTRONICS PROJECTS Vol. 22 63


Fig. 19: Component layout for the PCB
multivibrator. The output pulses from
IC1 are used as clock for decade counter
CD4017 (IC2). The ten sequential outputs
from IC2 are applied to npn BC547 tran-
sistors T1 through T10.
Similarly, the outputs from another
similar decade counter IC3 are connected
to pnp BC558 transistors T11 through
T110 via inverter gates N1 through N10
of IC3 and IC4 (CD4069). Each of these
100 transistors (T11 through T110)
provides one bit for one note. The out-
puts are taken from the collectors of
transistors and connected to the ‘variable-
resistor array and tone oscillator’ circuit.
(Note: Collectors of transistors represent-
ing identical notes are shorted together.)
As in the previous circuits of RAM-
and EPROM-based melody generators,
here also ‘Stop-clock’ and ‘Reset’ signals
are made available. You may program
any/all of the hundred transistors T11
64 ELECTRONICS PROJECTS Vol. 22
through T110 for 28 notes as well as for
the ‘Stop-clock’ and ‘Reset’ functions.
However, both ‘Stop-clock’ and ‘Reset’
functions are optional, depending upon
the number of tunes and number of notes.
For ‘Stop-clock’ function, the output from a
transistor is applied to inverter N11 whose
output is connected to reset pin 4 of IC1.
Similarly, for ‘Reset’ function, the output
from a transistor is applied to pins 15 of
IC3 and IC4.
The collectors of transistors pro-
grammed for each speci c note (including
‘Stop-clock’ and ‘Reset’ functions) are to be
strapped (shorted) together for connection
to the corresponding input points of the
‘variable-resistor array and tone oscil-
lator’ circuit, while the ‘Stop-clock’ and
‘Reset’ lines are to be connected as shown
in Fig. 17.
We can have a maximum of 30 output
lines (28 for the notes and two for ‘Stop-
clock’ and ‘Reset’
functions) from the
100-transistor ar-
ray. Transistors T1
through T10 are
used to switch on
Vcc to transistors
T11 through T110.
Fig. 20: Flow chart
for repetitive playing
of 99 notes (single
tune)
Operation
Initially, when power
is switched ‘on’ to the
circuit, IC2 and IC3 are
in Reset condition. So
only pin 3 (Q0) of IC2
and IC3 will be at ‘high’
logic. These high outputs
are applied to the base
of transistor T1 and the
input of inverter N1. As
a result, transistor T1
Fig. 21: is switched on and +5V
Flow chart Vcc is available at the
for repetitive
playing of a emitter of transistor T1.
number of
tunes This potential is extended
to the emitters of T11, T21, T31,…, T91
and T101. Simultaneously, the output of
inverter N1 will be at logic ‘0’, which is
applied to the bases of pnp transistors
T11 through T20.
Since transistor T11 is the only transistor that
has both Vcc at its emitter and nearly 0V at its base
simultaneously, it gets forward biased and its collec-
tor is pulled toward its emitter voltage (Vcc). Thus
initially, on powering the circuit, transistor T11 is
activated and its collector goes high.
The initial state lasts for a few
seconds and as soon as IC1 generates a clock pulse
(which is applied to the clock pin of IC2), Q1 (pin
2) of IC2 goes ‘high’ and pin 3 goes ‘low’, while no
change takes place in IC3. Now transistor T2 is
switched on.
Since the base of transistor T12 is at
low potential, the positive voltage will be
available at its collector. Thus transistors
T11 through T20 will be switched on and
off sequentially with the arrival of each new
clock pulse.
At the beginning of tenth pulse, the
carry-output pulse from pin 12 of IC2 is
applied to clock pin 14 of IC3. Now pin 3
(Q0) of IC2 and pin 2 (Q1) of IC3 go ‘high’.
Therefore, transistors T21 through T30 are
now switched ‘on’ and ‘off’ in a sequential
fashion. In this way one out of 100 transis-
tors is switched ‘on’ sequentially to produce
an output to drive the ‘resistor-array tone
oscillator’ according to the tune data. Thus
when power is switched on, the tune is
produced.
PCB layout and assembly
The PCB design should ideally be double-
sided for such types of transistor arrays.
However to keep the cost down, we have
included only a single-sided PCB layout,
which is shown in Fig. 18 with its compo-
nent layout in Fig. 19.
First, assemble transistors T11
through T110. Solder the transistors,
leaving a length from the PCB. Now take
a thin, bare wire and connect the emitter
leads of transistors T11, T21... T91 and
T101 together from the components side.
Similarly connect emitters of other rows of
transistors. Suitable pads for the purpose
have been provided on the PCB.
Similarly the collectrors of transis-
tors T1 through T10 may be connected
together using bare wire from the
components side. Now assemble all the
remaining components.
Programming
In this circuit, programming means hard
wiring. You should have a lot of patience
to do all the hard wiring. No hexadecimal
values are required. Before starting with
the wiring, label diodes D101 through
D128 of ‘variable resistor array oscil-
lator’ PCB (Fig. 7 and 9) in terms of
their respective notes i.e. label D101฀
as PA฀, D102 as dha฀, ..., D128 as NI ,
and so on.
Now starting from transistor T11
connect the transistor outputs (refer
PCB of Fig. 18) to diodes D101 through
D128 according to the tune note that
each transistor (T11 through T110)
sequentially represents. Extreme care
should be taken while wiring, because if
any error occurs, it will be very tedious
to nd out.
Let us consider the example of ve
notes ‘SA RE—GA SA PA’. In this case
programming can be done as under:
Connect
T11SAD6
T12RED8
T13NO connection, leave open (be-
cause the data is no sound)
T14GAD10
T15SAD6 (Again to D6)
T16PAD13
Reset. With this circuit a maximum
of 100 notes are feasible. However if all
notes are not utilised, Reset is necessary
after the last utilised note. Because if the
total number of notes is less than 98, for
example, 86, then after 86th note there are
14 more bits to reach for an automatic reset
to occur. (The circuit automatically resets
itself after 100th bit.) So there is a big delay
for the tune to get repeated. To skip the
delay, we use Reset. For this, the output
from the next transistor after the last note
is connected to point marked ‘RESET’ on
PCB. When the pulse appears at pin 15 of
IC2 and IC3, the circuit resets.
Stop-clock. Stop-clock is used when
more than one tune is to be programmed.
If the clock is to be stopped, say, after the
1st tune, we use stop-clock. For this, the
output from the next transistor after the
last note of the tune is connected to the
stop-clock point in the PCB. Please refer to
ow charts of Fig. 20 and 21, which show
occurance of automatic reset and use of
stop-clock and reset functions.
Housing. There is a lot of wiring in
between the ROM circuit of Fig. 17 and
the resistor-array oscillator. So the en-
closure must have enough space for all
the wires to t properly without getting
detached from the PCB while installing.
[EFY note. To overcome this problem to
some extent, a 28-pin (16+12) SIP con-
nector (with pins projecting towards both
sides of the PCB) may be used. This will
obviate the need to run loose wires between
ROM PCB and variable-resistor array
oscillator PCB. Wires originating from the
collectors of the transistor array may be
connected to one side of the connector on
ROM PCB itself and a ribbon cable with
28-pin SIP connector on both sides can be
used between the two PCBs.]
฀
ELECTRONICS PROJECTS Vol. 22 65
 AUTO CONTROL FOR
3-PHASE MOTORS
D. DINESH

I
nduction motors widely used in work- Automatic starting/tripping. PARTS LIST
shops, irrigation pump sets, etc re- Programmable timer with battery Semiconductors:
quire a 3-phase supply. Normally, backup to count the motor’s run time. IC1-IC3 - MCT2E optocoupler
these motors are connected to 3-phase sup- Latching circuit to prevent the IC4 - CD4027 J-K ip- op
ply from electricity boards using thermal motor from frequently starting and trip- IC5, IC6 - NE555 timer
IC7, IC9, IC10 - CD4017 decade counter
bimetal relays and relay contactors. Ther- ping. IC8 - CD4060 14-stage counter
mal relays protect the motor from over- Easy operation with just two switch- and oscillator
load. Relay coils having hold-on contacts es for time set and reset. IC11 - 7805 5V regulator
with push-to-‘on’ and push-to-‘off’ switches The phase-sequence detector protects D1-D30 - 1N4007 recti er diode
ZD1, ZD2 - 3.3V zener diode
are used for activating and deactivating the motor before starting, while the LED1-LED4 - Red LED
the relay contacts. current-sensing circuit protects it during Resistors (1/4W ± 5% carbon, unless speci ed
Single-phasing, line dropout, and running. This double protection makes the otherwise)
reverse phasing are harmful for 3-phase motor operation really safe. R1-R3 - 100-kilo-ohm, 0.5 watt
motors. In the event of line dropout and R4-R6, R16,
single-phasing, the motor draws a heavy R18-R23, R25,
current from the existing phases, and dur- Circuit description R30, R31, R38,
R47, R49 - 4.7-kilo-ohm
ing phase reversal the motor simply rotates
The schematic circuit diagram of induction R7, R24 - 27-kilo-ohm
in reverse direction. Further, an operator
motor controller is shown in Fig. 1. R8-R10 R17,
(attendant) for switching ‘on’/‘off’ the motor3-Phase sequence checker. The volt- R26, R29, R32,
R37, R39, R43,
is always not possible, especially when the
age from each of the three phases is con- R44, R46, R48,
motor has to be operated round the clock.nected to optocouplers IC1 through IC3 via R51-R53 - 10-kilo-ohm
recti er diodes D1 through D3. The out-
Also the protection provided by the thermal R11, R28, R34 - 1-kilo-ohm
relay in the starter assembly is inadequate,
puts from the optocouplers are half-wave R12 - 220-kilo-ohm
R13, R41 - 1-mega-ohm
recti ed DC pulses with a phase difference
since it involves some delay in activation. R14, R35, R36,
Thus some damage to the windings of the of 120° (during the conduction period of R45, R50 - 470-ohm
motor can take place, especially if overload
diodes), which are applied to a positive- R15 - 470-ohm, 0.5 watt
conditions occur frequently. edge-triggered, dual JK ip- op IC4. R27 - 180-kilo-ohm
R33 - 2.2-kilo-ohm
The circuit presented here incorpo- When the red phase rises, the output R40 - 22-kilo-ohm
rates the following features to overcome of IC1 goes from ‘low’ to ‘high’, resulting R42 - 82-kilo-ohm
all the above-mentioned problems: in clearing of both ip- ops FF1 and FF2 VR1 - 4.7-kilo-ohm preset
Electronic sensing of phase sequence
through 0.1µF capacitor C1. While the red VR2 - 47-kilo-ohm preset
with under-frequency cut-out. phase is still ‘high’, the yellow phase rises, Capacitors:
Current sensing for single-phasingresulting in the output of IC2 going ‘high’ C1-C3, C6,
C13 - 0.1 ceramic disk
prevention. and providing a clock pulse to FF1. As a C4, C7, C11, C17- 100µF, 63V electrolytic
Current sensing for overload result, Q output of FF1 goes ‘low’ (since C5, C14-C16,
cut-out. J1 input of FF1 is already ‘high’ when the C18, C19 - 10µF, 25V electrolytic
clock pulse arrives at CLK1 pin). Now, C8, C10, C12 - 47µF, 25V electrolytic
C9 - 1000µF, 63V electrolytic
TABLE I when the blue phase rises, the output of
Miscellaneous:
Phase sequence Signal OK LED RL1 IC3 goes ‘high’, while the output of IC2 is
X1-X3 - Current-sensing trans-
Correct On On already ‘high’, resulting in the output Q of formers
Incorrect Off Off FF2 going ‘low’. X4 - 0-230V AC primary to
The above process 12V-0-12V, 500mA sec-
TABLE II ondary transformer
repeats once dur-
Motor Core Core Primary Secondary S1 - ‘On’/‘off’ switch
ing each 50Hz cy- S2 - SPDT switch
HP size area Max SWG Turns S W G
Turns cle. If Q outputs S3 - 7-way rotary switch
(Max) amps of both FF1 and - 1.5V X4 battery
FF2 are ‘low’, the - Starter assembly
6 17 0.25 10 14 14 38 170 - Cabinet
20 23 0.56 22 11 9 38 110 phase sequence is

66 ELECTRONICS PROJECTS Vol. 22

Fig. 1: Schematic diagram of auto control for 3-phase motor

correct and both diodes D28 and D29 are As a result, IC5 is triggered and hence retriggerable monoshot. Its time period
in blocking mode. The base of transistor ‘sequence OK’ LED connected to pin 3 of is set at 25 milliseconds (approx.). If the
T1 is pulled towards ground via resistor IC5 via resistor R14, glows. monoshot is not retriggered within 25
R11 and transistor T1 starts conducting. IC5 is a popular 555 timer wired as a milliseconds, the ‘sequence OK’ signal goes

ELECTRONICS PROJECTS Vol. 22 67


Fig. 2: Actual-size, single-sided PCB layout for the circuit
‘low’. The circuit operates smoothly at
frequencies up to 42 Hz.
If any of the phase fails, the phase
sequence is disturbed, resulting in the
output of IC5 going ‘low’ and ‘sequence OK’
LED goes ‘off’. The LED status in relation
to the phase sequence is shown in Table I.
The output of IC5 is also used for driving
relay RL1 via transistor T2 (SL100).
Normally-open (N/O) contacts of relay
RL1 are wired in series with ‘off’ switch of
starter assembly as shown in the Fig. 1.
Thus when phase sequence is correct and
the frequency is above 42 Hz, the relay
is in energised state and it is feasible to
switch on the starter by momentary
energisation of relay RL2, whose N/O
68 ELECTRONICS PROJECTS Vol. 22
contacts are wired in parallel with the
‘on’ switch of starter assembly.
Auto-starter and current-sensing
circuit. As soon as the phase sequence is
detected to be correct (as
explained in the previous
section), the output of IC5
goes ‘high’. This output, Phase R Phase Y Phase B T6
via resistor R15, is used to (ON)
reset IC7 and enable IC6, (ON)
(ON)
besides acting as a clock (OFF)
for decade counter IC10. (OFF)
IC6 is an NE555 timer (ON)
wired in astable mode to (OFF)
In case of overloading
provide clock pulses to dec-
in any phase
ade counter CD4017 (IC7).
Eventually, when Q8 out- Note: R.B. = Reverse bias; F.B. = Forward bias; X = Don’t care
put of CD4017 (IC7) goes ‘high’, relay
RL2 energises through transistor T9
(SL100). N/O contacts of RL2 are con-
nected across ‘on’ switch of starter
assembly, as stated earlier and the
starter’s relay coil energises. The next
clock pulse to IC7 deactivates relay
RL2, but starter remains in ‘on’ state
due to hold-on contact (the fourth con-
tact of contactor in starter assembly).
When Q9 (pin 11) of IC7 goes ‘high’, its
CK pin 14 is muted due to conduction of
transistor T8 (which pulls it to ground)
to prevent further counting. The Q9
output of IC7 is also used in the motor
‘on’/‘off’ timer circuit, explained later.
The supply to starter is connected
through primaries of three small cur-
rent transformers used for sensing the
load in each phase. These transformers
can be constructed using common EI
laminations generally used for power
transformers. Core number 23 or 17
may be employed as per details given
in Table II.
The secondaries of these transform-
ers are connected to the current-sensing
circuit wired around transistors T3
through T5. If any phase goes ‘off’, it
cuts off the corresponding transistor
and thereby provides forward bias to
transistor T6.
The outputs of transistors T3
through T5 are wired-OR via diodes
D15, D16, and D17. Any excessive in-
crease in load current (overload) results
in forward biasing of transistor T7. The
excess current limit can be set with the
help of preset VR1.
The conduction of transistors T6
and/or T7 causes their common col-
lector junctions to be pulled low. This
‘low’ signal is coupled to transistor T2 via
diode D30. As a result, relay RL1 deacti-
vates to trip the starter and thus stop the
induction motor. The above conditions are
summarised in Table III.
TABLE III
Truth Table of Current Sensing Circuit
T7 RL1
(ON) (ON) R.B. R.B. Energised
(ON) (OFF) F.B. R.B. De-energised
(OFF) (OFF) F.B. R.B. De-energised
(OFF) (ON) F.B. R.B. De-energised
(ON) (OFF) F.B. R.B. De-energised
(OFF) (ON) F.B. R.B. De-energised
(ON) (ON) F.B. R.B. De-energised
— X F.B. De-energised

Fig. 3: Component layout for the PCB
Motor on/off counter and latch.
Frequent start and stop operations subject
the motor to lot of fatigue due to heavy
currents, which may damage the motor. In
this circuit, automatic restarting of motor
is limited to three attempts for each power
‘on’, by using another decade counter
CD4017 (IC10). It monitors each ‘on-off’
cycle of the motor by advancing the count
of decade counter by one on every start.
The clock for IC10 is obtained from
the output of IC5 via resistor R15. This
point i.e. the junction of resistor R15 and
diode D30 is also used as supply point for
transistors T6, T7, T12 and T13 as also
for reset pin of timer IC6. On the third
start, pin 7 (Q3) goes ‘high’ and transis-
tor T13 gets forward biased. As a result,
CK pin 14 of IC10 is pulled low to stop
any further clock to the decade counter,
which thus gets latched and LED3 glows
to indicate the latched state of the counter.
Simultaneously, this ‘low’ signal causes
transistor T2 to cut off and de-energise
relay RL1. Thus the motor cannot restart
automatically and only complete resump-
tion of power can reset the latch.
Motor on-off timer. A timer is provided to
run the motor for a predetermined time. It counts
run time of the motor and thereafter switches off
the motor automatically. The signal from pin 11
(Q9) of IC7 is connected to the base of transis-
tor T11 via resistor R38 (as referred
in ‘auto-starter and current-sensing
circuit’). Thus the collector of transistor
T11 goes ‘low’ to activate the oscillator
circuit of CD4060 (IC8), while the motor
is running. Prior to that, the oscillator
circuit of CD4060 was inactive because
its pin 11 was at logic ‘1’, being connect-
ed to +ve rails via resistors R39, R40 and
diode D22. The frequency of oscillation
is set by R-C network comprising 47µF
capacitor C8 and resistor R42 in series
with preset VR2.
A timing of either 30 minutes or 60
minutes can be selected with the help
of switch S2 for the output of ‘on’/‘off’
timer to go from ‘low’ to ‘high’ state.
The output from the pole of switch S2
is connected to the clock input of decade
counter IC9. The outputs of IC9 go ‘high’
sequentially after 30/60-minute time
intervals, depending on the selection
made via switch S2. Thus multiples
of 30-/60-minute basic timing can be
selected with the help of 7-way rotary
switch S3. (The 7-way rotary switch may
be substituted with decade thumb-wheel
switch, if desired.)
The output available at the pole of
rotary switch S3 goes ‘high’ after the
selected duration to forward bias tran-
sistor T12, which, in turn, causes de-en-
ergisation of relay RL1. Also, when the
selected run time is over, the oscillator
of IC8 (CD4060) gets inhibited because
oscillator pin 11 of IC8 goes ‘high’ due to
the feedback from the pole of switch S3
via resistor R43 and diode D23. LED1
glows to indicate that run time is over.
To restart the motor, IC8 and IC9 can
be manually reset by closing and then
opening switch S1. The timer may be
bypassed by keeping switch S1 closed.
The timer section requires very low
power in standby mode and is powered
by four 1.5V cells as standby supply. A
battery-low indicator is provided to warn
the user about the low battery condition.
Power supply. The normal DC power
supply for the circuit is provided by a
small step-down transformer X4 connected
between R (red) phase and neutral, fol-
lowed by recti er and lter capacitor. The
unregulated voltage is used for operation
of the relays, while the 5V regulated sup-
ply is used for the remaining circuit.
Construction and testing
An actual-size, single-sided PCB for the
ELECTRONICS PROJECTS Vol. 22 69

Fig. 4: Layout of cabinet for mounting trans-
former relays and the PCB
motor controller circuit of Fig. 1 is shown
in Fig. 2, with its component layout shown
in Fig. 3. It is recommended to use bases
for ICs.
Before connecting the circuit to starter
assembly, a bench test is required for
the adjustment of timer. Apply 3-phase
power to the circuit. Observe pin 3 of IC5
(NE555), which should go ‘high’, provided
the sequence is correct. Else, interchange
any two phase wires. As ‘sequence OK’
signal at pin 3 of IC5 goes ‘high’, relay RL1
energises and IC6 (IC555) is activated. As
a result, relay RL2 energises after a delay
of 15 seconds for one second.
Now adjust preset VR2
such that 30-minute-du-
ration pulse train (time
period 60 minutes) is
available at pin 14 of IC8
(CD4060). Flip switch S2
to 30-minute position. Se-
lect the required run time
using rotary switch S3. On
completion of the selected
run time, ‘time over’ LED
should glow and the timer
should stop. Relay RL1 Fig. 5: Creation of virtual neutral from 3-phaes 3-wires
system
should de-energise.
After resetting the timer with the all the wires to the starter point and the
help of switch S1, relay RL1 should load. Keep wiper contact of VR1 towards
energise once again. Then after a delay ground side and switch on the 3-phase
of 15 seconds, relay RL2 should again supply. Relay RL1 activates. After 5 sec-
energise for one second. Now short onds, relay RL2 also activates and the mo-
momentarily pin 14 of counter CD4017 tor starts running. Now slide the wiper of
(IC10) to ground thrice. On the third VR1 and mark the position just before the
touching, Q3 of IC10 will go ‘high’ and motor trips. (Remember that such trips
LED3 will glow, followed by de-energi- will be counted by latching counter.)
sation of relay RL1. The mains should be Caution. Some parts of this circuit
interrupted completely to reset IC10. contain live 3-phase voltages. So avoid
Current transformers X1 through X3, touching the circuit with bare hands.
step-down transformer X4, and relays Note. In the case of non-availability
RL1 and RL2 may be mounted side by of neutral terminal, assembler a circuit as
side in a compact box as shown in Fig. shown in Fig. 5. Connect ‘N’ marked wire
4. The PCB may be mounted over the (shown in Fig. 1) to two more transformers
transformers and relays using insulated X5 and X6 that are identical to X4. The
spacers. Current transformers are to secondaries of these transformers (X5 and
be connected before the starter relay X6) are kept open, while the secondary of
contacts. X4 is connected to the power-supply circuit
as shown in Fig. 1.
฀
Over-current adjustment can be done
only after connecting the load. Connect

Readers’ comments:
Q1. Please clarify the following:
1. Which starter in the circuit starts
the motor?
2. Is the starter manually operated or
automatically?
Ramaswamy Iyer
Through e-mail
Q2. When a 3-phase motor is started, it
takes six times the rated current. So the
current sense circuit will trip the motor
during start-up. If we adjust the overload
current setting for starting current, this
will not trip the motor during normal
running current through the load. Is
there any initial bypass provided for over-
current trip?
G. Saravana Mohan
Salem
Q3. The contactor-type starter can be used
for starting motors up to 10 HP. As I need
to control motors of 15 to 20 HP, please
clarify the following:
1. Can I use star-delta starter (which
can reduce the starting current and can
be used for motors up to 25 HP) instead of
the contactor-type starter? If no, suggest a
proper alternative as the starting current of
up to 40A may affect other components.
2. Are there any current-reducing
circuits used to withstand the high start-
ing current while using the contactor-type
assembly?
3. At the time of testing, what HP mo-
tor was used with contactor-type starter
assembly?
4. The 12V, 300-ohm, 1 C/O relays (RL1
and RL2) speci ed in the circuit are not tactor, an ‘on’ button (N/O), and an ‘off’
available. The available relays are 12V,
200-ohm, 1 C/O and 12V, 150-ohm, 1 C/O.
So which relay should I use? What is the
purpose of using VR2?
Ramaswamy Iyer
Through e-mail
Q4. I am facing the following problems in
the project:
1. In Table II, the turns ratio of cur-
rent transformers (CTs) is 12 for both 6HP
and 20HP motors. If the ratio is same, the
secondary currents of CTs work out to be
different, i.e. 1.8A for 20HP motor and
0.8A for 6HP motor.
2. In the phase-sequence indicator cir-
cuit, you have connected an RC (1-mega-
ohm-0.1µF) combination to the reset pin of
IC5 (NE555). In such a case, can the reset
pin get a high input.
Abhijeet S. Bhosle
Through e-mail
EFY: A1. 1. The starter comprises a con-
button (N/C). The contactor in Fig. 1 of
the project uses three main N/O contacts
connected to R, Y, and B phases and one
auxiliary N/O contact, which is wired
as shown in Fig. 1. The contactor coil is
rated at 415V AC. At EFY, we used ML1
contactor from L&T to make the starter
assembly.

70 ELECTRONICS PROJECTS Vol. 22

 2. You can manually operate the start-
er by making use of ‘on’ and ‘off’ buttons.
In automatic operation you don’t have
to use these switches. The circuit does it
through relays RL1 and RL2 as per the
logic explained in the project.
The author, D. Dinesh replies:
A2. A heavy current ows through to bypass the power-on surge current.
the motor winding for a moment only. A
certain delay is provided by capacitors
C12 (47 µF) and C17 (100 µF) to account
for this.
A3. 1. One can use star-delta starter
for a higher HP motor, provided that
star-to-delta changeover is done either
on releasing the ‘on’ pushbutton or after a
xed time delay. A typical semi-automatic the transistor. The bigger core is used to
star-delta starter made by L&T is Mark1
type bearing catalogue No. SS96255.
2. A delay is provided by capacitor C12
3. The circuit was tested using 6HP
borewell pump.
4. If the speci ed relay is not avail-
able, one can also use 12V, 200-ohm,
1C/O relay.
A4. 1. Current transformers are used
to sense the load current and these draw
only a few milliamperes of current to bias
cater to the wire gauge. One can use a
smaller core to hold this gauge by main-
taining the speci ed turn ratio.
2. Pulses at pin 14 of IC08 (CD4060)
should be adjusted to obtain 30-minute
delay by varying preset VR2. Pin 4 of IC5
is wired through RC network for delayed
reset at power-on (starting).
ELECTRONICS PROJECTS Vol. 22 71
 TELEPHONE
REMOTE CONTROL
JUNOMON ABRAHAM

T
elephone remote control implies operation is as
control of devices at a remote follows:
location via a circuit interfaced to 1. From the
the remote telephone line/device by dialing local telephone,
speci c DTMF (dual-tone multi-frequency) dial the number
digits from a local telephone. The tel- of the remote tel-
ephone remote control system described ephone to which
here has the following features: the circuit is con-
1. It can control multiple channels/ nected. In a short
relays. while you will
2. It provides you feedback when the hear a musical
current is in energized state and also note indicating
sends an acknowledgement indicating that the circuit
action w.r.t. the switching ‘on’ of each connected to the
requested relay and switching off of all remote telephone
relays (together). is active.
3. It can selectively switch ‘on’ any 2. Now if you
one or more relays one after the other and want to switch
switch ‘off’ all relays simultaneously. ‘on’ a particular
relay/device, press
‘*’ button on the
Operation telephone keypad
Instead of straightway proceeding with followed by any
the circuit description, we shall start one of digits 1
with the operation as this would help us to 7 correspond-
in understanding the circuit better. The ing to the device/
relay number
TABLE I(A) that you desire to
switch on . The
Input Output
A2 A1 A0 Qn = addressed switching ‘on’ of
L L L Q0 the relay will be
L L H Q1 acknowledged/in-
L H L Q2 dicated by a mu-
L H H Q3 sical note. Now
H L L Q4
you may keep the
H L H Q5
H H L Q6 handset on the
H H H Q7 cradle.
3. If you want
TABLE I(B) to switch ‘off’ the
WR R QQ relays, press ‘*’
addressed un-addressed and them press
L L = DATA hold key for digit 8.
L H = DATA L A musical note
H L hold hold
H H L L
is heard, which
indicated that all
H = High; L = Low
the relays have Fig. 1: Schematic diagram of the telephone remote control

72 ELECTRONICS PROJECTS Vol. 22

 PARTS LIST
Semiconductors:
IC1 - CA3140E op-amp
IC2 - NE556 dual timer
IC3 - CD4011 quad NAND gate
IC4 - CD406014-stage counter/
oscillator
IC5 - NE555 timer
IC6 - UM66 melody generator
IC7 - CM8870 DTMF-decoder
IC8 - CD4099 8-bit addressable
latch
IC9 - 7805 regulator +5V
T1 - BC548 npn transistor
T2-T9 - BC547 npn transistor (only
T2 and T6 shown)
LED1, LED2 - Green LED
LED3 - Yellow LED
LED4 - Red LED
D1, D2 - 1N4148 switching diode
D3-D10 - 1N4007 recti er diode (only
D3 and D4 shown)
Resistors (all 1/4-watt, ±5% carbon, unless
otherwise stated)
R1, R16. R17 - 150-kilo-ohm
Fig. 2: Actualsize, single-sided PCB for the circuit R2. R21 - 10-kilo-ohm
R3 - 33-kilo-ohm
R4 - 680-kilo-ohm
R5 - 560-ohm
R6, R10 - 22-kilo-ohm
R7 - 1-mega-ohm
R8, R15 - 390-ohm
R9, R12 - 15-kilo-ohm
R11 - 270-ohm
R13, R14 - 3.3k-kilo-ohm
R18 - 330-kilo-ohm
R19, R22-R27- 4.7-kilo-ohm (R22-R27 not
shown in the gure)
R20 - 220-ohm
VR1 - 10-kilo-ohm preset
VR2 - 1-mega-ohm preset
VR3 - 220-kilo-ohm preset
VR4 - 470-kilo-ohm preset
Capacitors:
C1 - 0.22uF ceramic disk
C2 - 220uF. 10V electrolytic
C3 - 100uF, 10V electrolytic
C4, C5, C8 - 0.0luF ceramic disk
C6, C11, C12 - 0.1uF ceramic disk
C7 - 10uF, 10V electrolytic
C9 - 0.02uF ceramic disk
CIO - 0.47uF, 100V polyester
Miscellaneous:
Fig. 3: Component layout for the PCB X PAL - 3.58MHz crystal
RL-RL7 - 9V, 150-ohm 1C/0 relay (only
been switched ‘off’. Keep the handset on When a ring is detected by IC1, its RL4 shown)
cradle. output triggers one of the timers in IC 556.
The output of the timer after inversion by is still persisting) applied to pin 9 of the
one of the NAND gates of IC3 (CD4011), same NAND gate (after inversion by an-
The Circuit enabled IC4 (CD4060) by taking its reset other NAND gate) will pass through it to
At the remote telephone end, the ringing pin 12 low . (IC4 is an oscillator-cum-14- trigger the second monostable inside IC2
signal is detected by a high-input-imped- bit binary counter.) As a result, IC4 starts (NE556) as well as IC5 (NE555), which
ance op-amp CA3140E that is wired as a counting when the ring signal strikes the is again wired as a monostable. This ar-
comparator. Since the op-amp output is input of the circuit. rangement avoids the circuit of being
open-controller type, the output pin has After some time, decided by the set- triggered by any transients or false ring
been pulled Vcc via 10-kilo-ohm resistor ting of preset VR3, Q12 output of IC4 signals on the telephone line.
R21, IC2 (NE556) comprised two timers goes high . This output coupled to pin 8 The output of the second monostable
(NE555 type) that have been con gured of a NAND gate inside IC3 will enable it. of IC2, available at its pin 9, drives tran-
as monostables. The detected ring signal (if the ring signal sistor T2 and shunts the telephone line

ELECTRONICS PROJECTS Vol. 22 73

voltage drops to around 10 to 12 volts.
This is equivalent to the lifting of the tel-
ephone handset of the remote telephone.
As mentioned earlier, both IC5 and the
second monostable of IC2 are triggered
simultaneously. The output of monostable
IC5 starts melody generator IC6 (UM66)
and the musical note obtained from it is
coupled to the telephone line. This informs
the caller that the remote circuit is in
energized state.
As the remote circuit is in energized
condition, the next step for the operator
at local telephone is to press the ‘*’ button,
which makes the local telephone to oper-
ate in the long-dialing mode. The digits
that are pressed after pressing the ‘*’ but-
ton are converted to DTMF tones.
The tone is decoded by IC7 and its
three LSBs (covering binary equivalent of
Readers’ comments:
Q1. In the circuit, if anyone makes a
call to the connected telephone line
and presses the consecutive switches,
the unauthorised person can also
switch the circuit on/off. Can the circuit
be altered such that switching on/off
the circuit is possible only after enter-
ing the authorisation code via telephone
keypad?
74 ELECTRONICS PROJECTS Vol. 22
decimal digits 0 through 7) are connected
to the address inputs, while the MSB line
is connected to reset pin 2 of IC8 (CD4099,
an 8-bit addressable latch). When a valid
DTMF tone is detected at the input of IC7,
its pin 15 goes ‘high’ to enable IC8 after
inversion by NAND gate of IC2. At the
same time, it triggers IC5 for informing
the caller that his key-press is accepted.
Numbers 1 to 7 on the local keypad
cause latching of the corresponding relays,
while number 8 causes reset operation,
which means that we can switch ‘on’
seven relays independently one by one
and switch ‘off’ all relays simultaneously
by pressing number 8. The output of IC8
drives the relays via the relay driver
transistor. Truth tables I(A) and I(B) of
CD4099 indicate relay operation.
Devjyoti Biswas
Through e-mail
The author, Junomon Abraham,
replies:
A1. It is possible to incorporate the
facility as desired by you by using a mi-
crocontroller. The microcontroller will
receive the signal from DTMF decoder
and it will verify whether the correct pass-
word has been received. The same can
Alignment
1. Connect the circuit to the telephone
line.
2. Adjust preset VR1 so the ringing
pulse causes LED1 to icker. For better
performance, set the voltage at pin 3 of
IC1 at approximately 2 volts.
3. The time required to activate ener-
gise the circuit is adjusted by preset VR3
with the help of LED2.
4. The time available for remote
switching action can be set by preset VR2
with the help of LED4. Indirectly, the set-
ting of preset VR2 determines the charge
that will have to be paid to the telecom
department.
5. The period of the musical note can
be controlled by the adjustment of VR4
with the help of LED3. ฀
be achieved with discrete ICs also, but
the microcontroller method is better
and exible.
EFY: Please refer to ‘Microcontroller-Based
Access Control System’ and ‘Multichannel
Access Control System’ projects published
in October and November issues of EFY for
implementation of the password authenti-
cation schemes used in such a system.
 MICROCONTROLLER-BASED
SCHOOL TIMER
U. B. MUJUMDAR

T
he basic requirements of a realtime PARTS LIST
programmable timer generally
Semiconductors:
used in schools and colleges for IC1 - 68HC705JIACP Microcontrol-
sounding the bell on time are: ler
Precise time base for time keeping. IC2 - CD4532 8-bit priority En-
Read/write memory for storing the coder
bell timings. IC3 - 74LS138 3-line to 8-line de-
coder
LCD or LED display for displaying IC4 - 74LS47 BCD-to-7-segment
real time as well as other data to make the decoder/driver
instrument user-friendly. T1-T3 - BC547/BC147 npn transistor
Keys for data entry. T4-T7 - 2N2907 pnp transistor
Fig. 1: MC68HC705J1A pin assignment D1-D7 - 1N4007 diode
Electromechanical relay to operate ZD1 - 5.6V, 0.5 watt zener
the bell. The time-keeping section. Ac- Resistors (1/4-watt, ±5% carbon, unless stated
We are describing here a sophisti- curate time-keeping depends on the otherwise)
cated, yet economical, school timer based accuracy of time base used for driving R1 - 210-ohm, 0.5 watt
on Motorola s 20-pin MC68HC705J1A the microcontroller. In this project, the R2 - 27-ohm
microcontroller. microcontroller is driven by AT-cut R3, R12-R14,
R24-R-27 - 1-kilo-ohm
parallel resonant crystal oscillator that
R4-R8 - 100-kilo-ohm
is expected to provide a very stable clock. R9-R11,
Description A 3.2768MHz crystal provides a time R23, R29 - 10-kilo-ohm
The pin assignments and main features of base to the controller. The frequency R15-R22 - 47 ohm
the microcontroller are shown in Fig.1 and (fosc) of the oscillator is internally divided R28 - 10-mega-ohm
the Box, respectively. The complete sys- by 2 to get the operating frequency (fop). Capacitors:
tem is divided into four sections, namely, This high-frequency clock source is used C1 - 350µF, 25V electrolytic
C2, C3 - 1µF, 16V electrolytic
the time keeping section, the input section to control the sequencing of CPU instruc- C4, C5 - 27µF ceramic disk
(keyboard), the output (display, indicators, tions. C6 - 0.1µF ceramic disk
and relay driving) section, and power sup- Timer. The basic function of a timer Miscellaneous:
ply and battery backup. is the measurement or generation of S1-S5 - Push-to-on switch (key)
time-dependant events. Timers usu- S6 - On/off switch
PZ1 - Piezo buzzer
RL1 - Relay 12V, 300-ohm, 1C/O
Main features of MC68H705J1A XTAL - 3.2768MHz AT-cut crystal
X1 - 230V AC primary to 12V-0-
14 bidirectional input/output (I/O) lines.
12V, 500mA secondary trans-
(All the bi-directional port pins are programmable as inputs or outputs.)
forer
10 mA sink capability on four I/O pins (PA0-PA3). DIS.1-DIS.4 - LTS542 common-anode dis-
1,240 bytes of OTPROM, including eight bytes for user vectors. play
- 4 x 1.2V Ni-Cd cells
64 bytes of user RAM.
Memory-mapped I/O registers.
Fully static operation with no minimum clock speed. ally measure time relative to the internal
Power-saving stop, halt, wait, and data-retention modes. clock of the microcontroller. The MC68H-
Illegal address reset. C705J1A has a 15-stage ripple counter
preceeded by a pre-scaler that divides the
A wide supply voltage range from-0.3 to 7 volts.
internal clock signal by 4. This provides the
Up to 4.0 MHz internal operating frequency at 5 volts.
timing references for timer functions.
15-stage multifunction timer, consisting of an 8-bit timer with 7-bit pre-scaler.
The programmable timer status and
On-chip oscillator connections for crystal, ceramic resonator, and external clock.

ELECTRONICS PROJECTS Vol. 22 75


Fig. 2: Schematic diagram of the microcontroller-based school timer
control register (TSCR) is used for de-
ciding the interrupt rate. It can be pro-
grammed to give interrupts after every
16,384, 3,2768, 65,536, or 131,072 clock
76 ELECTRONICS PROJECTS Vol. 22
cycles. In Table I, the control word is set to
provide the interrupts after every 16,384
cycles. For a 32,768MHz crystal, the
interrupt period will be 10ms. Thus,
timer interrupts will be generated after
every 10 ms (100 Hz). That is, 100 inter-
rupts will make 1 second.
Now time-keeping becomes very sim-
ple. As we are having a precise 1-second
time count, a real-time clock can be easily
built.
The MC68HC705J1A has a 64 byte
RAM that is used for data storage, Real
time (in terms of seconds, minutes, hours,
days of a month, and months) is stored in
this RAM. Thus an accurate real-time clock
is generated.
The input section. For setting the
real-time clock and storing operating times,
the timer requires to be programmed exter-
nally. Data is fed using the keyboard.
Press-to-on type keys are interfaced to
the microcontroller using an 8-bit priority
encoder CD 4532. This encoder detects
the key-press operation and generates
the equivalent 3-bit binary data. Its truth
table is shown in Table II. The priority
encoder is interfaced to port A of the mi-
crocontroller.
Various keys used in the timer,
along with their functions, are described
below:
Time (4): For setting real time in
minutes and hours.
Bell (5): For setting the bell s operat-
ing timings.
Digit Advance (6): Data setting is
done digitwise (hour s digit followed by
minute s digit). The Digit Advance key
shifts the decimal point to the right.
Store (7): For storing the data (real
time or bell time).
Delete (3): For deleting a particular
bell timing.
Here, the gures within parentheses
indicate the decimal equivalents of 3-bit
binary data from the keyboard.
Set and run modes. Data setting is
possible only in set mode. Set mode or
run mode can be selected by toggle switch
S6. By using a lock switch for S6, the
timer can be protected from unauthorized
data entry/storage.
In run mode if you press Bell
key once, the display shows the bell s
various operating timings one after the
other, in the same order in which these
had been previously stored. In case you
want to discontinue seeing all the bell
timings, you may press Time key at
any stage to revert back to the display
of real time.
The output section. Seven-segment
displays are used for data display. As
LEDs are brighter, these have been used
in the system. There are two techniques
for driving the displays: (i) driving each
display using a separate driver (like
74LS47 or CD4511) and (ii) using multi-
plexed displays.
The first technique works well,
but practically it has two problems: it
uses a large number of IC packages and
consumes a fairly large amount of cur-
rent. By using multiplexed display both
the problems can be solved. In multiplex-
ing only one input is displayed at any
given instant. But if you chop or alter
Fig. 3: Power supply circuit for the school timer
Fig. 4: Actual-size single-sided PCB for the circuits in Figs 1 and 2
inputs fast enough, your eyes see the re- backed power supply, so that in the
sult as a continuous display. With LEDs, case of power supply, so that in the
only one digit is lighted up at a time. This case of power failure the functioning
saves a lot of power and also components, of the controller’s timer section is not
making the system economical. affected. During power failure the
Generally, displays are refreshed at a timer is taken to low power mode (called
frequency of 50 to 150 Hz. Here, displays wait mode). In this mode the controller
are refreshed at a frequency of 100 Hz draws a very small current. So small Ni-
(after every 10 ms). The display-refreshing Cd batteries can provide a good backup.
program is an interrupt service routine A simple diode-resistance (27-ohm,
program. BCD-to-7-segment decoder/driv- ¼-watt) charger maintains the charge of
er 74LS47, along with transistor 2N2907, the battery at proper charging rate.
and 3-line-to-8-line decoder 74LS138
are used for driving
common-anode dis- Software
plays. Motorola offers Integrated Development
In multiplexed Environment (IDE) software for program-
display, the current ming its microcontroller and complete
through the seg- development of the system. The develop-
ments is doubled to ment board comes with Editor, Assembler,
increase the display’s and Programmer software to support
brightness. 74LS47 Motorola’s device programmer and soft-
is rated for sinking ware simulator. The ICS05JW in-circuit
a current of up to 24 simulator and non-real-time I/O emula-
mA. As the current tor for simulating, programming, and
persists for a very debugging code for a MC68HC705J1A/KJ1
small time in multi- family device.
plexed display, it is When you connect the pod to your
peaky and can be as host computer and target hardware, you
high as 40 mA per can use the actual inputs and outputs of
segment. the target system during simulation of
The decimal the code. You can also use the ISC05JW
point is control- software to edit and assemble the code in
led individually by standalone mode, without input/output
transistor BC547, to/from pod. The pod (MC68HC705J1CS)
as 74LS47 does not can be interfaced to any Windows 3.x-or
support the decimal Windows 95-based IBM computer using
point. PA0 and PA1 serial port.
bits of port A are The software for the timer has been
used for controlling so developed that the system becomes
the electro-mechani- as user-friendly as possible. The main
cal relay and buzzer, constraint is read/write memory (RAM)
respectively. space. As mentioned earlier, the micro-
Power supply controller has only 64 byte RAM. About
and battery twenty bell operating timings are required
backup . T h e to the stored. So the ef cient use of RAM
microcontroller becomes essential.
and the associ- The software routines for the timer,
ated IC packages along with their Assembly language codes,
require a 5V DC are listed in a folder. (Note: This folder,
supply, while the containing source code (.asm) and listing
relay and the le (.lst) will form part of the EFY-CD
buzzer require provided with the August 2001 issue. As
12V DC supply. les are quite large, it is not feasible to in-
A simple rectifier clude them here.) Basically, the following
along with zener functions are performed by the software
diode-regulated program:
power supply 1. Initialisation of ports and the
is used. The mi- timer.
crocontroller is fed 2. Reading of keypressed data.
through a battery- 3. Storing of real time and bell
ELECTRONICS PROJECTS Vol. 22 77
 TABLE I Set. The real time and bell timings
Timer Status and Control Register (TSCR) are stored using this part of the software.
Bit 7 6 5 4 3 2 1 0 Data is entered digitwise; for example,
Signal TOF RTIF TOIF RTIE TOFR RTIFR RTI RTO 08:30 a.m. will be stored a 0, followed by 8,
Reset 0 0 0 0 0 0 1 1 followed by 3, and nally 0. Data is stored
TOF: Timer over ow ag RTIE: Real-time interrupt enable
in 24-hour format.
RTIF: Real-time interrupt ag RTI and RTO: Real-time interrupt select bit
Data fed from the keyboard is con-
verted into equivalent hex and stored in
RTI RTO Interrupt period
RAM. Any particular operating timing can
0 0 fop ÷ 214 For 3.2768 MHz crystal
be deleted from the memory using Delete
0 1 fop ÷ 215 Frequency of operation (fop)
key, provided the timing is already stored
1 0 fop ÷ 216 = 3.7268x106/2 = 1.638x106MHz
in the memory.
1 1 fop ÷ 217 For RTI=RTO=0
Run. Here the real time is compared
Interrupt period = 10ms (100Hz)
with bell operating time. If the two match,
the relay is operated.
TABLE II DataCon. This part of the software
Truth Table for Priority Encoder CD4532 is used for nding out the decimal equiva-
Keys E1 D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 lent of hex data. The microcontroller
Store 1 1X X X X X X X 1 1 1 manipulates the hex data and converts it
Digit Adv. 1 01 X X X X X X 1 1 0 into BCD format for display.
Bell 1 00 1 X X X X X 1 0 1 Timer. The timer of the microcontrol-
Time 1 00 0 1 X X X X 1 0 0 ler is initialized to give an interrupt after
Delete 1 00 0 0 1 X X X 0 1 1 every 10 ms. A real-time clock is gener-
ated using the interrupt. Also the display
timings. 5. Display of data. is refreshed during the interrupt service
4. Comparison of real time and bell 6. Time-keeping. routine.
time. If the two match, the bell rings. For a user-friendly system, the as- For real-time systems battery backup
sociated software is is very essential, because power failure
required to perform affects the time keeping. In interrupt
many data manipula- service routine, the availability of
tion tricks and inter- power supply is checked. If the power is
nal branching. The available, displays are refreshed and
operation and logic the timer operates normally. However,
can be understood during the power-failure period, dis-
from the Assembly plays are off and system is taken to low
language listings. The power mode. In this mode only the
software is mainly di- timer part of the microcontroller remains
vided into the follow- activated while operations of all other
ing modules: peripherals are suspended. This consid-
Keyboard. When erably reduces the power consumption.
a key is pressed, When the supply gets restored, the
CD4532 sends the controller starts operating in normal
corresponding data. fashion.
After reading the
data, the controller
decides on the action.
Operating procedure
Set/ Run key (S6) When the power is switched on, the
is connected to port display shows 12.00. Two settings are
PA4. required in the timer: (a) setting of real
Bell. This part time and (b) setting of bell operating tim-
of the program is ings. For setting real-time clock Time
used for displaying key is used.
the bell operating Storing of real time. To store real
timings stored in the time, say, 05:35 p.m., ip Run / Set key
RAM. The operating (S6) to set mode. The display will show
timings are displayed 0.000 . Press Time key. Further press-
one by one with a ing of Time key will increment the data,
delay of 5 seconds like 0.000, 1.000, 2.000, and thereafter
between tow consecu- it will repeat 0.000, etc. To select the
tive timings. digit, press Digit Advance . This stores
Fig. 5: Component layout for the PCB the present digit and the next digit is

78 ELECTRONICS PROJECTS Vol. 22

selected as indicated by the decimal
pointer. Data is stored in 24-hour for-
mat. The time to be stored is 17.35, of
which the first digit will be 1.000. The
second, third, and fourth digits can
be stored in similar fashion. After the
fourthdigit, press Digit Advance key
once more. The display will show 1735
(with no decimal). Now press Store to
store the data.
Storing of bell timings. The pro-
cedure to store bell operating timings is
similar to that of setting real time. The
only difference is that here data is changed
by Bell key in place of Time key. Any
number of bell timings (<20) can be stored
in the same fashion. If the number of bell
operating timings exceeds 20, the timer
will not accept any new bell timings
until one of the previously stored timings
is deleted.
Deletion of bell operating timings.
For deleting a particular timing, rst store
this timing using the steps given above.
Then press Delete key to delete the spe-
ci c data from the memory.
Display of real time. If Run / Set
key is taken to run mode, real time will
be displayed.
Checking of bell operating times.
For checking the bell operating times,
press bell key in Run mode only. The
stored bell operating timings will be
displayed one by one with a delay of
5 seconds between two consecutive
timings.
Programming
There are two ways to program the
EPROM/OTPROM (one-time program-
mable ROM):
1. Manipulate the control bits in the
EPROM programming register to pro-
gram the EPROM/OTPROM on a byte-
by-byte basis.
2. Program the EPROM/OTPROM
with Motorola s MC68HC705J in-circuit
simulator.
The author has used the second
method for programming the OTPROM.
An actual-size, single-sided PCB for
the circuits in Figs 2 and 3 is shown in
Fig. 4, with its component layout shown
in Fig. 5. ฀

Readers’ comments:
Q1. I have assembled this circuit and
found that pins D0 and D1 of IC 4532
are not properly terminated. Will
this affect the keyboard data? Could
you please tell me from where I can
get the programmed controller?
Deep Saraf
Pune
Q2. Does the circuit work by just
assembling it with the IC (MC68H-
C705J1A) bought from the market,
or do we have to install a software
in it? From where can we get the
software? Give a detailed procedure
about how to install the software in
the IC. Fig. 1: Modification of display circuit to operate 2.5cm/5cm display
A. Rajasekaran
Chennai present circuit after omitting resistor R1. ment kit and IDE (integrated development
Q3. The circuit can be modi ed as shown Somnath Bera environment) software available through
in Fig. 1 for using a brighter and bigger Through e-mail Motorola distributors/Internet. The same
display. You can use this modi cation for A1 and 2. EFY: Leaving two of the un- can be purchased through our associate
one set of 2.5cm (1-inch) or 5cm (2-inch) used input pins open will not affect the Kits‘n’Spares.
display. For 5V supply, use 7805 regu- circuit performance. The microcontroller A3. EFY: The circuit sent by the reader
lator in place of the zener diode in the has to be programmed using a develop- had anomalies, which have been corrected.

ELECTRONICS PROJECTS Vol. 22 79

 DIGITAL CAPACITANCE-CUM-
FREQUENCY METER
PRATAP CHANDRA SAHU

and external frequency = 1 kHz, we can

He
re is an inexpensive circuit of PARTS LIST
a digital capacitance-cum-fre- read the value of the capacitor under test Semiconductors:
quency meter that can meas- (CUT) directly in nanofarads. With R = IC1 - NE555 timer
ure capacitance in the range of 1 pF to 1 kilo-ohm and frequency = 1 kHz, we IC2, IC3 - CA3140 high-input imped-
10,000 µF and frequency in the range of can read the value of the CUT directly in ance op-amp
microfarads. IC4 (A-D) - 7408 AND gate
0 to 100 kHz. With a slight modi cation, IC5 - MM74C925 4-digit counter/7-
this circuit can be used as an article coun- Frequency measurement. This segment driver
ter or a time meter. involves passing the unknown frequency IC6 - 74LS121 monostable MV
The principle. In a frequency coun- signal for a known time base period IC7-IC9 - 74LS90 decade counter
through the counter. In a 4-digit counter (divide-by-10)
ter, the unknown input is ANDed with a
IC10 - 7476 JK ip- op
known time-base period, so that the num- with a time base of one second, the maxi-
IC11 - 7805 regulator +5V
bers of cycles passed over the time-base mum display will be 9999, which means D1-D5 - 1N4007 recti er diode
period are counted. The time period can be that we cannot read a frequency of more D6 - 1N4148 switching diode
measured similarly if a known frequency than 9999 Hz (≈10 kHz). However, if we LED1 - Red LED
reduce the time base to 0.1 second, the T1-T5 - BC547B npn transistor
is gated with the unknown time period. T6 - BS107 FET
The same instrument can also determine frequency reading can go up by a factor of Resistors (all ¼ watt, ±5% carbon, unless
the time period of a periodic waveform or ten to 99.99 kHz (≈100 kHz) as the time stated otherwise)
the time elapsed between two events. base virtually divides the input frequency R1 - 2.2-kilo-ohm
by 10. For low-frequency measurement, R2, R5 - 1-mega-ohm
In this circuit, the capacitance meas-
R3, R8, R24 - 4.7-kilo-ohm
urement is nothing but the measurement we can increase the resolution by a factor
R4, R20 - 10-kilo-ohm
of the time between two events in a charg- of ten by increasing the time base period R6, R7, R18
ing capacitor. An R-C (resistor-capacitor) to 10 seconds, which is equivalent to the R21 - 1-kilo-ohm
circuit works as a time generator and the multiplication of the input frequency by a R9-R16 - 220-ohm
factor of 10. R17 - 20-kilo-ohm
time is directly proportional to capacitance R19 - 100-kilo-ohm
value under suitable conditions. In the R22, R23 - 560-kilo-ohm
present case the condition being satis ed VR1 - 1-kilo-ohm preset
is that the time period (T) is equal to the
Circuit and operation Capacitors:
The capacitance measurement mode. C1 - 15µF, 25V electrolytic
product RxC, where R is the value of the
C2 - 0.01µF ceramic disk
charging resistor in ohms and C the ca- During the capacitance measurement
C3 - 10nF ceramic disk
pacitance value in farads. mode, switches S1 through S5 are kept C4 - 10µF, 250V electrolytic
Capacitance measurement. One slided towards position ‘C’. The unknown C5 - 1000 µF, 25V electrolytic
RxC time (seconds) is required to charge capacitor is placed across CUT terminals. C6 - 100µF, 25V electrolytic
Ganged switches SR1 and SR2 are used C7, C8 - 22 pF ceramic
a capacitor to 63 per cent (approximately C9 - 0.01µF ceramic
two-third) of its nal value (applied volt- for capacitance measurement. Position 1 Miscellaneous:
age). is used for capacitance range of 1 pF to X1 - 230 AC primary to 9-0-9 volt,
Consider the following example: 9999 pF (≈10 nF), position 2 for capaci- 500mA secondary trans-
tance range of 1 nF to 9999 nF (≈10 µF), former
If C = 470 pF and R = 1 mega-ohm,
XTL - 1MHz quartz crystal
then one RC time period T = 470x10–6 and position 3 for capacitance range of 1
S1-S5 - Slide switch
seconds = 470 microseconds. µF to 9999 µF. S6, S7 - Push-to-on switch
If we select the external frequency for Switch SR1 selects 1 mega-ohm charg- SR1-SR2 - Ganged 3-way, 2-pole rotary
the counter as 1 MHz (time period = 1 mi- ing resistor in its positions 1 and 2, while switch
switch SR2 selects a frequency of 1 MHz SR3-SR4 - Ganged 3-way, 2-pole rotary
crosecond), the counter progresses by one switch
count every microsecond and the counter in position 1 and a frequency of 1 kHz in DIS1-DIS4 - LT543 common-cathode,
reading is 470, as the gate will be open for position 2 for the counter operation. In po- 7-segment display
470 microseconds for the above-mentioned sition 3, 1-kilo-ohm charging resistor R6 is
R and C under testing. We get the capaci- selected by SR1, while SR2 selects 1 kHz only. (EFY note. As decimal indication
tance value directly from the readout of as the frequency for counter operation. is not required during capacitance meas-
the counter in picofarads. Ganged rotary switches SR3 and SR4 urement, one might have an additional
Similarly, if we take R = 1 mega-ohm are used for frequency measurement mode ‘off’ position for SR3/SR4 ganged rotary
switch.)

80 ELECTRONICS PROJECTS Vol. 22

 81
ELECTRONICS PROJECTS Vol. 22
Fig. 1: Circuit diagram for digital capacitance-cum-frequency meter
 IC1 is a monostable multivibrator
based on timer NE555 and is meant for
capacitance measurement only. In normal
condition, the low output of the monostable
turns on the FET (BS107) switch. So the
capacitor under test gets shorted via the
FET switch. As and when triggered by the
momentary push-to-on operation of start
switch S6, the monostable provides a pulse
Fig. 2: Internal block diagram and functional description for IC 74C925
Fig. 3: Actual-size, single-sided PCB layout for digital capacitance-cum-frequency meter
82 ELECTRONICS PROJECTS Vol. 22
of 15-second duration. As soon as its out-
put goes high, it switches off FET switch.
Simultaneously, it takes pin 5 of AND
gate IC4A high.
Now let us examine the conditions at
IC2 and IC3 (both CA3140 op-amps). The
voltage across CUT, after being buffered
by IC2, is fed to the inverting input of IC3
wired as a comparator. The non-inverting
input of IC3 is biased at 0.63Vcc, which is
set accurately by 1-kilo-ohm preset VR1.
Now the capacitor begins to charge. As
soon as the voltage across the capacitor
crosses 0.63Vcc (i.e. 3.15 volts with Vcc
= 5 volts), the output of IC3 goes low.
Thus the output of IC3 and also that of
AND gate IC4A remains high until the
capacitor charges to 63 per cent of Vcc in
one RC time.
Latch-enable (LE) pin 5 of counter
IC5 (74C925) connected to pin 6 of IC4A
remains high to pass the clock selected
via rotary switch SR2 and coupled to
CL (clock) pin 11 of IC5 via AND gate
IC4B. It goes low after one CR time to
latch its count as the output of IC3 goes
low. Thus the number of cycles from the
frequency source passed over one CR
time is recorded in the counter and gets
displayed.
For precise generation of 1MHz fre-
quency, a 1MHz crystal oscillator is wired
around Schmitt inverter gates N3 and N4.
The oscillator output is routed via AND
gate IC4C to slide switch S2 and rotary
switch SR2 position 1. In capacitance (C)
position of switch S2, this signal, after
division by three decade counters IC7, IC8,
and IC9 (7490), which are common to both
frequency and capacitance meter modes,
provides 1kHz signal at pin 12 of IC9,
which, in turn, is extended to positions 2
and 3 of switch SR2. (Note. The outputs
of IC10 are not used during capacitance
measurement. IC10 comes into play only
during the frequency measurement as
explained later.)
The NE555 timer used as a monoshot
ensures the capacitance measurement in
an easy and automatic manner. The LED
connected to AND gate IC4D glows during
the charging of the capacitor. During the
measurement of high-value capacitances,
it may take several seconds to charge to
0.63Vcc. For low-value capacitances, the
LED glows for just a moment after press-
ing start switch S6. If the LED goes off af-
ter the start button is pressed, it indicates
that the measurement is over.
You can reset NE555 timer using
switch S7 if you want to make another
measurement. If this switch is not pro-
vided/operated, you would have to wait
for at least 15 seconds until NE555 timer
becomes normal. Alternatively, you will
have to switch off the complete circuit and
then switch it on again.
Frequency counting. In place of
1MHz oscillator, a 100Hz full-wave recti-
ed (pulsating DC) after being shaped by

Fig. 4: Component layout for the PCB
Schmitt inverter N2, is used as the master
clock to provide the required time bases.
The voltage divider network of resistors
R20 and R21 protects gate N2 against
high voltage.
R21 is test selected to get proper 100
Hz rectangular wave form at the output
Readers’ comments:
Q1. A provision to include inductance
measurement by using an FET-based
tank oscillator circuit (as shown in
Fig. 1) would enhance the utility of the
circuit. The tank circuit could be tuned by
trimmer CT for a frequency of, say, 1 MHz
with a standard inductor of 1 µH. Decade
dividers can be used for other ranges for
direct readout.
Fig. 1: FET-based tank oscillator circuit
of gate N2. This 100Hz signal is divided
by decade counters IC7, IC8, and IC9 to
obtain 10Hz, 1Hz, and 0.1Hz frequencies.
The frequency selected via rotary switch
SR3 is then divided by 2 by JK ip- op
7476 (IC10) so as to provide a gate time of
0.1 second, 1 second, or 10 seconds in po-
sitions 1, 2, and 3, respectively, of switch
Praveen Shankar
Haridwar
Q2. I have the following queries:
1. Are ICs DM74LS121 and SN74LS121
the same? Can I use DM74LS121 or
SN74LS121 as IC6?
2. Can I replace 15µF, 25V capacitor
C1 with a 22µF, 25V capacitor?
Chang Heen Loong
Through e-mail
The author, Pratap Chan-
dra Sahu, replies:
A1. Such a tank oscillator is
not suitable for this circuit as
the frequency in such a circuit
is inversely proportional to the
value of inductance and there
is an offset frequency. The
circuit proposed by the reader
could, however, be used in con-
junction with moving coil type
SR3. Q output of IC10 is used to enable
counter IC5.
The resetting of counter-cum-display
IC5 is accomplished by the narrow output
pulse from IC6 (74121), which is generated
by the leading (rising) edge of Q output of
IC10 connected to its B input (pin 5) via
switch S5. Thus at the beginning of each
counting period, IC5 is reset.
IC5 (74C925) is TTL-compatible with
a multiplexed 4-digit, 7-segment display
driver. Its internal block diagram and
functions are described in Fig. 2. The
maximum frequency display in positions
1, 2, and 3 of ganged switches SR3 and
SR4 is limited to 99.99 kHz, 9.999 kHz,
and 999.9 Hz. The decimal point position
is xed by switch SR4.
Calibration and testing. Connect a
multimeter to the non-inverting terminal
of IC3 and set the point at 0.63Vcc = 3.15
volts using 1-kilo-ohm preset VR1. To
test the capacitance meter, use a 470pF
polystyrene capacitor with one per cent
tolerance.
Precaution. Try to screen the mains
transformer from the input. Place the
transformer at a place where the chances
of its interference with the input are mini-
mal or nil. While measuring the frequency,
the frequency source under test should not
be touched or loaded to avoid affecting its
frequency due to stray capacitance associ-
ated with the test leads.
An actual-size, single-sided PCB
for the circuit of Fig. 1 is shown in Fig.
3, with its component layout shown in
Fig. 4. ฀
frequency meter after suitably calibrating
its scale.
A2. EFY: 1. Yes, ICs DM74LS121 and
SN74LS121 are similar and you may use
either of these two ICs as IC6.
2. You can replace 15µF, 25V ca-
pacitor C1 with a 22µF, 25V capacitor
by changing the value of resistor R2
(1 mega-ohm) such that R2 x C1 product
remains the same, in order to retain
the same output pulsewidth. Since IC1
(NE555) is a timer IC, con gured as
a monostable, the output at pin 3 is
approximately 16 seconds as per the
following relationship:
Pulsewidth = 1.1(R2 x C1) seconds
So, if the capacitor value is changed
from 15 µF to 22 µF, the resistor value
needs be changed from 1 mega-ohm to 680
kilo-ohms so that R2 x C1 product remains
almost the same.
ELECTRONICS PROJECTS Vol. 22 83
 FLUID-LEVEL CONTROLLER
WITH INDICATOR
he uid-level controller circuit pre-
T
sented here allows you to set the
lower and upper uid levels at
the desired speci c positions between
two extreme levels. The total uid level
is divided into ten equal parts. Any two
of these ten positions may be de ned as
‘low’ and ‘high’ level, respectively. The
system shows the preset levels on the
two 7-segment displays and the current
uid level at any instant on a 10-LED bar
graph indicator. The same circuit could
also be used for controlling temperature
in a similar fashion.
Fig. 1: Schematic diagram of uid-level controller with indicator
84 ELECTRONICS PROJECTS Vol. 22
BHASKAR BANERJEE
The circuit
The main part of the circuit as shown in
Fig. 1 is dot/bar graph driver LM3914
(IC1). This IC is linearly scaled and is
intended for use in LED voltmeter appli-
cation where the number of illuminated
LEDs indicates the value of input voltage.
It contains a oating 1.2V reference source
between pins 7 and 8 that may be used as
the reference input for the IC. The voltage
from the sensor is fed to the input of IC1
at pin 5.
The output of the sensor may vary
from ground level (0V) to supply voltage.
Thus the reference voltage source should
be externally preset, which is feasible with
the help of IC1. This IC can also display
the input voltage on a linear scale using
ten LEDs in the bar graph or the dot mode.
Here we have used the bar graph mode.
The outputs of IC1 are active-
‘low’ and hence they sink current to
illuminate LEDs. Inverters are used
between the outputs of IC1 and the
inputs of IC3 and IC4 to invert the
active-‘low’ outputs of IC1. There
are ten outputs available from IC1,
of which only
five are used
here. One may
use up to eight
outputs of IC1
since IC3 and
IC4 (4051) are
1-of-8 data se-
lectors. (Note.
If 4067 were
used in place of
4051, all the ten
outputs could be
used. It is also Fig. 2: Optical sensor
possible to get more than ten outputs by
cascading LM3941 ICs.)
Using this circuit, the maximum
uid level can be divided into four equal
parts giving ve different level readings
from ‘0’ (empty/low level) to ‘4’ (full/high
level). Thus the ve levels are empty, one-
fourth, half, three-fourth, and full. This
division is meant only for controlling the
level, while all levels including the inter-
mediate levels are constantly displayed
on LED bar graph.
The lower level can be set anywhere
between 0 and 3 in steps of 1 and high
level can be set between 1 and 4. The
uid level can be maintained between
any two levels by using IC3 and IC4.
IC3 selects the high level and gets inputs
of levels 1, 2, 3, and 4, while IC4 selects
the low level and gets inputs of levels 0,
1, 2, and 3. All switched on. This power-on-reset function
other unused is realised using capacitors C1 and C2,
input pins of and resistors R12 and R13. The part of
IC3 and IC4 are IC6 connected to high-level selector also
grounded. gets reset when the count is 5 (101 binary).
The selec- This reset pulse is generated using AND
tion takes place gates of IC CD4081.
according to the The selected minimum and maximum
binary word pre- levels are displayed by two 7-segment dis-
Fig. 3: Sensor us- set at the select plays DIS1 and DIS2 that are controlled
ing oat operated input pins (pin by two BCD-to-7-segment decoders 4511
potmeter 9, 10, and 11) (IC9 and IC10, respectively).
of IC3 and IC4. The outputs of IC3 and IC4 are fed
The required binary word is generated to the select input pins of IC5 (4051).
by a dual divide-by-16 counter IC6 (4520). The output of IC5 is fed back to one of
(IC6 can be replaced by a divide-by-10 its select inputs through an inverter. IC5
counter 4518, if desired.) Half of IC6 is determines the control logic. The pump
used for high level and the other half for (or the heater in temperature controller)
low level. IC6 gets its counting pulse from should be on when the uid (or tempera-
a 555 timer (IC7) used for generation of ture) level is below the minimum level and
approximately 1Hz pulse train. should remain ‘on’ until the maximum
The high level is set by pressing switch level is reached. It must not start if the
S1, while the low level is set by pressing uid level falls below the maximum level
switch S2. IC6 is reset when the power is but remains above the minimum level.

PARTS LIST
Semiconductors:
IC1 - LM3914 bar/dot display
driver
IC2 - 4069 hex inverter
IC3, IC4, IC5 - 4051 8-channel analogue
multiplexer
IC6 - 4520 dual binary counter
IC7 - 555 timer
IC8 - 4081 quad 2-input AND
gate
IC9, IC10 - 4511 BCD-to-7-segment
latch/decoder/driver
LED1, 3, 5, 7, 9 - Green LED
LED2, 4, 6, 8,
10, 11 - Red LED
Resistors (all ¼-watt, ±5% carbon unless
stated otherwise):
R1-R10,
R16-R31 - 470-ohm
R11-R15 - 10-kilo-ohm
R32-R33 - 47-kilo-ohm
R34 - 1-kilo-ohm
VR1 - 10-kilo-ohm preset
Capacitors:
C1, C2 - 22µF, 25V electrolytic
C3, C4 - 10µF, 25V electrolytic
C5 - 1µF ceramic disk
Miscellaneous:
DIS1, DIS2 - Common-cathode
7-segment display
S1, S2 - Push-to-on switch
Fig. 4: Actual-size, single-sided PCB layout for uid-level controller with indicator

ELECTRONICS PROJECTS Vol. 22 85


Fig. 5: Component layout of PCB
This function is realised by IC5 that can
operate a pump (or an alarm, or a ow
valve, or a heater, as required) according
to this control logic. For this, the input
lines of IC5 are set to appropriate logic
levels, which must not be disturbed.
Sensor. To control the uid level (say,
Readers’ comments:
Q1. Please explain the detailed working
of the circuit. Also elaborate as to how to
arrange the LDR and lament lamp in the
tank? Please give details, how water level
will be controlled by LDR? Is there any
re ection of light from water surface?
Ajit
Through email
A1. EFY: The optical sensor section (LDR
and lament lamp) can be xed rigidly on
the bottom side of the tank lid/cover using
M-seal or Fevi Quick or similar compound.
Alternatively, you may mount them on a
wooden strip and secure the strip to the
86 ELECTRONICS PROJECTS Vol. 22
water level in a tank), an optical sensor as
shown in Fig. 2 may be used. This optical
sensor consists of a small lament lamp
(generally used in torch or an IR LED as
light source) and an LDR or a photodiode
as the sensor. The lament lamp may
be powered using the same step-down
bottom side of the tank cover. The work-
ing of the LDR to control the water level is
explained below.
The light rays from the lamp are re-
ected from the water surface and fall on
LDR1. The orientation and the intensity
of light source are the deciding factors for
incidence of adequate re ected light on the
LDR for proper control of water level control.
No direct light should be allowed to fall
on the LDR. Fix a suitable opaque screen
closer to LDR, between the light source and
the LDR.
For any given orientation of the light
source and the position of the LDR, the
transformer that is used to power the cir-
cuit. Alternatively, a separate step-down
transformer may be used for the purpose,
but taking into account the voltage and
current ratings of the lamp.
One may also use the sensor described
in ‘Digital Water Level Meter’ in Circuit
Ideas section of the February 2000 issue of
EFY (also in Electronics Projects Vol. 21).
Use that sensor (VR4) as part of a voltage
divider network as shown in Fig. 3. If the
circuit is used as a temperature controller,
a temperature sensor using the popular
LM35 IC may be built (refer Circuit Ideas
published in March 1993 issue of EFY or
Electronics Projects Vol. 14).
Operation. The lower or the mini-
mum level is set by pressing switch S2 and
the upper or the maximum level by press-
ing switch S1. The two switches should
be kept pressed until the required level is
displayed. For example, if the lower level
is selected 1 and the upper level 3, the
pump (or heater or a ow valve) will start
when the uid falls below level 1 and will
stop when the uid reaches level 3.
Assembly and testing. The circuit
may be built on a veroboard. However,
an actual-size, single-sided PCB and its
component layout are shown in Figs 4 and
5, respectively. Switches used, should be of
good quality. After assembling, the circuit
may be tested using a voltage divider (po-
tentiometer) that could be varied between
ground and positive supply.
While testing, set preset VR1 to in-
crease or decrease the reference voltage
taking into account the maximum output
available from the actual sensor. In case
of power failure, there should be proper
battery back-up. Otherwise, the system
will not behave as desired. Red and green
LEDs are arranged in alternate fashion to
make the bar display look attractive. ฀
reflected light intensity received by
the LDR will be low when the water level
is low and it will increase as the water
level in the tank rises. (The intensity at
the LDR depends on the total length of
the path travelled by light.) Thus the re-
sistance of LDR is high when the level of
water is low and its resistance decreases
as the water level increases. The intensity
of light is indicated by the LEDs and
7-segment display in Fig. 1. of the article.
VR2 (preset) is used to vary the sensitivity
of LDR1 so as to obtain a predetermined
LED/7-segment display when a speci ed
level is reached.
 MGMA—A MIGHTY GADGET
WITH MULTIPLE APPLICATIONS
A. JEYABAL

M
GMA, pronounced as migma, is Fig. 1 shows the block diagram of tor C1, and potmeter VR1 form the oscillator
a versatile and multi-purpose the MGMA circuit. Block 1 is an oscil- circuit. Let us presume that capacitor C1 is in
gadget. It can be used for a lator that is controlled by block 2. Block discharged state and pin 2 of gate N1 is in high
range of applications, from a simple toy 2 contains another oscillator whose fre- state. As the input pin is low, output pin 3 is
to domestic and workbench applications. quency is much lower than that of the high and capacitor C1 starts charging through
It measures time, compares light output, former. The differentiator circuit in block potmeter VR1.
temperature, resistance and capacitance, 3 resets the decade counters periodically. When the voltage across capacitor
etc. You can use this gadget in a number Blocks 4 and 5 count the pulses, which, C1 reaches above half of the supply
of ways, depending on your imagination in turn, are displayed by blocks 6 and voltage, input pin 1 of gate N1 goes high
and creativity. 7. Digit 9 in tens counter is decoded and output pin 3 goes low. Now capaci-
Basically, MGMA is a resistance- by block 8, and its output disables the
capacitance-controlled oscillator that counting process and triggers the aural
counts the pulses for a speci c period. If indicator in block 9. Block 10 comprises PARTS LIST
any transducer, such as light-dependent the regulated power supply to run the Semiconductors:
resistor (LDR) or heat-dependent resis- gadget. IC1 - CD4093 quad 2-input Sch-
tor (thermistor), is connected to it, the mitt trigger NAND gate
IC2, IC3 - CD4033 decade counter/
display shows the value corresponding to 7-segment decoder
its resistance. Contact or break (normally Circuit IC4 - 7805 +5V regulator
open or closed) type transducers can also Oscillator. In Fig. 2, Schmitt trigger input T1 - BC557 pnp transistor
be used with MGMA. NAND gate N1 of IC1 (CD4093), capaci- T2 - SL100 npn transistor
D1-D7 - 1N4148 switching diode
D8, D9 - 1N4001 recti er diode
LED1 - Red LED
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise)
R1, R6-R9 - 100-kilo-ohm
R2 - 220-kilo-ohm
R3 - 470-kilo-ohm
R4 - 3.3-kilo-ohm
R5, R10, R11 - 330-ohm
VR1 - 1mega-ohm pot., linear
VR2 - 47-kilo-ohm pot., linear
Capacitors:
C1, C3 - 0.001µF ceramic disk
C2 - 4.7µF, 10V tantalum
C4 - 1000µF, 25V electrolytic
C5, C6 - 0.1µF ceramic disk
Miscellaneous:
X1 - 230V AC primary to 9-0-9V
AC, 100mA secondary trans-
former
S1, S2 - Push-to-on switch
S3 - SPST switch, 230V AC
DIS1, DIS2 - LT543 7-segment, common-
cathode type LED display
SOC1 - SOC4 - Earphone socket
SOC5 - DC IN socket
PZ1 - Piezo-buzzer
- IC bases, knobs, mains
chord, cabinet
- Banana-type earphone plugs
Fig. 1: Block diagram of the MGMA circuit

ELECTRONICS PROJECTS Vol. 22 87

Fig. 2: Schematic diagram of MGMA

tor C1 discharges through potmeter pulses through R1 when switch S1 is held low. So on reset, only DIS1 (unit
VR1. When the voltage across capacitor pressed. digit) will show zero as RBI pin 3 of
C1 falls below half of the supply voltage, Counter and display. The output of IC3 is grounded.
pin 1 of gate N1 goes low and the output the oscillator is connected to clock input Switch S2 is provided to reset the
pin goes high. Now capacitor C1 starts pin 1 of IC2 (CD4033, a decade counter counter manually. Current-limiting
charging again and the cycle repeats for unit digits). The carry-out pin 5 of IC2 resistors R5 and R10 provided with
DIS2 and DIS1, respectively, are used
itself. is connected to the clock input of decade
to reduce the component count and
The pulses from the output of gate counter IC3 that is meant for ten’s digits. ensure the proper operation of digit-9
N1 reach counter IC2 through resistor The segment outputs of both IC2 and decoder circuit.
R1. Switch S1 is provided to stop the IC3 go to the respective seven segments Display controller and differ-
counting manually by grounding the of DIS1 and DIS2 (LT543) for displaying en-tiator. For accurate reading of the
the number of pulses. counter, it must be reset periodically
TABLE Lamp-test (LT) pin 14 of and the pulses must be counted
Count Decoded output of IC CD4033 both IC2 and IC3 is grounded for a speci c period. For this an
a b c d e f g CO through 100-kilo-ohm resistor oscillator circuit comprising gate
0 1 1 1 1 1 1 0 1 R8. The test-point (TP) may N2, diodes D1 and D2, resistor R2,
1 0 1 1 0 0 0 0 1
potmeter VR2, and capacitor C2 is
be used to check the display.
2 1 1 0 1 1 0 1 1
used. This oscillator also works like
When a high-level voltage (5V) the previous one, but its charging
3 1 1 1 1 0 0 1 1 is applied to the test-point, all and discharging paths are separated
4 0 1 1 0 0 1 1 1 segment outputs go high and by diodes D1 and D2. Its ‘on’ time
5 1 0 1 1 0 1 1 0 the display shows 88. (high-level output) can be controlled
6 1 0 1 1 1 1 1 0 by potmeter VR2.
The display is blanked out
7 1 1 1 0 0 0 0 0 When output pin 4 of gate N2 goes
when the number to be dis-
8 1 1 1 1 1 1 1 0
played is 0, provided the ripple from low to high state, the differentiator
9 1 1 1 1 0 1 1 0
blanking input (RBI) pin 3 is circuit comprising capacitor C3 and resis-

88 ELECTRONICS PROJECTS Vol. 22

tor R9 produces a sharp pulse that resets
counters IC2 and IC3. At the same time,
gate N1 is enabled as output pin 4 of gate
N2 is connected to input pin 2 of gate N1,
Fig. 3: Actual-size, single-sided PCB pattern suggested for
the circuit in Fig. 2
Fig. 4: Component layout for the PCB
and it outputs clock pulses. These
pulses are counted by IC2 and IC3
and displayed on DIS1 and DIS2,
respectively. So the oscillator around
gate N1 is enabled and
disabled during the high
and low states, respec-
tively, of the output of
gate N2.
The counters retain
their last count for read-
ing until the output goes
high once again. This
reading time is about 2
to 3 seconds, which is
set by resistor R2. Any
increase in the value of
R2 will increase the read-
ing time and vice versa.
Resistor R3 connected in
parallel across capacitor
C3 is used to discharge
it quickly and diode D3
is used to block the DC
voltage (when switch S2 is
pressed) going to gates N1
and N3, and other parts of
the circuit.
Digit 9 decoder and
aural indicator. It is
very useful to sound an
alarm for a certain read-
ing or otherwise, say, for a
particular temperature or
light output or resistance
value, etc. A permanent
number 90 is chosen for
simplicity of the decoding
circuit. When the display
shows 90, the counter must
be disabled and the buzzer
enabled.
From the table of de-
coded outputs of IC 4033 it
is found that for number 9,
at least one of the segment
outputs is low (a, b and f
are high, while e is low).
For number 8, segment e
is inverted by transistor
T2. As RBI pin 3 of IC3 is
grounded, all the segment
outputs go low for 0. The
clock-enable (CE) pin 2 of
IC3 is pulled up by resis-
tor R7.
Pin 2 is also connected to
a, b, f and e segment outputs of
IC3 through diodes D5, D6, D7,
and transistor T2, respectively,
that altogether act as AND
gate and bring the CE pin to ground for
numbers 0 through 8. When the number
is 9, the segment outputs a, b, and e are
high, except the segment output e, which
is inverted by transistor T2. As a result,
CE pin of IC2 goes high and the counters
are disabled.
Simultaneously, this high-level out-
put is inverted by gates N3 and N4. The
inverted output from gate N4 forward
biases transistor T1 to drive the piezo-
buzzer, while the inverted output from
gate N3 grounds the resetting pulses.
Diode D4 prevents the high output of
N3 from reaching the reset pins of IC2
and IC3.
Power supply. In 5V DC power sup-
ply shown at the bottom in Fig. 2, IC 7805
(IC4) is employed for better regulation. DC
input/output socket (SOC5) is provided to
operate the gadget with external 9V bat-
tery. LED1 acts as a power-on indicator.
Construction
Figs 3 and 4 show suggested actual-size,
single-sided PCB layout and component
layout, respectively, for the circuit in Fig.
2. Solder the components in the order of IC
sockets, jumpers, resistors, capacitors, di-
odes, LED, and transistors. Then connect
the rest of the components through wires.
Fig. 5 shows the proposed front-panel
layout of MGMA.
Before connecting VR1 and VR2 to
the PCB, mark the dials using a digital
multimeter. Both dial 1 and dial 2 (refer
Fig. 5) are calibrated in terms of resist-
ance for the variable resistance values of
1 mega-ohm in case of VR1 and 47 kilo-
ohm in case of VR2, respectively, using a
digital multimeter. (Note. There may be
dead-ends on both ends of the potmeter,
and it may vary in construction from
manufacturer to manufacturer.) Mark the
dials for every ten units for easy reading
and setting.
Applications
For high-resistance and low-resistance
transducers, use earphone-type sock-
ets SOC1 and SOC3, respectively. For
low-capacitance and high-capacitance
testing, use earphone-type sockets SOC2
and SOC4, respectively. For SOC1 and
SOC2, the reading will decrease for
the increasing value of resistance and
capacitance, and vice versa for SOC3
and SOC4.
Strength-0-meter. This game re-
ELECTRONICS PROJECTS Vol. 22 89

Fig. 5: Proposed front-panel layout of MGMA
Fig. 6: Connections for water level monitor
quires two small rods or prods. Connect
them to an earphone plug using a pair of
wires half a metre long. Then insert the
plug into SOC1. Hold the rods in each
hand between forefinger and thumb.
Adjust dials 1 and 2 such that the buzzer
beeps. Then rotate dial 1 slightly in the
anti-clockwise direction to read around 70,
a point where the buzzer is silent. Now ask
your friends one by one to grip the rods
rmly. The winner is the one who sounds
the buzzer or scores higher on the meter.
This depends on how hard one holds the
rod, the internal resistance of the body,
and dampness of the ngers.
Plant tender. You can use MGMA
to indicate the time of watering in order
to avoid excessive watering of plants. For
this, insert two metal strips on both sides
of the plant. Connect them to an earphone
plug using wires and insert the plug into
socket SOC3. Since soil-resistance in-
creases with loss of water, the alarm can
be set/activated for a speci c moisture
level. Adjust dials 1 and 2 such that the
buzzer sounds when the plant needs to be
watered. The buzzer stops in a short while
on sprinkling water over the soil support-
ing the plant. The next time the buzzer
will sound automatically when the plant
needs to be watered.
90 ELECTRONICS PROJECTS Vol. 22
Game of quick hands. This game
requires an earphone plug with its two
terminals shorted. Inserting this plug into
SOC4 grounds input pins 5 and 6 of Sch-
mitt NAND gate N2 via the shorted plug
in SOC4. Since output pin 4 is always in
high state, its periodic action of disabling
gate N1 is no longer there.
Connect a 0.1µF capacitor to SOC2 us-
ing an earphone plug. Since its capacitance
value is higher than that of capacitor C1,
the frequency of the oscillator decreases.
The display shows a reading on momen-
tarily pressing start/reset button
S2 and then quickly depressing stop
button S1. Adjust the dial to read 50
in the display. Now tell your friends
to press button S2 momentarily and
then S1. One who scores less is more
quicker than the others, and hence
the winner.
Water-level monitoring. Five
resistors R12 through R16 are con-
nected in series and the junctions of
the resistors are extended to the ve
levels of the water tank using wires
(refer Fig. 6). A reference rod is also
tted with its lower end just below
level 1.
Plug-in a dummy resistor of
100k into SOC1 and rotate dial 1 to
the zero-resistance position. Adjust dial 2
to read 55 in the display. Cover the unit
digit with an opaque tape, so that only
the ten’s digit is visible. Now remove the
dummy resistor. Connect the other end
of ve-resistor ladder and the reference
probe to SOC1. The display will show the
water levels from one- fth to ve- fth of
the tank, depending on the actual level
at that time.
Measuring resistance. The idea is
simple. First, VR1 (dial 1) is excluded from
the circuit by rotating it to zero reading.
Then an unknown resistor is connected
to SOC1 and dial 2 is adjusted to read a
number just below 90. Now VR1 (dial 1) is
reinstated and rotated to display the same
reading. As dial 1 is marked for resistance
values, the position of dial 1 indicates the
value of unknown resistor.
With MGMA, up to 2-mega-ohm
resistor can be measured. Connect
the unknown resistor to SOC1 us-
ing crocodile clips. Rotate dial 1 to
the zero-resistance position without
touching the resistor, otherwise your
body resistance will get included in
the measurement. Adjust dial 2 such
that the display reads around 90. The
resistor is open if the display shows
0, and shorted if you’re unable to set the
reading near 90.
Remove the unknown resistor. With-
out disturbing dial 2, slowly rotate dial 1
to get the same reading. Now dial 1 shows
the value of unknown resistor.
If the resistor value is less than 40k,
use SOC3 and repeat the same procedure
with dial 2 instead of dial 1 for accurate
measurement. The resistance value can be
read from dial 2.
Checking and measuing capaci-
tance. Using MGMA you can measure
capacitances from 0.001 µF to 5 µF. First
check for the usability of the unknown
capacitor. Adjust dials 1 and 2 to read 50
in the display. Now check the unknown ca-
pacitor using SOC2 for unipolar or SOC4
for electrolytic/tantalum capacitors with
the inner and the outer terminals of the
socket for positive and negative terminals
of the capacitor. If there is no change
in the reading it means the capacitor is
shorted and a higher reading implies it
is good.
To nd the value of an unknown non-
electrolytic (unipolar) capacitor, connect
the same to SOC2. Adjust dials 1 and 2 to
read a number around 80 in the display.
Now, without disturbing the dials insert
the known capacitors one by one in SOC2.
The unknown capacitor value is equal to
the value of the known capacitor for which
the display shows the same reading or
near the number 80.
The procedure is same for electro-
lytic and tantalum capacitors, except
that SOC4 is to be used in place of SOC2,
ensuring that the inner and the outer ter-
minals of the socket are used for positive
and negative terminals of the capacitor,
respectively.
Testing a diode. Rotate dial 1 to
high-resistance position and adjust dial
2 such that the display shows a ickering
45. Test the diode in SOC3 using an ear-
phone plug in the same manner as men-
tioned earlier. Interchange the leads and
test again. A shorted diode will not make
any change in the reading, while a good
one gives a reading of around 60 and 90 in
both the tests. And for the open diode, the
display shows 90 in both the tests.
While checking the diodes, a parallel
resistance of 100k is required across the
diode. Our body resistance may also do.
Other utilities. Heat alarm, fire
alarm, security alarm, strain gauge, in-
truder alarm, rain alarm, number game,
timer, and many other circuits can be real-
ised using this MGMA circuit. ฀
 TRAFFIC AND STREET
LIGHT CONTROLLER
RAJESH GUPTA

his circuit of an adjustable traf c

T
signal for streetlight operation. Its opera- light modes (Part I) controls the switch-
and street light controller can con- tion does not require any software and ing time of streetlights in evenings and
trol the timings of four sides of hardware knowledge. mornings and the time to changeover from
traf c lights separately. It can also control This circuit can also be adopted for
the changeover from continuous traf c synchronisation with the signals of ad- PARTS LIST
light mode to blinking yellow light mode jacent traf c lights by introduction of Semiconductors:
(at night), and from blinking yellow light appropriate delay in traf c light signals IC1 - LM358 op-amp
mode to continuous traf c light mode timings. IC2 - 7404 Hex inverters
IC3, IC6, IC12 - NE555 timer
(during day). In addition, this circuit also IC4 - 74LS93 4-bit binary coun-
controls the automatic switching off/on ter
of the streetlights in the mornings and The circuit IC5 - 74LS164 8-bit serial shift
evenings with exible settings de ning The circuit has two parts the rst for register
IC7-IC9 - 7476 dual JK master-slave
the morning and evening time. In order generation of control signals for streetlight ip- op
to prevent false triggering of streetlight and traf c light modes and the second IC10 - 7400 Quad 2-input NAND
circuitry due to some shadow or light on for generation of four sides of traf c light gates
IC11 - 7410 Triple 3-input NAND
the sensor, some time delay is taken into signals. gates
consideration before sending the control The circuit for streetlight and traf c IC13 - 7408 Quad 2-input AND
gates
IC14-IC17 - 7402 Quad 2-input NOR
gates
T1-T6 - SL100 npn transistor
D1-D14 - 1N4007 recti er diode
LED1, LED3,
LED6, LED9,
LED12 - 3mm red LED
LED2, LED5,
LED8, LED11 - 3mm green LED
LED4, LED7,
LED10, LED13 - 3mm yellow LED
Resistors (all ¼-watt, 5% carbon, unless
stated otherwise):
R1, R2,
R18-R21 - 2.2-kilo-ohm
R3-R5, R8,
R12-R17,
R22-R25 - 100-kilo-ohm
R6 - 47-kilo-ohm
R7, R9, R11 - 10-kilo-ohm
R10 - 100-ohm
R26 - 47-ohm
R27 - 22-kilo-ohm
R28 - 6.8-kilo-ohm
VR1, VR2,
VR4-VR7 - 1-mega-ohm preset
VR3 - 100-kilo-ohm preset
VR8 - 10-kilo-ohm preset
Capacitors:
C1 - 220µ, 10V electrolytic
C2, C4, C6 - 0.01µ ceramic
C3, C5 - 6.8µ, 10V electrolytic
Miscellaneous:
LDR1
Fig. 1: Block diagram of traf c and street light controller S1 - Push-to-on switch

ELECTRONICS PROJECTS Vol. 22 91

Fig. 2: Schematic diagram for the traf c and street light controller

92 ELECTRONICS PROJECTS Vol. 22

continuous traf c light mode to blinking
yellow light mode (at night), and from
blinking yellow light mode to continuous
traf c light mode (in daytime). Thus it
decides the mode of operation.
The circuit for four sides of traf c
lights (Part II) also controls the time al-
lowed for each side of traf c. It is further
classified into continuous traffic light
mode (for day) and blinking yellow light
mode (for night).
Part I Circuit. The block diagram of
the circuit for signal generation for street-
light and traf c light modes is shown
above the dotted line in Fig. 1. A natural
light-dependent voltage and a reference
voltage, which determines the evening and
morning times are connected individually
to the two inputs of a comparator. Low
and high states of the comparator output
decide morning and evening timings,
respectively. The output of comparator is
properly delayed for obtaining the signals
for streetlight and traf c light modes.
In the detailed circuit diagram shown
above the dotted line in Fig. 2, a natural
light-dependent voltage is obtained at the
junction of light-dependent resistor LDR1
and resistor R7. Resistor R6 is used in
parallel with LDR1 to limit the variation
of the LDR. Light-dependent voltage and
variable reference voltage are connected to
the inverting and non-inverting terminals
respectively of comparator IC1(a).
In the evening, voltage at the invert-
ing terminal of the comparator decreases
with time due to the increasing resist-
ance of LDR1. At a particular natural
light intensity (determined by variable
reference voltage, which can be adjusted
with the help of preset VR8), it becomes
less than the voltage at the non-inverting
terminal. This drives the comparator into
positive saturation region. Similarly, in
the morning the comparator goes into
negative saturation region at the same
natural light intensity. In this way, the
comparator gives high voltage (logic 1)
for evening and low voltage (logic 0) for
morning.
IC1(b), with the non-inverting ter-
minal biased at about 1/3rd Vcc, is simply
used as an inverter (though wired as
comparator). The inverted output of
comparator IC1(a) is coupled to transistor
T1 through resistor R4, while its direct
output is coupled to transistor T2 via
resistor R5.
It is observed that transistor T1 is
cut off in the evening and Vcc is applied
to pin 7 of timer IC3 (wired in astable
multivibrator mode) via resistor combi-
nation RA1 (=R2+R3+VR1), while in the
morning T2 is cut off and Vcc is applied
to pin 7 of IC3 via RA2 (=R1+R8+VR2).
In other words, the time period of IC3 is
dependent on RA1 from the evening and
RA2 from the morning.
The diode pair of D1 and D2 or D4
and D5 is used to effectively isolate pin 7
of IC3 from being pulled towards ground
via the conducting transistor (T2 in the
evening and T1 in the morning). Time
period of 555 clock in astable mode can
be determined from the following rela-
tionship:
T = RA (C/1.44) + 2 RB (C/1.44)
where RA = RA1 from the evening and
RA = RA2 from the morning, while RB
= R9 = 10 kilo-ohm and C = C1 = 220
µF. Clock-1 output of IC3 is connected
to 4-bit negative-edge-triggered counter
74LS93 (IC4).
Period of output QD of IC4 is 16 times
the clock-1 time period. This QD output
(low for rst eight clock-1 cycles and high
for the next eight clock-1 cycles, and re-
peating thereafter) of IC4 is connected to
the clock input of an 8-bit (positive-edge-
triggered) serial shift register 74LS164
(IC5).
The output of IC1(a) forms the data
(D) input for the shift register. The data
(D) at QA output is available after eight
clock-1 cycles, while that at QH is avail-
able after 120 clock-1 cycles. Thus morn-
ing/evening (low/high) data is available at
QA and QH outputs after 8 and 120 clock-1
cycles, respectively. Note that the clock-1
period itself differs for morning data and
evening data.
Streetlight indicator (LED1) is con-
nected to QA output of shift register IC5.
TABLE I
Functional Summary of Part I Circuit
Time Output Output at Output at Activated RA Street Traf c
of IC1(a) QA of IC5 QH of IC5 Resistance Light Light
Evening HIGH LOW
After 8 cycles of clock-1 HIGH HIGH
(Delay time for streetlight)
After 120 cycles of clock-1 HIGH HIGH
(Delay time for night)
Morning LOW HIGH
After 8 cycles of clock-1 LOW LOW
(Delay time for streetlight)
After 120 cycles of clock-1 LOW LOW
(Delay time for day)
Evening HIGH LOW
Delay times and evening/morning times are adjustable.
A: Continuous traf c light mode B: Blinking yellow light mode
The evening data (high) from comparator
IC1(a) passes to the streetlight after eight
clock cycles of clock-1. This delay is taken
into consideration in order to prevent
false signals to the streetlight due to some
shadow or light on the sensor.
The delayed high QH output provides
the control signal for night to the second
part of circuit and changes continuous
traf c light mode to blinking yellow light
mode. In this way the time at which night
functioning of traf c light starts can be
adjusted by choosing appropriate time
period for clock-1 by adjusting the value
of RA1. Similarly, the time at which day
functioning of traf c light starts (stop
blinking yellow light mode and start
continuous traf c light mode) can be
adjusted by RA2.
Low (delayed morning signal) and
high (delayed evening signal) QH outputs
go to the second part of circuit for se-
lecting the mode of traf c light. Table I
summarises the functioning of the circuit
for signal generation for streetlight and
traf c light modes.
Part II Circuit. The block diagram
of the circuit for signal generation for
four sides of traf c lights is given below
the dotted line in Fig. 1. Here, the 4-bit
and 2-bit counters are joined together to
form a 6-bit counter. Outputs of the 2-bit
counter, representing two MSB digits, are
connected to a decoder that has two con-
trol inputs and four outputs. The decoder
activates one of the four outputs depend-
ing upon the input (00 or 01 or 10 or 11)
of 2-bit counter.
Each output of the decoder can drive
clock-2 at a different frequency. These four
outputs are connected to the four sides of
traf c lights and select each side one after
(LED1) Mode
LOW RA1 OFF A
LOW RA1 ON A
HIGH RA1 ON B
HIGH RA2 ON B
HIGH RA2 OFF B
LOW RA2 OFF A
LOW RA1 OFF A
ELECTRONICS PROJECTS Vol. 22 93
Fig. 3: Actual-size, single-sided PCB for the circuit in Fig. 2

Fig. 4: Component layout for the PCB

94 ELECTRONICS PROJECTS Vol. 22

another. The time in which the preceding
4-bit counter counts from 0000 to 1111
(16 counts) is the time allowed for each
side of traf c lights.
First, when the 4-bit counter counts
from 0000 to 0001 (two counts), yellow
light of the selected side will turn ‘on’.
From count 0010 to 1101 (12 counts),
green light will turn ‘on’. Again from
1110 to 1111 count (two counts), yellow
light will turn ‘on’. Meanwhile, in the
other three sides of traf c lights that are
Fig. 5: Connections for vehicular traf c lights and pedestrians signals
Fig. 6: The traf c and street light controller
not selected by the decoder, red light will
be ‘on’. Similar operation will repeat for
each of the selected side in its turn.
Reset pin of clock-3 and clear pins of
the 6-bit counter are controlled by output
QH from IC5 of Part I. At night, QH will go
high and the 6-bit counter will clear, while
clock-3 becomes active. As a result, yellow
lights of the four sides of traf c light will
blink simultaneously.
The detailed circuit diagram is
given below the dotted line in Fig. 2. The
active-‘low’, clear input signal for the 6-bit
counter (formed by dual J-K ip- ops
inside IC7 through IC9) is provided
from the output of NOR gate E1, whose
one input is connected to QH output
of shift register IC5 of Part I and the
other input is connected to the output of
inverter gate N3. The input of inverter
gate N3 is connected to push-to-on reset
switch S1.
Thus the 6-bit counter will clear when
QH output is high or the reset button is
pressed. The reset key, when pressed, also
causes counter IC4 and shift register IC5
of Part I to be cleared. QH output of IC5 is
connected to reset pin 4 of clock-3 (IC12).
The output of this clock is connected to
inverter gate N4. Low QH (during day)
activates the 6-bit counter and deactivates
clock-3. Due to this, the output of inverter
gate N4 will be high during the day. This
output is connected to one of the inputs of
four AND gates H1 through H4. Each of
these AND gates is a part of one side of
traf c light circuit.
NAND gates B1, B2, and B3 are con-
nected to the outputs of ip- ops F2, F3,
and F4 of the 6-bit counter. The nal
output of this circuit (the output of gate
B2) will be high whenever the rst four
bits of the counter are 1110 or 1111 or
0000 or 0001 (14 or 15 or 0 or 1), otherwise
it will be low. Accordingly, inverter N5
output will be low for the above contents
of the counter and high for the remaining
contents (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
or 13).
The output of NAND gate B2 and its
complement (the output of inverter N5)
are connected to NOR gates X2 (=E2,
J2, K2, and M2) and X3 (=E3, J3, K3,
and M3) of the each side of traf c light,
respectively. Other inputs of X2 and X3
NOR gates are common.
The last two ip- ops (F5 and F6) of
the 6-bit counter are connected to four
NAND gates G1 through G4 in such a way
that the output of G1, G2, G3, and G4 will
be low when last two counter bits are 00
(0), 01 (1), 10 (2) and 11 (3), respectively.
For example, when last two bits of counter
contents are 01 (1), only output of NAND
gate G2 will be low and others (G1, G3 and
G4) will be high.
The complements of these four NAND
gate outputs (obtained from collectors of
transistors T3 through T6) are connected
to the four RA resistors of 555 clock-2.
Other terminals of these four resistors
are connected to the anodes of diodes D8,
D10, D12, and D14, while their cathode
ELECTRONICS PROJECTS Vol. 22 95
 of rst side will depend on the output of
TABLE II
the three-NAND gate circuit (comprising
Daytime Functions of Part II Circuit
gates B1, B2, and B3).
Counter Decoder output Activated RA Glowing LEDs When the 6-bit counter counts from
contents G1 G2 G3 G4 resistance
000000 to 000001, the output of the three-
000000 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and
000001 red light of other sides)
NAND gate circuit will be high, which is
000010 - 0 1 1 1 RA3 2,6,9,12 (Green light of 1st side and connected to NOR gate X2 of each side
001101 red light of other sides) and its complement is connected to NOR
001110 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and gate X3 of all sides. Due to this, the output
001111 red light of other sides) of NOR gate E3 will be high and those of
010000 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and NOR gates E2 and E4 low. In short, dur-
010001 red light of other sides) ing the count period 000000 to 000001
010010 - 1 0 1 1 RA4 3,5,9,12 (Green light of 2nd side and yellow light of the rst side of traf c light
011101 red light of other sides)
and red light of the other three sides will
011110 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and
011111 red light of other sides) be ‘on’.
100000 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and When the counter counts up further
100001 red light of other sides) from 000010 to 001101, the output of the
100010 - 1 1 0 1 RA5 3,6,8,12 (Green light of 3rd side and three-NAND gate circuit will be low and
101101 red light of other sides) its complement will be high. Due to this
101110 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and reason, the output of NOR gate E2 will
101111 red light of other sides) go high and that of NOR gates E3 and
110000 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and E4 low. Therefore, when counter contents
110001 red light of other sides)
increment from 000010 to 001101, green
110010 - 1 1 1 0 RA6 3,6,9,11 (Green light of 4th side and
111101 red light of other sides) light of rst side and red light of all the
111110 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and other sides will be ‘on’.
111111 red light of other sides) Again from 001110 to 001111, the
Note. The two MSB digits determine the side, while the next four digits determine the time for output of three-NAND gate circuit will
which the mentioned LEDs are ‘on’. go high, due to which yellow light of rst
side and red light of the other sides will
terminals are all connected to pin 7 of of NOR gates X3(=E3, J3, K3 and M3) turn ‘on’. The time in which the counter
555 clock-2 (IC6). This is analogous to the of each side, because one of the inputs counts from 000000 to 001111 can be
fashion in which RA1 and RA2 have been of AND gates is high in daytime. Low adjusted by RA3. The functioning of the
connected in Part I in the clock-1 circuit. QH (during daytime) forces NOR gates other three sides of the traf c light is
When last 2-bit counter contents are J1, K1, and M1 to work as the inverter similar.
00, RA3 (=R21+R25+VR7) will become gate for the other inputs. Therefore the Daytime functional summary of the
active and other three resistors RA4, RA5, common input of NOR gates X2 and X3 circuit for signal generation for four sides
and RA6 will become inactive. Therefore of sides 1, 2, 3, and 4 will be the same as of traf c light is given in Table II. Change
the time period of clock-2 of the 6-bit coun- the output of NAND gates G1, G2, G3, in RB resistance (VR3+R11) of clock-2,
ter will be dependent upon RA3. and G4, respectively. being common for all sides, will change
Similarly, when last 2-bit counter con- Let us suppose that initially the the time allowed for each side of traf c
tents are 01 or 10 or 11, the time period contents of the 6-bit counter are 000000. light by an equal amount.
of clock-2 will be dependent upon RA4 When the counter counts up from 000000 At night, QH output of IC5 will be
(=R20+R24+VR6), RA5 (=R19+R13+VR5), to 001111, the output of NAND gate high, due to which the 6-bit counter will
and RA6 (=R18+R12+VR4), respectively. G1 will be low and that of other NAND clear and clock-3 will start working. The
The output of NAND gate G1 is con- gates G2, G3, and G4 high. Due to this, output of NOR gates J1, K1, and M1 and
nected to the common input of NOR gates RA3 will be active and the time period of NAND gate G1, and the complement of
E2 and E3 of the rst side of traf c light clock-2 of the counter will be according the output of the three-NAND gate cir-
and complements of the outputs of other to RA3. cuit will be low. This forces the output of
three NAND gates G2, G3, and G4 are The high output of NAND gates G2, NOR gate X3 of each side to high state.
connected to one of the inputs of NOR G3, and G4 forces the output from NOR This high output will turn off all the red
gates J1, K1, and M1, respectively. The gates J2, K2, M2 and J3, K3, M3 to low lights and give high signal to one of the
other inputs of these NOR gates are con- state. These low outputs are input to inputs of AND gates H1 through H4. The
nected to QH output of IC5. Red and green NOR gates J4, K4, and M4, due to which other input of these AND gates is con-
lights are connected to the outputs of NOR the output of these gates will be high. It nected to the complement of clock-3, due
gates X4 (=E4, J4, K4, and M4) and X2 means yellow and green lights will be ‘off’ to which all the four sides of yellow light
(=E2, J2, K2, and M2), and yellow light is and red light will be ‘on’ in the remaining will blink.
connected to AND gate of each side of the three sides of the traf c light. The four sides of traf c light signals
traf c light. Due to the low output of NAND gate can be used for driving vehicular traf c
During daytime, the outputs of AND G1 (which is connected to the common signals for straight, right, and left turns
gates (which are connected to yellow input of NOR gates E2 and E3 of rst and pedestrian’s signals. Fig. 5 shows
lights) will be the same as the outputs side), the output of NOR gates E2 and E3 one of such possible connections of vehicu-

96 ELECTRONICS PROJECTS Vol. 22

lar and pedestrian’s signals. The complete
circuit in model form is shown in Fig. 6.
Actual-size, single side PCB for the circuit
shown in Fig. 2 is given in Fig. 3 with its
component layout in Fig. 4.
Calibration
Set preset VR8 in such a position that the
output of comparator IC1(a) switches from
one state to the other at a particular in-
tensity of natural light. Variable resistors
VR1 and VR2 can be calibrated on a time
scale using the following relationships:
VR1 = (1/120) (1.44 TNight/220) 106 –
(122.2) 103
VR2 = (1/120) (1.44 TDay/220) 106 –
(122.2) 103
where TDay and TNight are delay times in
seconds (time interval between switching
of comparator IC1(a) and when the traf c
light switches its mode) corresponding to
day and night, respectively.
Variable resistors VR4 through VR7
can be calibrated on a time scale by the
following relationship:
VR (4,5,6,7) = (1/16)(1.44 T/6.8) 106 –
(122.2) 103 – 2 VR3
where T is the time allowed (in seconds)
for the side of traf c light in which the
corresponding variable resistance is con-
nected.
Possible enhancements. Stepper
motor-driven wiper can be used for clean-
ing the dust over the light sensor during
night time. Control signal for this can be
obtained from the shift register.
Also, time-controlling variable resis-
tors VR4 through VR7 of Part II can
be replaced by LDRs with a small light
source whose light intensity varies accord-
ing to the strength of traf c on each side.
Implementation of this system requires
traf c-sensing sensors. This system will
change the time of each side of traf c
light according to the strength of traf c.
Further, the present circuit being
only a demonstration model uses LEDs
for lights. To drive high-wattage lights,
one can easily boost the signals used for
driving the LEDs to operate solidstate or
electomechanical relays.
฀
ELECTRONICS PROJECTS Vol. 22 97
 LEAD-ACID BATTERY
CHARGER WITH ACTIVE
POWER CONTROL
M.K. CHANDRA MOULEESWARAN

igh-power lead-acid battery char- to vary the charging current in accordance

H
gers usually employ constant
voltage charging method. In
such chargers the charging is monitored
against the battery terminal voltage.
Constant voltage at a constant current
results in a very large initial current in
a at battery and a very low current in
a partially charged battery. To overcome
this problem, the charger should be made
with the existing terminal voltage of the
battery.
In the circuit presented here the
charging current is adjusted against the

Fig. 1: Schematic diagram of lead-acid battery charger

98 ELECTRONICS PROJECTS Vol. 22

 terminal voltage in such a way
that any battery with any level
of charge can be connected to the
charger without requiring any
manual adjustment. The charg-
ing voltage is held constant, while
an appropriate charging current
range is automatically selected
at successive different battery
terminal voltages. And when the
battery gets fully charged, the
charger switches over to trickle-
charge mode.
Fig. 2: Charging current versus battery terminal voltage The circuit consists of the
Fig. 3: Actual-size, single-sided PCB for battery charger
Fig. 4: Component layout for the PCB
following sections:
1. The DC power supply section.
2. The series DC voltage regulation
section.
3. The battery status indication-cum-
charge current regulation section.
The DC power supply section. The
230V AC mains supply is connected to
a step-down transformer with a second-
ary rating of 24V AC, 5A through DPDT
toggle switch S1. When switch S1 is
in off position, the availability of
mains supply is indicated by green
LED1. When switch S1 is toggled to on
position, red LED2 glows to indicate
that the charger is on . The four
15-kilo-ohm resistors R1, R2 and
R3, R4 in the path of LED1 and
LED2, respectively, are rated at
1 watt each.
The output from the secondary
of transformer X1 is recti ed by the
bridge recti er comprising 1N5408
diodes D3 through D6, rated at 800V,
3A. The recti ed output is smoothed
by three capacitors C1, C2, and C3
before being applied to the rest of the
circuit. The 4.7-kilo-ohm resistor R6
acts as a bleeder resistance. LED7
indicates that DC is available at the
output of this section.
The series DC voltage regu-
lation section. This section is
con gured around power Darlington
transistor TIP142 (T1) that functions
in conjunction with transistor T3
(BC549) and preset VR2 to regulate
the output voltage from the DC volt-
age regulator section.
Since zener diode ZD1 conducts
only after the output voltage reaches
15 volts, the output voltage needs to
be adjusted in the vicinity of 15 volts
with the help of preset VR2. When
transistor T3 conducts fully, the base
of transistor T1 is pulled towards
ground via resistor R8 and it stops
conducting after the output voltage
exceeds a speci c value.
Transistor T2 (also a BC549)
helps in current limit adjustments.
Low-value, high-wattage resistors
R15 (shunted by R14) through R19
connected in series form a current-
limiting resistor network at the
output of transistor T1. This resistor
network limits the charging cur-
rent depending on the energisation/
de-energisation state of relays RL1
through RL4 that select the cur-
rent range. The resistors are either
ELECTRONICS PROJECTS Vol. 22 99
 PARTS LIST TABLE
Semiconductors: LED/Relay Operation and Charging Resistance
IC1 - LM324 quad op-amp Battery LED/Relay status Charging Preset
T1 - TIP142 power Darlington
transistor voltage LED3 LED4 LED5 LED resistance current
T2, T3 - BC549 npn transistor /RL1 /RL2 /RL3 /RL4
T4-T7 - 2N2222A npn transistor <10.5V Off Off Off Off 1 ohm 1A
D1, D2, 10.5V On Off Off Off 0.33 ohm 3A
D7-D11 - 1N4007 recti er diodes 11.5V On On Off Off 0.53 ohm 2A
D3-D6, D12 - 1N5408 recti er diodes 12.5V On On On Off 1 ohm 1A
LED1 - Green LED 13.5V On On On On 2 ohms 0.5A*
LED2 - Red LED
LED3 - Bright yellow LED * 0.5A is taken as the trickle charging current.
LED4, LED5 - Bright green LED
LED6, LED7 - Bright red LED
ZD1 - 15V, 1W zener diode
shorted or added by respective relay edand left unattended under the control of
ZD2 - 6.8V, 1W zener diode contacts RY1 through RY4 depending on this charger circuit.
Capacitors: the charging current requirement from
C1, C2 - 2200µF, 40V electrolytic the regulator.
C3 - 1000µF, 40V electrolytic
C4 - 470µF, 25V electrolytic The battery status indication-cum- When the battery is at with termi-
C5 - 100nF ceramic charge current regulation section. In nal voltage below 10.5 volts, the initial
Resistors (all ¼-watt, ±5% carbon unless this circuit, a quad op-amp LM324 (IC1) charging current is selected at just one
stated otherwise) ampere because a higher initial charging
R1-R4 - 15-kilo-ohm, 1W is wired as a four-stage comparator to
R5 - 2.2-kilo-ohm indicate the battery voltage with the help current may cripple both the battery and
R6 - 4.7-kilo-ohm, 0.5W of four LEDs (LED3 through LED6), while the charger. A higher charging current is
R7, R10, R12 - 1-kilo-ohm at the same time selecting and driving selected only when the battery has reached
R8 - 100-ohm
R9 - 470-ohm corresponding relays to set the charging a safe level of terminal voltage.
R11 - 4.7-kilo-ohm current range. Later, as the battery starts charging
R13 - 47-ohm The 6.8V reference voltage developed and its terminal voltage starts rising, the
R14-R15 - 0.66-ohm, 3W wirewound or charging current is decreased in proper
fusible across zener diode ZD2 is proportion-
R16 - 0.67-ohm, 3W wirewound or ately applied to the inverting terminals steps. Upon reaching the full voltage of 13.5
fusible of comparators A1 through A4, while the volts, the charger switches to the trickle
R17 - 0.20-ohm, 3W wirewound or charge mode with resistor R19 coming into
fusible
sampled battery voltage is proportionately
R18 - 0.47-ohm, 3W wirewound or applied to the non-inverting terminals of the charging path. Optionally, one can
fusible all the comparators. switch off the charger on energisation of re-
R19 - 1.0-ohm, 1W wirewound Preset VR3 may be adjusted to obtain lay RL4 by just removing resistor R19 from
R20-R23 - 470-ohm, MFR 0.5% or 0.1%
R24 - 820-ohm, MFR 0.5% or 0.1% the reference voltages as shown in Fig. 1. the circuit. Whenever the terminal voltage
R25 - 10-kilo-ohm, MFR 0.5% or Preset VR4 may be adjusted by applying level of the battery goes low, the charger
0.1% an external xed voltage of 10.5V, 11.5V, automatically resumes charging.
R26-R28 - 1.2-kilo-ohm Figs 3 and 4 show the actual-size, sin-
R29 - 1.5-kilo-ohm 12.5V, or 13.5V across the battery s screw
VR1-VR2 - 2.2-kilo-ohm preset terminals, ensuring that the correspond- gle-sided PCB and the component layout,
VR3 - 10-kilo-ohm preset ing LEDs (and relays) light up (energise) respectively, of the charger circuit.
VR4 - 15-kilo-ohm preset in accordance with the table. Note. To ensure proper functioning
Miscellaneous:
RL1-RL4 - 24V DC, 500-ohm relay In the charge characteristic curve of of the circuit, use good-quality relays and
contacts at 10A DC Fig. 2, it can be seen that the terminal precise-value resistors (R14 through R24)
X1 - 230V AC primary to 0-24V, voltage is compared by the comparators with tolerance as mentioned in the Parts
5A secondary transformer List. Connect the metal housing of the
S1 - DPDT toggle switch against the preset values and the charg-
F1 - 750mA cartridge glass fuse ing current is selected accordingly. Thus a charger circuit to the earth line of the AC
battery of any charge level can be connect- mains supply for personal safety. ฀

100 ELECTRONICS PROJECTS Vol. 22

AMPLITUDE MEASUREMENT OF
SUB-MICROSECOND PULSES
ANIL KUMAR MAINI

A
pulse or a repetitive train of
pulses is one of the most fre-
quently encountered electronic
signals, and the conventional way to
determine its peak amplitude is to have
an oscilloscope display of the waveform.
An oscilloscope that has the required
bandwidth to correctly display sub-
microsecond-wide pulses is an expensive
instrument, and is often beyond the reach
of most electronics enthusiasts, hobby-
ists, and small-scale units. The circuit
presented here allows you to measure the
peak amplitude of a single pulse as well
as of a repetitive train of pulses with a
conventional multimeter.
The circuit is capable of measuring
peak amplitude of pulses as narrow as
100 nanoseconds (ns) up to a maximum of
100V amplitude. There is practically no
limit on the maximum value of the pulse
width. It can also be used to measure the
peak amplitude of a repetitive pulsed
waveform as long as the time interval
between two successive pulses is greater
than 100 microseconds (µs).

The circuit
The pulse under measurement is fed to
the input of a cascaded arrangement of
two unity-gain peak detection stages built
around IC1 and IC2 using high-speed
op-amps AD829, as shown in Fig. 1. The
op-amp has a guaranteed unity-gain band-
width of 120 MHz and a slew rate of 230
V/µs, and it is capable of driving highly
capacitive loads. This makes it ideal for
receiving input pulses as narrow as 100
ns. D1 and D2 (1N914) are high-speed
switching diodes having a response time
of the order of 2 ns to 3 ns.
The input pulse gets stretched to
about 10 µs at the output of the rst peak-
detection stage built around IC1 and to
about 100 µs at the output of the second
peak-detection stage built around IC2.
With switch S1 open, the circuit can Fig. 1: Circuit for measuring sub-microsecond pulses

ELECTRONICS PROJECTS Vol. 22 101

 Photograph of author’s prototype

switch causes mum input pulse amplitude of 100 volts,

division of the the ADC analogue input is limited to 5
input voltage
PARTS LIST
by a factor of
Semiconductors:
10 due to the
IC1, IC2 - AD829 op-amp
arrangement IC3 - LM329 comparator
of resistors R1 IC4 - 74121 monostable multivi-
through R3. brator
Fig. 2: Waveforms at various points of the circuit The peak IC5 - AD0808 analogue-to-digital
converter
amplitude of IC6 - DAC0808 digital-to-ana-
receive input pulses greater than 100 mV the stretched pulse at the output of the logue converter
(which is the same as the reference voltage second peak detector is the same as IC7 - LF356 op-amp
set for comparator IC3, LM319) but less the input pulse peak amplitude. This IC8 (N1-N3) - 74HCT04 hex inverter
IC9 (N4-N7) - 7400 NAND gate
than or equal to 10 volts. output amplitude is halved by resistors
D1, D2 - 1N914 high-speed switching
With switch S1 closed, the input pulse R9 and R10 before feeding the same to diode
amplitude may be anywhere between the analogue input of IC5 (ADC-type ZD1 - 2.5V zener diode
1 volt and 100 volts. The closure of the AD0808). This ensures that for the maxi- Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1, R2 - 18-kilo-ohm
R3, R16 - 1-kilo-ohm
R4 - 12-kilo-ohm
R5, R6 - 22-kilo-ohm
R7, R8 - 15-kilo-ohm
R9-R12 - 100-kilo-ohm
R13 - 470-ohm
R14 - 220-kilo-ohm
R15, R18, R19,
R24, R25 - 10-kilo-ohm
R17 - 2.2-kilo-ohm
R20, R21 - 2.7-kilo-ohm
R22 - 4.7-kilo-ohm
R23 - 33-kilo-ohm
VR1 - 50-kilo-ohm preset
Capacitors:
C1, C2, C4, C5,
C7-C9, C11-C17
C19 - 0.1µF ceramic disk
C3, C10 - 0.001µF ceramic disk
C6 - 0.01µF ceramic disk
C18 - 56 pF ceramic disk
Miscellaneous:
S1, S2 - On/off switch (SPST)
Meter - Multimeter
Fig. 3: Actual-size, single-side PCB layout for the circuit

102 ELECTRONICS PROJECTS Vol. 22


Fig. 4: Component layout for the PCB
volts, which is the maximum amplitude
it can accept.
The output of the rst peak detector
stage after a division by a factor of 2 by
the arrangement of resistors R11 and
R12 feeds comparator LM319 (IC3). The
leading edge of the pulse output from the
comparator coincides with the leading
edge of the input pulse. The leading-edge
comparator output triggers monoshot
74121 (IC4) to produce a 1µs pulse (as
determined by timing components R-
7-C10) at its Q-output, with its leading
edge coinciding with the leading edge of
the input pulse.
The monoshot output is passed
through an appropriate NAND gate
logic circuit built around 7400 (IC9) and
it acts as the start-of-conversion pulse
for analogue-to-digital converter IC5
(ADC0808). The NAND logic is used here
to incorporate the reset feature.
The clock generator circuit for IC5
is built around 74HCT04 (IC8) to pro-
vide 1MHz clock. The clock frequency
is decided by R24, R25, and C18. The
latched digital output from IC5 feeds the
corresponding inputs of DAC0808 (IC6).
The DAC output, which is a latched DC
current, is converted into a proportional
voltage in the current-to-voltage circuit
built around op-amp LF356 (IC7). This DC
voltage is connected to the multimeter for
indication of peak amplitude of the input
pulse to the circuit. Potentiometer VR1 is
meant for calibration.
Operation
Every time there is a pulse at the input,
there is a stretched pulse appearing at the
analogue input of the ADC, with its lead-
ing edge coinciding with the leading edge
of the input pulse. Fig. 2 shows waveforms
available at various test points marked A,
B, C, D, and E in the circuit shown in Fig.
1. Also, there is a start-of-conversion pulse
appearing at the relevant input of the
ADC. The conversion starts at the trailing
edge (test point E) of this pulse 1 µs after
the leading edge of the input pulse.
Since the stretched pulse is about
100µs wide, the peak amplitude of the
pulse 1 µs later is almost the same as the
actual peak amplitude. At the same time,
this small delay ensures that the analogue
input is already present on the relevant
input at the start of conversion.
The latched digital output from the
ADC feeds the corresponding inputs of
the DAC0808 (IC6) as stated earlier. The
output of the DAC, after conversion into
the proportional voltage by LF356 (IC7),
is fed to the multimeter (set to appropri-
ate DC voltage scale) for measurement of
peak pulse amplitude. Potentiometer VR1
is used for calibration.
The display holds the peak amplitude
of the last pulse until it is reset using
switch S2 or it is updated by another
pulse at the input. The accompanying
photograph shows the assembled circuit
that the author used for performance
evaluation.
An actual-size, single-side PCB for the
circuit is shown in Fig. 3 and its component
layout in Fig. 4. ฀
ELECTRONICS PROJECTS Vol. 22 103
 AUTOMATIC SUBMERSIBLE
PUMP CONTROLLER
A
number of construction projects as
well as circuit ideas for water-/
uid-level control have appeared
in EFY over the years, but so far no dedi-
cated project has appeared for automating
the control of submersible water pumps.
Looking into the demand for such a project
from readers, we present here a circuit for
Fig. 1: Line diagram of control panel for manual operation of ESP motor
automating the operation of an electrical
submersible pump (ESP) based on the
minimum and the maximum levels in the
overhead tank (OHT). This circuit can be
interfaced to the existing manual control
panel of an ESP and can also be used as a
standalone system after minor additions.
ESP basics
Electrical submersible pumps are single-
or multiple-stage radial- ow pressure se-
ries impeller pumps that are close coupled
to the motor for low and medium heads.
These nd applications in domestic, in-
dustrial, irrigation, air-conditioning, and
various other systems.
The ESPs are classi ed by the bore
diameter (which generally varies from
100 mm to 200 mm), horse-power (from
about 0.5 HP to 40 HP), and discharge rate
(typically 120 litres per minute for 0.5 HP
to about 2000 litres per minute for 40 HP).
These are run at a xed speed, which is
104 ELECTRONICS PROJECTS Vol. 22
K.C. BHASIN
2850 rpm typically. the run capacitor value can be calculated
The ESP body is made of cast iron using the simple thumb rule (70 µF per
or stainless steel. For low and medium HP), while the start capacitor value may
range, one can use 3-phase or split-phase be determined from Table I.
(also referred to as 2-phase) supply. ESPs Manual operation of ESP motor
of 3 HP or higher rating invariably use (Fig. 1). The control panel comprises an
3-phase supply. isolator switch, push-to-on single-/dual-
Let us consider a typical case of 1.5HP section ‘start’ button, push-to-off ‘stop’
button, a triple-pole moulded case circuit
breaker (MCCB) for motor protection with
magnetic trip and resetting facility (with
an adjustable current range of 12 to 25 am-
peres), start and run capacitors, ampere-
meter, voltmeter, neon indicators, etc.
(Note. The MCCBs used for motor con-
trol are termed as motor circuit protectors
(MCPs). These are classi ed/catalogued
by number of poles, continuous ampere rat-
ing, and magnetic trip range (current). For
details, you may visit Cutler-Hammer’s
Website or contact Bhartia Cuttler-Ham-
mer dealers.)
Fig. 1 shows a simpli ed control panel
diagram, along with ESP motor wiring.
The ‘start’ pushbutton (green), which is
ESP with 100mm bore diameter, using normally open, and the ‘stop’ pushbutton
a split-phase motor. The motor draws a (red), which is normally closed, are in
running current of 10 to 11 amp, while
Motor rating Start capacitor value (µF)
the starting current is around 2.5 to three in HP 230V AC (working)
times the running current value. 275V AC (surge)
To obtain a higher initial torque, the 1/6 20-25
run winding is connected in series with a 1/5 30-40
parallel combination of 120-150µF, 230V 1/4 40-60
AC bipolar paper electrolytic capacitor 1/3 60-80
and 72µF, 440V AC run-mode capacitor.
1/2
3/4
80-100
100-120
After two or three seconds of running, 1 120-150
when the motor has picked up suf cient 1½ 150-200
speed, the start capacitor goes out of the 2 200-250
circuit because of the opening
of the centrifugal switch in- TRUTH TABLE FOR RELAY OPERATION
side the motor, while the run Water level Relay operation (2.5 – 3 sec.) Pump motor
capacitor stays in the circuit in tank RL1 (stop) RL2 (Start) operation
permanently. For ESPs that Below
don’t have an integral cen- low level No Yes Starts
trifugal switch arrangement, Above
a dual-section start switch low level
(explained later) can be used but below
high level No No Remains on
to perform the function of the
Reaches
centrifugal switch.
high level Yes No Stops
For the split-phase motor,
Fig. 2: Circuit diagram for automatic control of ESP motor via control panel (Fig. 1)
series with the live or phase line.
The isolator switch is normally in ‘on’
position. When ‘start’ button is momentar-
ily pressed, the contactor energises via the
closed contacts of ‘off’ button. One of the
contact pairs of the contactor is used as
the hold contact to shunt ‘on’ button and
provide a parallel path to the contactor
coil, which thus latches.
The supply to the motor gets completed
via the other N/O contacts of the contac-
tor and the pump motor starts. When the
motor gains suf cient speed (around 80
per cent of the normal running speed), the
Fig. 3: Actual-size, single-sided PCB layout for Fig. 2
centrifugal switch opens to take the start
capacitor out of the circuit and only the run
capacitors (2x36 µF) permanently stay in
series with one of the two stator windings
of the ESP motor.
In case the ESP is not provided with
an integral centrifugal switch, a second
section in ‘start’ button (shown in light
shade in Fig. 1) can be used to shunt
points ‘E’ and ‘F’. Since this switch sec-
tion has no hold on contacts, the start
capacitor will go out of circuit as soon as
‘start’ button is released. The motor can be
switched off by momentarily depression of
‘off’ button, which interrupts the supply to
the contactor coil.
To interface the control circuit shown
in Fig. 2, we use circled points A and B
(in parallel with ‘on’ button) and C and D
(formed by disconnecting one of the wires
going to ‘off’ button terminal, i.e. in series
with ‘off’ button). Points E and F will be
used if the ESP does not have an integral
centrifugal switch.
It may be recalled, by referring to Fig.
1 of the project ‘Auto Control for 3-phase
Motor’ published in EFY’s June issue
(same EP Vol. 22), that wiring of ‘on’ and
‘off’ buttons of 3-phase (4-wire system)
and split-phase motors are identical.
Hence the control circuit described here
can equally be used for 3-phase motors of
up to about 10 HP. For motors of higher
HP, one must use star-delta type starter
con guration.
The circuit
As shown in Fig. 2, the 230V AC mains
(tapped from the same points from which
it is fed to the control panel of Fig. 1) is
stepped down to 12V-0-12V by trans-
former X1. The recti ed output smoothed
by capacitor C1 is used for operation of
ELECTRONICS PROJECTS Vol. 22 105

Fig. 4: Component layout for the PCB
heavy-duty 24V, 250-ohm relays RL1
and RL2 having contact rating of 30 amp.
The relay contacts identi ed by letters A
through ‘F’ in Fig. 2 are to be connected to
identically marked points in Fig. 1.
Note that point C in Fig. 1 is created
by breaking the connection going to point
D on the ‘stop’ switch. We have used relay
RL1 with single changeover contacts. If
you need higher current rating, use re-
lays with double changeover contacts by
interconnecting N/C, N/O, and pole of one
set to the corresponding terminals of the
other set. The circuit, except for the relay
drivers, is operated with regulated +12V
supply developed across capacitor C2.
The +12V supply is fed to the common
probe in the overhead tank/storage tank
via 10-kilo-ohm resistor R1 and diode
D9. Low-level and high-level probes are
connected to the input of CMOS inverter
gates N3 and N1, respectively, via 10-kilo-
ohm resistors.
The nal low-level output at pin 10 of
gate N5 goes high when the water level
in the overhead/storage tank is below the
low-level probe. The nal high-level output
at pin 4 of gate N2 goes high as soon as the
water touches the high-level probe.
Both IC1 and IC2 have been con g-
ured as monostables with a pulse width of
about 2.5 to 3 seconds. This period is found
to work optimally for ‘start’ and ‘stop’
switch operation of the manual control
panel. The respective monostables for low
level (IC2) and high level (IC1) get trig-
gered via transistors T2 and T1 when the
nal output at pin 10 of gate N5 or pin 4 of
gate N2, respectively, goes high.
The connection of reset pins of IC2 and
IC1 to the outputs of gates N1 and N2,
respectively, ensures that no false trig-
gering of monostables takes place due to
the noise generated during changeover of
106 ELECTRONICS PROJECTS Vol. 22
PARTS LIST
Semiconductors:
IC1, IC2 - NE555 timer
IC3 - CD4049 hex inverter/buffer
T1, T2 - BC548 npn transistor
T3, T4 - BD139/SL100 npn transis-
tor
D1-D4, D7-D9 - 1N4007 recti er diode
D5, D6 - 1N4001 recti er diode
ZD1 - 12V, 1W zener diode
Resistors (all ¼-watt ±5% carbon unless stated
otherwise)
R1, R3, R5,
R7, R9, R12,
R14 - 10-kilo-ohm
R2, R6, R11,
R15-R17 - 1-kilo-ohm
R4, R13 - 220-kilo-ohm
R8, R10 - 330-kilo-ohm
relay contacts, and also that the two relays R18 - 330-ohm
never operate simultaneously. Capacitors:
In the case of mains failure, the pump C1 - 470µF, 63V electrolytic
stops if it was already running. When the capacitors
mains supply resumes, the pump starts C2 - 470µF, 25V electrolytic
only when the water goes below the low capacitors
C3, C7 - 47µ, 25V electrolytic capaci-
level. In such a situation, you can restart
tors
the motor by manual operation of ‘start’ C4, C6 - 0.01µF ceramic disk
button on the control panel. C5, C8 - 10µF, 25V electrolytic
The connections for the ammeter and capacitors
the voltmeter, not shown in Fig. 1, can be Miscellaneous:
made easily. Connect the voltmeter across X1 - 230V AC primary to 12V-0-
the incoming live and neutral lines, and 12V, 1amp
Secondary transformer
insert the ammeter in series with the stop L1 - NE2 (neon bulb with inbuilt
switch by breaking the live line connection resistor)
after the stop switch. S1 - On/off switch
Transformer, relays, switches, fuse, F1 - 3amp fuse
and neon indicator (with integral resistor) RL1 - 24V, 250-ohm, 1 c/o relay,
30A contact rating
are to be mounted on the cabinet.
of ESP motor as possible and extend
connections from tag blocks for relay and
Precautions power supply to the corresponding points,
The following are the vital points to be borne as explained earlier, using cables of cor-
in mind during wiring, assembly, and instal- rect ratings.
lation: 5. For probes, use stainless steel
1. One-watt resistor R18 should be rods of about 10cm length and 5 to 8 mm
mounted leaving some space below it. diameter with arrangement for screwing
2. Use multistrand insulated copper wires the telephone-type 25/26 SWG wire to be
of 15-amp rating for taking connections from used for extending the probes’ connections
relay terminals and terminate them on a tag to the circuit. Te on-insulated wires are,
block, marking each terminal properly. Simi- however better as they would last longer.
larly, terminate the points to be extended to The joint may be covered by epoxy.
the OHT/storage tank on a tag block (TB) us- 6. The probes can be hung from the
ing 25-28SWG wire, marking them suitably. lid of the tank to appropriate levels using
3. Mount the relays inside the body of a the same wire. Make sure that the com-
suitable metallic enclosure. The enclosure mon probe goes up to the bottom of the
should be properly earthed via the earth lead tank/storage tank.
of the mains. Also mount the step-down trans- 7. All the wires from tank to the TBs
former inside the same enclosure/cabinet. Use in the cabinet should be routed in such a
a TB for incoming live, neutral, and earth con- way that they do not interfere with any
nections from the mains (to be taken from the mains wiring. The length of the wires
manual control panel of ESP motor). hardly matters as the CMOS gates used
4. After assembly, position the cabi- for terminating the wires from probes
net as close to the manual control panel have very high input impedance.
฀
 TRANSISTOR CURVE TRACER
T
ransistor is the basic component
of all electronic equipment. A good
design of electronic circuitry re-
quires proper knowledge of the character-
istics and parameters of transistors. Due
to such factors as changes in doping level
of impurities and physical dimensions,
production imperfections, and environ-
mental (ambient temperature, humidity,
etc) changes, no two transistors can have
the same characteristics.
Transistor is an active device and
even a very small change in its param-
eters causes a large drift in its operation.
This affects the overall ef ciency and the
reliability of an equipment. Hence for an
ef cient, reliable, and trouble-free design/
operation of the electronic equipment, the
designer must know the characteristics
and parameters of each transistor used in
the equipment.
The manufacturer provides general-
ised family characteristics of transistors
bearing speci c part numbers. These
characteristics are drawn under speci c
test conditions such as 25oC temperature
and 10mA collector current IC. But as the
Fig. 1: Block diagram for tracing transistor output characteristics
Fig. 2: Block diagram for tracing transistor input characteristics
A. SARAVANAN
circuit designed may need to be operated
at different conditions (for example, at an
ambient temperature of 40°C and collec-
tor current of 10 mA), the manufacturer’s
data is no longer adequate. The manual
procedure to draw the characteristics of
a transistor is tedious and cumbersome.
Further, using the manual procedure, it
is not feasible to draw the dynamic char-
acteristics of a transistor.
The transistor curve tracer circuit
presented here enables one to draw the
input and output characteristics of npn
transistors in common-emitter con gura-
tion on a cathode ray oscilloscope (CRO).
It can be constructed and calibrated by the
designer himself.
The circuit can be upgraded to
draw the characteristics of both npn
and pnp transistors, field effect tran-
sistors (FETs), metal-oxide semicon-
ductor field effect transistors (MOS-
FETs), unijunction transistors (UJTs),
silicon-controlled rectifiers (SCRs),
TRIACs, etc. In general, it can be up-
graded for any two- or three-terminal
analogue electronic device that has a
single control terminal unlike op-amps.
Block diagram
The transistor curve tracer is built around
the ramp generator and the current-to-
voltage converter. The ramp generator
produces a linear ramp that is applied
to the transistor under test either as
the collector-emitter voltage (VCE) or the
base-emitter voltage (VBE). The ramp is
also used to de ect the electron beam
horizontally (along x-axis) on the screen of
the CRO. Similarly, the current-to-voltage
converter converts either the collector
current (IC) or the base current (IB) into a
proportional voltage that is used to de ect
the electron beam vertically (along y-axis)
on the screen.
The signal conditioning and switching
circuits, along with the ramp generator
and current-to-voltage converter, make
a complete curve tracer for the input and
output characteristics of an npn transis-
tor.
Output characteristics (Fig. 1).
The ramp and clock generator generates
a linear ramp and 1 kHz clock pulses. The
ramp is ampli ed by the ramp buffer am-
pli er to 0 to 5 volts. This ampli ed ramp
is applied to the collector of the transistor
under test as the collector-emitter volt-
age (VCE) through the current-to-voltage
converter.
The current-to-voltage converter gives
an output voltage proportional to collector
current IC that is applied to the CRO to
de ect the beam in y-axis. The 0-5V ramp
output is applied to the CRO to de ect the
beam in x-axis. Hence we can trace the
output characteristics of the transistor
with the collector-emitter voltage (VCE) on
x-axis and IC on y-axis.
To trace the output characteristic
graph for various base current (IB) val-
ues, the generator’s clock output fed to
the counter is incremented for each clock
pulse. The count sequence is 000, 001,
010, 011, 100, 101, 110, and 111 (0 to
7 decimal). After 111, the counter resets
ELECTRONICS PROJECTS Vol. 22 107
Fig. 3: Circuit diagram of transistor curve tracer
automatically to 000 and the sequence
repeats. The lower three bits of the coun-
ter are applied to the base-current control
circuit.
The base-current control circuit sets
IB in eight discrete 100µA steps, i.e. 0 µA,
100 µA, 200 µA, 300 µA, 400 µA, 500 µA,
600 µA, and 700 µA. Adjust the step width
(100 µA) using a potentiometer such that
the output characteristics of various npn
transistors with various current gains (β)
are traced/accommodated.
Input characteristics (Fig. 2).
Here again, the ramp and clock generator
generates a linear ramp and 1kHz clock
pulses. The ramp is ampli ed by the ramp
buffer ampli er to 0-5V. This ampli ed
ramp is attenuated and ampli ed as re-
quired to get 0-1V ramp and applied to
the base of the transistor under test as
the base-emitter voltage (VBE) through the
current-to-voltage converter.
The current-to-voltage converter gives
an output voltage proportional to base
current IB that is applied to the CRO to
de ect the beam in y-axis. The 0-1V ramp
output is applied to the CRO to de ect the
beam in x-axis. Hence we can trace the
108 ELECTRONICS PROJECTS Vol. 22
input characteristics of the transistor with
VBE on x-axis and IB on y-axis.
To trace the input characteristics
graph for various VCE values, the clock
output of the generator is fed to the coun-
ter and switching circuit. The counter
counts the number of pulses in the binary
form. Q0 output of the counter is used as
the collector-emitter voltage control that
toggles VCE with 0 volt and 10 volts for
every clock pulse. Thus we can trace the
input characteristics for VCE = 0 volt and
VCE = 10 volts.
The circuit
The transistor curve tracer circuit (Fig. 3)
comprises power supply, ramp and clock
generator, ramp buffer and offset null,
current-to-voltage converter, counter, base
current control, and switching sections.
1. The power supply section. The
circuit operates on ±12V regulated power
supply. The input AC mains supply is
stepped down by transformer X1 to deliver
a secondary supply of 15-0-15V AC at 1
ampere. The output of the transformer is
recti ed by a bridge recti er. The 1000µF,
35V capacitors act as lters to eliminate
ripples and provide unregulated DC out-
put voltage.
The unregulated dual DC voltage is
converted by three-terminal ICs AN7812
and AN7912 into ±12V regulated power
supply. (Note. Connect 0.1µF decoupling
capacitors between the supply terminals
and ground of every IC in order to sup-
press unwanted noise signals in the sup-
ply voltage.)
2. The ramp and clock generator
section. The ramp and clock generator
uses a constant current source (LM334)
and a capacitor, in conjunction with timer
NE555 (IC3) wired as an astable multi-
vibrator, to generate a linear ramp. The
control terminal of timer 555 (pin 5) is
held at a reference voltage of 5 volts by a
zener diode so that the upper threshold
(VUTP) is at 5 volts and the lower threshold
(VLTP) at 2.5 volts.
The output current from IC LM334
can be controlled with the help of poten-
tiometer VR1. This current charges the
capacitor linearly in the form of a linear
ramp. As soon as the voltage across the
capacitor exceeds the upper threshold volt-

Fig. 4: Actual-size, single-side PCB layout for transistor curver tracer
Fig. 5: Component layout for the PCB
age (VUTP), the output of timer 555 changes
its state and goes low. This activates the
discharge terminal (pin 7) of timer 555
and hence the capacitor quickly discharges
through the timer.
As the voltage across the capacitor
drops below the lower threshold voltage
(VLTP), the output of timer 555 changes
its state and goes high to disable the dis-
charge terminal and further discharging of
capacitor stops. Once again the capacitor
gets charged linearly through the constant
current source and the sequence repeats.
Thus the potential across the capacitor is
a positive linear ramp between 2.5 volts
and 5 volts. The ramp frequency can be
controlled by varying the charging current
using potentiometer VR1. (EFY Lab note.
During lab testing, we used AD590 tem-
perature transducer in place of LM334H
as the constant current source, and the
method of using the same is shown in Fig.
3 within dotted lines.)
3. The ramp buffer and offset null
section. Since the output impedance of
the ramp source is very high, we cannot
load it. Also, a DC offset voltage equal to
the lower threshold voltage (VLPT = 2.5V)
is present in the ramp output. In order
to nullify the offset voltage of the ramp
and to source the current from the ramp,
use a buffer ampli er. An op-amp in non-
inverting ampli er con guration is used
to achieve this function.
As the input impedance of the non-
inverting ampli er is very high, it will not
load the ramp source. Also, it is possible to
nullify the DC offset voltage present in the
ramp output with the help of ramp offset
adjustment preset VR2.
By adjusting feedback preset VR3, the
output of ramp buffer can be set to deliver
a linear 0-5V ramp. This output is used as
VCE for the transistor under test to source
the collector current (IC).
To draw the input characteristics of
the transistor, the base-emitter voltage
(VBE) should be varied linearly. For this we
require a linear 0-1V ramp with suf cient
current sourcing capability. In order to
achieve this, a ramp attenuator (voltage
divider) and an ampli er are used.
The 0-5V ramp output of ramp buffer
is attenuated by the potential divider
network (comprising resistors R4 and R5)
followed by an op-amp (IC5) connected in
non-inverting con guration. The gain of
the op-amp can be adjusted using preset
VR5 connected in the feedback path.
In order to nullify the offset voltage of
ELECTRONICS PROJECTS Vol. 22 109
the op-amp, balancing preset VR4 is con-
nected between the offset null terminals
of the op-amp. The output of the op-amp
is 0-1V linear ramp, which is used as the
base-emitter voltage (VBE) for sourcing
the base current (IB) of the transistor
under test.
4. The current-to-voltage convert-
er section. The spot on the CRO screen
is de ected in proportion to the potential
applied to its input. Hence in order to
de ect the beam along y-axis, which is
the current axis (collector current IC in
Fig. 6: Waveforms at various points in the circuit
110 ELECTRONICS PROJECTS Vol. 22
the transistor output characteristics and
base current IB in the transistor input
characteristics), the current component
is to be converted into a proportional
voltage.
The current to be measured is passed
through series resistor R7 of 10-ohm,
±1% MFR (metal lm resistor). Potential
drop Vout across the resistor, according to
the Ohm’s law, is proportional to current
I through it and is given by the following
relationship:
V = IR
where Vout = 10xI
Hence, there is a potential drop of 10 mV
per mA of the current through the circuit.
We cannot apply this small oating potential
directly to the CRO for a signi cant de ection.
Therefore we use a differential ampli er to
have an output voltage with respect to the
ground that is proportional to the current
though the circuit. The differential ampli er
has a gain of 100 that can be ne-tuned with
the help of gain adjust preset VR7 in the feed-
back path.
The current-to-voltage converter converts
the current of 1 mA into a potential difference
of 1 volt that can be applied to the CRO to
de ect the beam in vertical axis. In order to
nullify the offset voltage of the op-amp, connect
a balancing preset to the offset null terminals
of the op-amp.
5. The counter section. The base cur-
rent (IB) is to be changed in discrete steps
for every ramp to enable the transistor’s
output characteristics for various IB values
simultaneously on the CRO screen.
In the counter circuit, the output of
timer 555 (IC3) from pin 3 is a square wave
that intimates the end of ramp. This output
is used as clock pulse for the counter wired
around CMOS binary/decade, up/down IC
MC14029B or CD4029B (IC7).
IC7 is wired as a 3-bit binary up-
counter so that the output of the counter
(Q2, Q1, and Q0) is incremented by bi-
nary 1 for every clock pulse. The count
sequence is 000, 010, 011, 100, 101, 110,
and 111, i.e. 0 through 7 decimal. After
111, the counter is automatically reset to
000, and once again the count sequence
repeats. Hence we get eight discrete logic
levels, and accordingly we can set the
base current (IB) using a base current
control circuit.
Similarly, to draw the input charac-
teristics of the transistor under test for
various collector-emitter voltage (VCE)
values, the collector-emitter voltage (VCE)
is to be changed for each ramp. The least
signi cant bit (Q0) of the counter is used
to toggle the collector-emitter voltage (VCE)
from 0 volt to 10 volts. Thus we can view
the input characteristics of the transistor
for VCE= 0 volt to VCE= 10 volts simultane-
ously on the screen of the CRO.
6. The base current control
section. This section receives the
input from the counter circuit and
varies the base current (I B ) of the
transistor. The output of counter IC7
in series with a high-value resistor
acts as the constant current source.

Fig. 7: Actual output curves on CRO (shown
without retrace)
Fig. 8: Actual input curves on CRO (shown
without retrace)
The high-level outputs of the counter
are fairly constant at 10 volts.
When we connect a resistor of 100
kilo-ohms in series with Q0 output of the
counter, it supplies a constant current of
100 µA during its logic 1 state. Similarly,
when we connect a resistor of 50 kilo-ohms
(two 100 kilo-ohm resistors in parallel)
in series with Q1 output of the counter,
it supplies a constant current of 200 µA
during its logic 1 state. Using 25-kilo-ohm
resistor in series with Q2 output we can
get a constant current source of 400 µA.
When more than one current source
are connected in parallel, the result is
similar to having a current source equal to
the sum of individual source currents.
If we use the base current (IB) setting
as it is for a transistor with large current
ampli cation factor (α), its collector cur-
rent (IC) gets saturated for much smaller
values of IB and only two or three traces
appear on the screen of the CRO. To get
the maximum number of traces, reduce
the base current by increasing the series
resistor values through IB SET potentiom-
eter VR8. With the help of VR8, we can
adjust the base current in incremental
steps from 10 µA to 100 µA.
(Note. Connect two 100-kilo-ohm re-
sistors in parallel to get 50-kilo-ohm resis-
tor. Similarly, connect four 100-kilo-ohm
resistors in parallel to have 25-kilo-ohm
resistor. This method has been shown in
Fig 3.)
7. The switching section. Certain
circuits are common in tracing both the
output characteristics and input charac-
teristics. The ramp and clock generator,
ramp buffer and ampli er, and counter
circuits are retained at their places for
both output and input characteristics. But
to trace the output characteristics the cur-
rent-to-voltage converter is to be connected
in the collector of the transistor under test
and to trace the input characteristics it is
to the connected in the base of the transis-
tor (refer Figs 1 and 2 for output and input
characteristics, respectively).
To have minimum complexity, the
collector and the base circuits of the
transistor are switched suitably using a
changeover switch on the front panel. The
switching details are obvious from the
circuit diagram in Fig. 3.
Construction
Wire the circuit on a 2.5mm, IC-type gen-
eral-purpose printed circuit board (PCB)
as shown in Fig. 3. The use of glass-epoxy
PCB is recommended. An actual-size,
single-side PCB for the circuit is shown in
Fig. 4, with its component layout shown
in Fig. 5.
Carefully solder all the components
and use sockets for ICs. All range resis-
tors used should be stable, close-tolerance
type (preferably MFRs). Preferably use
linear-type IB SET potentiometer and
mount it on the front panel of the instru-
ment. Enclose the circuit board, power
transformer, and other circuit compo-
nents in a metal box having approximate
dimensions of 22x17x7.5 cm. Extend
input and output leads to the correspond-
ing points in the circuit. Terminate the
outputs for connection to the CRO in
BNC(F) connectors.
Calibration
After construction, check the circuit
thoroughly for short circuits, breaks,
and open circuits on the PCB. After
switching on the instrument, let it
warm up for a few minutes before
commencing with the calibration.
Calibration procedure of the circuit is
as follows:
1. Check and ensure ±12V regu-
lated voltage with respect to ground.
2. Connect a CRO to shorted pins 2
and 6 of timer 555 (ramp output). A lin-
ear ramp with positive slope is observed
on the screen of the CRO. By adjusting
frequency control potentiometer VR1, set
the frequency of the ramp at 1 kHz (refer
waveform 1 in Fig. 6).
3. Connect the CRO to the output of
ramp buffer. Adjust preset VR2 to nul-
lify the DC offset voltage in the output of
ramp buffer. Adjust preset VR3 to set the
amplitude of ramp output to 0 to 5 volts
(refer waveform 2 in Fig. 6).
4. Connect CRO at the output of ramp
attenuator and ampli er. Adjust preset
VR4 to nullify the DC offset voltage in the
output of ramp buffer. Adjust preset VR5
to set the amplitude of ramp output to 0 to
1 volt (refer waveform 3 in Fig. 6).
5. Calibrate the current-to-voltage
converter by connecting a 1-kilo-ohm. 1%
metal lm resistor between the collector
and emitter terminals of the transistor
under test. Connect the output of the
current-to-voltage converter to a CRO.
By observing the ramp waveform on
the screen of the CRO, nullify DC offset
voltage using preset VR6 and adjust the
amplitude of the observed ramp wave-
form to 0-5 volts with the help of preset
VR7. Calibrate the current-to-voltage
converter to convert 1 mA of current into
1 volt (refer waveform 4 in Fig. 6). Then
check the clock output by connecting the
CRO to pin 3 of timer 555 (refer waveform
5 in Fig. 6).
6. Verify the outputs of the counter by
using a dual-trace oscilloscope. Connect
one input channel of the CRO with clock
pulses at pin 3 of IC3 and the outputs at
pins 6, 11, and 14 of counter IC7 to the
other input of the CRO sequentially (refer
waveforms 5, 6, 7, and 8 in Fig. 6).
7. Short-circuit the base-emitter ter-
minals of the transistor under test. Select
input/output characteristics switch S2 to
output characteristics position and con-
nect the CRO to the output of the current-
to-voltage converter. By adjusting IB SET
potentiometer VR8 on the front panel of
the instrument, check proper operation
of the base-current section by observing
stair-case ramp of varying amplitude on
the screen of the CRO (refer waveform 9
in Fig. 6).
Operation
After calibration, the instrument is ready
for use to trace the input and output
characteristics of npn transistors. Follow
the operating procedure given below every
ELECTRONICS PROJECTS Vol. 22 111
 PARTS LIST corresponding inputs of the CRO. characteristics position.
Semiconductors:
2. Plug in the AC cord of both the CRO 16. Set the volts/div control of x-axis to
IC1 - 7812, +12V regulator and the transistor curve tracer and switch 0.1 volt/div and observe the input charac-
IC2 - 7912, –12V regulator them on. teristics likewise.
IC3 - NE555 timer 3. Set the CRO inputs to ground. Figs 7 and 8 show a typical transis-
IC4, IC6 - µA741 op-amp (IC OP-07 4. Allow warm-up time of at least 10 tor’s output and input characteristics,
op-amps can be used
in place of µA741 with minutes for the circuit components to get respectively, on the CRO screen (without
advantage) stabilised. retrace).
IC7 - MC14029B/CD4039 binary/ 5. Set the CRO for X-Y mode of opera-
decade up-/down-counter tion.
IC8 - LM334H/AD590 tempera-
ture sensor
6. Adjust intensity and focus controls Conclusion
D1-D4 - 1N4007 recti er diode to get a sharp spot on the screen of the To draw the characteristics of pnp tran-
ZD1 - 5V zener diode CRO. sistors, insert an inverter circuit in the
Resistors (all ¼-watt, ±1% MFR, unless stated 7. Set the volts/div control of x-axis to ramp path of collector-emitter voltage
otherwise): 0.5 volt/div. VCE and base-emitter voltage VBE, and
R1, R5, R6, 8. Set the volts/div scale of y-axis to invert the output of the current-to-voltage
R8, R9 - 1-kilo-ohm 2 volts/div. converter.
R2, R4 - 22-kilo-ohm
R7 - 10-ohm 9. Adjust the position controls of the By using a potential divider and
R3, R10, R11 CRO to position the spot on the left bot- buffer ampli er circuit in place of the
(A,B), R12(A-D) - 100-kilo-ohm tom of the screen ((0,0) position in the base-current control circuit you can
VR1 - 1-kilo-ohm preset graph). draw the characteristics of FETs and
VR2 - 2.2-kilo-ohm preset
VR3, VR4,
10. Set the inputs for DC coupling to MOSFETs.
VR5, VR6 - 10-kilo-ohm preset the CRO. To trace the forward characteristics
VR7 - 150-kilo-ohm preset 11. Connect the transistor whose of diodes, connect the anode of the diode
VR8 - 1-mega-ohm potmeter characteristics are to be traced to the to the base terminal and the cathode to
Capacitors: transistor curve tracer, ensuring correct the emitter terminal. Set the transistor
C1-C4, C9 - 0.1µF ceramic disk pin con guration. curve tracer to draw input characteristics,
C5, C6 - 1000µF, 35V electrolytic 12. Set the selector switch for input/ and the CRO screen displays the forward
C7, C8 - 100µF, 25V electrolytic
C10 - 0.01µF ceramic disk output characteristics to the output char- characteristics of the diode.
acteristics position. Similarly, with simple add-on circuits
Miscellaneous:
X1 - 230V AC primary to 13. Release the CRO inputs from to the motherboard, you can draw the
15V-0-15V AC, 500mA ground and switch them over to connect characteristics of UJTs, SCRs, TRIACs,
secondary transformer inputs. etc.
S1 - On/off switch 14. Now view the output characteris- Thin and faint retrace lines visible
S2 - DPDT switch
tics of the transistor. Fine-tune the IB set along with the characteristic traces can
potentiometer to get eight traces on the be removed by connecting a retrace blank-
time to get correct traces of input and out- screen of the CRO. ing circuit to the Z-mod input of the CRO.
put characteristics of the transistor: 15. To trace input characteristics of Almost all CROs exceeding 30MHz band-
1. Connect the x-axis and y-axis BNC the transistor, change the input/output width have the Z-mod input facility.
pins of the transistor curve tracer to the characteristics selector switch to the input ฀

112 ELECTRONICS PROJECTS Vol. 22

 TRIPPING SEQUENCE
RECORDER-CUM-INDICATOR
R.G. THIAGRAJ KUMAR AND S. RAMASWAMY
I
n applications like power stations and
continuous process control plants, a
protection system is used to trip
faulty systems to prevent damages and
ensure the overall safety of the personnel
and machinery. But this often results in
multiple or cascade tripping of a number
of subunits.
Looking at all the tripped units doesn’t
reveal the cause of failure. It is therefore
very important to determine the sequence
of events that have occurred in order to
exactly trace out the cause of failure and
revive the system with minimal loss of
time.
The circuit presented here stores the
tripping sequence in a system with up to
eight units/blocks. It uses an auxiliary relay
contact point in each unit that closes when-
ever tripping of the corresponding unit oc-
curs. Such contact points can be identi ed
easily, especially in systems using program-
mable logic controllers (PLCs).
This circuit records tripping of up to
eight units and displays the order in which
they tripped. A clock circuit, however fast,
cannot be employed in this circuit because
the clock period itself will be a limiting
factor for sensing the incidence of fault.
Besides, it may also mask a number of
Fig. 1: Block diagram of tripping sequence recorder-cum-indicator
events that might have occurred during
the period when the clock was low. Hence The circuit
the events themselves are used as clock IC1 and IC2 (CD4043) Quad NOR RS
signals in this circuit. ip- ops in Fig. 2 are used to capture and
Fig. 1 shows the block diagram of the store the information pertaining to the
tripping sequence recorder-cum-indicator. tripping of individual units. Reset pins of
The inputs derived from auxiliary relay all the eight ip- ops and sub-parallel en-
contacts (N/O) of subunits or push-to-on able (PE) pin 1 of BCD up-/down-counter
switches are latched by RS ip- ops when CD4510 (IC3) are returned to ground via
the corresponding subunits trip, causing 10-kilo-ohm resistor R22, while set pins
the following four actions: of all RS ip- ops are returned to ground
1. The latch outputs are ORed to acti- via individual 10-kilo-ohm resistors R14
vate audio alarm. through R21.
2. The latch outputs are differentiated Initially, all the eight Q outputs of
individually and then ORed to provide IC1 and IC2 are at logic 0. The auxiliary
clock pulses to the counter to increment relay contacts of the subunits, which are
the output of the counter that is initially depicted here by push-to-on switches S1
preset at 1 (decimal). through S8, connect the set terminal of the
3. Each individual latch output acti- corresponding stage of RS ip- op to +12V
vates the associated latch/decoder/driver whenever tripping of a speci c subunit
and 7-segment display set to display the occurs. This makes the output of the as-
number held at the output of the counter, sociated ip- op go high. Thus whenever
which, in fact, indicates the total number
of trips that have taken place since the PARTS LIST
last presetting. Semiconductors:
4. LEDs associated with each of the IC1, IC2 - CD4043 quad NOR RS latch
IC3 - CD4510 BCD up-/down-
latch, decoder, and driver sets remain lit counter
to indicate the readiness of the sets to re- IC4-IC11 - CD4511 BCD-to-7-segment
ceive the tripping input. LEDs associated latch/decoder/driver
with the tripped unit go off. T1-T11 - BC547 npn transistor
T12-T19 - BC557 pnp transistor
D1-D16 - 1N4007 recti er diode
DIS1-DIS8 - LT543 common-cathode
7-segment display
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1-R11,
R13-R38 - 10-kilo-ohm
R12, R39-R46 - 1-kilo-ohm
R47-R102 - 470-ohm
Capacitors:
C1-C8 - 0.01µF ceramic disk
Miscellaneous:
S1-S8 - Push-to-on switch or relay
contacts (N/O)
S9 - Push-to-on switch
PZ1 - Piezobuzzer
- 12V, 500mA power supply
ELECTRONICS PROJECTS Vol. 22 113
Fig. 2: Schematic diagram of tripping sequence recorder-cum-indicator

a sequence of tripping of subunits

occurs, the corresponding outputs
(1Q to 8Q) go high in the order
of the tripping of the associated
subunits.
All the eight Q outputs are
connected to the correspond-
ing latch-enable inputs of BCD
latch-cum-decoder-driver ICs
(CD4511). These Q outputs
are also ORed using diodes D1
through D8 to activate an audible
alarm and also routed to a set of
differentiator networks (compris-
ing capacitors C1 through C8 and
resistors R2 through R9).
A differentiator provides a
sharp pulse corresponding to the
tripping of a subunit. All such
differentiated pulses are ORed
via diodes D9 through D16 and
coupled to the counter stage Fig. 3: Actual-size, single-side PCB of the main control portion of tripping sequence controller-cum-
formed by IC3 (CD4510, a syn- indicator circuit

114 ELECTRONICS PROJECTS Vol. 22


Fig. 4: Component layout for Fig. 3
Fig. 5: Actual-size, single-side PCB for
latch decoder/driver and display circuit of
one subunit
chronous up-/down-counter with preset)
after ampli cation and pulse shaping by
transistor ampli er stages built around
transistors T2 and T3. These pulses serve
as clock to count the number of trippings
that occurred after a reset.
Operation
Let us assume that three units, say, E, H,
and A ( fth, eighth, and rst), tripped in
that order following a fault.
When the system is reset (before
any tripping), the outputs of all RS ip-
ops (1Q through 8Q) are low. This LE*
active-low makes latches IC4 through
IC11 transparent and as the counter is
preset to 1 (since P1 input is high while
P2, P3, and P4 are low) with the help
of switch S9, all the latches hold that
‘1’ and their decoded ‘b’ and ‘c’ segment
Fig. 6: Component layout for Fig. 5
outputs go high.
However, the common-cathode drive
is absent in all the 7-segment displays
because driver transistors T4 through T11
are cut off due to the low outputs of all RS
ip- ops and hence the displays are blank.
At the same time, the low outputs of all
RS ip- ops (1Q through 8Q) forward bias
pnp transistors T12 through T19 associ-
ated with LED1 through LED8 of each of
the displays. As a result, all these LEDs
glow, indicating no tripping.
Now when unit E trips, output 5Q
of RS ip- op IC2 goes high to provide
the base drive to common-cathode drive
transistor T8. This, in turn, activates DIS5
( fth from left in Fig. 2) to display 1 , indi-
cating that unit E tripped rst. The corre-
sponding LED5 goes off as transistor T16
is cut off. Also, latch IC8 is disabled due
to logic 1 on its pin 5 and therefore it does
not respond to further changes in its BCD
data input. Simultaneously, the
buzzer goes on to sound an audible
alarm, indicating the emergency
situation at the plant.
The differentiator formed
by C5 and R6 responds to the
low-to-high transition of 5Q and
generates a short pulse. This pulse
passes through diode D13 and
transistors T2 and T3 and reaches
clock pin of counter IC3. The
counter counts up and its output
becomes 0010 (decimal 2).
As mentioned earlier, all the
display units other than E have
the drive signal on segments a, b,
g, e, and c now but are off because
of the missing common-cathode
drive. When the next subunit H
trips, output 8Q experiences a
low-to-high transition and the cor-
responding display (DIS8) shows
digit ‘2’. The above sequence of
operation holds true for any further
subunit tripping—with the displayed
digit incrementing by one for each se-
quential tripping.
In the prototype, LEDs D17 through
D24 were xed below the corresponding
7-segment displays pertaining to subunits
A through H to provide a visual indication
that these units are ready to respond to
a tripping.
The circuit works satisfactorily with
twisted-pair wires of length up to 5 me-
tres. In electrically noisy environments,
the length of the cable has to be reduced
or a shielded twisted-pair cable can be
used.
An actual-size, single-side PCB layout
for the main control portion of the tripping
sequence recorder-cum-indicator circuit is
shown in Fig. 3 and its component layout
in Fig. 4. The PCB layout for the indica-
tor set comprising IC4, DIS1, transistors
T4 and T12, LED1, etc is shown in Fig. 5
and its component layout in Fig. 6. The
indicator set of Fig. 5 can be connected
to the main PCB of Fig. 3 using Bergstrip
type SIP (single-inline-pin) connectors as
per requirements.
This tripping sequence recorder-cum-
indicator circuit can also be used in quiz
games to decide the order in which the
teams responded to a common question.
For this, provide push-to-on switches on
the tables of individual teams and a mas-
ter reset to the quiz master. Modify the
alarm circuit suitably with a retriggerable
monostable stage so that the audible alarm
stops after a short interval. ฀
ELECTRONICS PROJECTS Vol. 22 115
 SECTION B :
CIRCUIT IDEAS
 ELECTRONIC STARTER
FOR SINGLE-PHASE MOTORS
SARAT CHANDRA DAS

A
novel single-phase electronic hence relay RL2 latches even if switch The contact rating for relays RL1 and
starter circuit meant for 0.5HP S1 is subsequently opened. The other N/O RL2 should be 5 amperes, while contact
and 1HP motors is presented here. contacts RL2(b) of relay RL2, on energisa- ratings of relay RL3 should be 10 to 15
It incorporates both overload and short- tion, connect the voltage developed across amperes.
circuit protections. A special current- capacitor C2 to relay RL3, which thus Transformer X1 can be wound using
sensing device has been added in this energises and completes the supply to the any suitable size CRGO core. (One can
starter to sense the current being drawn motor, as long as current passing through use a burntout transformer core as well.)
by the motor. primary of transformer X1 is within limits The primary comprises 30 to 31 turns for
If the motor jams due to bearing fail- (for a 1HP motor). use with 1HP motor and additional eight
ure or defect in the pump or any other When the current drawn by motor turns, if you are using a 0.5HP motor.
reason, it would draw much higher current exceeds the limit (approx. 5A), the volt- Fuses F1 and F2 are kit-kat type. The ‘on’
than its normal rated current. This will age developed across the secondary of pushbutton is normally-‘off’ type, while
be sensed by the current-sensing device, transformer X1 is suf cient to energise ‘off’ pushbutton S2 is of normally-‘on’
which will trip the circuit and protect the relay RL1 and trip the supply to relays type. Capacitors C1 and C2, apart from
motor. Some other reasons for the motor RL2 and RL3, which was passing via the smoothing the recti ed output, provide
drawing higher current are as follows: N/C contact of relay RL1. As a result, the necessary delay during energisation and
(a) Windings damaged or short-circuit supply to the motor also trips. de-energisation of relays. Diodes across
between them.
(b) Shorting of motor terminals by
mistake.
(c) Under voltage or single phasing
occuring in the mains supply source (nor-
mally, a 440V AC, 3-phase with neutral
four-wire system).
The main components used in the
circuit comprise a specially wound sensing
transformer X1, another locally available
step-down transformer X2, single-change-
over relay RL1, two double-changeover
relays (RL2 and RL3), and other discrete
components shown in the gure. The
mains supply to the motor is routed in
series with the primary of transformer
X1 via normally-open contacts of relay
RL3. The primary of transformer X1 is
connected in the neutral line.
To switch on the supply to the mo-
tor, switch S1 is to be pressed momen-
tarily, which causes the supply path
to the primary of transformer X2 to
be completed via N/C contacts of relay
RL1. Relay RL2 gets energised due to
the DC voltage developed across capac-
itor C2 via the bridge rectifier. Once
the relay energises, its N/O contacts
RL2(a) provide a short across switch
S1 and supply to the primary of trans-
former X2 becomes continuous, and

ELECTRONICS PROJECTS Vol. 22 119

relays are used for protection as free-
wheeling diodes.
Starters for 0.5HP and 1HP motors
are not easily available in the market.
Readers’ comments:
 I would like to have some doubts
cleared:
1. In the circuit, AC supply was in-
dicated by phase and neutral. If phase
and neutral are changed, what will be
the result?
2. What is the suggested core size of
transformer X1 tested by the author?
3. Can we use ferrite core transformer
instead of CRGO core?
J.V.K. Naidu
Eluru
The author, Sarat Chandra Das,
replies:
1. The mains supply is taken from 3-phase,
4-wire system. When you are using any do-
mestic appliance such as fan, TV, etc, you
MODEM ‘ON’/‘OFF’ INDICATOR
H
ere is an interesting, low com-
ponent-count, and easy-to-build
electronic circuit for the Internet
surfers. This circuit, using two LEDs,
indicates the modem status, i.e. whether
it is in use or not.
The incoming telephone line termi-
nating on a master phone is shunted by a
metal oxide varistor.
The circuit is con gured around the
popular timer chip NE555, which is wired
as an astable multivibrator. When power
is applied to the circuit, the astable starts
working as usual. However, LEDs D2 and
D3 connected to its output pin 3 would not
glow as transistor T1 is in off condition and
hence resistor R4’s bottom end is hanging
in high impedance state.
However, when the modem is work-
ing, voltage drop across preset VR1
illuminates the LED inside the opto-
coupler (IC2). As a result, transistor
T1 gets sufficient base-bias through
activated transistor inside opto-coupler
via resistor R3. Consequently, LEDs
120 ELECTRONICS PROJECTS Vol. 22
Users are therefore compelled to use
10-amp rated circuit breaker for such mo-
tors. A mechanical starter or auto starter
would turn out to be costlier than the
Fig. 1: Suggested ‘El’ core dimensions
do not make sure as to which is phase and
neutral in the socket (when using a 2-pin
plug top). Nothing happens when phase
and neutral are interchanged.
(EFY: Nothing untoward happens as
long as supply in the gadget is rst routed
to a transformer. In some appliances neu-
T.K. HAREENDRAN
D1 and D2 start blinking at the bist-
able IC1’s frequency determined by the
values of resistors R1 and R2 and capaci-
tor C1.
A 9V, 0.5A AC adapter can be used
to power the circuit. Finally, one minor
adjustment is required for successful op-
eration of the gadget. For this, rst switch
on the supply to the gadget and then
switch ‘on’ the modem. Now adjust the
circuit given here, which works very reli-
ably. Parts used in this circuit are easily
available in most of the local markets.
tral and ground are shorted together and
thus the body of the gadget becomes ‘live’
and one could get a shock on touching the
gadget. One must use a 3-pin plug and
socket system in which live and neutral
conventions are adhered to as per ISI speci-
cations/Electricity Act and rules.)
2. The suggested core size is shown in
Fig. 1. I suggest the use of a 220V/6V-0-
6V, 500mA to 1A rating step-down trans-
former core used in battery eliminators
(new or burnt), which is available in the
local market.
3. Ferrite core is better than CRGO,
but it is costlier and not easily available
in the local market, while CRGO core is
easily available. Technically, turns ratio
in winding will change.
wiper of preset VR1 very slowly until the
LEDs start blinking. Memorise the wiper
position and x it in this position using a
good-quality glue/compound.
After construction, x the complete
circuit in a suitable and attractive cabinet
with one LED in its front panel. Keep
the whole unit near the modem and t
another LED near the master telephone
with the label ‘Modem in Use’.
 TOUCH-SELECT AUDIO SOURCE
O
ften you need to connect out-
put from more than one source
(preamplifier) such as tape
recorder/player and CD (compact
disc) player to audio power ampli er.
This needs disconnecting/connecting
wires when you want to change the
source, which is quite cumbersome
and irritating.
Here is a circuit that helps you choose
between two stereo sources by simple
touch of your hand. This circuit is so com-
PRECISION ATTENUATOR
WITH DIGITAL CONTROL
W
hen instruments are designed,
an analogue front-end is es-
sential. Further, as most equip-
ment have digital or microcontroller in-
terface, the analogue circuit needs to have
digital control/access.
The circuit of a programmable attenu-
SARAVANAN J.
pact that it can be xed within the audio
power ampli er cabinet and can use the
same power supply source.
The circuit uses just two CMOS ICs
and a few other componenets. The ICs
used are MC14551/CD4551 (quad 2-chan-
nel analogue multiplexer) and CD4011
(quad 2-input NAND gate). When touch-
plate S1 is touched (its two plates are
to be bridged using a ngertip), gate N1
output (IC1, pin 3) goes high while the
output of gate N2 at pin 4 goes low. This
ANANTHA NARAYAN
ator with digital control is described here,
where digital control can be a remote dip
switch, or CMOS logic outputs of a decade
counter (having binary equivalent weight
of 1, 2, 4, and 8, respectively), or I/O port
of a microcontroller like 80C31.
The heart of this circuit is the popu-
causes selection of CD outputs being con-
nected to the power ampli er input, which
is indicated by lighting of LED1.
When touch-plate S2 is touched, the
outputs of gates N1 and N2 toggle. That
is, IC2 pin 3 is pulled ‘low’ while its pin 4
goes ‘high’. This results in selection of tape
recorder outputs being connected to the
input of power ampli er. This is indicated
by lighting of LED2.
Pin 9 is the control pin of IC2. In the
circuit, the state of multiplexer switches
is shown with pin 9 ‘high’
(CD source selected). When
pin 9 is pulled ‘low’, all the
switches within the multi-
plexer change over to the
alternate position to select
tape player as source.
EFY Lab note. Al-
though one can connect pin
7 (VEE) of IC2 to ground,
but for operation with
preampli er signals going
above and below ground
level, one must connect it
to a negative voltage (say,
–1V to –1.5V) to avoid
distortion.
lar OP07 op-amp with ultra-low offset
in the inverting con guration. A dual,
4-channel CMOS analogue multiplexer
switch CD4052 enables the change in
gain. An innovative feature of the circuit
is that the ‘on’ resistance (around 100
ohms) of CD4052 switch is bypassed so
ELECTRONICS PROJECTS Vol. 22 121

that no error is introduced by its use.
Resistors R1 to R6 used in the cir-
cuit should be of 0.1 per cent tolerance,
50 ppm (parts per million) if you use
3½-digit DPM, i.e. ±1999 counts (approx.
11 bits). But for 4½-digit DPM (approx.
14 bits), you may need to have trimpots
(e.g. replace 1k-ohm resistor R6 by a xed
900-ohm resistor in series with a 200-ohm
trimpot) to replace R3, R4, R5, and R6
gain selection resistors for proper calibra-
tion to required accuracy. However, for
testing or trials, use 1 per cent 100ppm
MFR resistors. The expected errors will
be around 1 per cent.
To keep parts count (hence cost) to
a minimum, the common or ground is
used as the positive input terminal and
one end of resistor R1 as the negative.
This is so because the op-amp inverts
the polarity as it is used in inverting
con guration. This does not matter as
the equipment will be isolated by the
power supply transformer and all po-
larities are relative. In case you want
the common to be the negative, you will
PRECISION AMPLIFIER
WITH DIGITAL CONTROL
T
his circuit is similar to the pre-
ceding circuit of the attenuator.
Gain of up to 100 can be achieved
122 ELECTRONICS PROJECTS Vol. 22
have to add some stages (IC4 and IC5
circuitry shown in precision ampli er
circuit described later).
The OP07 pinout is based on stand-
ard single op-amp 741. Any other
op-amp like CA3140, TLO71, or LF351 can
be used but with offset errors in excess of 1
per cent, which is not tolerable in precision
instrumentation.
The OP07 has equivalent ICs like
µA741 and LM607 having ultra-low
offset voltage (<100µV), low input bias
current (<10nA), and high input imped-
ance (>100M), which are the key require-
ments for a good instrumentation op-amp
for use with DC inputs.
The following design considerations
should be kept in mind:
(a) Input: 500V max
Since ¼W resistors can withstand
up to 250V, resistors R1 and R2 in series
are used for 1 meg-ohm with 500V (max)
input limit. These resistors additionally
limit the input current as well. Diodes D1
and D2 clamp the voltage across input of
op-amp to ±0.5V, thereby protecting the
ANANTHA NARAYAN
in this con guration, which is useful for
signal conditioning of low output of trans-
ducers in millivolt range.
op-amp.
(b) Output
The output can be connected to a
7107/7135-based DPM or any other ana-
logue-to-digital converter or op-amp stage.
Use a buffer at the output if the output has to
be loaded by a load less than 1 meg-ohm.
Use an inverting buffer if input leads
have to have polarity where ground is the
inverting terminal. (For details, see next
circuit.)
(c) CD4052 CMOS switch
The on-resistance (100-ohm approx.)
comes in series with the op-amp output
source resistance, which produces no er
Truth Table (Control input VS attenuation)
X,Y (ON-switch (2) (1) Gain
Pair) B A (Attenuation)
X0,Y0 0 0 1/1000
X1,Y1 0 1 1/100
X2,Y2 1 0 1/10
X3,Y3 1 1 1
ror at output.
Caution. The circuit does not isolate,
it only attenuates. When high voltage is
present at its input, do not touch any part
of the circuit.
(d) Digital control options
(i) A and B can be controlled by I/O
port of a microcontroller like 80C31 so that
the controller can control gain.
(ii) A and B can be given to counters
like 4029/4518 to scroll gain digitally.
(iii) A and B can be connected to DIP
switch.
(iv) A and B can be connected to a
thumbwheel switch.
Notes. 1. Digital input logic 0 is 0V and
logic 1 is 5V.
2. All resistors are metal lm resistors
(MFR) with 1% tolerance, unless speci ed
otherwise.
3. C2 and C3 are ceramic disk capaci-
tors of 0.1µF = 100nF value.
The gain selection resistors R3
to R6 can be selected by the user and
can be anywhere from 1 kilo-ohm to 1
meg-ohm. Trimpots can be used for obtain-
ing any value of gain required by the user.
The resistor values shown in the circuit
are for decade gains suitable for an autor-
anging DPM.
Resistor R1 and capacitor C1 reduce
ripple in the input and also snub tran-
sients. Zeners Z1 and Z2 limit the input to
±4.7V, while the input current is limited
by resistor R1. Capacitors C2 and C3 are
the power supply decoupling capacitors.
Op-amp IC1 is used to increase the
input impedance so that very low inputs
are not loaded on measurement. The user
can terminate the inputs with resistance
of his choice (such as 10 meg-ohm or 1
meg-ohm) to avoid oating of the inputs
when no measurement is being made.
IC5 is used as an inverting buffer
to restore polarity of the input while
IC4 is used as buffer at the output
of CD4052, because loading it by
RANDOM NUMBER GENERATOR
BASED GAME
T
his electronic game is simulation
of one-arm bandit game. Elec-
tronics hobbyists will nd it very
interesting. When toggle switch S1 is in
resistance of value less than 1 meg- pin-compatible) in place of OP07 and use ±7.5V
ohm will cause an error. An alterna- instead of ±5V supply.
tive is to make R9=R10=1 meg-ohm Eight steps for gain or attenuation can
and do away with IC4, though this be added by using two CD4051 and pin
may not be an ideal method. 6 inhibit on CD4051/52. More steps can
be added by cascading many CD4051, or
Truth Table (Control Input vs Gain) CD4052, or CD4053 ICs, as pin 6 works
X,Y (On-switch (2) (1) Gain like a chip select.
Pair) B A (Av.) Some extended applications of this
X0,Y0 0 0 1/10 circuit are given below.
X1,Y1 0 1 1
1. Error correction in transducer am-
X2,Y2 1 0 10
X3,Y3 1 1 100 pli ers by correcting gain.
2. Autoranging in DMM.
3. Sensor selection or input type selec-
Gains greater than 100 may not be practi- tion in process control.
cal because even at gain value of 100 itself, 4. Digitally preset power supplies or
a 100µV offset will work out to be around 10 electronic loads.
mV at the output (100µV x 100). This can be 5. Programmable precision mV or mA
trimmed using the offset null option in the sources.
OP07, connecting a trimpot between pins 1 6. PC or microcontroller or microproc-
and 8, and connecting wiper to +5V supply essor based instruments.
rails. For better performance, use ICL7650 (not 7. Data loggers and scanners.
K. UDHAYA KUMARAN
‘run’ position, all segments of 7-segment tinue advancing and the final display
displays (DIS1 through DIS3) will light is unpredictable. Thus the nal number
up. On turning toggle switch S1 from ‘run’ displayed in DIS1 through DIS3 is of
to ‘stop’ position, displayed digits will con- random nature. The speed with which
ELECTRONICS PROJECTS Vol. 22 123
the number in 7-segment display keeps
changing on ipping switch S1 from run
to ‘stop’ condition slowly decays before
stopping with a random number display.
To play this game, one has to obtain
three identical numbers in displays DIS1
through DIS3. The contestant would
score 1 (one) point if he manages to get a
nal display of 000 , 2 points for getting
‘111’ display, 3 points for ‘222’,… and so
on—up to ten points for ‘999’. He should
try to score maximum possible points in
xed numbers of attempts (say, 20 to 25
attempts).
Apart from using this circuit as
a game for entertainment, one can use
it as random number generator for
any other application as well. The
decay time with the given component
values is around 15 seconds before the
display could stop at a final random
number.
The circuit comprises clock oscillator
built around NE555 timer IC4, three- timing capacitor C3 to change the op- by 1 for every positive clock transition.
stage clock pulse counter built using three erating frequency of the astable from Reset pin 15 of all counter ICs is held low
CD4033 ICs (IC1 to IC3), and three 7-seg- around 35 kHz to around 65 Hz. Now through resistor R25. Thus reset facility
ment LED displays (DIS1 to DIS3). capacitor C1 slowly starts charging as is not used in this circuit.
In clock oscillator circuit, NE555 it is connected in the discharge path Due to persistence of vision, one can-
timer IC4 is used in a similar way as a of the timing capacitors C3 and C4. not distinguish 0-9 counting in DIS1 to
free-running astable multivibrator, the The clock frequency of IC4 gradually DIS3 when the clock frequency is high.
only difference being the additional ca- reduces and after 15 seconds, when All 7-segment displays appear to show
pacitor C1 introduced between pin No. 7 capacitor C1 is sufficiently charged, digit 8, while the red LED1 remains lit
of IC4 and junction of resistors R22 and the oscillating frequency gradually continuously, indicating clock counter is
R24. When toggle switch S1 is in ‘run’ po- drops and finally it stops oscillating. in running condition.
sition, both terminals of capacitor C1 are Thus, pin 3 of IC4 becomes low. On sliding toggle switch S1 from
shorted by switch S1 and timer IC4 works Second part of the circuit comprises ‘run’ to ‘stop’ position, the counting
as a free-running astable multivibrator. three cascaded ICs, IC1 through IC3 speed of individual digits falls immedi-
The operating frequency is in the vicin- (CD4033 decade upcounter cum 7-seg- ately due to the clock frequency chang-
ity of 35 kHz, determined by the value of ment decoder). In conjunction with three ing to around 65 Hz. Now, the counting
timing components. 7-segment displays (DIS1 to DIS3), these speed will be 65 Hz for DIS3, 6.5 Hz for
When toggle switch S1 is flipped form a 3-digit clock counter. The clock DIS2, and 0.6 Hz for DIS1. This speed of
from ‘run’ to ‘stop’ position, capacitor counting speed is dependant upon the individual digit counting slowly decays,
C1 is introduced in the discharge path clock pulse frequency of IC4. It is con- until the counter stops and LED1 stops
of pin No. 7 of IC4 and junction of re- nected to clock input pin 1 of IC1 while blinking, and the nal count (random
sistors R22 and R24. At the same time, chip enable pin 2 of IC1 to IC3 are held numbers) are displayed in DIS1, DIS2,
capacitor C4 comes in parallel with low. Thus all clock counter ICs advance and DIS3.

9-LINE TELEPHONE SHARER

DHURJATI SINHA

T
his circuit is able to handle nine
independent telephones (using a
single telephone line pair) located
at nine different locations, say, up to a
distance of 100m from each other, for re- line is to be shared by more members re-
ceiving and making outgoing calls, while siding in different rooms/apartments.
maintaining conversation secrecy. This Normally, if one connects nine phones
circuit is useful when a single telephone in parallel, ring signals are heard in all

124 ELECTRONICS PROJECTS Vol. 22


the nine telephones (it is also possible that
the phones will not work due to higher
load), and out of nine persons eight will
nd that the call is not for them. Further,
one can overhear others’ conversation,
which is not desirable. To overcome these
problems, the circuit given here proves
bene cial, as the ring is heard only in the
desired extension, say, extension number
‘1’.
For making use of this facility, the
calling subscriber is required to ini-
tially dial the normal phone number
of the called subscriber. When the call
is established, no ring-back tone is
heard by the calling party. The call-
ing subscriber has then to press the
asterik (*) button on the telephone to
activate the tone mode (if the phone
normally works in dial mode) and dial
ceiver CM8870 (IC3) outputs
code ‘0001’, which is fed to the
4-bit BCD-to-10 line decimal
decoder IC4 (CD4028). The
output of IC4 at its output
pin 14 (Q1) goes high and
switches on the SCR (TH-1)
and associated relay RL1.
Relay RL1, in turn, connects,
via its N/O contacts, the 50Hz
extension ring signal, derived
from the 230V AC mains, to
the line of telephone ‘1’. This
ring signal is available to tele-
phone ‘1’ only, because half of
the signal is blocked by diode
D1 and DIAC1 (which do not
conduct below 35 volts).
As soon as phone ‘1’ is
lifted, the ring current in-
creases and voltage drop
across R28 (220-ohm, 1/2W
resistor) increases and oper-
ates opto-coupler IC5 (MCT-
2E). This in turn resets timer
IC2 causing:
(a) interruption of the
power supply for processing
circuitry as well as the ring
signal relays RL1 through
RL9, and
(b) removal of loop re-
sistance R16, via the second
contact of relay RL10.
As a result, the telephone
line voltage shoots up to 48V,
DIAC1 and diode D1 con-
nected in series with phone
1 conduct within a few mil-
liseconds, and phone 1 comes
into operation. The telephone
exchange does not interpret
extension number, say, ‘1’, within 10 sec-
this as break in off-hook condition, since
onds. (In case the calling subscriber fails
some delay margin is set at exchange.
to dial the required extension number
When phone ‘1’ is busy, the other
within 10 seconds, the line will be discon-
eight phones will not work, since line
nected automatically.) Also, if the dialed
voltage will again drop to 10V and the
extension phone is not lifted within 10
other diacs will not conduct. Thus conver-
seconds, the ring-back tone will cease.
sation secrecy will be maintained.
The ring signal on the main phone
The other extensions also work in a
line is detected by opto-coupler MCT-
similar manner when another extension
2E (IC1), which in turn activates the
number is dialed and its corresponding
10-second ‘on timer’, formed by IC2 (555),
relay energises to extend the 50Hz ring
and energises relay RL10 (6V, 100-ohm,
to another extension.
2 C/O). One of the ‘N/O’ contacts of the
The 24V, 50Hz ring signal derived
relay has been used to connect +6V rail
from transformer X1 is suf cient for
to the processing circuitry and the other
working with phones of Beetel and ITI
has been used to provide 220-ohm loop re-
make, but for Pretel and some other
sistance to de-energise the ringer relay in
makes, it may be necessary to increase
telephone exchange, to cut off the ring.
the ring voltage to about 30 volts or even
When the caller dials the extension
higher.
number (say, ‘1’) in tone mode, tone re-
ELECTRONICS PROJECTS Vol. 22 125
 ELECTRONIC CARD LOCK SYSTEM
PRIYANK MUDGAL

T
his circuit of electronic card lock
system is much simpler and
cheaper than other similar circuits
that have appeared in earlier issues of
EFY.
The circuit is configured around
an addressable 1 of 16 demultiplexer
CD4514B (IC1). Any number in binary
form, when available at input pins 2,
3, 21, and 22 (address pins A0 through
A3), makes corresponding output go logic
high, thus turning on the appliance
through relay contacts. Up to 15 appli-
ances can be switched on/off (one at a
time). Output Q0 (pin 11) can be used
for visual indication, to show that circuit
is active.
A 40W bulb illuminates LDR1
result, transistor T1 conducts and ex-
tends positive supply to the collectors of
transistors T2 through T5. Then, depend-
ing upon the holes blocked/punched in
the inserted card, any combination of
emitters of transistors T2 through T5
turns logic ‘high’ (transistors’ output
corresponding to blocked LDRs only goes
‘high’). These outputs connected to address
input pins A0 through A3 of IC1

TABLE I
Appliance LDR2 LDR3 LDR4 LDR5
no.
1 - * * *
2 * - * *
3 - - * *
4 * * - *
5 - * - *
6 * - - *
7 - - - *
8 * * * -
9 - * * -
10 * - * -
11 - - * -
12 * * - -
13 - * - -
14 * - - -
15 - - - -
- Blocked hole corresponding to selected
binary address.
* Punched holes corresponding to LDR posi-
tion on card

switch on the corresponding appliance

to LDR5 (one out of 15).
constantly. The card used should be of opaque
This pulls plastic. It should be able to withstand
down bases some heat from the bulb, even though the
of transis- appliance remains ‘on’ only for the period
tors T1 for which the card is in the slot.
through T5 The card has a triangular notch that
to ground. shows correct orientation/direction of
LDR1 en- insertion of card and prevents false op-
sures that card is prop- eration. LDRs can be placed in a line, or
erly inserted into the randomly, to increase security.
card slot. The order in which holes should be
When the card is punched for each appliance is given in
correctly inserted, it Table I. Two illustrations, one each for
covers the hole/open- card-2 and card-5, are shown in the ac-
ing for LDR1 and thus companying gures. An elevation and
blocks the light from plan/top view of the gadget is also shown
falling on LDR1. As a in the gures.

126 ELECTRONICS PROJECTS Vol. 22

 PULSED OPERATION
OF A CW LASER DIODE
H
ere a simple low-cost technique
for converting a CW laser di-
ode at 670 nm wavelength to
pulsed laser up to a frequency of 500 kHz
is presented.
A low-power pulsed radiation source
is very important for any laboratory in-
volved in optical pulsed systems—laser,
DR. ALIKA KHARE
pulsed discharges, optical communication,
fibre-optic sensors, image processing,
etc—where one is required to check the
frequency response of the detection system
or optical simulation of an optical source
or local networking using optical bre
cable. Fast-speed LED offers the solu-
tion for such requirements, but because
of very low power and large
divergence, its use remains
limited. On the other hand,
a pulsed diode laser offers
a very good solution for this
problem.
Commercial systems are
usually expensive. However,
a CW diode laser operating
at 670 nm can easily be
pulsed up to a frequency of
500kHz with low-cost technique, using
a function generator and an inexpensive
push-pull ampli er interface circuit. The
block diagram of the system is shown in
Fig. 1.
A 3mW CW diode laser at 670 nm
with voltage and current rating of 3V
at 100mA, respectively, is used. The
source (a function generator) is capable of
delivering square pulses of 3V amplitude,
which are ampli ed by a complementary
symmetry push-pull circuit shown in Fig.
2.
The output of the
amplifier is
connected to
the diode la-
ser for pulsed
operation.
The laser is
focused onto
a photodiode
terminated
with 50-ohm
resistor (Fig.
1). The out-
put of pho-
todiode is
displayed on
digital storage oscilloscope and it is also
connected to the PC for getting a hard
copy.
Up to a frequency of around 20 kHz,
the threshold voltage for laser oscillations
is around 2.4V. For frequencies greater
than 20 kHz, the threshold for laser
oscillations depends on the operating
frequency and is higher than 2.4V. The
behaviour of laser pulses up to 10 kHz is
nearly similar. Laser output at a typical
frequency of 2 kHz is shown in Fig. 3, at
various voltages (2.6V, 3.4V, and 4V). The
input waveform ‘A’ is shown at the bottom
of the gure.
For a driving pulse of about 3V (which
is the normal operating voltage for CW
operation), the laser pulse becomes at
after a delay of approximately 40 µs (time
taken to build up the laser oscillations
to its maximum amplitude). Above 3V,
probably population inversion is devel-
oped much above threshold, before the
laser oscillations build up into the cavity,
and so we observe the sharp peak in laser
output (for more details, refer Laser Fun-
damentals book by W. T. Silfvast, pub-
lished by Cambridge University Press),
exponentially decaying to a steadystate
value with a time constant depending on
the initial peak intensity and the carrier
life time in the excited state. After the
ELECTRONICS PROJECTS Vol. 22 127
input pulse is over, the oscillations die
down within 5 µs.
Therefore above 3V, up to a fre-
quency of 10 kHz, the laser is operated
in quasi CW mode. In the frequency
range of 10 kHz to 50 kHz, the laser
output keeps on increasing, even dur-
ing the flat portion of the input current
pulse, and falls down to zero during the
off period of the driving pulse. Fig. 4
GENERATION OF 1-SEC. PULSES
SPACED 5-SEC. APART
T
his circuit using a dual-timer
NE556 can produce 1Hz pulses
spaced 5 seconds apart, either
manually or automatically. IC NE556
comprises two independent NE555 timers
in a single package. It is used to produce
two separate pulses of different pulse
widths, where one pulse initiates the acti-
vation of the second pulse.
The rst half of the NE556 is wired
for 5-second pulse output. When slide
switch S2 is in position a , the rst
timer is set for manual operation, i.e.
by pressing switch S1 momentarily
you can generate a single pulse of 5-sec-
ond duration. When switch S2 is kept in
‘b’ position, i.e. pins 6 and 2 are shorted,
128 ELECTRONICS PROJECTS Vol. 22
shows the laser waveforms at 50 kHz,
100 kHz, 200 kHz, 300 kHz, and 500
kHz, respectively.
All these pulses were recorded at
around 4V. In this range of frequencies,
the duration for which voltage is on/off
is of the order of less than 5 µs, and so
the driving pulses switch off before the
termination of laser oscillations. There-
fore the laser output shows a modulation
PRAVEEN SHANKER
timer 1 in NE556 triggers by itself.
The output of the rst timer is con-
nected to trigger pin 8 of second timer,
which, in turn, is connected to a potential
divider comprising resistors R4 and R5.
Resistor R1, preset VR1, resistor R2,
preset VR2, and capacitors C2 and C5 are
the components determining time period.
Presets VR1 and VR2 permit trimming of
the 5-second and 1-second pulse width of
respective sections.
When switch S2 is in position ‘a’
and switch S1 is pressed momentarily,
the output at pin 5 goes high for about
5 seconds. The trailing (falling) edge of
this 5-second pulse is used to trigger
the second timer via 0.1µF capacitor
with the DC component in it. Beyond
500 kHz, it is difficult to observe laser
oscillations even at voltages higher
than 4V.
Lab note. Tests conducted at EFY
using laser diode of laser torch (rated for
<5mW) with identical inputs at 2 kHz did
not show any marked departure of output
waveform (square wave) from the input
square wave.
C6. This action results in momentar-
ily pulling down of pin 8 towards the
ground potential, i.e. ‘low’. (Otherwise
pin 8 is at 1/2 Vcc and triggers at/below
1/3 Vcc level.) When the second timer is
triggered at the trailing edge of 5-second
pulse, it generates a 1-second
wide pulse.
When switch S2 is on posi-
tion ‘b’, switch S1 is discon-
nected, while pin 6 is connected
to pin 2. When capacitor C2
is charged, it is discharged
through pin 2 until it reaches
1/3Vcc potential, at which it is
retriggered since trigger pin 6 is
also connected here. Thus timer
1 is retriggered after every
5-second period (corresponding
to 0.2Hz frequency). The second
timer is triggered as before to
produce a 1-second pulse in
synchronism with the trailing
edge of 5-second pulse.
This circuit is important wherever a
pulse is needed at regular intervals; for
instance, in ‘Versatile Digital Frequency
Counter Cum Clock’ construction project
published in EFY Oct. ’97 (or Electronics
Projects Vol. 18), one may use this circuit
in place of CD4060-based circuit. For
the digital clock function, however, pin 8
and 12 are to be shorted after removal of
0.1µF capacitor and 10-kilo-ohm resistors
R4 and R5.
 HIGH-/LOW-VOLTAGE
CUTOUT WITH TIMER
T
his inexpensive circuit can be
connected to an air-conditioner/
fridge or to any other sophisticated
electrical appliance for its protection.
Generally, costly voltage stabilisers are
used with such appliances for maintain-
ing constant AC voltage. However, due to
uctuations in AC mains supply, a regular
‘click’ sound in the relays is heard. The
frequent energisation/de-energisation of
the relays leads to electrical noise and
shortening of the life of electrical appli-
ances and the relay/stabiliser itself. The
costly yet fault-prone stabiliser may be
replaced by this inexpensive high-low
cutout circuit with timer.
The circuit is so designed that relay
RL1 gets energised when the mains
voltage is above 270V. This causes re-
sistor R8 to be inserted in series with
the load and thereby dropping most of
the voltage across it and limiting the
current through the appliance to a very
low value.
If the input AC mains is less than 180
volts or so, the low-voltage cut-off circuit
interrupts the supply to the electrical ap-
pliance due to energisation of relay RL2.
After a preset time delay of one minute
(adjustable), it automatically tries again.
If the input AC mains supply is still low,
the power to the appliance is again inter-
DR D.K. KAUSHIK
rupted for another one minute, and so
on, until the mains supply comes within
limits (>180V AC). The AC mains supply
is resumed to appliance only when it is
above the lower limit.
When the input AC mains increases
beyond 270 volts, preset VR1 is adjusted
such that transistor T1 conducts and
relay RL1 energises and resistance
R8 gets connected in series with the
electrical appliance. This 10-kilo-ohm,
20W resistor produces a voltage drop
of approximately 200V, with the fridge
as load.
The value and wattage of resistor R8
may be suitably chosen according to the
electrical appliance to be used. It is
practically observed that after con-
tinuous use, the value of resistor R8
changes with time, due to heating. So
adjustment of preset VR1 is needed two
to three times in the beginning. But once
it attains a constant value, no further
adjustment is required. This is the only
adjustment required in the beginning,
which is done using a variac.
Further, the base voltage of transis-
tor T2 is adjusted with the help of pre-set
VR2 so that it conducts up to the lower
limit of the input supply and cuts off
when the input supply is less than this
limit (say, 180V). As a result, transis-
tor T3 remains cut off (with its collector
remaining high) until the mains supply
falls below the lower limit, causing its
collector voltage to fall. The collector of
transistor T3 is connected to the trigger
point (pin 2) of IC1.
When the input is more than the lower
limit, pin 2 of IC1 is nearly at +Vcc. In
this condition the output of IC1 is low,
relay RL2 is de-energised and power is
supplied to the appliance through the N/C
terminals of relay RL2.
If the mains supply is less than the
lower limit, pin 2 of IC1 becomes momen-
tarily low (nearly ground potential) and
thus the output of IC1 changes state from
‘low’ to ‘high’, resulting in energisation
of relay RL2.
As a result, power
to the load/appli-
ance is cut off.
Now, capacitor
C2 starts charg-
ing through resis-
tor R6 and preset
VR3. When the
capacitor charges
to (2/3)Vcc, IC1
changes state
from ‘high’ to
‘low’. The value
of preset VR3 may be so adjusted that it
takes about one minute (or as desired) to
charge capacitor C1 to (2/3)Vcc. Relay is
now de-energised and the power is sup-
plied to the appliance if the mains supply
voltage has risen above the lower cut-off
limit, otherwise the next cycle repeats
automatically.
One additional advantage of this
circuit is that both relays are de-
energised when the input AC mains
voltage lies within the speci ed limit
and the normal supply is extended to
the appliance via the N/C contacts of
both relays.
ELECTRONICS PROJECTS Vol. 22 129
 AUTOMATIC
HEAT DETECTOR
SUKANT KUMAR BEHARA

T
his circuit uses a complementary To test the working of the circuit, bring conducting. Simultaneously, transistor
pair comprising npn metallic tran- a burning matchstick close to transistor T2 also conducts because its base is con-
sistor T1 (BC109) and pnp germa- T1 (BC109), which causes the resistance nected to the collector of transistor T1. As
nium transistor T2 (AC188) to detect heat of its emitter-collector junction to go low a result, relay RL1 energises and switches
(due to outbreak of re, etc) in the vicinity due to a rise in temperature and it starts on the siren circuit to produce loud sound
and energise a siren. The collector of tran- of a rebrigade siren.
Pin Designation Sound Effect
sistor T1 is connected to the base of tran- Lab note. We have added a
SEL1 SEL2
sistor T2, while the collector of transistor table to enable readers to obtain
No Connection No Connection Police Siren
T2 is connected to relay RL1. +3V No Connection Fire Engine Siren all possible sound effects by re-
The second part of the circuit com- Ground No Connection Ambulance Siren turning pins 1 and 2 as suggested
prises popular IC UM3561 (a siren and Do not care +3V Machine Gun in the table.
machine-gun sound generator IC), which
can produce the sound of a re-brigade
siren. Pin numbers 5 and 6 of the IC are
connected to the +3V supply when the re-
lay is in energized state, whereas pin 2 is
grounded. A resistor (R2) connected across
pins 7 and 8 is used to x the frequency of
the inbuilt oscillator. The output is avail-
able from pin 3.
Two transistors BC147 (T3) and
BEL187 (T4) are connected in Darlington
con guration to amplify the sound from
UM3561. Resistor R4 in series with a 3V
zener is used to provide the 3V supply to
UM3561 when the relay is in energised
state. LED1, connected in series with
68-ohm resistor R1 across resistor R4,
glows when the siren is on.

Readers’ comments: EFY: transistor BC108 in place of BC109, and

 I have tried to construct the circuit,
which failed to respond even after sup-
plying heat for a long time. How can one
check the transistor if the relay does not
operate? Can you suggest me an alterna-
tive for transistor T1? Please help.
Saket
Through e-mail
 In the project, on heating the base of
transistor T1, the circuit does not work.
I was even more surprised to see that the
circuit had been ‘EFY Tested.’
Manish Poudwal
Through e-mail
In reply to Saket:
The circuit has been tested and there
is nothing wrong in the circuit. To test the
transistor, take a lighted matchstick (or
candle) close to the BC109 (or the BC549).
(For higher ampli cation, use BC109C or
BC549C.) The relay should energise via
the ampli er comprising complementary
pair of transistors T1 and T2. When you
gradually withdraw the candle or burning
matchstick, the brightness of the LED
will gradually decrease and it will nally
go off.
We have also tried the circuit with
it worked well.
In reply to Manish Poudwal:
All the circuits are undoubtedly tested
and records maintained. If you have not
been able to achieve the results, there
is likely to be some aw. You may have
used a silicon transistor for AC188. Note
that AC188 is a germanium transistor (in
metal can). Please check.
Response from the reader: As guessed
correctly by you, I was using a silicon
transistor AC188 instead of germanium
transistor. Now the circuit does work.

130 ELECTRONICS PROJECTS Vol. 22

 MUSICAL ‘TOUCH’ BELL
H
ere is a musical call bell that can
be operated by just bridging the
gap between the touchplates with
one s ngertips. Thus there is no need
for a mechanical ‘on’/‘off’ switch because
the touch-plates act as a switch. Other
features include low cost and low power
consumption. The bell can work on 1.5V
or 3V, using one or two pencil cells, and
can be used in homes and of ces.
Two transistors are used for sensing
the nger touch and switching on a melody
IC. Transistor BC548 is npn type while
Readers’ comments:
 The circuit starts ringing (without
touching the screw) when connected to
3V. On disconnecting points 1 and 2 (kept
open), I still received the ring. Why so?
A. Vaidhyanathan
NON-CONTACT
LIQUID-LEVEL CONTROLLER
E
FY readers are quite familiar with
liquid-level controllers. But the
one presented here is different.
Usually, transducers using electric con-
SUKANT KUMAR BEHARA
transistor BC558 is pnp type.
The emitter of transistor BC548 is
shorted to the ground, while that of tran-
sistor BC558 is connected to the positive
terminal. The collector of transistor BC548
is connected to the base of BC558. The
base of BC548 is connected to the washer
(as shown in the gure). The collector of
BC558 is connected to pin 2 of musical IC
UM66, and pin 3 of IC UM66 is shorted
to the ground. The output from pin 1 is
connected to a transistor ampli er com-
prising BEL187 transistor for feeding the
Pollachi
The author, Sukant Kumar Behara,
replies:
You can rectify this snag by changing
transistor T1 (BC148) with a new one.
On touching the base of transistor T1, its
R.G. THIAGARAJ KUMAR
duction, or variation in resistance or
capacitance principle, are employed for
level sensing.
In conduction type of sensors, the elec-
loudspeaker. One end of 2.2-mega-ohm
resistor R1 is connected to the positive rail
and the other to a screw (as shown in the
gure). The complete circuit is connected
to a single pencil cell of 1.5V.
When the touch-plate gap is bridged
with a nger, the emitter-collector junc-
tion of transistor BC548 starts conduct-
ing. Simultaneously, the emitter-baser
junction of transistor BC558 also starts
conducting. As a result, the collector of
transistor BC558 is pulled towards the
positive rail, which thus activates melody
generator IC1 (UM66). The output of IC1
is ampli ed by transistor BEL187 and fed
to the speaker. So we hear a musical note
just by touching the touch points.
The washer’s inner diameter should
be 1 to 2 mm greater than that of the
screwhead. The washer could be xed in
the position by using an adhesive, while
the screw can be easily driven in a wooden
piece used for mounting the touch-plate.
The use of brass washer and screw is rec-
ommended for easy solder-ability.
emitter-collector junction starts conduct-
ing. But you’ve mentioned that even with-
out touching the base of transistor T1, the
bell starts ringing, which means that the
emitter-collector junction of the transistor
has got shorted internally.
tric current passes through the liquid. The
corrosion of contacts is a major problem
while using DC excitation. The cost and
the size are the two restrictive factors
ELECTRONICS PROJECTS Vol. 22 131

in using AC excitation. Further, passing
current through the liquid in combustive
environments is not permissible.
In resistance type sensors, the resist-
ance is altered through some mechani-
cal arrangement, which means a large
operating force is required, which may be
a problem in small tanks. In capacitive
transducer type, the construction cost is
high.
In the present project, an easy but ef-
fective liquid-level controller is presented
using the magnetic principle. It is non-con-
tact type and hence can be used in almost
all applications, irrespective of whether
the liquid is conductive or not. Two reed
switches (with glass enclosure) and a ring
Readers’ comments:
 The circuit is indeed very effective and
accurate, while being very simple and
straightforward. Congratulations to the
author!
Based on this circuit, I successfully
arranged a number of reed switches us-
ing a 24-lead at cable inside a PVC tube,
132 ELECTRONICS PROJECTS Vol. 22
magnet (normally used in loud-speakers)
form the sensor unit. The reed switches
used are normally-open type and they
close when placed (and oriented properly)
in a magnetic eld.
The electronic circuit is a simple bist-
able multivibrator wired around the com-
mon 555 timer IC. It can be set or reset by
the closure of reed switches. The output of
the multivibrator drives the relay, which
controls the AC mains supply to the pump
motor or any other controller (such as a
solenoid-operated valve).
The reed switches are connected as
shown in the gure. These are put in a
closed (non-conductive) tube, which is
then placed in the tank. The ferrite ring
for monitoring a vehicle’s fuel tank level.
Since the idea of using an electric conduc-
tion method is out of question with petrol,
I was agonisingly pondering over various
alternatives. The idea given by Mr Kumar
is what exactly I was looking for.
M.K. Chandra Mouleeswaran
Tamil Nadu
magnet is put inside the
oat, and it moves up and
down along the tube de-
pending upon the level of
the liquid in the tank.
When the level of the
liquid in the tank is low,
the magnet comes closer
to reed switch S2. As a
result, switch S2 is closed
+
and the bistable multi-
vibrator sets. This actu-
ates the relay, thereby
starting the pump to ll
the tank. The level of the
liquid in the tank starts
increasing.
When the level of the
liquid in the tank is high enough,
the ring magnet comes close to
reed switch S1, and it closes. The
bistable multivibrator now resets
and the pump is switched off.
This process is repeated and the
tank gets lled automatically.
Switches S1’ and S2’ are
used for testing the circuit or
when the reed switches are non-
functional. A neon bulb is used to
indicate the presence of the AC
supply in the plug. An optional
piezobuzzer is used to raise an
audible alarm when the relay
energises.
If you desire to display the
level of the liquid in the tank, additional
reed switches would need to be placed in-
side the tube at different levels (say, 1/4th,
1/2, 3/4th, and near-over ow level). They
can be connected between the LEDs and
the supply via current-limiting resistors
for level indication. The LEDs can be ar-
ranged in a model tank diagram printed
on the front panel of the controller. The
LED corresponding to the level of the
liquid in the tank would glow in this ar-
rangement.
The selection of oat material is to be
done carefully to avoid chemical reaction
and/or pollution of the liquid. Te on oats
are suitable for most applications.
 We are undergraduate students from a
leading University of Sri Lanka and have
constructed the project successfully.
The IC should function when both
switches S1 and S2 are open and the AC
supply is switched on, but we found that
it becomes on automatically. Also explain
the purpose of using diode D3 and capaci-
tor C2 in the circuit.
Menaha Shah and Colleagues
Through e-mail
EFY: During lab testing (with DC sup-
ply) we haven t noticed any such fault.
The stated fault could occur only if the
HIGH-POWER BICYCLE HORN
A
n interesting circuit of a bicycle
horn based on a popular, low-cost
telecom ringer chip is described
here. This circuit can be powered us-
ing the bicycle dynamo supply and does
not require batteries, which need to be
replaced frequently.
The section comprising diodes (D1
and D2) and capacitors (C1 and C2) forms
a half-wave voltage-doubler circuit. The
output of the voltage doubler is fed to ca-
pacitor C3 via resistor R1. The maximum
DC supply that can be applied to the input
AC MAINS PHASE-SEQUENCE
INDICATOR
A
mains phase-sequence indicator
serves as a hand-tool in checking
electrical wiring, especially the wiring
of three-phase AC motors.
gap between reed switch contacts is too
small. Try placing 0.1µF capacitor across
resistors R1 and R2 to bypass any noise
surge at switching on as it may trigger
the timer.
Diode D3 acts as a free-wheeling diode
T.K. HAREENDRAN
terminals of IC1 is 28V. Therefore zener
diode ZD1 is added to the circuit for pro-
tection and voltage regulation.
The remainder of the circuit is the
M.K. CHANDRA MOULEESWARAN
The basic idea of the circuit is that
when any (say, Y) of the three phases
(RYB), taken as a reference phase, is at
negative-going zero voltage, its leading
to dissipate the stored energy in the relay
coil when the transistor suddenly cuts off
and the magnetic eld collapses. Capacitor
C2 at control pin 5 of timer 555 is used as
a lter capacitor when the timer is used in
noisy environments.
tone generator based on IC1 (KA2411).
The dual-tone output signal from pin 8 of
IC1 is fed to the primary of transformer
X1 (same as used in transistor radios) via
capacitor C6. The secondary of X1 is con-
nected to a loudspeaker directly.
In case you are interested in connect-
ing a piezoceramic element in place of the
loudspeaker, remove capacitor C6, trans-
former X1, and the loudspeaker. Connect
one end of the piezoceramic disk to pin 5
of IC1 and the other end to pin 8 of IC1
through a 1/4W, 1-kilo-ohm resistor.
IC1 KA2411 is also available in COB
style, with the same pin con guration.
Both packages work equally well. How-
ever, to get the best results with the COB
package, change values of resistors R2
through R4 to 330-kilo-ohm, capacitor C4
to 0.47µF, 63V electrolytic (positive end to
pin 3 of IC1), and C5 to 0.005µF, 63V.
This bicycle horn project can also be
used as a telephone extra ringer by just
removing all components on the left side
of capacitor C3 and connecting the circuit
shown in Fig. 2 to the terminals of capaci-
tor C3.
phase (say, R) is positive while its lagging
phase (B) is negative, and these states can
be easily veri ed.
The circuit comprises two main parts.
ELECTRONICS PROJECTS Vol. 22 133
 The first part The astable multivibrator section
comprises provides clock pulses in the 10 to 1000Hz
transistorised range to the decade counter and the LED
multivibrator, array section. The LEDs are grouped into
decade counter- two parts to form two distinctive indica-
cum-LED driver, tors. These two groups are successively
and LED arrays driven by Q0 to Q4 and Q5 to Q9 outputs
arranged in a of IC1. Only one of the two groups’ LEDs
specified fash- will turn on sequentially, depending on
ion, as shown in which of the two transistors (transistor
the figure. The T3 or transistor T4) is on, which, in turn,
second part com- is dependent upon the phase sequence
prises the phase- of the three-phase supply. This becomes
sequence detec- clear from the following explanation of the
tor followed by second part of the circuit.
phase-sequence The three phases (R, Y, and B) are
sensor operat- brought to an arti cial neutral at the
ed flip-flop and junctions of resistors R17 through R19
LED switching (each 22 kilo-ohm, 2-watt) to serve as
transistors. the common reference. As stated earlier,

for a given phase sequence,

when phase R is at its neg-
ative-going zero, phase B is
negative. So data-input pin
5 of the ip- op (IC2) is logic
‘high’ (due to non-conduction
of transistor T5). Meanwhile,
clock-input pin 3 of the ip-
op goes from low to high due
to phase R (refer waveforms
for condition 1, as observed
by EFY Lab). The ‘high’ at
data pin appears at the Q
output (pin 1) while Q output
remains ‘low’ as long as the

134 ELECTRONICS PROJECTS Vol. 22

phase sequence is clockwise. Therefore
the Q output drives transistor T3 to ex-
tend the ground path for green LEDs D1
through D10 to show a clockwise-rotating
LED ring.
When any of the two phases gets
interchanged (say, after a maintenance
work at the power-house or repair/re-
placement of a 3-phase transformer), the
conditions are reversed (refer waveform
for condition 2, as observed by EFY Lab),
and Q become ‘high’ and red LEDs D11
through D20 are switched on (sequentially)
LUXURIOUS TOILET/
BATHROOM FACILITY
Ag
ed persons in the house and
guests often fumble while search
ing for the toilet and bath-
room switches at night. Also, very few
of us take care to switch off the lights of
toilets/bathrooms after using them. The
circuit given here helps to overcome both
the problems.
The gure shows two symmetrical
by transistor T4 to show an anticlockwise-
rotating ring.
While testing for the phase sequence,
there is no need to keep the device on for
a long time. A push-to-on read switch
can be used during the phase-sequence
testing. If the device is to be used for
long periods, use a high-capacity battery
in place of PP3 battery. Also replace 2W
resistors R17 to R19 with 5W fusible-type
resistors.
The frequency of the astable multi-
vibrator is unimportant, except that the
A.R. GIDWANI
circuits (one each for toilet and bath-
room) sharing common power supply and
a melody generator-cum-audio warn-
ing unit. The reed switches S1 and S2
are of normally-open type, operated by
permanent magnets appropriately xed
to the doors of bathroom and toilet, re-
spectively. When the doors of bathroom
and toilet are closed, the reed switches
speed of the LED ring must be easily vis-
ible. Zener diodes ZD1 and ZD2 are used
for protection of transistors T5 and T6,
respectively.
Precautions. 1. Never use an AC
mains adaptor-type power supply in place
of the battery.
2. Correctly position LEDs D1 through
D20 in the ring for its proper viewing.
3. Assemble resistors R11 to R19 on
the PCB at a slightly elevated level us-
ing ceramic beads for proper dissipation
of heat.
are also closed, and vice versa. (Door is
assumed in closed condition with nobody
inside bathroom/toilet, i.e. reed switch is
activated.)
The operational features of the circuit
are:
Lamp and exhaust fan are switched
on when the door is opened.
Soft music is played continuously
ELECTRONICS PROJECTS Vol. 22 135

until the door is closed from inside/out-
side.
With a person inside the room,
lamp and fan remain on, until the door
is reopened. They go off when the door is
reopened.
Visual indication of whether the
toilet/bathroom is occupied/vacant is given
by two bicolour LEDs xed on a panel,
which may be tted near the door with
corresponding ‘toilet’/‘bathroom’ labels
on them. Here the LED colour turns from
‘green’ to ‘red’ if the room gets occupied,
and vice-versa.
If the door is opened once, and not
closed back within 10 seconds, the lamp
and fan are automatically switched off,
thus conserving electricity. But the music
remains on as a reminder that the door is
not closed.
For cleaning of bathroom/toilet with
doors kept open, a parallel on/off switch is
included on the switchboard to bypass the
relay contacts and manually control the
switching on/off of the light and exhaust
fan. (This is the service mode.) In this
case, the music remains on as long as the
door remains open. In case of failure of the
unit, the same on/off switch can be used as
usual until the circuit is repaired.
Due to battery backup facility,
even with power failure, when a person
is inside, the door status is maintained.
However, the lamp and fan will be on only
on mains resumption.
EEPROM W27C512
(WINBOND) ERASER
E
PROMs (electrically erasable
PROMs) are generally erased by
ultraviolet rays, and it takes half
an hour or so to erase the data in an
136 ELECTRONICS PROJECTS Vol. 22
Also, when a person leaves the room
during power failure, with door closed, the
lamp and fan are kept off on resumption of
power. (Intelligent-mode!)
However, the circuit can be fooled
by opening and closing the door within
10 seconds, without entering inside. In
this case, the lamp and fan will continue
to be on and would require reopening and
closing of the door to bring the circuit to
order.
This problem can be prevented to
some extent by using a hydraulic door
opener, which would approximately take
10 seconds to close the opened door. A
delay period of 10 seconds is deliberately
chosen for letting the person inside the
toilet/bathroom in normal case!
IC1 is a dual positive edge-triggered ‘D’
type ip- op. IC1(a) gets triggered when
bathroom door (and switch S1) is opened
and hence IC1(b) toggles, as Q output of
IC1(a) is connected to clock input pin of
IC1(b). As a result, relay RL1 energises
through transistor T3, thereby switching
on the lamp and exhaust fan. (Please refer
to Fig. 2, the separate wiring diagram of
lamp and exhaust fan via the N/O contacts
of the relay.) Simultaneously, pin 2 (Q1) of
IC1(a) goes low, switching transistor T5
‘on,’ which switches on melody generator
IC4, letting out a sweet audio tune via
transistor T6 and loudspeaker.
In normal condition, when some-
one opens the bathroom door and gets
inside within preset time of IC3(a) (10
seconds here), and closes the door from
inside, the music stops with lamp and
fan ‘on.’ Now, in case someone opens
the door before or after use, and forgets
to shut it, the lamp and exhaust fan
are switched off after 10 seconds but
the music remains ‘on’ as a reminder
that the door is to be closed. This hap-
pens due to mono multivibrator (MMV)
J.P. SHARMA
ERPOM. Nowadays a special EEPROM
from Winbond is available in the market,
which is being used in telecommunica-
tion due to its low cost.
IC3(a), which resets pin 10 of IC1(b)
through transistor T1 after 10 seconds.
(This period can be adjusted by vary-
ing the values of resistor R11 and/or
capacitor C7.)
It should be noted here that although
IC3 is used as ‘MMV,’ it is triggered here
with a positive pulse through its pin 4
(reset pin) rather than its pin 6 (trigger
pin). This arrangement makes it unique
for setting and resetting IC3 through pin
4, and resetting IC1(a) through pin 5 of
IC3 and transistor T1.
Battery backup facility ensures mem-
ory backup during power failure. Power
supply uses a normal 2-diode full-wave
recti er circuit, which needs no further ex-
planation. The purpose of using bi-colour
LED1 and LED2 is that, initially when the
door is closed these emit green light—as
the green LED part gets the supply via
resistor R15—to indicate that bathroom/
toilet is vacant. When bathroom/toilet is
occupied, transistor T3/T4 conduct to light
up the red LED part as well.
Melody generator IC4 (UM66) is
switched on through diodes D3/D4 and
transistor T5, which conducts when IC1(a)
pin 2 or IC2(a) pin 2 goes low. When
transistor T5 conducts, zener ZD1 breaks
down and supplies regulated 3.9V to IC4,
to produce a melodious tune via transistor
T6 and the speaker.
As most toilets and bathrooms are ‘at-
tached’ nowadays, only a single circuit is
required, and the circuit can be wired on
a general-purpose veroboard.
A small modi cation of the circuit,
by adding additional SPST switch S3, as
shown in Fig. 2, needs to be done inside
the wooden switchboard box. This permits
the user to operate the lamp and fan dur-
ing cleaning of the toilet or for bypassing
the circuit, when bathroom or toilet un-
dergo repair work.
The simple, low-cost circuit presented
here takes only 100 ms to erase old pro-
grams electrically. The programming
voltage VPP for the mentioned IC is 12.7V,
unlike the 28xxxx series EEPROMs that
can be written to or read like a RAM, in
situ. Multiple ICs connected in parallel
can be erased simultaneously using the
given circuit.
The circuit requires 15V to 20V DC.
Timer IC3 (LM555) is used for generation
of clock pulses of 200 millisecond time
period with an ‘on’ time of 100 millisec-
onds. Pulse time is achieved by using
presets VR1 and VR2 and capacitor C1.
The ‘on’/‘off’ time of pulse may be set with
the help of an oscilloscope or by taking ap-
propriate values of presets VR1 and VR2
(in-circuit resistances) and capacitor C1
using the following relationship:
On time=0.69VR1xC1=Off Time=
0.69VR2xC1=100 milliseconds
IC1 (7812) and IC2 (7805) are voltage
regulator ICs that are used to obtain regu-
Readers’ comments:
 Please clarify the following:
1. Why all address pins, except 24
(A9), are connected to 0V (GND)?
2. If there are more than A15 address
pins (as in 27C010, 27C020, 28C020 etc),
which address pin willbe connected to Vcc
(+5V)?
INTELLIGENT ELECTRONIC LOCK
T
his intelligent electronic lock cir-
cuit is built using transistors
only. To open this electronic lock,
lated 14V DC and 5V DC, respectively,
required for operation of the circuit. The
clock with time period of 200 milliseconds
is fed to IC4 (CD4017). In this IC, the out-
put is available successively only at one of
the output pins with a delay of 200 milli-
seconds when reset pin 15 is low. The 14V
DC is made available via transistors T1
and T2 to pins 22 and 24 of IC5 (27C512,
which is the IC under erasure).
As soon as push-to-on switch S1 is
pressed momentarily, it resets IC4 by ap-
plication of 5V DC to reset pin 15, and the
output at pin 3 (Q0) goes high. This high
output is shifted to the next output pin
with the successive clock pulse received
at pin 14.
Q5 output from pin 1 of IC4 is inverted
using transistor T3 and is given to chip-
enable pin 20 of IC5, when 14V DC is
3. Is it possible to set pulse time with
DTM?
4. Is it possible to erase EEPROM
other than Winbond make?
Angika Electronics, Bhagalpur
The author, J.P. Sharma, replies:
1. The given con guration is mandatory
as per the manufacturer’s catalogue for
K. UDHAYA KUMARAN
one has to press tactile switches S1
through S4 sequentially. For deception
you may annotate these switches with
already available at pins 22 and 24 of IC5.
All address pins, except pin 24 (A9), are
set low and all data pins (11 through 13
and 15 through 19) are at high level (+5V).
Then pins 22 and 24 are pulsed low for 100
milliseconds. Immediately all data (cells)
are set high. (Data output is high only in
erased condition.)
At the end when Q9 output of IC4
goes high, transistor T4 conducts, pulling
its collector low. LED1 glows to indicate
completion of erasure. Simultaneously,
pin 4 of timer IC3 is taken low to stop
generation of further clock pulses until
IC4 is reset.
Insert the next IC to be erased in IC5
socket (preferably use a ZIF socket) and
reset IC4 by pushing switch S1 momentar-
ily. It takes only 100 milliseconds to erase
the EEPROM IC.
erasing W27C512 EEPROM.
2. 27C010 and 27C020 are UV eras-
able EPROMs (with less than A15 pins).
For 28C020, refer the datasheet.
3. A monostable low pulse of 100 mil-
liseconds can be set with DTM.
4. You can erase similar EEPROMs
electrically.
different numbers on the control panel/
keypad.
For example, if you want to use ten
ELECTRONICS PROJECTS Vol. 22 137

switches on the keypad marked ‘0’ through
‘9’, use any four arbitrary numbers out of
these for switches S1 through S4, and the
remaining six numbers may be annotated
on the leftover six switches, which may
be wired in parallel to disable switch S6
(shown in the gure). When four password
digits in ‘0’ through ‘9’ are mixed with the
remaining six digits connected across disa-
ble switch terminals, energisation of relay
RL1 by unauthorised person is prevented.
For authorised persons, a 4-digit password
number is easy to remember.
To energise relay RL1, one has to
press switches S1 through S4 sequentially
within six seconds, making sure that each
of the switch is kept depressed for a dura-
tion of 0.75 second to 1.25 seconds. The
relay will not operate if ‘on’ time duration
of each tactile switch (S1 through S4) is
less than 0.75 second or more than 1.25
seconds. This would amount to rejection
of the code.
A special feature of this circuit is that
pressing of any switch wired across dis-
able switch (S6) will lead to disabling of
the whole electronic lock circuit for about
one minute. Even if one enters the cor-
rect 4-digit password number within one
minute after a ‘disable’ operation, relay
RL1 won’t get energised. So if any un-
authorised person keeps trying different
permutations of numbers in quick succes-
sions for energisation of relay RL1, he is
not likely to succeed. To that extent, this
electronic lock circuit is foolproof.
This electronic lock circuit comprises
disabling, sequential switching, and
relay
138 ELECTRONICS PROJECTS Vol. 22
latch-up sections.
The disabling section comprises zener
diode ZD5 and transistors T1 and T2. Its
function is to cut off positive supply to se-
quential switching and relay latch-up sec-
tions for one minute when disable switch
S6 (or any other switch shunted across its
terminal) is momentarily pressed.
During idle state, capacitor C1 is
in discharged condition and the voltage
across it is less than 4.7 volts. Thus zener
diode ZD5 and transistor T1 are in non-
conduction state. As a result, the collector
voltage of transistor T1 is suf ciently
high to forward bias transistor T2. Con-
sequently, +12V is extended to sequential
switching and relay latch-up sections.
When disable switch is momentar-
ily depressed, capacitor C1 charges up
through resistor R1 and the voltage avail-
able across C1 becomes greater than 4.7
volts. Thus zener diode ZD5 and transis-
tor T1 start conducting and the collector
voltage of transistor T1 is pulled low. As
a result, transistor T2 stops conducting
and thus cuts off positive supply voltage
to sequential switching and relay latch-
up sections.
Thereafter, capacitor C1 starts dis-
charging slowly through zener diode ZD5
and transistor T1. It takes approximately
one minute to discharge to a suf ciently
low level to cut-off transistor T1, and
switch on transistor T2, for resuming
supply to sequential switching and relay
latch-up sections; and until then the cir-
cuit does not accept any code.
The sequential switching section com
prises transistors T3 through
T5, zener diodes ZD1 through
ZD3, tactile switches S1 through
S4, and timing capacitors C2
through C4. In this three-stage
electronic switch, the three tran-
sistors are connected in series to
extend positive voltage available
at the emitter of transistor T2
to the relay latch-up circuit for
energising relay RL1.
When tactile switches S1
through S3 are activated, tim-
ing capacitors C2, C3, and C4
are charged through resistors
R3, R5, and R7, respectively.
Timing capacitor C2 is dis-
charged through resistor R4,
zener diode ZD1, and transis-
tor T3; timing capacitor C3
through resistor R6, zener di-
ode ZD2, and transistor T4; and timing
capacitor C4 through zener diode ZD3
and transistor T5 only. The individual
timing capacitors are chosen in such a
way that the time taken to discharge ca-
pacitor C2 below 4.7 volts is 6 seconds, 3
seconds for C3, and 1.5 seconds for C4.
Thus while activating tactile switches
S1 through S3 sequentially, transistor T3
will be in conduction for 6 seconds, tran-
sistor T4 for 3 seconds, and transistor T5
for 1.5 seconds.
The positive voltage from the emit-
ter of transistor T2 is extended to tactile
switch S4 only for 1.5 seconds. Thus one
has to activate S4 tactile switch within
1.5 seconds to energise relay RL1. The
minimum time required to keep switch S4
depressed is around 1 second.
For sequential switching transistors
T3 through T5, the minimum time for
which the corresponding switches (S1
through S3) are to be kept depressed is
0.75 seconds to 1.25 seconds. If one op-
erates these switches for less than 0.75
seconds, timing capacitors C2 through
C4 may not get charged suf ciently. As
a consequence, these capacitors will dis-
charge earlier and any one of transistors
T3 through T5 may fail to conduct before
activating tactile switch S4. Thus sequen-
tial switching of the three transistors will
not be achieved and hence it will not be
possible to energise relay RL1 in such a
situation.
A similar situation arises if one keeps
each of the mentioned tactile switches de-
pressed for more than 1.5 seconds. When
the total time taken to activate switches S1
through S4 is greater than six seconds,
transistor T3 stops conducting due to time
lapse. Sequential switching is thus not
achieved and it is not possible to energise
relay RL1.
The latch-up relay circuit is built
around transistors T6 through T8, zener
diode ZD4, and capacitor C5.
In idle state, with relay RL1 in de-
energised condition, capacitor C5 is in
STABLE 455KHz BFO
FOR SSB RECEPTION
M
ost Indian amateur radio op-
erators prefer to operate on
SSB (single sideband) and CW
because these carry the signal over a long
distance for a given transmitter power.
Broadcast receivers are not meant to
directly receive Morse code transmission
on SSB and CW. Short-wave listeners
require some arrangement to receive the
same. One such arrangement comprises a
simple IF BFO (beat frequency oscillator),
which is an RF oscillator of conventional
type. The output of BFO is heterodyned
to beat with another frequency to obtain
a resultant frequency (difference of the
two frequencies) lying in the audio range
(about 1 kHz).
BFO can be used to get an audio note
from CW reception and also to resolve SSB
signals. An SSB signal is transmitted with-
out carrier signal. In ordinary receivers, it
does not produce speech with suf cient
AUTO SHUT-OFF FOR CASSETTE
PLAYERS AND AMPLIFIERS
H
ere are two simple, low-cost cir-
cuits that can be used to shut
off the mains supply to any
audio or video equipment (such as
discharged condition and zener diode ZD4
and transistors T7, T8, and T6 in non-
conduction state.
However, on correct operation of se-
quential switches S1 through S4, capaci-
tor C5 is charged through resistor R9 and
the voltage across it rises above 4.7 volts.
Now zener diode ZD4 as well as transis-
tors T7, T8, and T6 start conducting and
relay RL1 is energised. Due to conduction
D. PRABAHARAN
clarity. When BFO signal is heterodyned
with SSB signal, this RF acts like a carrier
and the signal is well resolved.
The BFO circuit comprises transis-
tors T1 and T2, which are connected
in a straightforward two-stage, direct-
coupled, common-emitter con guration.
The input and output are in phase and
ARTHUR LOUIS
tape recorder, CD player, and ampli er).
These circuits are helpful to those in the
habit of falling asleep with their music
system on.
of transistor T6, capacitor C5 remains
in charged condition and the relay is in
continuously energised condition.
Now if you activate reset switch S5
momentarily, capacitor C5 is immediately
discharged through resistor R8 and the
voltage across it falls below 4.7 volts. Thus
zener diode ZD4 and transistors T7, T8,
and T6 stop conducting again and relay
RL1 de-energises.
positive feedback between the two
is provided by ceramic lter CF1.
A signi cant amount of feedback
is provided only at the operating
frequency of the lter, which is
455 kHz. So the circuit oscillates
at this frequency. The ceramic lter
gives good frequency stability and
requires no adjustment in order to
produce the correct frequency. This
BFO is meant for single-sideband
reception only.
There is no need to connect
BFO to receiver. Tune your BC
receiver to any SSB signal, and then on
keeping BFO just close to it, you may
notice some hissing noise in your receiver.
Match BFO frequency to your receiver’s
IF, which may be between 452 and 460
kHz, until you get clear sound. If the BFO
signal is too strong, increase the distance
between BFO and receiver.
The circuits will also protect the
equipment from getting damaged due to
high-voltage spikes whenever there is a
resumption of power after a break. This
ELECTRONICS PROJECTS Vol. 22 139

is possible because the equipment will get
switched off automatically under such con-
ditions but will not get switched on auto-
matically on resumption of mains supply.
The circuit in Fig. 1 can be used to
shut off any cassette player that has a
reliable auto-stop mechanism. Whenever
switch S1 is pressed momentarily, it ex-
tends the supply to the step-down trans-
former of the tape recorder and charges
capacitor C1 through diode D1. This, in
turn, makes transistor T1 conduct and
energise relay RL1 to provide a parallel
path to switch S1, so that supply to the
step-down transformer continues even
when switch S1 is released.
When any button on the cassette
player is pressed, the capacitor charges
through diode D2. This ensures conduction
140 ELECTRONICS PROJECTS Vol. 22
of transistor T1 and thus the continuity
of operation of cassette player. However,
whenever the auto-stop mechanism func-
tions at the end of a tape, the leaf switch
gets opened. This cuts the charging path
for the capacitor and it starts discharg-
ing slowly. After about one minute, the
relay opens and interrupts main power
to the transformer. The time delay can
be increased by increasing the value of
capacitor C1.
If the appliance used is a two-in-one
type (e.g. cassette player-cum-radio), just
connect another diode in parallel with
diodes D1 and D2 to provide an additional
path for charging capacitor C1 via the
tape-to-radio changeover switch, so that
when radio is played the relay does not
interrupt the power supply.
The other circuit, shown in
Fig. 2, functions on the basis of
the signal received from preamp
of the appliance used. In this
circuit, opamp µA741 is wired
in inverting opamp con gura-
tion. It ampli es the signal re-
ceived from the preamp. Timer
NE555 is used to provide the
necessary time delay of about
one minute.
Preset VR1 is used to con-
trol the sensitivity of the circuit
to differentiate between the
noise and the signal. Resistor
R4 offers feedback resistance to
control the gain of the opamp.
By increasing or decreasing the
value of resistor R4, the gain
can be increased or decreased,
respectively. The preset time
delay of timer NE555 (which
is about one minute) can be in-
creased by increasing the value
of C4.
Initial energisation of relay
RL2 and charging of capacitor
C4 take place on depression of
switch S3 in the same man-
ner as charging of capacitor
C1 (refer Fig. 1) on depression
of switch S1. As a result, pins
2 and 6 of NE555 go high and
the output of timer goes low to
switch off mains supply from
the relay to step-down trans-
former X2 of the appliance.
Bleeder resistor R6 is used to
discharge capacitor C4. Now
if signals are received from
the preampli er, these are am-
pli ed by µA741 and fed to the
base of transistor T2, which keeps capaci-
tor C4 charged through resistor R5. When
there is no signal, T2 will not conduct and
the capacitor slowly discharges through
R6. The output of 555 goes high to switch
off the relay and thus the mains supply
to transformer X2. Switch S2 can be de-
pressed momentarily if the device needs
to be manually switched off.
Note. The 12V supply should be pro-
vided to the circuit from the equipment’s
power supply. Opamp µA741 should be
driven from the preampli er of the gadget
used, and not from its power ampli er
output. Switches S1 and S2 are 2-pole
push-to-on switches. These can also be
fabricated from 2-pole on-off switches,
which are widely used in cassette players,
by removing the latch pin from them.
 HOUSE SECURITY SYSTEM
H
ere is a low-cost, invisible laser
circuit to protect your house
from thieves or trespassers. A
laser pointer torch, which is easily avail-
able in the market, can be used to operate
this device.
The block diagram of the unit shown
in Fig. 1 depicts the overall arrangement
for providing security to a house. A laser
torch powered by 3V power-supply is used
for generating a laser beam. A combina-
tion of plain mirrors M1 through M6 is
MALAY BANERJEE
used to direct the laser beam around
the house to form a net. The laser beam
is directed to nally fall on an LDR that
forms part of the receiver unit as shown
in Fig. 2. Any interruption of the beam
by a thief/trespasser will result into
energisation of the alarm. The 3V power-
supply circuit is a conventional full-wave
recti er- lter circuit. Any alarm unit
that operates on 230V AC can be con-
nected at the output.
The receiver unit comprises
two identical
step-down
transformers
(X1 and X2), two 6V relays (RL1 and
RL2), an LDR, a transistor, and a few
other passive components. When switches
S1 and S2 are activated, transformer
X1, followed by a full-wave recti er and
smoothing capacitor C1, drives relay RL1
through the laser switch.
The laser beam should be aimed contin-
uously on LDR. As long as the laser beam
falls on LDR, transistor T1 remains forward
biased and relay RL1 is thus in deenergised
condition. When a person crosses the line
of laser beam, relay RL1 turns ON and
transformer X2 gets energised to provide
a parallel path across N/C contact and the
pole of relay RL1. In this condi-
tion, the laser beam will have no
effect on LDR and the alarm will
continue to operate as long as
switch S2 is on.
When the torch is switched
on, the pointed laser beam is
re ected from a de nite point/
place on the periphery of the
house. Making use of a set
of properly oriented mirrors
one can form an invisible net
of laser rays as shown in the
block diagram. The nal ray
should fall on LDR of the
circuit.
Note. LDR should be kept
in a long pipe to protect it from
other sources of light, and
its total distance from the
source may be kept limited to
500 metres.
ELECTRONICS PROJECTS Vol. 22 141
 SIMPLE
WATER-
LEVEL
INDICATOR-
CUM-
ALARM
PRADEEP G.

T
his water-level indicator-cum-
alarm circuit is con gured around
the well-known CMOS input-
compatible, 7-channel IC ULN2004 Dar-
lington array.
As the water level rises in the tank, it
comes in contact with probes P1 through
P7 and thereby makes pins 7 through 1
high, sequentially. As a result, the cor-
responding output pins 10 through 16 go
low one after the other, and LED1 through When water comes in contact with the the piezo-buzzer connected to output pin
LED7 light up in that order. nal probe P7, it results in sounding of 16 along with LED7.

PRECISION INDUCTANCE AND

CAPACITANCE METER
P. THANGAVEL

T
his circuit for measurement of in-
ductance and capacitance can be
used to test whether the values of
inductors and capacitors quoted by the
manufacturer are correct.
The principle used in the circuit is
based on the transient voltages produced
across inductors and capacitors connected
as series R-L and R-C networks, respec-
tively, across a constant voltage source.
The time constant for R-C and R-L net-
works is given by the relationships t=RxC
and L/R, respectively, where resistance
R is in ohms, capacitance C in Farads,
inductance L in Henries, and time t in
seconds.
The voltage across capacitor in R-C
network rises exponentially to 0.632 of
the applied voltage and voltage across
inductor in R-L network degrades expo-
nentially to 0.368 of the applied voltage
in one RxC and one L/R time (referred to
as time constant T of the combination),
respectively.
When the inductor/capacitor under
test is connected across terminals A
and B shown in the circuit, it is dis-
charged through the normally-closed
contacts of two-way push-to-on/off switch
S1. When switch S1 is pushed, the
capacitor’s voltage begins to grow (or
the inductor’s voltage begins to drop).
Simultaneously, the output of timer 555
IC, which is wired as an astable multi-
vibrator, is passed through NOR gates
N1 and N2 and applied to the counter
circuit.
When the time constant (one CxR or
one L/R, as the case may be) reaches, gate
N2 is inhibited as its pin 2 goes high and
the counter circuit freezes. Mode switch
S2 is to be kept in position ‘a1’ for capaci-

142 ELECTRONICS PROJECTS Vol. 22

 1. The po-
sition of mode-
select switch S2
and range-select
switch S3 should
be changed be-
fore switch S1 is
pressed.
2. If the cir-
cuit is allowed to
function until it
displays a con-
stant value, the
maximum time
taken for meas-
urement will be
10 seconds.
3. When mode-
select switch S2
is in position a1,
capacitances can
be measured,
and when it is in
position a2, in-
ductances can be
measured.
4. When
range-select
switch S3 is in
position ‘b1’, the
output of 555 IC
will have a time
inductors cov- period of 1 ms
TABLE
ered in each (frequency = 1 kHz), and when it is in posi-
555 IC Capacitance Inductance Displayed
range, together tion ‘b2’, the output of 555 IC will have a
Time period range range value
C=Tx10 –3
L=Tx103 with displayed time period of 1 µs.
1 ms When T=1 ms, When T=1 ms, L=1H Capacitance in values, are (EFY lab note. The guaranteed
(Switch S3 in C=1 µF When T=9999 ms, µF and inductance shown in the frequency of NE555 is limited to 500
position b1) When T= L=9999 H in H table. kHz, and hence it may not be possible to
9999 ms, From the get 1µs period. One may therefore use a
C=9999 µF
table it is obvi- 2nF capacitor to get a period of 2 µs and
1 µs When T=1 µs, When T=1 µs, Capacitance in nF
(Switch S3 in C=1 nF L=1 mH and inductance ous that this multiply the displayed value by 2, in b2
position b2) When T=9999 µs, When T=9999 µs, in mH circuit can range.)
C=9999 nF L=9.999H measure ca- 5. Use a breadboard for connecting
=9.999 µF =9999 mH pacitance from inductors or capacitors across terminals
1 nF to 9,999 A and B.
tance measurement and in position ‘a2’ for µF and inductance from 1 mH to 9999 6. Using both the ranges for meas-
inductance measurement. H. While presets VR1 and VR2 are to be uring an inductor or capacitor enables
As series resistance R1 is 1 kilo-ohm, adjusted for the in-circuit value of 1.717 one to obtain the accurate value. For
the capacitance value is given by the kilo-ohm each, the in-circuit value of example, a 4.7µF capacitor will display
relationship C=Tx10–3 while the inductor preset VR3 is close to 4.7 kilo-ohm. If a only 4 µF when measured in range b1 ,
value is given by the relationship L=Tx103. regulated +5V is not used, the measure- while in b2 range it will display 4700 nF
The time period (1/frequency) of timer ment of capacitance and inductance will (or 4.7 µF).
555 (IC2) is adjusted for 1 ms and 1 µs in be imprecise. 7. Don’t press switch S1 before insert-
‘b1’ and ‘b2’ positions, respectively, of the Given below are some important ing the capacitor or the inductor between
range switch. The values of capacitors and points to be taken care of: terminals A and B.

Readers’ comments: tor and the inductor aren’t connected for in the said circuit idea? Kindly tell me the
 I have asssembled the circuit, which measurement, it still shows some values. cause of this problem.
doesn’t work at all. It is showing different I have checked all the ICs and found them Asif Draboo
values all the time. Even when the capaci- all in good condition. Is there any misprint Bemiba, Jammu & Kashmir

ELECTRONICS PROJECTS Vol. 22 143

The author, Thangavel Ponnusamy,
replies:
Please go through the article throughly.
There are some rules to be followed to get
proper performance from the instrument:
1. The circuit should be switched on
only after connecting the capacitor or the
inductor for measurement. If you connect
UNDER-/OVER-VOLTAGE BEEP
FOR MANUAL STABILISER
M
anual stabilisers are still popu-
lar because of their simple con-
struction, low cost, and high re-
liability due to the absence of any relays
while covering a wide range of mains AC
voltages compared to that handled by au-
tomatic voltage stabilisers. These are used
mostly in homes and in business centres
for loads such as lighting, TV, and fridge,
and in certain areas where the mains
AC voltage uctuates between very low
(during peak hours) and abnormally high
(during non-peak hours).
Some manual stabilisers available in
the market incorporate the high-voltage
auto-cut-off facility to turn off the load
when the output voltage of manual stabi-
liser exceeds a certain preset high voltage
limit. The output voltage may become high
due to the rise in AC mains voltage or due
to improper selection by the rotary switch
on manual stabiliser.
One of the major disadvantage of us-
ing a manual stabiliser in areas with a
wide range of voltage uctuations is that
one has to keep a watch on the manual
stabiliser’s output voltage that is dis-
played on a voltmeter and keep changing
the same using its rotary switch. Or else,
144 ELECTRONICS PROJECTS Vol. 22
the capacitor or the inductor (for measure-
ment) after the circuit is powered on, you
are bound to get wrong results.
2. Check the position of mode switch,
which needs to be set in appropriate mode
before switching on the circuit. No switch
should be changed when the circuit is
powered on. For large-value inductors
K. UDHAYA KUMARAN
the output voltage may reach the preset
auto-cut-off limit to switch off the load
without the user’s knowledge. To turn on
the load again, one has to readjust the
stabiliser voltage using its rotary switch.
Such operation is very irritating and in-
convenient for the user.
This under-/over-voltage audio alarm
circuit designed as an add-on circuit for
the existing manual stabilisers over-
comes the above problem. Whenever the
stabiliser’s output voltage falls below a
preset low-level voltage or rises above
a preset high-level voltage, it produces
different beep sounds for ‘high’ and ‘low’
voltage levels—short-duration beeps
with short intervals between successive
beeps for ‘high’ voltage level and slightly
longer-duration beeps with longer interval
between successive beeps for ‘low’ voltage
level. By using these two different types
of beep sounds one can readily readjust
the stabiliser’s AC voltage output with the
help of the rotary switch. There is no need
of frequently checking voltmeter reading.
It is advisable to preset the high-
level voltage 10V to 20V less than
the required high-voltage limit for
auto-cut-off operation. Similarly,
and capacitors, the results will be stable
only after a few seconds, so wait until the
results stabilise.
3. Ensure that you are using good ca-
pacitors and inductors for measurement.
I hope the above tips will help you to
get yor instrument working.
for low level one may preset low-
level AC voltage 20V to 30V above
minimum operating voltage for a
given load.
The primary winding terminals of
step-down transformer X1 are connected
to the output terminals of the manual
stabiliser. Thus, 9V DC available across
capacitor C1 will vary in accordance with
the voltage available at the output ter-
minals of the manual stabiliser, which is
used to sense high or low voltage in this
circuit.
Transistor T1 in conjunction with
zener diode ZD1 and preset VR1 is used
to sense and adjust the high-voltage level
for beep indication. Similarly, transistor
T2 along with zener ZD2 and preset VR2 is
used to sense and adjust low voltage level
for beep indication.
When the DC voltage across ca-
pacitor C1 rises above the preset
high-level voltage or falls below the
preset low-level voltage, the collector
of transistor T2 becomes high due to
non-conduction of transistor T2, in ei-
ther case. However, if the DC voltage
sampled across C1 is within the preset
high- and low-level voltage, transistor
T2 conducts and its collector voltage
gets pulled to the
ground level. These
changes in the col-
lector voltage of tran-
sistor T2 are used to
start or stop oscilla-
tions in the astable
multivibrator circuit
that is built around
transistors T3 and
T4. The collector of
transistor T4 is con-
nected to the base of
buzzer driver transistor T5 through
resistor R8. Thus when the collector
voltage of transistor T4 goes high, the
buzzer sounds. Preset VR3 is used to con-
trol the volume of buzzer sound.
In normal condition, the DC voltage
sampled across capacitor C1 is within the
permissible window voltage zone. The
base of transistor T3 is pulled low due to
conduction of diode D2 and transistor T2.
As a result, capacitor C2 is discharged. The
astable multivibrator stops oscillating and
transistor T4 starts conducting because
transistor T3 is in cut-off state. No beep
ULTRA-SENSITIVE
SOLIDSTATE CLAP SWITCH
H
ere is the circuit of a highly sen-
sitive clap switch that can be
operated from a distance of up to
10 metres from the microphone.
Signals picked up by the microphone
are ampli ed by transistors T1, T2, and
T3. Diode D1 detects clap signals and the
resulting positive voltage is applied to the
base of transistor T4. The output from
15-STEP DIGITAL POWER SUPPLY
H
ere is a simple circuit to obtain
variable DC voltage from 1.25V
to 15.19V in reasonably small
sound is heard in the buzzer due to conduc-
tion of transistor T4 and non-conduction of
transistor T5.
When the DC voltage across capacitor
C1 goes above or below the window voltage
level, transistor T2 is cut off. Its collec-
tor voltage goes high and diode D2 stops
conducting. Thus there is no discharge
path for capacitor C2 through diode D2.
The astable multivibrator starts oscillat-
ing. The time period for which the beep is
heard and the time interval between two
successive beeps are achieved with the
help of the DC supply voltage, which is
PRADEEP G.
transistor T4 is further ampli ed by tran-
sistor T5, whose output is used to trigger
a monostable multivibrator wired around
the 555 timer (IC1).
The output of IC1 is used as a clock for
decade counter 4017 (IC2) that is wired
as a divide-by-two counter. For each suc-
cessive clap, transistor T6 conducts and
cuts off alternately. As a result, for each
NAVEEN THARIYAN
steps as shown in the table. The input
voltage may lie anywhere between
20V and 35V.
low during low-level voltage sampling and
high during high-level voltage sampling.
The time taken for charging capacitors C2
and C3 is less when the DC voltage is high
and slightly greater when the DC voltage
is low for astable multivibrator operation.
Thus during low-level voltage sensing
the buzzer beeps for longer duration with
longer interval between successive beeps
compared to that during high-voltage level
sensing.
This circuit can be added to any exist-
ing stabiliser (automatic or manual) or
UPS to monitor its performance.
clap signal, the lamp is either switched
‘on’ or ‘off’.
Triac 8T44A (or ST044) can drive load
of up to 4-amp rating. The 12V DC for
operation of the circuit is directly derived
from the mains using recti er diode D2,
current-limiting resistor R16, and 12V
zener ZD1 shunted by lter capacitor C7.
The first section of the circuit com-
prises a digital up-down counter built
around IC1—a quad 2-input NAND
ELECTRONICS PROJECTS Vol. 22 145
schmitt trigger (4093), followed by
IC2— a binary up-down counter (4029).
Two gates of IC 4093 are used to gener-
ate up-down logic using push buttons S1
and S2, respectively, while the other two
gates form an oscillator to provide clock
pulses to IC2 (4029). The frequency of
oscillations can be varied by changing
the value of capacitor C1 or preset VR1.
IC2 receives clock pulses from the
oscillator and produces a sequential bi-
nary output. As long as its pin 5 is low,
the counter continues to count at the
rising edge of each clock pulse, but stops
counting as soon as its pin 5 is brought
to logic 1. TABLE
Logic 1 at pin 10 makes the counter Binary Equivalent LED4 LED3 LED2 LED1
to count upwards, while logic 0 makes it output dec no. R14 (W) R13 (W) R12 (W) R11 (W) R2' (W) Vout (V)
count downwards. Therefore the counter 0000 0 Shorted Shorted Shorted Shorted 0 1.25
0001 1 Shorted Shorted Shorted 220 220 2.27
counts up by closing switch S1 and counts 0010 2 Shorted Shorted 470 Shorted 470 3.43
down by closing switch S2. 0011 3 Shorted Shorted 470 220 690 4.44
The output of counter IC2 is used to 0100 4 Shorted 820 Shorted Shorted 820 5.05
realise a digitally variable resistor. This 0101 5 Shorted 820 Shorted 220 1040 6.06
0110 6 Shorted 820 470 Shorted 1290 7.22
section consists of four N/O reed relays
0111 7 Shorted 820 470 220 1510 8.24
that need just about 5mA current for their 1000 8 1500 Shorted Shorted Shorted 1500 8.19
operation. (EFY lab note. The original 1001 9 1500 Shorted Shorted 220 1720 9.21
circuit containing quad bilateral switch 1010 10 1500 Shorted 470 Shorted 1970 10.37
IC 4066 has been replaced by reed relays 1011 11 1500 Shorted 470 220 2190 11.39
1100 12 1500 820 Shorted Shorted 2390 11.99
operated by transistorised switches because 1101 13 1500 820 Shorted 220 2540 13.01
of unreliable operation of the former.) 1110 14 1500 820 470 Shorted 2790 14.17
The switching action is performed using 1111 15 1500 820 470 220 3010 15.19
BC548 transistors. External resistors are
connected in parallel with the reed relay The measured output is nearly equal to and R2' = R11 + R12 + R13 + R14
contacts. If particular relay contacts are the theoretically calculated output across = 220 + 470 + 820 +1500 ohms
opened by the control input at the base regulator IC3 (LM317). The output voltage = 3,010 ohms (with all relays ener-
of a transistor, the corresponding resistor is governed by the following relationship gised)
across the relay contacts gets connected as long as the input-to-output differential One can use either the binary
to the circuit. is greater than or equal to 2.5V: weighted LED display as indicated by
The table shows the theoretical output Vout = 1.25(1+R2'/R1') LED1 through LED4 in the circuit or a
for various digital input combinations. Where, R1' = R15 = 270 ohms ( xed) 74LS154 IC in conjunction with LED5

146 ELECTRONICS PROJECTS Vol. 22

through LED20 to indicate one of the 16
selected voltage steps of Table I. The input
for IC4 is to be tapped from points marked
A through D in the gure. This arrange-
ment can be used to replace the LED ar-
rangement at points A, B, C, and D. This
74LS154 IC is a decoder/demultiplexer
that senses the output of IC2 and accord-
ingly activates only one of its 16 outputs
in accordance with the count value. LEDs
at the output of this IC can be arranged in
a circular way along side the correspond-
ing voltages.
MICROPHONE FOR COMPUTER
B
uying a microphone for a com-
puter is costly. Especially when
there is a need to have two mi-
crophones—one for modem and another
for sound card—or if the present micro-
phone is not working properly and needs
to be replaced, you are likely to feel the
burden of extra cost. Here is a low-cost
microphone circuit that comes within
your budget.
All sound cards and modems have a
socket for microphone that is in compatible
with stereo jack pins. The stereo socket
takes condenser microphone as input and
VERSATILE ZENER DIODE TESTER
Z
ener diodes available in the mar-
ket are speci ed according to their
breakdown voltage as well as toler-
ance. The tolerance may vary from 5 per
cent to 20 per cent. The circuit of a versa-
tile zener diode tester presented here ena-
bles you to verify the speci ed breakdown
voltage and tolerance values. In addition,
you can check the dynamic impedance of
Working
When the power is switched on, IC2 resets
itself, and hence the output at pins 6, 11,
14, and 12 is equivalent to binary zero, i.e.
‘0000’. The corresponding DC output of the
circuit is minimum (1.25V). As count-up
switch S1 is pressed, the binary count of
IC2 increases and the output starts in-
creasing too. At the highest count output
of 1111, the output voltage is 15.19V (as-
suming the in-circuit resistance of preset
VR2 as zero). Preset VR2 can be used for
VYJESH M.V.
provides the necessary positive voltage
for a condenser microphone. Before build-
ing the full circuit, connect three wires to
the jackpin, switch on the computer, and
insert the jack pins; into the socket of the
K. UDHAYA KUMARAN
a zener diode.
The dynamic impedance characteris-
tics of a zener diode determine as to how
well the zener diode regulates its own
breakdown voltage. Thus this circuit can
be used to compare the dynamic imped-
ance characteristics of zener diodes from
a lot and segregate/categorise them ac-
cordingly.
trimming the output voltage as desired.
To decrease the output voltage within
the range of 1.25V to 15.2V, count-down
switch S2 is to be depressed.
Notes. 1. When relay contacts across
a particular resistor are opened, the cor-
responding LED glows.
2. The output voltages are shown as-
suming the in-circuit resistance of preset
VR2 as zero. Thus when the in-circuit
resistance of preset VR2 is not zero, the
output voltage will be higher than that
indicated here.
sound card. With the help of a
multimeter, nd out the posi-
tive terminal out of the three
wires.
There exists a potential dif-
ference of 4V or so between the
positive and ground terminals.
The third terminal will obvi-
ously be for the signal input.
The positive terminal is used for biasing
the condenser microphone. After iden-
tifying all the terminals, connect them
as shown in the accompanying circuit
diagram.
For full- edged zener diode testing
you will have to refer to the manufac-
turer’s datasheet to check zener diode
parameters such as zener voltage, power,
and current (maximum/nominal) rat-
ings. In addition, temperature coef cient
and dynamic impedance have also to be
checked if zener diode is to be used for
critical functions such as voltage reference
ELECTRONICS PROJECTS Vol. 22 147

power supply is quite complicated and is
TABLE I
Minimum and Maximum Test Current prone to damage if excess current is drawn
Values accidentally.
Zener diode values IT(min) IT(max) The zener diode tester circuit pre-
3.3V to 4.3V 10mA 15mA sented here has been designed considering
4.7V to 18V 5mA 10mA the above factors. It is capable of testing
20V to 39V 2mA 4mA zener diodes of breakdown voltage ratings
Note: Zener diode power ratings are 250 mW, of upto 120V and wattage ratings of 250
400 mW, and 500 mW.
mW, 400 mW, 500 mW, and 1W.
The circuit can be deployed in quick-
test mode as also in quality-test mode of
TABLE II
operation. In quick-test mode, you can
Minimum and Maximum Test Current perform a rough check of zener diode’s
Values
breakdown voltage up to 47 volts. In
Zener diode values IT(min) IT(max)
quality-test mode, you can check dynamic
3.3V to 12V 10mA 15mA impedance characteristic for zener diodes
13V to 27V 5mA 10mA
30V to 43V 2mA 5mA from 3.3V to 120V.
47V to 75V 1.5mA 3mA Commonly available step-down trans-
82V to 120V 1mA 2mA formers X1 and X2 (230V AC primary to
Note: Zener diode power rating is 1 watt. 9V AC, 750 mA sec. each) are connected
back-to-back as shown in the gure. A
for digital voltmeters, control systems, and bridge recti er followed by lter capacitor
precision power-supply circuits. However, C1 converts the output from X2 trans-
for a common hobbyist it is not necessary former to DC. Neon lamp L1 indicates
to check zener diodes critically, and only the presence of higher DC voltage (220V
checking its dynamic impedance charac- approximately) across capacitor C1, which
teristic is suf cient. is used to test various zener diode values
Dynamic impedance implies the de- from 3.3V to 120V.
gree of change in a zener diode’s voltage An advantage of using this high-
with the change in current. Expressed voltage circuit is that the current gets
in ohms, it equals the small change in restricted to a low value. It delivers only
zener voltage divided by the correspond- 3 mA (approx.) when testing zener diodes
ing change in zener current (centered with higher breakdown values (e.g. 120V
around the test current gure prescribed zener diode), but while testing zener
in datasheets by manufacturers). From diodes of low breakdown values, such as
datasheets it is observed that test current 3.3V, it delivers a current slightly above
value is high for low-voltage zener diodes 20 mA. Such power-supply characteristics
and low for higher-voltage zener diodes. suit our requirement, as stated earlier.
However, the dynamic impedance value Since a small current is used for testing of
will be low for low-voltage zener diodes zener diodes, there is no danger of zener
and vice versa for higher-voltage zener diodes getting damaged during testing us-
diodes. ing the dynamic impedance method.
To test 3.3V to 120V zener diodes by Before using the circuit, check DC volt-
the practical dynamic impedance method, age across test terminals A and B without
you need to have a variable voltage (0 to connecting any zener diode and then ip
above 120V) and current (1 mA to 150 toggle switch S2 to quick-test position. DC
mA) supply source. Designing this type of voltage available across terminals A and
148 ELECTRONICS PROJECTS Vol. 22
B will be around 200V
DC. Now put toggle switch
to quality-test position.
DC voltage can now be
adjusted from 6V DC to
200V DC (approx.) with
the help of potentiometer
VR1. After these prelimi-
nary checks, the circuit is
ready for operation.
To test zener diode by
quick-test method, con-
nect zener diode across
terminals A and B and ip
switch S1 to ‘on’ position.
Note down DC voltage in digital multim-
eter M2, which is the rough breakdown
voltage. In quick-test method you can test
zener diode values up to 47 volts safely.
For higher-value zener diodes you will
have to increase the value of resistor R3
suitably. If zener diode presents a short,
digital multimeter M2 will read ‘0’ volts.
To perform quality test on the same
zener diode, turn switch S1 ‘off’ and re-
move zener diode from across terminals
A and B. Now turn switch S1 ‘on’ and
adjust potentiometer VR1 to obtain DC
voltage (on digital multimeter) across
terminals A and B equal to the one
found during quick test method. Now
keep potentiometer VR2 in mid position
and connect zener diode across terminals
A and B.
(Note. Before testing zener diode, re-
fer Table I and Table II for the minimum
test current (ITmin) and maximum test
current (ITmax) required for various zener
diode values, depending upon their watt-
age rating.)
Test current is adjusted using poten-
tiometer VR2 and measured using meter
M1 (A 0-25mA analogue milliampere
meter or a 0-20mA digital multimeter can
be used.)
Now adjust potentiometer VR2 and
note down changes in zener voltage dur-
ing ITmin and ITmax conditions. If the re-
quired current is not available, increase
DC voltage by adjusting potentiometer
VR1 suitably. While changing test cur-
rent from ITmin to ITmax, the voltage
variation across zener diode should be
less than 1 volt for lower-value zener
diodes and a few volts for higher-value
zener diodes. A voltage variation of more
than this value indicates that zener
diode is not properly regulating. When
comparing zener diodes of same values,
the zeners showing less voltage deviation
would regulate better.
 DTMF PROXIMITY DETECTOR
A
DTMF-based IR transmitter and
receiver pair can be used to rea-
lise a proximity detector. The
circuit presented here enables you to
detect any object capable of re ecting
the IR beam and moving in front of the IR
LED photodetector pair up to a distance of
about 12 cm from it.
The circuit uses the commonly avail-
able telephony ICs such as dial-tone gen-
erator 91214B/91215B (IC1) and DTMF
decoder CM8870 (IC2) in conjunction
with infrared LED (IR LED1), photodiode
D1, and other components as shown in
the gure. A properly regulated 5V DC
power supply is required for operation of
the circuit.
The transmitter part is con gured
around dialer IC1. Its row 1 (pin 15) and
column 1 (pin 12) get connected together
via transistor T2 after a power-on delay
STEPPER MOTOR CONTROL
A
simple, low-cost hardwired step
per motor control circuit that can
be used in low-power applications,
K.S. SANKAR
(determined by capacitor C1 and resis-
tors R1 and R16 in the base circuit of
the transistor) to generate DTMF tone
(combination of 697 Hz and 1209 Hz)
corresponding to keypad digit “1” con-
tinuously.
LED 2 is used to indicate the tone
output from IC3. This tone output is
ampli ed by Darlington transistor pair of
T3 and T4 to drive IR LED1 via variable
resistor VR1 in series with xed 10-ohm
resistor R14. Thus IR LED1 produces
tone-modulated IR light. Variable re-
sistor VR1 controls the emission level
to vary the transmission range. LED 3
indicates that transmission is taking
place.
A part of modulated IR light signal
transmitted by IR LED1, after re ection
from an object, falls on photodetector
diode D1. (The photodetector is to be
JAYDIP APPASAHEB DHOLE
such as moving toys etc is presented here.
The circuit comprises a 555 timer IC
con gured as an astable multivibrator
shielded from direct IR light transmis-
sion path of IR LED1 by using any
opaque partition so that it receives only
the re ected IR light.) On detection of
the signal by photodetector, it is coupled
to DTMF decoder IC2 through emitter-
follower transistor T1.
When the valid tone pair is detected
by the decoder, its StD pin 15 (shorted to
TOE pin 10) goes ‘high’. The detection of
the object in proximity of IR transmitter-
receiver combination is indicated by
LED1. The active-high logic output pulse
(terminated at connector CON1, in the
gure) can be used to switch on/off any
device (such as a siren via a latch and
relay driver) or it can be used to clock a
counter, etc.
This DTMF proximity detector nds
applications in burglar alarms, object
counter and tachometers, etc.
with approx. 1Hz frequency. The fre-
quency is determined from the following
relationship:
ELECTRONICS PROJECTS Vol. 22 149

Frequency = 1/T = 1.45/(RA + 2RB)C
Where RA = RB = R2 = R3 = 4.7 kilo-ohm
and C = C2 = 100 µF.
The output of timer is used as clock
for two 7474 dual D ip- ops (IC2 and
IC3) con gured as a ring counter. When
power is initially switched on, only the
rst ip- op is set (i.e. Q output at pin
5 of IC2 will be at logic ‘1’) and the other
three ip- ops are reset (i.e. their Q out-
puts will be at logic ‘0’). On receipt of a
clock pulse, the logic 1 output of the rst
ip- op gets shifted to the second ip-
op (pin 9 of IC2). Thus with every clock
pulse, the logic ‘1’ output keeps shifting
in a ring fashion.
Q outputs of all the four ip- ops are
ampli ed by Darlington transistor arrays
inside ULN2003 (IC4) and connected to
the stepper motor windings marked ‘A’
through D in the gure. The common
point of the winding is connected to +12V
DC supply, which is also connected to pin
9 of ULN2003. The colour code used for
the windings is shown in the gure.
When the power is switched on, the
control signal connected to SET pin of the
rst ip- op and CLR pins of the other
three ip- ops goes active low (because
of the power-on-reset circuit formed by
R1-C1 combination) to set the rst ip- op
and reset the remaining three ip- ops.
On reset, Q1 of IC2 goes ‘high’ while all
other Q outputs go ‘low’. External reset
can be activated by pressing the reset
switch. By pressing the reset switch, you
can stop the stepper motor. On releas-
ing the reset switch, the stepper motor
again starts moving further in the same
direction.

LOW-COST INTERCOM
PRADEEP G.

T
he intercom circuit described here
uses two transistors, an audio
transformer, and a few passive
components in addition to condenser
microphone and low-wattage speaker
(refer Fig. 1). The complete unit
can be made on a
general-purpose
veroboard.
The micro-
phone signals are
amplified by a
two-stage transistor C3 gets connected between the base of
ampli er, while the transistor T2 and the top end of primary
speaker is driven winding of audio output transformer. As a
through an audio result, the ampli er circuit wired around
output transformer transistor T2 gets converted into a Hartley
(similar to the one oscillator and produces an audible tone
used in transis- for call-bell.
tor radios). When To build a two-way intercom set, make
ring button (push- two identical units with the speaker of
to-on switch S1) is each circuit installed near the other unit
pressed, capacitor as shown in Fig. 2.

150 ELECTRONICS PROJECTS Vol. 22

 HIGH-POWER
CAR BAT TERY ELIMINATOR
T.K. HAREENDRAN

T
o operate car audio (or video) sys-
tem from household 230V AC
mains supply, you need a DC adap-
tor. DC adaptors available in the market
are generally costly and supply an unregu-
lated DC. To overcome these problems, X1
an economical and reliable circuit of a
high-power, regulated DC adaptor using
reasonably low number of components is
presented here.
Transformer X1 steps down 230V AC
mains supply to around 30V AC, which GND
is then rectified by a bridge rectifier
comprising 1N5406 recti er diodes D1
through D4. The recti ed pulsating DC is
smoothed by two 4700µF lter capacitors unregulated DC sup-
C1 and C2. ply, resulting in the
The next part of the circuit is a series- blowing of fuse F1
transistor regulator circuit realised using instantly. This offers
high-power transistor 2N3773 (T1). Fixed- guaranteed protec-
base reference for the transistor is taken tion to the equipment
from the output pin of 3-pin regulator IC1 connected and to the
(LM 7806). The normal output of IC1 is circuit itself.
raised to about 13.8 volts by suitably bias- This circuit can
ing its common terminal by components be assembled using
circuit is added. If the output voltage
ZD1 and LED1. This simple arrangement a small general-purpose PCB. A good-
exceeds 15V due to some reason such as
provides good, stable voltage reference at quality heat-sink is required for transis-
component failure, the SCR res because
a low cost. LED1 also works as an output tor T1. Enclose the complete circuit in a
of the breakdown of zener ZD2. Once SCR
indicator. readymade big adaptor cabinet as shown
res, it presents a short-circuit across the
Finally, a crowbar-type protection in the gure.

Readers’ comments:
 The way of biasing of transistor
T1 seems to be wrong. As per the da-
tasheet, the transitor T1 should be of
pnp type and connected as shown in
Fig. 1 here.
Chittaranjan Parida
Cuttack Fig. 2: Schematic of a conventional series
Fig. 1: Reader s modi cation to battery regulator
The author, T.K. Hareendran, re-
eliminator circuit
plies: role of a bypass transistor. At low
As clearly mentioned in the text, transistor T1 regulator IC1 is used to increase the ef ciency load currents, all the load current is
works as a series regulator transistor. In conven- and lifetime. The schematic of a conventional provided by IC1 and whenever the
tional circuits, one ordinary zener diode is used series regulator is shown in Fig. 2. load current is increased beyond a
to provide a xed-base bias to T1. The circuit Th e c ir c u it in dic ated by you , preset value (decided by R) transis-
published is an improved version based on NSC datasheet, is in fact tor T1 comes into picture and sup-
and the fixed three-terminal voltage a current booster. Here T1 plays the plies all the excess current.

ELECTRONICS PROJECTS Vol. 22 151

 AUTOMATIC PLANT IRRIGATOR
T
he circuit presented here waters
your plants regularly when you
are out for a vacation.
The circuit comprises a sensor part
built using only one op-amp (N1) of quad
op-amp IC LM324. Op-amp N1 is con-
gured here as a comparator. Two stiff
copper wires are inserted in the soil con-
taining plants. As long as the soil is wet,
conductivity is maintained and the circuit
remains off.
When the soil dries out, the resistance
between the copper wires (sensor probes
A and B) increases. If the resistance in-
creases beyond a preset limit, output pin
SIMPLE TELEPHONE RING TONE
GENERATOR
H
ere is a simple telephone ring
tone generator circuit designed
using only a few components.
It produces simulated telephone ring
152 ELECTRONICS PROJECTS Vol. 22
PRIYANK MUDGAL
1 of op-amp N1 goes ‘low’. This triggers To arrange the circuit, insert copper
timer IC2 (NE 555) con gured as a monos- wires in the soil to a depth of about 2 cm,
table multivibrator. As a result, relay RL1 keeping them 3 cm apart. When the soil
is activated for a preset time. The water gets dried, adjust VR1 towards ground
pump starts immediately to supply water rail until LED1 turns off and relay RL1
to the plants. is energised. The motor starts pumping
As soon as the soil becomes suf- the water. LED1 glows up as the water
ciently wet, the resistance between reaches the probes.
sensor probes decreases rapidly. This For small areas a small pump such as
causes pin 1 of op-amp N1 to go ‘high’. the one used in air coolers is able to pump
LED1 glows to indicate the presence of enough water within 5 to 6 seconds. The
adequate water in the soil. The threshold timing components for IC2 are selected
point at which the output of op-amp N1 accordingly. The timing can be varied with
goes ‘low’ can be changed with the help the help of preset VR2.
of preset VR1. The circuit is more effective indoors
if one intends to use
it for long periods.
This is because the
water from reservoir
(bucket, etc) evapo-
rates rapidly if it
is kept in the open.
For regulating the
ow of water, either
a tap can be used or
one end of a rubber
pipe can be blocked
using M-seal com-
pound, with holes
punctured along its
length to water sev-
eral plants.
K. UDHAYA KUMARAN, VU3GTH
tone and needs only DC voltage (4.5V loud when this circuit is operated on
DC to 12V DC). One may use this cir- +12V DC power supply. However, the
cuit in ordinary intercom or phone- volume of ring sound is adjustable.
type intercom. The sound is quite The commonly available 14-stage
 +
binary ripple counter with built-in oscil-
lator (CMOS IC CD4060B) is used to
generate three types of pulses, which
are available from pin 1(O11), pin 3 (O13),
and pin 14 (O7), respectively. Preset VR1
is adjusted to obtain 0.3125Hz pulses
(1.6-second ‘low’ followed by 1.6-second
‘high’) at pin 3 of IC1. At the same time,
pulses available from pin 1 will be of
1.25 Hz (0.4-second ‘low’, 0.4-second
‘high’) and 20 Hz at pin 14. The three
output pins of IC1 are connected to base
terminals of transistors T1, T2, and T3
through resistors R1, R2, and R3, re-
DUAL-INPUT HIGH-FIDELITY
AUDIO MIXER
Th
e circuit described here is based
on the superior characteristics of
dual-gate MOSFET (metal-
oxide semiconductor eld-effect transistor).
It exhibits a very high input impedance
that lends for good sensitivity and very
less loading of the input signal source.
Low cross-modulation characteristic leads
to minimal distortion of the output with
respect to the input signals. Also, the
MOSFET offers low feedback capacitance
and high transconductance. All these ad-
vantages make the MOSFET the most ef-
fective for high-quality mixer and converter
applications.
This dual-input audio frequency
mixer circuit employs a single dual-gate
spectively.
Transistors T1 through T3 are cas-
caded in such a way that the positive
voltage available at the emitter of tran-
sistor T1 is extended to the collector of
Transistor T3 when the outputs of all
the three stages are low. As a result,
transistors T1 through T3 are forward
biased for 0.4, 1.6, and 0.025 seconds,
respectively and reverse biased for simi-
lar durations.
Using a built-in oscillator-type piezo-
buzzer produces around 1kHz tone. In
this circuit, the piezo-buzzer is turned
PRASAD J.
MOSFET 3N200. One may, however,
substitute it with any other dual-gate
‘on’ and ‘off’ at 20Hz for ring tone sound
by transistor T3. 20Hz pulses are avail-
able at the collector of transistor T3 for
0.4-second duration. After a time interval
of 0.4 second, 20Hz pulses become again
available for another 0.4-second dura-
tion. This is followed by two seconds of
nosound interval. Thereafter the pulse
pattern repeats itself.
Refer the figure that indicates
waveforms available at various points
including the collector of transistor T3.
Preset VR2 can be used for adjusting the
amplitude of the ring tone.
MOSFET such as 3N187 and BF966. (It
is to be noted that BF966 is not gate-pro-
tected and hence
calls for suitable
precaution in han-
dling it.)
The audio fre-
quency (AF) input
from the rst chan-
nel (CH1) is ap-
plied on gate 1 (G1)
of the MOSFET
through 500-kilo-
ohm potentiometer
VR1. The AF input
from the second
channel (CH2) is
ELECTRONICS PROJECTS Vol. 22 153
applied on gate 2 (G2) of the MOSFET
through another 500-kilo-ohm potenti-
ometer VR2. Potentiometers VR1 and
VR2 serve as gain controls for the mixer
inputs.
Gate 1 receives the negative bias
resulting from the voltage developed
by the current passing through resis-
tor R1 that is in series with the source.
Gate 2 receives the positive bias
produced across resistor R3 by the
voltage divider formed by resistors R3
and R4.
The mixed common output signal
developed across drain load resistor R2
is coupled to the output through capaci-
tor C5. This output can be, in turn, fed
to any audio ampli er system for further
ampli cation.
The input impedance at each signal
input is approximately 500 kilo-ohm,
which is determined largely by the re-
sistance of potentiometers VR1 and VR2.
Higher input impedance may be obtained
by substituting higher-resistance potenti-
ometers, but this will lead to the pickup
of stray signals.
The current drain of this circuit at 6V
DC is less than 3 mA. The open-circuit
voltage gain is 10 for each channel. The
maximum amplitude of input signals at
gates G1 and G2 is 0.1V RMS. Signals
of higher amplitudes are reduced by the
adjustment of potentiometers VR1 and
VR2, hence evading the output signal
peak-clipping. The corresponding output
signal amplitude is 1V RMS.
The entire circuit can be built on
a general-purpose PCB or veroboard.
The complete assembly is shielded using
a metal container. The two input jacks
should be xed on the opposite sides of
the container against the output jack.
This simple circuit can be utilised for
various combinations of devices at the
input end. A few examples are two micro-
phones, two audio players, or one audio
player and one microphone, etc.
Note. Adequate precautions should
be taken to prevent the destruction of
MOSFET due to static electricity. The use
of a grounded tip for the soldering iron is
recommended.

UNIPOLAR/BIPOLAR
TRIANGULAR AND BIPOLAR
SQUARE WAVE GENERATOR
YOGESH KATARIA

T
he circuit given here is capable of S1 is open, it generates unipolar trian-
generating unipolar and bipolar gular and bipolar square waves—both
triangular waves as well as bi- having double the frequency in the
polar square waves. In unipolar mode, first case.
the output frequency is double that of Op-amp 301 acting as a compara-
bipolar mode (using identical component tor produces bipolar square wave with
values). output swinging between +Vcc and –VEE.
When switch S1 is closed, the circuit The square wave output is fed to op-amp
generates bipolar triangular as well as 741 that is con gured as an integrator to
bipolar square waves, and when switch produce a triangular waveform.
Figs 2 and
3 show the
waveforms
with switch S1
in closed and
open positions,
respectively,
using 0.047µF
capacitor C and
in-circuit value
of preset VR1 as
28 kilo-ohm. The
circuit is capable
of working on
a few hertz to
around 250kHz.

154 ELECTRONICS PROJECTS Vol. 22

ANTI-THEFT SECURITY FOR CAR AUDIOS
T
his small circuit, based on popu-
lar CMOS NAND chip CD4093,
can be effectively used for pro-
tecting your expensive car audio system
against theft.
When 12V DC from the car battery
is applied to the gadget (as indicated by
LED1) through switch S1, the circuit
goes into standby mode. LED inside
optocoupler IC1 is lit as its cathode
terminal is grounded via the car audio
(ampli er) body. As a result, the output
at pin 3 of gate N1 goes low and disables
the rest of the circuit.
Whenever an attempt is made to re-
move the car audio from its mounting by
cutting its connecting wires, the optocou-
pler immediately turns off, as its LED
cathode terminal is hanging. As a result,
Readers’ comments:
 The oscillator circuit built around
gates N1, N2, and N3 is not working. The
circuit works like a timer when pin 2 of
MCT2E is connected to the body of the
audio. There is no change in the perform-
ance when pin 2 is left hanging. But when
pins 2 and 4 of MCT2E are shorted, the
circuit starts working.
T.K. HAREENDRAN
the oscillator circuit built around gates
N2 and N3 is enabled and it controls the
‘on’/‘off’ timings of the relay via transis-
tor T2. (Relay contacts can be used to
energise an emergency beeper, indicator,
car horns, etc, as desired.)
Different values of capacitor C2 give
different ‘on’/‘off’ timings for relay RL1 to
be ‘on’/‘off’. With 100µF we get approxi-
mately 5 seconds as ‘on’ and 5 seconds as
‘off’ time.
Gate N4, with its associated com-
ponents, forms a self-testing circuit.
Normally, both of its inputs are in ‘high’
state. However, when one switches off the
ignition key, the supply to the car audio is
also disconnected. Thus the output of gate
N4 jumps to a ‘high’ state and it provides a
differentiated short pulse to forward bias
Also clarify the use of R3 in
the circuit and show pin connec-
tions of MCT2E.
D. Mohan Kumar, Trivandrum
The author, T.K. Hareendran,
replies:
Carefully recheck your assembled
circuit. No modi cation/corrections Fig. 1: MCT2E pin
are required in the published de- configuration
transistor T1 for a short duration. (The
combination of capacitor C1 and resistor
R5 acts as the differentiating circuit.)
As a result, buzzer in the collector
terminal of T1 beeps for a short duration
to announce that the security circuit is
intact. This ‘on’ period of buzzer can be
varied by changing the values of capacitor
C1 and/or resistor R5.
After construction, x the LED and
buzzer in dashboard as per your require-
ment and hide switch S1 in a suitable lo-
cation. Then connect lead A to the body of
car stereo (not to the body of vehicle) and
lead B to its positive lead terminal. Take
power supply for the circuit from the car
battery directly.
Caution. This design is meant for car
audios with negative ground only.
sign. The fault indicated
may be due to a faulty opto-
coupler (MCT2E).
Resistor R3 (100 kilo-
ohm) is used to pull down
the input of gate N1 (wired
as inverter) in active state.
The pin con guration of
MCT2E is shown in Fig. 1.
ELECTRONICS PROJECTS Vol. 22 155
 PC-BASED DIAL CLOCK-CUM-
ELECTRONIC ROULETTE
T
his hardware-cum-software project
is meant to control hardware
through software. The hardware
using LEDs to simulate both dial clock and
electronic roulette is rather simple.
Of the two 4-line-to-16-line decoders
used in the circuit, the rst (IC1) drives
‘hour LEDs’ and the other (IC2) drives
‘minute LEDs.’ These decoders are in-
terfaced directly to the PC’s printer port
provided on its backside.
Data output lines D0 to D3 (pins 2
through 5 of 25-pin ‘D’ connector) of the
printer port are connected to four address
inputs of the decoder used for minute
156 ELECTRONICS PROJECTS Vol. 22
VIJAYA KUMAR P.
display, while data output lines D4 to D7
(pins 6 through 9) are connected to four
data inputs of the decoder used for hour
display.
Since the outputs of these decoders are
active-low, the positive terminals of LEDs
are made common. This obviates the need
to use additional inverters. In accordance
with 4-bit binary address at inputs A
through D of decoders, only one of the 16
outputs at a time goes active-low to light
the corresponding LED.
Since a dial clock requires only 12
LEDs, only 12 of 16 outputs of 74154
decoders are used in this circuit. Only the
minute decoder (IC2) is used for electronic
roulette.
The dial clock and electronic roulette
functions, which can be selected via the
software program, are explained below:
Dial clock. When dial clock is selected,
system time is displayed on the LED panel.
The hour-indicating LED glows continu-
ously, while minute-indicating LED blinks
for each odd second (i.e. 1, 3, 5, ...., and so
on). The clock incorporates hourly chime
and alarm setting features. Chime and
alarm sound can be distinguished from the
duration for which it will sound.
Electronic roulette. Roulette is a
game of chance that basically comprises
a circular wheel divided into a number
of sectors that are numbered serially and
a pointer. There exists a relative motion
between the pointer and the wheel. The
rotation is initiated by mechanical means.
The wheel is allowed to stop itself and the
number indicated by the pointer decides
the winner.
This game can also be arranged elec-
tronically by using sequential running
lights, which will simulate the rotating
wheel, and making them to stop at ran-
dom position. The chance of a number to
be winner is 1 out of 12 in the PC-based
electronic roulette explained here. The
software for dial clock and electronic rou-
lette is written in ‘C’ language.
For simulation of dial clock, the soft-
ware uses gettime () function to read time
from the computer, which is then stored
in a variable. This time is written into
the parallel-port as 8-bit binary number
by using outportb () function. To make
minute-indicating LED to blink, minute
variable is multiplied by (second % 2). The
multiplication result comes out to be 1 for
odd seconds and 0 for even seconds.
i=sc%2;
mn=mn*i;
The binary equivalent of minute vari-
able is written into data pins D0 to D4 of
the parallel-port. Hour variable is multi-
plied by 16 to write the binary equivalent
of hour into data pins D5 to D7.
Outportb (0x0378,ho*16+mn);
Simulation of roulette wheel is quite
simple. The software uses a decimal
number (1 through 13) generator whose
binary equivalents are written into data
pins D0 to D4 of the parallel port using
outputb () function. The roulette can be
reset by initialising decimal number gen-
erator that simulates running lights.
The decimal number generator can be
stopped at random for play. The speed of
running can be adjusted by using delay ()
function. The delay time has to be selected
appropriately, as it should not be either
too low or too high. Keeping the delay time
very low is undesirable, since it will cause
continuous glowing of LEDs. Similarly, a
very high delay time is also undesirable,
since the player can stop the wheel at his
winning position.

DialCLK.C
#include <stdio.h> if(ho>12) scanf(“%d” ,&mns);
#include <dos.h> { printf(“Enter seconds\n”);
#include <stdlib.h> ho=ho-12; scanf(“%d” ,&scs);
#de ne PORT 0x0378 } Aclock(hrs,mns,scs);
main() if(ho==0) }
{ int k=0; { alarm(int beps) /*Function to produce beeping sound*/
clrscr(); ho=12; {
gotoxy(30,10); } int i;
printf(“1.(D)ial Clock\n”); i=sc % 2; for(i=0;i<beps;i++)
gotoxy(30,12); mn=mn*i; /*Making minute LED to blink*/ {
print(“2.(R)un Electronic Roulette \n”); mn=mn/5; sound(1500);
gotoxy(30,14); outportb(PORT,ho*16+mn); delay(100);
printf(“3.(E)xit\n”); printf(“hour:min:sec = %2d:%02d:02d\n”,ho,mnt,sc); nosound();
do gotoxy(30,10); delay(100);
{ printf(“1.(G)oto MAIN MENU\n”); }
k=getch(); gotoxy(30,12); }
k=touchper(k); printf(“2.(S)et Alaram\n”); Roulet()/*Function for Roulette Wheel*/
if(k==’D’) if(shor==ho&&smin==mnt&&ssec==sc) {
{ { int i,k=0;
Aclock(0,0,0); alarm(15); clrscr();
} } gotoxy(30,10);
if(k==‘R’) if(mnt==0&&sc==0) printf(“1.Press any key to Reset\n”);
{ { gotoxy(30,12);
Roulet(); alarm(1); printf(“2.(P)lay\n”);
} } gotoxy(30,14);
} if(bioskey(1))/* To check Whether any keyis pressed */ printf(“3.(G)oto MAIN MENU\n”);
while(k!=‘E’); k=getch(); k=getch();
clrscr(); k=toupper(k); k=toupper(k);
print(“By Vijaya kumar.P,3rd Sem,E&C, K.V.G.C.E,Sullia\n”); if(k==‘S’) do
printf(“Dedicated to Father of Electricity Michael Faraday who { {
is my favourite Scientist.\n”); setala(); for(i=1;i<13;i++)/* To generate decimal number from 1 to 12*/
exit(0); } {
} } if(bioskey(1))
Aclock(int shor,int smin,int ssec) while(k!=‘G’); k=getch();
{ { k=toupper(k);
int ho,sc,mn,mnt,k,i=0; outportb(PORT,0); if(k==‘P’)
struct time tim; main(); break;
clrscr(); } outportb(PORT,i);/*outputting binary equivalents of i
do } through Data pins of LPT port*/
{ setala() /*Function to set Alarm*/ delay(50);
gettime(&tim); { }
gotoxy(30,8); int hrs,mns,scs; }
ho=tim.ti_hour; clrscr(); while(k!=‘G’);
mn=tim.ti_min; printf(“Enter hour\n”); outportb(PORT,0);
sc=tim.ti_sec; scanf(“%d” ,&hrs); main();
mnt=mn; printf(“Enter Minute\n”); }

LONG-RANGE
CORDLESS BURGLAR ALARM
T.K. HAREENDRAN

T
his long-range cordless burglar
alarm circuit makes use of a
cordless telephone (CLT) unit with
paging facility and a few low-cost discrete
components. The circuit is so simple that
even a novice can easily construct it with-
out any dif culty.
When the ‘page’ button on a CLT is
pressed and held in that position, the
handset starts beeping to indicate that
somebody is calling. This function is used
here to build the gadget. The system con-
sists of three sub-assemblies:
1. Wireless beeper. The handset of
the CLT.
Fig. 1
2. Infrared transmitter. A number

ELECTRONICS PROJECTS Vol. 22 157

Fig. 2
of IR transmitter circuits based on the
well-known 555 chip have been published
earlier in EFY. Just select one circuit with
a modulating frequency of 36 to 38 kHz
and assemble it on a veroboard. After that,
enclose it in a proper cabinet. (EFY note. A
typical IR transmitter circuit used during
testing is shown in Fig. 1.)
3. Infrared receiver-cum-control
unit. The circuit diagram of this unit is
shown in Fig. 2. Front end of this block is
TSOP1736 infrared receiver module. This
module can demodulate 36kHz modulated
IR beam to produce an active-similar
‘low’ output. You may also use any other
module, provided it has an active-‘low’
output. The modulated IR beam from the
transmitter is received by the receiver
module and its output at pin 2 goes ‘low’.
The rest of the circuit is in sleep mode
as it does not get power for its operation.
The SCR here plays the role of an elec-
tronic switch.
WATER-LEVEL CONTROLLER
n most houses, water is rst stored
I
in an underground tank (UGT) and
from there it is pumped up to the
158 ELECTRONICS PROJECTS Vol. 22
Fig. 3
When the infrared beam is interrupt-
ed, the output of the receiver module goes
‘high’ to apply a forward bias to the base of
transistor T1. As a result, the gate of SCR
gets suf cient forward bias to conduct (and
JOYDEEP KUMAR CHAKRABORTY
overhead tank (OHT) located on the roof.
People generally switch on the pump when
their taps go dry and switch off the pump
latch). The astable multivibrator
built around IC1 starts working to
control the ‘on’/‘off’ relay timings.
Diode D1 prevents the relay from
latching and diode D2 works as a
free-wheeling diode.
Normally open (N/O) contacts
of the relay are used to close the
‘page’ button contacts until the
circuit is reset by pressing push-
to-off switch S1 (N/C type). One
may replace switch S1 with a
key-lock switch to avoid its unau-
thorised operation. The astable
circuit helps the handset user to
distinguish between a normal pag-
ing call and an intrusion warning
alarm.
After construction, fix the
transmitter and receiver modules
at opposite sides in the door frame
as shown in Fig. 3. Carefully open
the CLT and solder two wires to
the ‘page’ button ter-
minals with their free
ends connected to the
relay contacts (N/O).
Now your cordless
burglar alarm with
a wireless monitor-
ing range of about
500 metres (actual
range is based on the
CLT’s paging range)
is ready to detect an
intruder.
EFY note. The au-
thor has successfully
tested his prototype
with the following
CLT makes:
1. Panasonic KX-T
3611 BH (made in Japan)
2. Panaphone WT-3990 (made in
China)
3. Citizen JRT-5400 (made in India)
when the overhead tank starts over ow-
ing. This results in the unnecessary wast-
age and sometimes non-availability of
water in the case of emergency.
The simple circuit presented here
makes this system automatic, i.e. it
switches on the pump when the water
level in the overhead tank goes low and
switches it off as soon as the water level
reaches a pre-determined level. It also
prevents ‘dry run’ of the pump in case the
level in the underground tank goes below
the suction level.
In the gure, the common probes con-
necting the underground tank and the
overhead tank to +9V supply are marked
‘C’. The other probe in underground tank,
which is slightly above the ‘dry run’ level,
is marked ‘S’. The low-level and high-level
probes in the overhead tank are marked
‘L’ and ‘H’, respectively.
When there is enough water in the
underground tank, probes C and S are
connected through water. As a result,
transistor T1 gets forward biased and
starts conducting. This, in turn, switches
transistor T2 on. Initially, when the
overhead tank is empty, transistors T3
and T5 are in cut-off state and hence pnp
transistors T4 and T6 get forward biased
via resistors R5 and R6, respectively. and C-L, respec-
As all series-connected transistors tively. Resistor R4
T2, T4, and T6 are forward biased, they ensures that transis-
conduct to energise relay RL1 (which is tor T2 is ‘off’ in the
also connected in series with transistors absence of any base
T2, T4, and T6). Thus the supply to the voltage. Similarly,
pump motor gets completed via the lower resistors R5 and R6
set of relay contacts (assuming that switch ensure that transis-
S2 is on) and the pump starts lling the tors T4 and T6 are
overhead tank. ‘on’ in the absence
Once the relay has energised, tran- of any base voltage.
sistor T6 is bypassed via the upper set Switches S1 and S2
of contacts of the relay. As soon as the can be used to switch
water level touches probe L in the over- on and switch off, re-
head tank, transistor T5 gets forward spectively, the pump
biased and starts conducting. This, in manually.
turn, reverse biases transistor T6, which You can make
then cuts off. But since transistor T6 is and install probes
bypassed through the relay contacts, the on your own as per
pump continues to run. The level of water the requirement and
continues to rise. facilities available.
When the water level touches probe However, we are de-
H, transistor T3 gets forward biased and scribing here how the
starts conducting. This causes reverse probes were made for
biasing of transistor T4 and it gets cut this prototype.
off. As a result, the relay de-energises The author used a piece of non- in Fig. 2.
and the pump stops. Transistors T4 and metallic conduit pipe (generally used for Care has to be taken to ensure that
T6 will be turned on again only when the domestic wiring) slightly longer than the probes H and L do not touch wire C di-
water level drops below the position of depth of the overhead tank. The common rectly. Insulation of wires is to be removed
L probe. wire C goes up to the end of the pipe from the points shown. The same arrange-
Presets VR1, VR2, and VR3 are to be through the conduit. The wire for probes ment can be followed for the underground
adjusted in such a way that transistors L and H goes along with the conduit from tank also. To avoid any false triggering
T1, T3, and T5 are turned on when the the outside and enters the conduit through due to interference, a shielded wire may
water level touches probe pairs C-S, C-H, two small holes bored into it as shown be used.

ELECTRONICS PROJECTS Vol. 22 159

 INVISIBLE BROKEN WIRE DETECTOR
P
ortable loads such as video cam-
eras, halogen ood lights, elec-
trical irons, hand drillers, grind-
ers, and cutters are powered by connect-
ing long 2- or 3-core cables to the mains
plug. Due to prolonged usage, the power
cord wires are subjected to mechanical
strain and stress, which can lead to in-
ternal snapping of wires at any point. In
such a case most people go for replacing
the core/cable, as nding the exact loca-
tion of a broken wire is dif cult. In 3-core
cables, it appears almost impossible to
detect a broken wire and the point of
break without physically disturbing all
the three wires that are concealed in a
PVC jacket.
The circuit presented here can easily and
quickly detect a broken/faulty wire and its
breakage point in 1-core, 2-core, and 3-core
cables without physically disturbing wires.
It is built using hex inverter CMOS CD4069.
Gates N3 and N4 are used as a pulse gen-
erator that oscillates at around 1000 Hz in
audio range. The frequency is determined by
timing components comprising resistors R3
and R4, and capacitor C1. Gates N1 and N2
Readers’ comments:
฀ I congratulate the author for giving a
smart, useful, and compact circuit of ‘In-
visible Broken Wire Detector’ in August
issue. I have the following queries regard-
ing this circuit:
160 ELECTRONICS PROJECTS Vol. 22
K. UDHAYA KUMARAN, VU3GTH
are used to sense the presence of 230V AC
eld around the live wire and buffer weak
AC voltage picked from the test probe. The
voltage at output pin 10 of gate N2 can en-
able or inhibit the oscillator circuit.
When the test probe is away from any
high-voltage AC eld, output pin 10 of
gate N2 remains low. As a result, diode
D3 conducts and inhibits the oscillator
circuit from oscillating. Simultaneously,
the output of gate N3 at pin 6 goes ‘low’ to
cut off transistor T1. As a result, LED1 goes
off. When the test probe is moved closer to
230V AC, 50Hz mains live
wire, during every positive
half-cycle, output pin 10 of
gate N2 goes high.
Thus during every
positive half-cycle of the
mains frequency, the os-
cillator circuit is allowed
to oscillate at around 1
kHz, making red LED
(LED1) to blink. (Due to
the persistence of vision,
the LED appears to be
glowing continuously.)
This type of blinking
reduces consumption of
the current from button
cells used for power supply.
A 3V DC supply is suf cient for power-
ing the whole circuit. AG13 or LR44 type
button cells, which are also used inside
laser pointers or in LED-based continuity
testers, can be used for the circuit. The
circuit consumes 3 mA during the sensing
of AC mains voltage.
For audio-visual indication, one may
use a small buzzer (usually built inside
quartz alarm time pieces) in parallel with
one small (3mm) LCD in place of LED1
and resistor R5. In such a case, the cur-
rent consumption of the circuit will be
1. How do gates N1 and N2 sense the
presence of 230V AC eld around the live
wire?
2. What is meant by buffering weak
AC voltage?
3. Why only 1kHz oscillator is used
around 7 mA. Alternatively, one may use
two 1.5V R6- or AA-type batteries. Using
this gadget, one can also quickly detect
fused small lament bulbs in serial loops
powered by 230V AC mains.
The whole circuit can be accommo-
dated in a small PVC pipe and used as
a handy broken-wire detector. Before
detecting broken faulty wires, take out
any connected load and nd out the faulty
wire rst by continuity method using any
multimeter or continuity tester. Then con-
nect 230V AC mains live wire at one end of
the faulty wire, leaving the other end free.
Connect neutral terminal of the mains
AC to the remaining wires at one end.
However, if any of the remaining wires is
also found to be faulty, then both ends of
these wires are connected to neutral. For
single-wire testing, connecting neutral
only to the live wire at one end is suf cient
to detect the breakage point.
In this circuit, a 5cm (2-inch) long,
thick, single-strand wire is used as the
test probe. To detect the breakage point,
turn on switch S1 and slowly move the test
probe closer to the faulty wire, beginning
with the input point of the live wire and
proceeding towards its other end. LED1
starts glowing during the presence of AC
voltage in faulty wire. When the break-
age point is reached, LED1 immediately
extinguishes due to the non-availability
of mains AC voltage. The point where
LED1 is turned off is the exact broken-
wire point.
While testing a broken 3-core rounded
cable wire, bend the probe’s edge in the
form of ‘J’ to increase its sensitivity and
move the bent edge of the test probe closer
over the cable. During testing avoid any
strong electric eld close to the circuit to
avoid false detection.
for the detection of signal at pin 10 of IC
4069?
4. While searching broken points in
faulty wires, why the remaining wires are
neutralised?
Rajeev Mehndiratta, Rohtak
฀ We used the circuit as continuity tester
as follows:
Keep the nger in the positive ter-
minal of the battery.
Touch the wire end that is to be
checked.
Keep the test probe on the other end
of the wire.
If the wire is good, the LED glows.
Otherwise, the LED does not glow.
In this regard, we require some clari-
cation on the following:
1. In case the probe touches on AC
230V, what will happen to the circuit?
2. Shall we get a shock if we place
our hand on the positive terminal of the
battery?
P. Ramesh and S. Ponkumar
Tuticorin
In reply to Rajeev Mehndiratta, the
author, K. Udhaya Kumaran, states:
1. CMOS gate has a very high input im-
pedance. When the test probe is placed
closer to 230V AC electrical eld, some
AC voltage is induced in the test probe,
PC-BASED MULTI-MODE
LIGHT CHASER
F
or those who want to use their PC
for various electronic functions,
here is a circuit that converts a PC
to a multi-mode light chaser. The advan-
tage of this light chaser over other light
chasers is that users can de ne their own
patterns (designs) of running lights by
altering the source program that requires
a simple hardware. The program given
here produces 24 different patterns of
running light.
The circuit shown in Fig. 1 is mainly
used to physically isolate the PC hardware
from the mains supply and to make it
capable of driving 230V loads. The PC’s
parallel port (LPT1) provided on its back
is used to interface with the circuit. LPT
port is terminated in a 25-pin ‘D’ type
female connector. Its pin con guration is
shown in Table I.
Triacs are used to drive 230V bulbs.
which is suf cient to make the output gate
of N1 go low and the output gate of N2 go
high. Thus during every positive cycle, pin
10 of gate N2 goes high, which activates
the oscillator circuit.
2. As diode D1 conducts during
every positive half cycle of AC, the DC
voltage available at the cathode of diode
D1 provides a very small source current,
which is not able to control the oscilla-
tor circuit directly. When gates N1 and
N2 are used as buffer (booster), the DC
voltage available at pin 10 of IC1 is capa-
ble of enabling/inhibiting the oscillator
circuit.
3. The 1kHz oscillator circuit is not
used to detect signals at pin 10 of IC1,
but it is used for providing audio-visual
indication during sensing of 230V AC eld.
During rest of the period, the oscillator
remains inhibited.
4. While connecting 230V AC phase
point to the faulty wire, there is a possi-
bility of voltage induction into the wires
that are in close proximity to the faulty
VIJAYA KUMAR P.
TABLE I
Pin Con guration
Pin Description
1 *Strobe
2 Data bit 0
3 Data bit 1
4 Data bit 2
5 Data bit 3
6 Data bit 4
7 Data bit 5
8 Data bit 6
9 Data bit 7
10 Acknowledge
11 *Busy
12 Paper end
13 Select
14 *Auto feed
15 Error
16 Initialise
17 *Select input
18-25 Ground
Note: *indicates that pins are internally
(hardware) inverted.
wire. This may lead to false detection of
broken wire point or no detection. By con-
necting remaining wires to neutral, there
is no likelihood of false detection.
Reply to P. Ramesh and S. Ponkumar:
In the prototype circuit, single strand
wire with sleeve was used as the probe, so
there is no chance for the probe to come in
direct contact with the mains AC voltage.
However, nothing will happen if you use
a naked wire as a probe that is in direct
contact with mains live wire. If you touch
the positive terminal of the battery, you
won’t get any lethal electrical shock be-
cause resistance between the test probe
and ground (resistor R1 + your body resist-
ance) is more than 1 mega-ohm.
As described by you using my circuit
as continuity tester, some time testing
continuity of long wire may not be reliable
because my circuit show wrong continuity
indication even if in between any part of
wire are partially contacted or long wire
may act as probe and sense any neigh-
bouring electrical eld.
Triac BT136 used here can take up a load
of up to 800 watts. If you want to drive
higher loads, BT136 (4A) can be replaced
with triacs of higher current ratings, like
BT139 (16A). Since we are using triacs to
drive 230V bulbs, the mains supply would
also appear on the PC. Optocouplers have
been used to isolate the PC from 230V
mains supply.
The circuit can be assembled on a
general-purpose dotted PCB and can be
linked to the PC’s LPT port (female) us-
Decimal number Binary equivalents
1 00000001
2 00000010
4 00000100
8 00001000
16 00010000
32 00100000
64 01000000
128 10000000
ELECTRONICS PROJECTS Vol. 22 161

ing a 25-pin male ‘D’ type connector along
with a 25-core cable. Instead of connect-
ing 230V bulbs you can connect small
6.2V miniature lamps, which are easily
available in electrical shops. Connections
are shown in Fig. 3. While using 6.2V
162 ELECTRONICS PROJECTS Vol. 22
input decimal number
from the keyboard. The
outportb() function di-
rectly outputs the binary
equivalent of the decimal
number to LPT1 (Port ID
is 0x0378). For example,
if the number entered is
15, its binary equivalent
00001111 is written into
data pins D0 to D7 of
the parallel port.
To understand the
logic of multi-mode light
chaser, first consider
the following simple se-
quential running light
program:
#include <stdio.h>
#include <dos.h>
#include <math.h>
main()
{
int temp=0,i,ch,PORT =
0x0378;
printf(“Press x to exit”);
run:
for(i=0;i<8;i++)
{
tempb=pow(2,i);
outportb(PORT,temp); /*
outputs BINARY no.
to
LPT1 */
delay(2000); /*using delay
to control speed */
if(bioskey(1))/*To check
miniature lamps, 50 miniature lamps whether any key is
must be connected in series and the net pressed */
combination of 50 bulbs in series should ch=getch();
be connected to each channel (channel 1 ch=toupper(ch);
through channel 8). if(ch==’X’)
Since LEDs require very small cur- {
rent, parallel ports can directly drive exit(0);
LEDs. Software can be tested using simple }
hardware as shown in Fig. 2. }
C language provides a built-in out- goto run;
portb() function to output binary data to a }
hardware port. To understand this, let us In the above program, ‘for’ loop is
consider the following program: used to increment ‘i’ in steps of 1 up to
#include <dos.h> 7. As these values of ‘i’ get substituted in
main() temp=pow(2,i), numbers temp= 20=1, 21=2,
{ 22 =4, 23=8, 24=16, 25=32, 26=64, and 27=128
int i; are generated. The outportb() function is
printf(“Input a decimal number”); used to write binary equivalents of 1, 2, 4,
scanf (“%d”,&i); 8, 16, 32, 64, and 128 to data pins D0 to
outportb() (0x0378,i); D7, with D0 as the least signi cant digit
} and D7 as the most signi cant digit.
The above program is used to output a The binary equivalents of numbers
binary equivalent of the decimal number obtained by incrementing powers of 2 up
entered. Scanf function is used to take the to 7 are given below:

It is clear from the table that the
resulting binary numbers will produce
the running light effect. Delay function
de nes the speed of running. Go to
statement is used to take control uncon-
ditionally to ‘for’ loop, so as to repeat the
running process.
By changing the formula of produc-
ing binary number patterns, one can get
different actions. The multi-mode light
chaser program is divided into a number
of cases. Each case will produce two
or more actions. These cases are made
to switch automatically using switch
statement and one ‘for’ loop. Further, by
changing the delay time, one can increase
or decrease the speed of running lights.
EFY note. The complete source-code
of multi-mode chaser lights in C lan-
guage has been included along with the
executable version of the program in the
accompanied CD.

FUSE STATUS INDICATORS

FOR POWER-SUPPLIES
M.K. CHANDRA MOULEESWARAN

F
use status indicators are very with all sorts of power-supplies and other LED in series with the red part of the
simple to construct using a few instruments that use power-supply sec- bi-colour LED. So the fuse failure is in-
components. These go very nicely tions. The logic and the formula, if any, dicated by the ashing of LED as well as
used with each cir-
cuit/ gure are shown
in the corresponding
truth tables.
Fig. 1 shows the
use of a 3-pin bi-col-
our LED. When the
fuse is intact, both
red and green parts
of the LED are lit and the LED
emits a yellow light. With the fuse
in blown condition, only the bottom
part of the LED gets the supply
and therefore only the red part of
the LED is lit. The formulae for
working out the values of current-
limiting resistors
TABLE I (REFER FIG. 1) for each colour
Indicator Details LED are shown the red part of the bi-colour LED.
Fuse status Bias to LED1 Colour of LED1 in Table I. These Fig. 3 shows the use of a bi-colour
A1-red anode A2-green anode relationships are LED in the AC mains supply circuit. The
Intact Forward Forward Red+green=yellow applicable to the unique feature of this circuit is that just
Blown Forward Nil Red circuits of Figs 1 by altering the resistor values, it can be
Relationship to evaluate R1 and R2 in Figs 1 and 2: and 2. used in low-voltage AC circuits or DC
DCVin-VLED % ILED=R1 or R2 in ohms Fig. 2 em- circuits.
where Vin and VLED are in volts, ILED in amperes
In Fig. 2, VLED=VD2+VLED for asher LED path
ploys an addi- The AC is converted into pulsating
tional flashing DC using recti er diodes before appli-

ELECTRONICS PROJECTS Vol. 22 163

 TABLE II (REFER FIG. 2) cation to the LED sections via current-
Indicator Details limiting resistors. For higher power
Fuse status Bias to LED1 and LED2 Colour of
dissipation in current-limiting resistors,
LED2-anode A1-red anode A2 green anode LED1 and LED2 a series combination of resistors can be
Intact Forward Forward Forward Continuous green LED1+ used. Because of the pulsating voltage,
ash red LED1+ ash red the LEDs would produce a ickering
LED2=green and yellow effect. The total series resistance with
alternate+ ash red each LED section may be calculated by
Blown Forward Forward Nil Flashing red LED1 and LED2
dividing 200 volts with the desired LED
current (say, 10 mA).
Fig. 4 shows the use of a 2-pin bi-
TABLE III (REFER FIG. 3)
colour LED. The two LEDs are internally
Indicator Details
connected in reverse, so they glow both
Bias to LED1 Colour of LED1 ways of the supply polarity connections
A1-red anode A2-green anode
and can be easily used for AC circuits as
Intact Forward Forward Red+green=yellow at 50Hz icker
Blown Forward Nil Red at 50Hz icker
indicators. The correct polarity is indi-
cated by green and the reverse polarity
Note. Approximate DCVin at C of D1 or D2 is 200 volts
by red. The AC supply is shown by yel-
low, which, in fact, is due to the turning
TABLE IV (REFER FIG. 4) ‘on’ of both the colours at the AC mains
Indicator Details
frequency. When the frequency is more
than 20 Hz, the two colours combine to
Supply input Polarity of Polarity to LED1 Colour of LED1
the supply at P1 at P2 produce yellow light. Pin identi cation
DC Forward Positive Negative Red-continuous of this LED is done usually by using a
Reverse Negative Positive Green-continuous current-limiting resistor and DC sup-
AC Alternates Alternates Alternates between red ply only.
at 50Hz/s at 50Hz/s and green at 50 Hz and All the circuits can be effectively al-
appears yellow
tered to suit an individual’s requirement.

A HIERARCHICAL PRIORITY ENCODER

DR BHASKARA RAO N.

A
normal priority encoder encodes
only the highest-order data line.
But in many situations, not only
the highest but the second-highest
priority information is also needed. The
circuit presented here encodes both
the highest-priority information as well as
the second-highest priority information of
an 8-line incoming data. The circuit uses
the standard octal priority encoder 74148
that is an 8-line-to-3-line (4-2-1) binary
encoder with active-‘low’ data inputs and
outputs.
The first encoder (IC1) generates
the highest-priority value, say, F. The
active-‘low’ output (A0, A1, A2) of IC1 is
inverted by gates N9 through N11 and fed
to a 3-line-to-8-line decoder (74138) that
requires active-‘high’ inputs. The decoded
outputs are active-‘low’. The decoder identi-
es the highest-priority data line and that
data value is cancelled using XNOR gates
(N1 through N8) to retain the second-
highest priority value that is generated by
the second encoder.
To understand the logic, let the incom-
ing data lines be denoted as L0 to L7. Lp
is the highest-priority line (active-‘low’)
and Lq the second-highest priority line
(active-‘low’). Thus Lp=0 and Lq=0. All
lines above Lp and also between Lp and
Lq (denoted as Lj) are at logic 1. All lines
below Lq logic state are irrelevant, i.e.
‘don’t care’. Here p is the highest-priority
value and q the second-highest-priority
value. (Obviously, q has to be lower than
p, and the minimum possible value for p
is taken as ‘1’.)
Priority encoder IC1 generates binary
output F2, F1, F0, which represents the
value of p in active-‘low’ format. The
complemented F2, F1, and F0 are ap-
plied to 3-line-to-8-line (one out of eight
outputs is active-‘low’) decoder 74138.
Let the output lines of 74138 be denoted
as M0 through M7. Now only one line
is active-‘low’ among M0 through M7,
and that is Mp (where the value of p is
explained as above). Therefore the logic
level of line Mp is ‘0’ and that of all other
M lines ‘1’.
The highest-priority line is cancelled
using eight XNOR gates as shown in the
gure. Let the output lines from XNOR
gates be N0 through N7. Consider inputs
Lp and Mp of the corresponding XNOR
gate. Since Mp = 0 and also Lp = 0, the
output of this XNOR gate is Np = com-
plement of Lp = 1. All other L’s are not
changed because the corresponding M’s
are all 1’s. Thus data lines N0 through N7
are same as L0 through L7, except that
the highest-priority level in L0 through

164 ELECTRONICS PROJECTS Vol. 22

L7 is cancelled in N0 through N7.
The highest-priority level in N0
through N7 is the second-highest priority
leftover from L0 through L7, i.e. Nq=0
and Nj=1 for q<j≤7. Now these N lines
are applied to priority encoder 2 (IC3) to
generate S2, S1, S0, which represent q.
Thus the second-highest priority value
DIGITAL MAINS VOLTAGE INDICATOR
C
ontinuous monitoring of the mains
voltage is required in many ap-
plications such as manual voltage
stabilisers and motor pumps. An ana-
logue voltmeter, though cheap, has many
disadvantages as it has moving parts and
is sensitive to vibrations. The solidstate
voltmeter circuit described here indicates
the mains voltage with a resolution that
is comparable to that of a general-purpose
analogue voltmeter. The status of the
mains voltage is available in the form of
an LED bar graph.
Presets VR1 through VR16 are used
is extracted. Through cascading one can
recover the third-highest priority, and
so on.
For example, let L0 through L7 = X X
X 0 1 1 0 1. Here the highest ‘0’ line is L6
and the next highest is L3 (X denotes ‘don’t
care’). Thus p=6 and q=3. Now the active-
low output of the rst priority encoder will
PRATAP CHANDRA SAHU
to set the DC voltages corresponding to
the 16 voltage levels over the 50-250V
range as marked on LED1 through
LED16, respectively, in the gure. The
LED bar graph is multiplexed from the
bottom to the top with the help of ICs
CD4067B (16-channel multiplexer) and
CD4029B (counter). The counter clocked
by NE555 timer-based astable multi-
vibrator generates 4-bit binary address
for multiplexer-demultiplexer pair of
CD4067B and CD4514B.
The voltage from the wipers of presets
are multiplexed by CD4067B and the
be F2 F1 F0 = 0 0 1. The input to 74138 is
1 1 0 and it outputs M0 through M7 = 1 1
1 1 1 1 0 1. Since M6=0, only L6 is comple-
mented by XNOR gates. Thus the outputs
of XNORs are N0 through N7 = X X X 0 1 1
1 1. Now N3=0 and the highest priority for
‘N’ is 3. This value is recovered by priority
encoder 2 (IC3) as S2 S1 S0 = 1 0 0.
output from pin 1 of CD4067B is fed to
the non-inverting input of comparator
A2 (half of op-amp LM358) after being
buffered by A1 (the other half of IC2). The
unregulated voltage sensed from recti er
output is fed to the inverting input of
comparator A2.
The output of comparator A2 is low
until the sensed voltage is greater than
the reference input applied at the non-
inverting pins of comparator A2 via
buffer A1. When the sensed voltage goes
below the reference voltage, the output of
comparator A2 goes high. The high output
ELECTRONICS PROJECTS Vol. 22 165
from comparator A2 inhibits the decoder
(CD4514) that is used to decode the out-
put of IC4029 and drive the LEDs. This
ensures that the LEDs of the bar graph
are ‘on’ up to the sensed voltage-level pro-
portional to the mains voltage.
The initial adjustment of each of the
ELECTRONIC DICE
H
ere is a small circuit of an elec-
tronic dice to interface with your
PC. The circuit simulates a digital
dice and uses the parallel-port LPT1 pro-
vided on the back of the PC. LPT employs
a 25-pin ‘D’ type female connector.
‘C’ language provides a built-in out-
portb() function to output binary data to
166 ELECTRONICS PROJECTS Vol. 22
presets can be done by feeding a known
AC voltage through an auto-transformer
and then adjusting the corresponding
preset to ensure that only those LEDs that
are up to the applied voltage glow.
(EFY note. It is advisable to use ad-
ditional transformer, recti er, lter, and
VIJAYA KUMAR P.
the hardware port. To understand this,
let us consider the following program:
#include <dos.h>
main()
{ number entered via the keyboard.
int i;
printf(“Input a decimal number”);
scanf (“%d”,&i);
regulator arrangements for obtaining a
regulated supply for the functioning of the
circuit so that performance of the circuit is
not affected even when the mains voltage
falls as low as 50V or goes as high as 280V.
During Lab testing regulated 12-volt sup-
ply for circuit operation was used.)
outportb(0x0378,i);
}
The above program is used to out-
put the binary equivalent of a decimal
‘Scanf’ function is used to take the input
decimal number from the keyboard. The
‘outportb()’ function directly outputs the
 binary equivalent of decimal number to
LPT1 (port ID is 0x0378).
For example, after you convert the
above program into an executable le
using Turbo C compiler and run it, the
program prompts you to “Input a decimal
number”. Suppose you enter 15 , then its
binary equivalent 00001111 is output
(written) to data pins D0 through D7
(pins 2 through 9) of the 25-pin parallel
port. If LEDs are connected to the out-
put pins of the parallel port, along with
Fig. 1 resistors of 220-ohm in series, they can
be directly driven to indicate the binary
TRUTH TABLE output number, as the parallel port can
directly support the current required for
Throw Data pins State of LEDs Display
Logic state
driving the LEDs.
D2 D1 D0 A B C D E F G The electronic dice program generates
a random decimal number that is output
1 0 0 1 OFF OFF OFF OFF OFF OFF ON through data-output lines D0 through D2
2 0 1 0 ON OFF OFF OFF OFF ON OFF
(pins 2 through 4) of the LPT port in the
form of a 3-bit binary number.
3 0 1 1 ON OFF OFF OFF OFF ON ON Fig. 1 shows the hardware interface
circuit of a BCD-to-decimal converter
4 1 0 0 ON OFF ON ON OFF ON OFF
employing a 7-segment display driver IC
5 1 0 1 ON OFF ON ON OFF ON ON 7447, which directly converts the input
BCD number into 7-segment display.
6 1 1 0 ON ON ON ON ON ON OFF Fig. 2 shows the circuit simulating the
electronic dice with dot pattern display
that satis es the truth table shown. Fig.
3 shows the Karnaugh Map simpli cation
of minterms.
When the software program using
‘C’ language is run after compilation, it
prompts you to press letter ‘T’ for simu-
lating an action equivalent to throwing of
dice by generating/outputting a random
number, or press letter ‘X’ to exit the pro-
gram. The program is given below:
#include <stdio.h>
#include <dos.h>
#include <conio.h>
#include <graphics.h>
#include <stdlib.h>
#define PORT 0x0378 /*LPT1 Data Port
Fig. 2 Address */
/*Use 0x0278 for LPT2 */
void main(void)
{
int ran;
int gd=DETECT,gm,ch,x,y;
initgraph(&gd,&gm ,""); /* Initializes
graphics mode */
/* Decorating the screen */
x = getmaxx();/*Get maximum screen
coordinates x & y*/
y = getmaxy();
setbkcolor(BLUE);
rectangle(10,y-10,x-10,10);
setcolor(YELLOW);
settextstyle(DEFAULT_FONT,
Fig. 3

ELECTRONICS PROJECTS Vol. 22 167

 HORIZ_DIR,2);
outtextxy(120,20,"*** ELECTRONIC
DICE ***");
setcolor(GREEN);
outtextxy(x/5,180,"1.Press T to Throw
Dice");
outtextxy(x/5,230,"2.Press X to Exit");
/* Actual program */
randomize();/*Initializes random number
generator */
do {
LIGHT-OPERATED ORGAN
PRADEEP G.
H
ere is a circuit based on a
unijunction transistor (UJT)
2N2646 or its equivalent that can
be used as a light-operated organ. Wired
as a relaxation oscillator, it can oscillate
independently without a tank circuit or
complicated RC feedback network.
A light-dependent resistor (LDR) is
STEREO TAPE HEAD PREAMPLIFIER
FOR PC SOUND CARD
H
ere is a stereo tape head pream-
pli er circuit for your PC sound
card that can playback your
favourite audio cassette through the
PC. Audio signals from this circuit can
be directly connected to the stereo-input
(line-input) socket of the PC sound card
for further processing.
The circuit is built around a popular
stereo head preamp IC LA3161. Weak
electrical signals from the playback
heads are fed to pins 1 and 8 of IC1 via
DC decoupling capacitors C1 and C6,
respectively. Components between pins 2
and 3 and pins 6 and 7 provide adequate
equalisation to the signals for a normal
tape playback.
168 ELECTRONICS PROJECTS Vol. 22
ch= getch();
ch= toupper(ch);
if(ch=='T') /* If T is Pressed */
{ Port */
ran=random(6); /* to generate
random number between 0&7 */
ran=ran+1;
outport(PORT,ran); /* outputs
BINARY no. to LPT's Data Port */
} (EFY note. Source code has also been
} included in the accompanied CD.)
included in the emitter circuit of T1 as
T.K. HAREENDRAN
The ampli ed and equalised signals
available at output pins 3 and 6 of IC1
are coupled to the inputs of line ampli-
er circuit built around transistors T1
(via capacitor C5, potmeter VR1, resis-
tor R8, and capacitor C12) and T2 (via
capacitor C10, potmeter VR2, resistor
R19, and capacitor C16), respectively.
Left and right playback levels can be
adjusted by variable resistors VR1 and
VR2. The audio signals are nally avail-
able at the negative ends of capacitors
C13 and C17.
The circuit wired around relay driver
transistor T3 serves as a simple source
selector. This is added deliberately to help
the user share the common PC sound card
while(ch!='X'); /* Exit the program if X is
pressed */
outportb(PORT,0); /* Clears LPT's Data
closegraph(); /*Shuts down graphics
mode */
printf("By Vijaya Kumar.p");
exit(0);
}
shown in the diagram. When LDR re-
ceives light from a light source,
such as an electric bulb, a
sharp and pleasing audio tone
is heard from the speaker. The
intensity of light falling on
LDR can be varied by waving
a hand to and fro between the
lamp and the LDR. As a result,
the frequency of the output
sound changes.
line-input terminal for operating some
other audio device as well.
When the preampli er is in off state,
switching relay RL1 is off and it allows
connection of external signals to the sound
card. When the preampli er is turned
‘on’, the relay is energised by transistor
T3 after a short delay determined by
the values of resistor R21 and capacitor
C20. On energisation, the relay contacts
changeover the signals to internal source,
i.e. the head preampli er.
After constructing the whole circuit
on a veroboard, enclose it in a mini metal-
lic cabinet with level controls and sockets
at suitable points. Use a regulated 1A,
12V DC power supply for powering the
whole circuit including the tape deck lytic capacitor and 78M12 regulator is mechanism with this circuit. Use of good-
mechanism. (A 1A, 18V AC secondary suf cient.) quality playback head and well-screened
transformer with 4700µF, 40V electro- You can use any kind of tape deck wires are recommended.

HEART BEAT MONITOR

PRADEEP G.

H
ere is a simple and low-cost cir-
cuit of heart beat monitor using
readily available components. It
uses the piezo-electric plate of audible
piezobuzzers as the sensing device, which
can be purchased for around Rs 2 only
from component vendors.
The sensor is pressed against human
body near the heart region. It should make
a solid contact with your palm to convert
heart beat sound into low-frequency elec-
trical variations. These electrical varia-
tions are ampli ed by transistor T1 that is
con gured as a common-emitter ampli er.
Ampli ed signals are coupled to transistor
T2 for driving the audio power ampli er
stage. The speaker reproduces heart beat used in the power output stage are freely silicon transistors, replace 220-ohm resis-
notes as audible sound. available. In case you use AC188/128 ger- tors with 47-ohm resistors and 680-ohm
The two BEL188 silicon transistors manium transistors in place of BEL188 resistors with 1-kilo-ohm resistors.

ELECTRONICS PROJECTS Vol. 22 169

 DIGITAL FAN REGULATOR
SUNIL P.B.

T
he circuit presented here can be duration current pulses at its gate. For The pedestal voltage is derived from
used to control the speed of fans this purpose a UJT relaxation oscillator the non- ltered DC through optocoupler
using induction motor. The speed is used that outputs sawtooth wave- 4N33. The conductivity of the Darlington
control is nonlinear, i.e. in steps. The form. This waveform is coupled to the pair transistors inside this optocoupler is
current step number is displayed on a gate of the triac through an optocoupler varied for getting the pedestal voltage. For
7-segment display. Speed can be varied (MOC3011) that has a triac driver out- this, the positive supply to the LED inside
over a wide range because the circuit can put stage. the optocoupler is connected via different
alter the voltage applied to the fan motor Pedestal voltage control is used for values of resistors using a multiplexer
from 130V to 230V RMS in a maximum of varying the ring angle of the triac. The (CD4051).
seven steps. power supply for the relaxation oscillator The value of resistance selected by
The triac used in the nal stage is is derived from the recti ed mains via the multiplexer depends upon the control
red at different angles to get differ- 10-kilo-ohm, 10W series dropping/limiting input from BCD up-/down-counter CD4510
ent voltage outputs by applying short- resistor R2. (IC5), which, in turn, controls forward
biasing of the transis-
tor inside optocoupler
4N33. The same BCD
outputs from IC5 are
also connected to the
BCD-to-7-segment de-
coder to display the
step number on a 7-seg-
ment display.
NAND gates N3
and N4 are con gured
as an astable multi-
vibrator to produce rec-
tangular clock pulses
for IC5, while NAND
gates N1 and N2 gener-
ate the active-low count
enable (CE) input using
either of push-to-on
switches S1 or S2 for
count up or count down
operation, respectively,
of the BCD counter.
Optocoupler 4N33
electrically isolates
the high-voltage sec-
tion and the digital
section and thus pre-
vents the user from
shock hazard when
using switches S1 and
S2. BCD-to-7-segment
decoder CD4543 is
used for driving both
common-cathode and
common-anode 7-seg-
ment displays. If phase
input pin 6 is ‘high’
the decoder works as
a common-anode de-

170 ELECTRONICS PROJECTS Vol. 22

coder, and if phase input pin 6 is ‘low’ it slightly even when the display is zero, i.e. preset VR1 as required using a plastic-
acts as a common-cathode decoder. pin 13 (X0, at ground level) is switched to handled screwdriver to get no output at
Optocoupler 4N33 may still conduct output pin 3. To avoid this problem, adjust zero reading in the display.

RUNNING LIGHTS AND

RUNNING HOLES
VIJAYA KUMAR P.

T
his four-channel, two-mode light astable multivibrator for generating clock using preset VR1. CD4030 (IC3) is a quad
chaser circuit produces effects of signals for decade counter CD4017 (IC2). XOR gate that can be used both as an in-
running holes and running lights. The speed of running lights can be varied verting and a non-inverting gate by tying

Fig. 1

Each effect, i.e. running lights or running

12V
holes, is repeated ve times. Applications
include decorating photographs using
LEDs or driving 230V bulbs via triacs.
Fig. 1 shows the circuit for driving the
bulbs using triacs, while Fig. 2 is a modi-
cation of Fig. 1 for driving LEDs without
using triacs.
In Fig. 1, timer 555 is used as an

Fig. 2

ELECTRONICS PROJECTS Vol. 22 171

any one of the XOR gate inputs high and
low, respectively (refer the table).
For every fourth clock to IC2, its pin
7 goes high, which, in turn, clocks IC4.
Since the rst ve outputs of IC4 are
connected together (wired ORed) using
diodes D3 through D7, the output at
the tied end remains high for every ve
clock pulses at IC4. This output is cou-
pled to one of the inputs of all the four
XOR gates.
When the output of IC4 (Q) goes
high, the outputs of IC2 get inverted and
produce the running hole effect. And when
the output of IC4 (Q) goes low, XOR gates
act as non-inverters and the outputs of
IC2 remain as original and produce the
running light effect.

A SIMPLE TRANSISTOR TESTER

J. BALAJI

T
his simple-to-construct circuit is
useful for testing both npn and
pnp low-power transistors. It com-
prises a few resistors, LEDs, diodes, and
a mains step-down transformer.
The 230V mains voltage is stepped
down to about 6 volts AC before applica-
tion to the circuit. The leads of transis-
tor under test are inserted in the test
terminals (sockets) marked E, B, and C
(for emitter, base, and collector, respec-
tively) appropriately, i.e. the emitter of the
transistor is to be inserted in terminal
E, the base of the transistor in terminal
B, and the collector of the transistor in
terminal C. the transistor. Two different coloured not. Likewise, when a pnp transistor is
The resistor to be connected in series (green and red) LEDs are used for indi- tested, the glowing of red LED indi-
with the base terminal is selected with cation. cates that the transistor is good and no
the help of a 6-position rotary switch Green LED glows if the npn tran- glowing indicates that the transistor
S1 as per base current requirement for sistor under test is good, otherwise is bad.

12V, 3A POWER SUPPLY

D. PRABAKARAN

T
his circuit provides a 12V regu-
lated power supply with output
current up to 3 amperes. It is spe-
cially designed for use with 2m handheld
rigs with linear power ampli er and CB
portable QRP rigs.
The circuit uses monolithic IC CA3085
voltage regulator in 8-lead TO-5 package.
Its salient features include good load and
line regulation, output current up to 100
mA (which can be increased to several
amperes with additional pass transistors),
output short-circuit protection, and lower
input voltage.
A low power dissipation is achieved
by driving external series-pass transis-
tor 2N4241 (T1) from pin 2 of CA3085.
Normal output pin 8 is returned to ground
via diodes D3 and D4 to ensure error am-
pli cation operation in the linear region.
Ripple rejection is approximately 50 dB on
no load and 35 dB on full load.

172 ELECTRONICS PROJECTS Vol. 22

 A 2x2x2.5cm aluminium heat sink fas-
tened onto a 1.5mm blackened aluminium
sheet of 12.5cm2 area on 2N4241 helps the
circuit in dissipating heat without exceed-
SPELLER EFFECT SIGN DISPLAY
T
he circuit described here uses low-
cost and easily available IC
CD4017 to produce a speller type
light display. In such displays, each letter
of the sign sequentially lights up, one after
the other, until all letters are glowing.
After a few seconds, the letters switch off
and the cycle repeats. This circuit provides
a maximum of nine channels and therefore
can be used to spell a word or sign having
up to nine characters.
Timer IC1 (555) is con gured in asta-
ble mode to produce clock signal for trig-
gering IC2 (CD4017). Speed of switching
on the display can be controlled by varying
preset VR1.
CD4017 is a decade counter having ten
outputs, of which one output is high for
each clock pulse. However, this produces
ing maximum device ratings.
CA3085 can dissipate up to 650mW
power in free air, without any heat sink.
AFCO-make C-05-4 heat sink is suitable
VIJAYA KUMAR P.
running lights effect. To change this se-
quence to get the speller effect, pnp tran-
sistors T1 through T9 are wired as shown
in the gure. Nine triacs (triac 1 through
triac 9) are used to drive 230V bulbs. (In
place of 230V bulbs, miniature lamps con-
nected in series in the form of characters
or letters can also be used, provided the
voltage drop across the series combination
is 230 volts.)
When any of the outputs of IC2 goes
high, the corresponding transistor con-
nected to the output goes off. When Q0 is
high, transistor T1 goes off and its output
at the collector goes low. Since the emit-
ter of transistor T2 is connected to the
collector of transistor T1, and collector
and emitter terminals of transistors T1
through T9 are connected in series, all
for this IC. An improper heat sink may
cause device junction temperature to
exceed the limit, resulting in progressive
deterioration of the device.
transistors next to transistor T1, i.e. tran-
sistors T2 through T9, do not get supply
and hence all their outputs go low.
Next, when Q1 output goes high,
transistor T2 goes off. Thus outputs of
transistors T2 through T9 remain low.
Since Q0 output at this instant is low,
transistor T1 is forward biased and its
output goes high to light up the rst
character.
Similarly, when Q2 output goes high,
Q0 and Q1 outputs are low and there-
fore outputs of transistors T1 and T2
go high to light up the rst and second
characters.
This process continues until all tran-
sistors turn on, making all the characters
to light up. The cycle repeats endlessly,
producing the speller type light effect.
ELECTRONICS PROJECTS Vol. 22 173
 DARKROOM TIMER
T
he timer circuit described here pro-
vides a pleasant musical tone in
your darkroom at 1-second in-
tervals. The circuit takes up very little
space and can be easily converted into a
metronome.
Unijunction transistor (UJT) T1 func-
tioning as a relaxation oscillator triggers
the phase-shift audio oscillator circuit
ACTIVE SHORTWAVE ANTENNA
T
he circuit presented here boosts
weak shortwave signals so that
these can be heard with enhanced
clarity over a shortwave receiver. Fur-
ther, the receiver doesn’t require any
physical connection as its placement in
the vicinity (within 6 to 7 cm) of the cir-
cuit will suf ce. The circuit works well
over a wide range of supply voltage from
3 volts to 12 volts.
Low-noise transistor T1 (BF494 or
BF495) is connected as shown in the
gure. Resistor R1 gives the DC bias to
T1. R1’s value may lie anywhere between
l00 kilo-ohms and 22 kilo-ohms; it deter-
174 ELECTRONICS PROJECTS Vol. 22
D. PRABAKARAN
built around transistor T2, turning it transistor T2 is coupled to a small speaker
on and off. As capacitor C1 is charged through a transistor-radio type output
through preset VR1 and resistor R1, the transformer.
emitter voltage of UJT rises toward the The 22-kilo-ohm value of resistor R3
supply voltage. represents a compromise between tone
When the emitter voltage becomes suf- duration and intensity. You can use resis-
ciently positive, the emitter becomes for- tors having a value anywhere between 10
ward biased and discharges capacitor C1 kilo-ohms and 25 kilo-ohms for different
through the emitter-base 1 (B1) junction durations and intensities of the output
and resistor R2. signals.
The voltage drop Since the unijunction transistor is
across R2 forward functioning as the oscillator trigger,
biases transis- changing the values of one or more com-
tor T2 and turns ponents in the UJT circuit will change the
it on. As capaci- rate of the tone burst. The tone frequency
tor C1 becomes can be varied by changing the value of
discharged, the any or more of capacitors C2 through C4
current through and resistors R5 and R6 in the phase-shift
resistor R2 drops network.
and transistor T2 The primary winding of transformer
is cut off. X1 can be tuned for a slight increase in
A tone sig- the output, using capacitor values between
nal is generated 0.05 and 0.25 µF for C5 by trial-and-error
by transistor T2 method. Tone pulses should begin about
and R-C coupled ten seconds after the unit is turned on.
phase-shift oscil- After a minute or so, adjust preset VR1 for
lator. Part of the 1-second beats by comparing the timing of
signal taken from the beats with the seconds needle on your
the collector of wristwatch.
PRAVEEN SHANKER
mines the quiescent base-emitter current
for transistor T1. Resistor R2 limits the
current owing through transistor T1
and, in conjunction with capacitor C2,
determines the operating point for its
stable operation.
The number of turns in inductor L1
would have to be reduced as operation
area shifts towards the upper end of the
high-frequency band. A 180µH RFC in
series with positive supply rail, along
with a bypass capacitor to the ground, is
recommended for reducing signal loss in
the power supply.
The current consumption is well be-
low 10 mA. The transistor works well at
maximum supply and so reduction of re-
sistor R1’s value below 22 kilo-ohm is not
recommended, as otherwise the transistor
may burn off.
This circuit works satisfactorily
for boosting signals in 13m-49m band.
LONG-RANGE
TARGET SHOOTER
P
racticing target shooting using a
real gun is both expensive and
risky. Also, it is not possible for
However, as the frequency increases, its
performance deteriorates. The same hap-
pens when the frequency decreases below
that of the shortwave range. For input
use a long wire as the antenna, while the
output antenna wire may be limited to
about 30 cm.
PRATAP CHANDRA SAHU
everybody to have a gun. The circuit
presented here makes you feel the excite-
ment of shooting a target situated at a
Note. The circuit is prone to self-
oscillations if the aerial (input) wire
picks up stray radiations from the
power supply wires or from the
output. So keep the power supply and
output wires well isolated from the
input.
distance of more than 100 metres without
any risk or much expenditure.
The circuit simply uses a laser pointer
(also referred to as laser torch) as the
transmitter at the gun end. Laser point-
ers can reach a maximum of 1 kilometre
distance but it is advisable to limit the
range within, say, 200 metres.
While constructing the gun no change
has to be made in the readymade pointer.
Just tightly t the pointer inside the toy
gun, so that the triggering switch can ac-
tivate the press-to-on button of the laser
pointer, as shown in Fig. 1.
The receiver comprises a counter-cum-
7-segment display driver IC (CD4033)
with a debouncer formed by 555 timer and
an LDR sensor at the input. The counter
works as a scoreboard and directly shows
the number of successful hits.
The LDR senses the pointer’s laser
beam and activates the monostable mul-
tivibrator wired around 555 timer IC. To
increase the sensitively of the receiver,
the LDR signal is ampli ed by transis-
tor T1. The timer pulse-width is set at
around 100 milliseconds so as to work as
a debouncer. The timer output is coupled
to IC CD4033.
CD4033 is a serial decade counter-
cum-7-segment decoder/driver. With
every output pulse from monostable IC1,
the count in CD4033 gets incremented by
one. Thus the output of IC2 re ects the
latest score by a competitor. Pressing reset
switch resets the display too.
You can increase the size of the
display board manyfolds using the ad-
ditional circuit shown in Fig. 3. This
multiplexed board avoids higher power
ELECTRONICS PROJECTS Vol. 22 175
 consumption and is neces-
sary if you are using the
module for long-range shoot-
ing.
For each segment, you
can wire up to ten LEDs in
parallel. Short the anodes
of LEDs of all segments
as it is a common-anode
type display. (The output
from ULN2003 will be
active-low.)
For proper functioning of
the receiver, the LDR should
be kept covered in such
a way that no external light
falls on it. Further, the
receiver should be fixed
at least two metres from
the ground so that the laser
beam is accidentally not
directed towards anybody’s
eyes. The game can be played
both in daylight as well as
at night.
Caution. Never look or
stare at the beam source and
do not bounce the beam on
a mirror.

POWER SUPPLY FOR

WALKIE-TALKIES
PRADEEP G.

H
ere is a simple power supply cir-
cuit that can be used for citi-
zen-band and VHF walkie-talkies
of power rating up to 10 watts. The circuit
uses a step-down transformer, followed by
bridge recti er, lter, regulator, and cur-
rent booster stages.
A pnp power transistor is added to
the circuit to increase its current sourcing
capabilities. Regulator 7812 can support
around 100 mA current. When the cur-
rent owing through R1 nears 100mA
value, the voltage (>0.65V) across the
emitter-base junction makes transistor
T1 to conduct and provide a path for ad-
ditional current.
The circuit can source around one am-
pere of current at 12+1.4 volts=13.4 volts. Both the regulator IC and the power transistor must be mounted on heat sinks.

176 ELECTRONICS PROJECTS Vol. 22

 HIGH-PERFORMANCE
INTERRUPTION DE TECTOR
T
he circuit presented here detects
interruption in security systems.
Its features include no false trigger-
ing by external factors (such as sunlight
and rain), easy relative positioning of the
sensors and alignment of the circuit, high
sensitivity, and reliability.
The circuit comprises three sections,
namely, transmitter, receiver, and power
supply. The transmitter generates modu-
lated IR signals and the receiver detects
the change in IR intensity. Power supply
provides regulated +5V to the transmitter
and the receiver.
The power supply and the speaker
are kept inside the premises while the
transmitter and the receiver are placed
opposite to each other at the entrance
where the detection is needed. Three
connections (Vcc, GND, and SPKR) are
needed from the power supply/speaker
to the receiver section, while only two
connections (Vcc and GND) are required
to the transmitter.
The transmitter is basically an astable
multivibrator con gured around NE555
(IC3). Its frequency should match the
frequency of the detector/sensor module
(36 kHz for the module shown in gure)
JUNOMON ABRAHAM
in the receiver. The transmitter frequency
is adjusted by preset VR2. For making
the duty cycle less than 50 per cent, diode
1N4148 is connected in the charging path
of capacitor C7.
The output of astable multivibrator
modulates the IR signal emitted from IR
LEDs that are used in series to obtain a
range of 7 metres (maximum). To increase
the range any further, the transmitted
power has to be raised by using more
number of IR LEDs. In such a case, it is
advisable to use another pair of IR LEDs
and 33-ohm series resistor in parallel
with the existing IR LEDs and resistor R5
across points X and Y.
The receiver unit consists of a monos-
table multivibrator built around NE555
(IC2), a melody generator, and an IR sen-
sor module. The output of the IR sensor
module goes high in the standby mode
or when there is continuous presence of
modulated IR signal.
When the IR signal path is blocked,
the output of the sensor module still re-
mains high. However, when the block is
removed, the output of the sensor module
brie y goes low to trigger monostable
IC3. This is due to the fact that the sen-
sor module is meant for pulsed operation.
Thus interruption of the IR path for a brief
period gives rise to pulsed operation of the
sensor module.
Once monostable IC2 gets triggered,
its output goes high and stays in that state
for the duration of its pulse width that can
be controlled by preset VR1. The high
output at pin 3 of the monostable makes
the musical IC to function. Voltage divider
comprising R2 and R3 reduces the 555
output voltage to a safer value (around
3V) for UM66 operation. The duration of
the musical notes is set by preset VR1 as
stated earlier.
For proper operation of the circuit,
use 7.5V to 12V power supply. A bat-
tery back-up can be provided so that the
circuit works in the case of power failure
also. Potmeter VR3 serves as a volume
control.
The transmitter, receiver, and power
supply units should be assembled sepa-
rately. The transmitter and the receiver
should have proper coverings (booster) for
protection against rain. The length of the
wire used for connecting the IR sensor mod-
ule and IR LEDs should be minimum.
Note. The heart of the circuit is the
ELECTRONICS PROJECTS Vol. 22 177
IR sensor module (usually used in VCRs
and TVs with remote); the circuit works
satisfactorily with various makes of
Readers’ comments:
 This circuit helps me in various ways. I
have the following queries regarding it:
1. How can I t a lamp in place of the
speaker or another device?
2. Can I perform more than one func-
DIGITAL RELAY TESTER
FOR RAX AND MAX
T
his high-speed relay tester is in-
tended for testing 12V DC 2C/O
(changeover) and 4C/O PCB-
178 ELECTRONICS PROJECTS Vol. 22
sensors. The entire circuit can be xed
in the same cabinet if the connection
wires to the sensors are smaller than 1.5
tion using this circuit?
Bhavik A. Patel
Through e-mail
The author, Junomon Abraham,
replies:
Thank you for your keen interest in this
KRISHNA SHARMA
mounted relays used in RAX (small-
capacity rural automatic exchange) and
MAX (main automatic exchange) of C-
metres. The re ection property of IR sig-
nals can also be used for small-distance
coverage.
circuit! A lamp can be connected easily by
using a simple transistor driver circuit at
output pin 3 of IC2 (NE555). For larger
loads, you may need a relay circuit to
connect the load through the contacts of
the relay.
DOT origin. It is a reliable tool for testing
relays in bulk. For other than 2C/O and
4C/O contact relays, slight modi cation
in the circuit is required.
As soon as the relay is inserted in
28-pin ZIF socket and test pushbutton S2
is pressed, the tester displays ‘pass’ or ‘fail’
on 7-segment display. If the relay coil is
open or N/O and N/C contacts are not func-
tioning as they should during operate and
release conditions, the tester immediately
displays ‘fail’ on 7-segment display. If the
relay under test is good, the display shows
‘pass’ on 7-segment display.
When the mains supply is connected
to the circuit by closing switch S1, 5V
DC supply goes to the ICs, transistors
(collectors), and common points (poles) of
the relay under test, and 12V DC supply
goes to one of the terminals of the coil of
relay under test. The outputs from four
N/C and four N/O contacts are alternately
applied to N1 and N2 gates, respectively,
FASTEST FINGER FIRST INDICATOR
Qu iz-type game shows are increas-
ingly becoming popular on tele-
vision these days. In such games, fastest
nger rst indicators (FFFIs) are used to
test the player’s reaction time. The play-
er’s designated number is displayed with
an audio alarm when the player presses
his entry button.
The circuit presented here determines
of dual 4-input AND gate IC3 (74LS21).
The high output of gate N1 goes to pin
1 of gate N3 of IC4 (7400), while the low
output of gate N2 goes to pin 2 of gate N3
of IC4. As a result, the output of gate N3
becomes high and transistor T1 conducts
to complete the path for supply to the coil
of the relay under test.
For a good relay, the output of gate
N4 is high before its energisation. After
energisation of the relay, the output of
gate N3 remain high whereas the output
of gate N4 goes low. This signal is inverted
by gate N5 to display ‘pass’. The output of
gate N5 is further inverted by gate N6 to
display ‘fail’.
The common segments of ‘pass’ and
‘fail’ characters are illuminated by OR gat-
ing via diodes D5 and D6, while exclusive
‘pass’ and ‘fail’ segments are illuminated
P. RAJESH BHAT
as to which of the four contestants rst
pressed the button and locks out the re-
maining three entries. Simultaneously,
an audio alarm and the correct decimal
number display of the corresponding con-
testant are activated.
When a contestant presses his
switch, the corresponding output of latch
IC2 (7475) changes its logic state from
directly through resistors R12 and R13
(whichever is high), respectively.
For testing 2C/O relays, keep the knob
of push switch S3 (wiring of S3 to relay
socket is shown separately) pressed to
bypass two C/O contacts out of four C/O
contacts.
The test procedure is summarised
below:
1. Switch on the power supply to the
tester.
2. Insert the relay to be tested into ZIF
socket and lock it.
3. For 4C/O relay leave knob S3 re-
leased, and for 2C/O relay keep the knob
pressed.
4. Press test switch S2 and observe the
display for ‘pass’/ ‘fail’.
5. Unlock ZIF socket and segregate the
relay as per the result.
1 to 0. The combinational circuitry com-
prising dual 4-input NAND gates of IC3
(7420) locks out subsequent entries by
producing the appropriate latch-disable
signal.
Priority encoder IC4 (74147) encodes
the active-low input condition into the
corresponding binary coded decimal (BCD)
number output. The outputs of IC4 after
ELECTRONICS PROJECTS Vol. 22 179
inversion by inverter gates inside hex
inverter 74LS04 (IC5) are coupled to BCD-
to-7-segment decoder/display driver IC6
(7447). The output of IC6 drives common-
anode 7-segment LED display (DIS.1,
FND507 or LT542).
The audio alarm generator comprises
clock oscillator IC7 (555), whose output
drives a loudspeaker. The oscillator fre-
quency can be varied with the help of pre-
set VR1. Logic 0 state at one of the outputs
of IC2 produces logic 1 input condition at
pin 4 of IC7, thereby enabling the audio
oscillator.
IC7 needs +12V DC supply for
sufficient alarm level. The remain-
ing circuit operates on regulated +5V
DC supply, which is obtained using
IC1 (7805).
Once the organiser identi es the con-
testant who pressed the switch rst, he
disables the audio alarm and at the same
time forces the digital display to ‘0’ by
pressing reset pushbutton S5.
With a slight modification, this
circuit can accommodate more than four
contestants.

Readers’ com-
ments:
 What modi-
fications are
required to
accommodate
more than four
contestants?
Suyash
Narayan
Delhi
EFY: To ac-
commodate up
to eight con-
testants, the
modified cir-
cuit is shown
in Fig. 1 below.
In this circuit,
IC8 (7475) is
added to the
previous circuit
to accommo-
date switches
S5 through S8. Fig. 1: Modification of the fastest finger first circuit for eight contestants
In place of IC3
(7420) of the (74LS00) have been used to lock out the propriate latch-disable signal. The rest
previous circuit, IC9 (74LS30) and IC10 subsequent entries by producing the ap- of the circuit remains the same.

DECORATIVE SIGNBOARD
PRATAP CHANDRA SAHU

T
his eye-catching signboard can be
used for special occasions such as
birthdays and marriage ceremo-
nies. The characters in the display board
are illuminated one by one, each for one
second. After the last character is illumi-
nated, the entire board gets illuminated
for 4 to 5 seconds. The above two sequenc-
es are repeated continuously.
Timer 555 (IC1) generates 1Hz pulses,
which are applied to decade-counter
CD4017B (IC5). The output from pin
Q9 of IC5 triggers 4- to 5-second (pulse
width) monostable multivibrator IC2. The
output of IC2 is ANDed in gate A1 with
100Hz stepped down/pulsating DC sup-
ply available at the output of the bridge
recti er comprising diodes D1 through
D4. The output of AND gate A1 drives
second decade counter IC4, whose outputs
(Q1 through Q8) are ORed with the cor-
responding outputs of rst counter IC5.
(Note. Only eight of the ten outputs of
CD4017s have been used.)
Driving characters at 1 Hz ensures
that the characters are illuminated one
by one for one second each. Similarly,
100Hz signal driving IC4 ensures that
the characters are refreshed rapidly for a
continuous glow effect due to persistence
of vision. AND gate A2 is used to block
1Hz signal reaching the rst counter (IC5)
while the second counter (IC4) is active,
i.e. when the output of IC2 is high. When
IC2 output goes low after 4-5 seconds, it
enables gate A2 to pass 1Hz clock to the

180 ELECTRONICS PROJECTS Vol. 22

 rst counter (IC5) and disables the second
counter (IC4) via its reset pin 15. Transis-
tor T1 acts as an inverter.
For illuminating more than one mes-
sage, use two rows of characters wired
reverse to each other. This sequence of
characters in opposite directions gives a
CONDENSER MIC AUDIO AMPLIFIER
T
he compact, low-cost condenser
mic audio ampli er described here
provides good-quality audio of 0.5
special effect.
The characters can be made by wir-
ing LEDs/torch bulbs (6V, 200mA type)
in series/parallel combination or densely
painted glass or transparent plastic illu-
minated by torch bulbs. The bulbs should
be placed behind each painted character.
D. PRABAKARAN
watts at 4.5 volts. It can be used as part
of intercoms, walkie-talkies, low-power
transmitters, and packet radio receivers.
Each of the eight outputs of ULN2803 can
sink a maximum of 500 mA at supply volt-
age of up to 50 volts.
Note. The supply for ULN2803 can be a
separate one or the same as used for the rest
of the circuit. However, ensure the ground
reference is same in both the cases.
Transistors T1 and T2 form the mic
preampli er. Resistor R1 provides the
necessary bias for the condenser mic while
ELECTRONICS PROJECTS Vol. 22 181

preset VR1 functions as gain control for
varying its gain. In order to increase the
audio power, the low-level audio output
from the preampli er stage is coupled via
coupling capacitor C7 to the audio power
ampli er built around BEL1895 IC.
BEL1895 is a monolithic audio power
ampli er IC designed speci cally for sen-
sitive AM radio applications that delivers
1 watt into 4 ohms at 6V power supply
voltage. It exhibits low
distortion and noise and
operates over 3V-9V sup-
ply voltage, which makes
it ideal for battery opera-
tion. A turn-on pop re-
duction circuit prevents
thud when the power
supply is switched on.
Coupling capaci-
tor C7 determines low-
frequency response of
the ampli er. Capacitor
C9 acts as the ripple-
rejection lter. Capacitor
C13 couples the output
available at pin 1 to the
loudspeaker. R15-C13
combination acts as the
damping circuit for out-
put oscillations. Capaci-
tor C12 provides the boot
strapping function.
This circuit is suitable for low-power
HAM radio transmitters to supply the
necessary audio power for modulation.
With simple modi cations it can also be
used in intercom circuits.

SMOKE ALARM
PRADEEP G.

T
he smoke alarm circuit presented to interrupter module is used as the
here is based on the readily avail- smoke detector, while timer 555 is
able photon-coupled interrupter wired in astable configuration as an
module and timer IC NE555. The pho- AF oscillator for sounding alarm via a
loudspeaker.
In the ab-
sence of any
smoke, the gap
of photo inter-
rupter module
is clear and the
the timer is reset and hence the alarm
light from LED
does not sound.
falls on the pho-
However, when smoke is present in
totransistor
the gap of the photo interrupter module,
through the slot.
the light beam from LED to the pho-
As a result, the
totransistor is obstructed. As a result, the
collector of pho-
phototransistor stops conducting and pin
totransistor is
4 (reset) of IC 555 goes high to activate
pulled towards
the alarm.
ground. This
Note. The unit must be housed
causes reset pin
inside an enclosure with holes to allow
4 of IC 555 to go
entry of smoke.
low. Accordingly,

182 ELECTRONICS PROJECTS Vol. 22

 OVERLOAD PROTECTOR
WITH RESET BUT TON
VIJAY KUMAR P.

old pin that resets the ip- op output to

I
n applications like inverters and set combination R3-VR1 also increases.
UPS, the load must not exceed the (Note. The power dissipated in 1-ohm low state. The circuit can be reset after
rated output power since it can cause resistor for 500W load is just 2.1 watts, removing unwanted loads.
excess heating of output transformer which is negligible compared to the Note. Since the circuit is very sensi-
windings and active driving devices and maximum power rating of the load. To tive, uctuations in AC mains can also
thereby damage them.
The circuit presented
here can be used as over-
load protector for inverters
or as an electronic fuse
in AC mains supply. The
mains supply to the load
is routed via the the N/C
(normally closed) contacts
of relay RL1. In an in-
verter, the relay contacts
could be used as ‘inverter
oscillator’ on/off control.
Whenever overload occurs,
it inhibits inverter oscilla-
tor circuit, which, in turn,
stops generation of power.
Resistor R1 is used
as the overload sensing
element. When the load
exceeds the maximum
rated value, it draws current in excess of use this circuit for 1kW load, select R1 trigger the circuit undesirably. This effect
its rated value. This causes the potential as 0.5-ohm, 10W.) can be eliminated by using 4.7µF bypass
drop across resistor R1 to increase. An Overload limiting point can be set by capacitor C1 as shown in the gure.
optocoupler is used to sense this volt- preset VR1. When the potential at wiper of Since some equipments like TV draws
age drop. The optocoupler, in addition, preset VR1 becomes greater than VZ+VBE more current initially for few seconds,
isolates the AC mains part from the rest (where VZ is the breakdown voltage of this can cause the overload protector to
of the circuit. Zener diode ZD1 across the zener diode ZD1 and VBE the forward volt- cutoff the supply, which is undesirable.
optocoupler MCT2E, which is connected age drop at the base-emitter junction of Inserting a small time delay of around 5
in reverse prevent inbuilt LED of the transistor T1), it causes forward biasing seconds by using a capacitor C3 of 220µF
optocoupler MCT2E from negative half of transistor T1. This results in the col- can eliminate this. The time delay can
cycles across R1. lector of transistor T1 to be pulled down be increased by using higher values of
Resistor R1 is selected as 1 ohm for to ground and trigger IC555, which is C3 and can be decreased by using higher
230V, 500 watts (max.) load capacity. connected in bistable mode. values of C3.
When the load just exceeds 500 watts, The output of IC1 forward biases If you are using the circuit for loads,
the current through R1 is approximately transistor T2 to energise the relay RL1 which do not draw more current initially,
2.1 amperes, producing a potential and causes overload indicating LED1 to the delay feature may be useless and even
difference of 2.1 volts across R1. The glow. Once the output of bistable IC1 goes be harmful. Therefore disable the feature
inbuilt transistor inside the optocoupler high, it continues to remain high, unless by simply disconnecting capacitor C3.
senses this voltage and its collector cur- reset pushbutton S1, which is connected While adjusting the overload cutoff
rent increases proportionally. When the between Vcc and threshold terminal (pin point disconnect C3, which will otherwise
current reaches the required designed 6) of timer 555, is pressed. On pressing can cause confusion, and reconnect it
value, voltage drop across resistor-pre- S1, a high pulse is applied to the thresh- after nal adjustments.

ELECTRONICS PROJECTS Vol. 22 183