Alpha-II Integrated: Schematic Component Notation "NI", "DNI" Not Installed

5 4 3 2 1
Alpha-II Integrated
D D
Table of Contents Notes

Schematic component notation "NI", "DNI" = Not Installed
01) Cover Sheet 34) Discharge Switches
02) Block Diagram 35) CPLD, Watchdog
03) Legacy ETXe-PC Chipset Block Diagram 36) Legacy ETXe-PC Hierarchy Connections 1
04) Legacy ETXe-PC Power Distribution Overview 37) Legacy ETXe-PC Hierarchy Connections 2
05) Legacy ETXe-PC Power On Timing Diagram 38) PCI Express Hierarchy
06) Legacy ETXe-PC Thermal Diagram 39) PCI Express Graphics Slot
07) Legacy ETXe-PC Clock Distribution Diagram 40) PCI Express x1 Slot
08) CPU (Penryn) 41) PCI Express Gigabit Ethernet 2
09) CPU Power 1 42) Front Panel I/O Hierarchy
C
10) CPU Power 2 43) Front Panel USB & Ethernet C
11) GMCH (Cantiga) Host & Memory 44) Front Panel Audio, Serial, Misc. SMBus address part name
12) GMCH Graphics & Misc. 45) Front Panel Analog Video A0h DDR3 channel A (SO-DIMM0)
13) GMCH Power 1 46) Audio Codec A4h DDR3 channel B (SO-DIMM1)
30h Thermal sensor SO-DIMM0
14) GMCH Power 2 47) LPC_BIOS (FWH), TPM Socket 34h Thermal sensor SO-DIMM1
5Ch HW Monitor
15) GMCH Power 3 48) Backplane Connectors D2h Clock Generator
16) Clock Generator CK505 49) SATA Connectors
17) ICH9 1 50) RS-232 Serial Transceivers
I2C address part name
18) ICH9 2 51) Jurisdiction EEPROM, Board Rev. ID
A0h-A3h JIDA EEPROM
19) ICH9 Power 52) Battery, NVRAM B2h Watchdog
20) DDR3 SO-DIMM A 53) ATX Power Connector, Crowbar
21) DDR3 SO-DIMM B 54) Game Doors, Test Switch, Card Detect
B
22) Gigabit Ethernet 1, SPI BIOS, JIDA EEPROM 55) I/O Buffer Hierarchy B
23) Fan Controller 56) Misc. Communications Buffers

24) SATA-PATA Bridge A 57) Input Buffers
25) SATA-PATA Bridge B 58) Output Buffers
26) CompactFlash Connectors 59) Actel FPGA
27) LVDS/Analog Video Bridge 60) PCI UART Hierarchy
28) Regulators V3.3_S5, V1.2_PATA_S0, V1.5_S0 61) Exar Octal UART
29) Regulators V1.05_S0, V1.05_M, V1.8_S3 62) Exar Quad UART
30) Regulator V1.5_SYS_MEM (DDR3)
31) Regulator VCCGFXCORE
32) Regulator VCORE
33) V3.3_RTC, V_IN_12_PWRGD, V_IN_DUAL_Switches
A ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE A

PERTAINING TO THE ARTICLE SHOWN ON THIS
SHEET IS THE EXCLUSIVE PROPERTY OF BALLY
D. LEBLANC 4/14/2011 Bally
TECHNOLOGIES
BALLY TECHNOLOGIES, INC
6601 SOUTH BERMUDA ROAD
LAS VEGAS, NEVADA 89119
TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
SAME IS PROECTEDTO THE EXTENT PERMITTED TITLE
UNDER THE LAWS OF THE UNITED STATES AND ENGR.
NEVADA. THIS INFORMATION IS DISCLOSED IN ALPHA 2 iMPU, MARVELL
ENG. APP.
CONFIDENCE AND IS NOT TO BE COPIED,
REPRODUCED, REVEALED TO OR APPROPRIATED COVER PAGE
PROD. APP.
BY OTHERS, IN PART OR IN WHOLE, WITHOUT
THE EXPRESS CONSENT OF BALLY. THIS PRINT MATL. APP.
IS LOANED ONLY AND RECIPIENT COVENANTS DWG. SIZE DWG. NO. REV.
IT WILL NOT BE USED IN ANY MANNER Q.A. APP.
DETRIMENTAL TO THE INTEREST OF BALLY, AND C PCA212268-2-1 A
MUST BE RETURNEDTO BALLY ON DEMAND. ORCAD FILE DWG. SCALE PLOT SCALE SHEET OF
PCA212268-2-1 1/1 1/1 1 62
5 4 3 2 1
5 4 3 2 1
VCC3.3SBY VCC3.3 LPC BIOS - TPM

ETXexpress Compact Flash/SATA
LPC_AD[0..3] SATA_ACT# VCC5 VCC3.3
LPC_AD[0..3] LPC_FRAME# LPC_AD[0..3] SATA_ACT# SATA0_TX+ SATA_ACT#
LPC_FRAME# LPC_CLK LPC_FRAME# SATA0_TX+ SATA0_TX- SATA0_TX+
VCC3.3 LPC_CLK CB_RESET# LPC_CLK SATA0_TX- SATA0_RX+ SATA0_TX-
LPC BIOS CB_RESET#
BIOS_DISABLE#
BIOS_DISABLE#
LPC_SERIRQ
CB_RESET#
BIOS_DISABLE#
SATA0_RX+
SATA0_RX-
SATA0_RX-
SATA1_TX+
SATA0_RX+
SATA0_RX-
VCC3.3SBY LPC_SERIRQ LPC_SERIRQ SATA1_TX+ SATA1_TX+ VCC5
TPM BUF_PCI_RESET#
SUS_STAT#
BUF_PCI_RESET#
SUS_STAT#
IDE_RESET# SUS_STAT#
SATA1_TX-
SATA1_RX+
SATA1_TX-
SATA1_RX+
SATA1_RX-
SATA1_TX-
SATA1_RX+
DGND IDE_RESET# PCI_CLKRUN# SATA1_RX- SATA1_RX-
PCI_CLKRUN# PCI_CLKRUN# ACTIVITY_LED_CATHODE#
ACTIVITY_LED_CATHODE#
IDE_RESET# VCC3.3
PS_ON# IDE_RESET#
VCC12
Audio Codec
47 LPC BIOS - TPM
IDE_A_A[0..2]
IDE_A_A[0..2] Compact Flash + SATA
VCC5 IDE_A_IOWG#
SOFT_PWR_OFF IDE_A_IOWG# IDE_A_IOW#
VCC3.3 AC_BITCLK IDE_A_IOW#
AC_BITCLK AC_SDOUT AC_BITCLK IDE_B_IOWG#
D AC_SDOUT AC_SDOUT IDE_B_IOWG# D
AC_SDIN0 IDE_B_IOW#
VCC12 AC_SDIN0 AC_SYNC AC_SDIN0 IDE_B_IOW#
VCC5 Audio Codec AC_SYNC

AC_RESET#
AC_RESET#
PC_SPEAKER
AC_SYNC
AC_RESET# IDE_B_A[0..2]
IDE_B_A[0..2]
PC_SPEAKER PC_SPEAKER CD_DET2#
VCC3.3
S/PDIF_OUT
S/PDIF_OUT CPU, GMCH, ICH CD_DET2#
CD_DET1#
CD_DET1# DGND
LINE_OUT_R
LINE_OUT_L
AGND1
LINE_IN_R
RAM, GbE, Power Regulators
LINE_IN_L
MIC_IN_R
MIC_IN_L
VGA2_RED
DGND VGA2_GRN SPI_BIOS_WP#
VGA2_BLU
VGA2_HSYNC PCIE_TX-[0..1] 49 SATA Connectors
VGA2_VSYNC PCIE_TX-[0..1] PCIE_TX+[0..1]
VGA2_I2C_CLK PCIE_TX+[0..1] PCIE_RX-[0..1]
46 Audio Codec VGA2_I2C_DAT PCIE_RX-[0..1] PCIE_RX+[0..1]
AGND1 VGA2_RED PCIE_RX+[0..1]
VGA2_GRN PCIe Video
VGA2_BLU VGA_RED
VGA2_HSYNC VGA_GRN CLK_PCIE+[0..2] VCC12 VCC3.3 VCC3.3SBY
VGA2_VSYNC VGA_BLU CLK_PCIE+[0..2] CLK_PCIE-[0..2] CLK_PCIE+[0..2]
PCIE_RX+[0..1]
PCIE_RX-[0..1]
PCIE_TX+[0..1]
PCIE_TX-[0..1]
VGA2_I2C_CLK VGA_HSYNC CLK_PCIE-[0..2] CLK_PCIE-[0..2]
VGA2_I2C_DAT VGA_VSYNC PRSNT#_SLOT0 VCC12
VGA_I2C_CLK PEG_+TX[0..15] PRSNT#_SLOT0
VGA_RED VGA_I2C_DAT PEG_+TX[0..15] PEG_-TX[0..15] PEG_+TX[0..15]
VGA_GRN PEG_-TX[0..15] PEG_+RX[0..15] PEG_-TX[0..15] VCC3.3
VGA_BLU GBE0_MDI+0 PEG_+RX[0..15] PEG_-RX[0..15] PEG_+RX[0..15]
VGA_HSYNC GBE0_MDI-0 PEG_-RX[0..15] SMB_DAT PEG_-RX[0..15]
VGA_VSYNC
VGA_I2C_CLK
GBE0_MDI+1
GBE0_MDI-1
SMB_DAT
SMB_CK
SMB_CK
WAKE0#
SMB_DAT
SMB_CK PCIe Cards + GbE VCC3.3SBY
VGA_I2C_DAT GBE0_MDI+2 WAKE0# WAKE1# WAKE0#

LINE_OUT_R
LINE_OUT_L
GBE1_LINK1000#
EXT_SYS_RESET#
GBE0_MDI-2 WAKE1# WAKE1#
GBE1_LINK100#
BUF_PCI_RESET#
PEG_ENABLE#
LINE_IN_R
LINE_IN_L
MIC_IN_R
MIC_IN_L
GBE0_MDI+3 PEG_ENABLE# PCIE_RESET# PEG_ENABLE#
GBE1_MDI+0
GBE1_MDI+1
GBE1_MDI+2
GBE1_MDI+3
GBE1_MDI-0
GBE1_MDI-1
GBE1_MDI-2
GBE1_MDI-3
GBE1_ACT#
USB_0_1_OC#
USB_2_3_OC#
USB_4_5_OC#
USB_6_7_OC#
PCI_DEVSEL#
GBE0_MDI-3 PCIE_RESET# PCIE_RESET#
PCI_AD[0..31]
PCI_FRAME#
SDVO_DATA
USB_D+[0..3]
USB_D-[0..3]
Front Panel I/O
VCC12_AUX
THRMTRIP#
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
PCI_IDSEL0
PCI_IDSEL1
PCI_IDSEL2
GBE0_CTREF SDVO_DATA SDVO_DATA DGND
PCI_SERR#
PCI_PERR#
PCI_TRDY#
PCI_STOP#
PCI_IRQC#
PCI_IRQA#
PCI_IRQB#
PCI_IRDY#
SDVO_CLK
VCC5SBY
USB_D+4
USB_D+5
SDVO_CLK SDVO_CLK
SUS_S3#
PWR_OK
PCI_PAR
USB_D-4
USB_D-5
PCI_CLK
OTEMP#
GBE0_MDI+0
VCC3.3
GBE0_MDI+0 GBE0_LINK100#
VBATT
GBE0_MDI-0
DGND
VGA2_RED
VGA2_GRN
VGA2_BLU
VGA2_HSYNC
VGA2_VSYNC
VGA_RED
VGA_GRN
VGA_BLU
VGA_HSYNC
VGA_VSYNC
VGA2_I2C_CLK
VGA_I2C_CLK
VGA2_I2C_DAT
VGA_I2C_DAT
GBE0_MDI-0 GBE0_MDI+1 GBE0_LINK1000#

GBE0_MDI+1 GBE0_MDI-1 GBE0_ACT# PWRBTN#
LINE_IN_L GBE0_MDI-1 GBE0_MDI+2
GBE1_LINK1000#
GBE1_ACT#
LINE_IN_R GBE0_MDI+2
GBE1_LINK100#
GBE0_MDI-2 37 PCI Express
GBE1_MDI+0
GBE1_MDI+1
GBE1_MDI+2
GBE1_MDI+3
GBE1_MDI-0
GBE1_MDI-1
GBE1_MDI-2
GBE1_MDI-3
USB_0_1_OC#
USB_2_3_OC#
USB_4_5_OC#
USB_6_7_OC#
GBE0_MDI-2 GBE0_MDI+3 02 ETXexpress PC
MIC_IN_L GBE0_MDI+3 VCC12_AUX
GBE0_MDI-3 THRMTRIP# VCC5SBY
MIC_IN_R GBE0_MDI-3 GBE0_CTREF
GBE0_CTREF VBATT
BUF_PCI_RESET#
LINE_OUT_L VCC3.3
GBE0_LINK100#
PCI_DEVSEL#
LINE_OUT_R GBE0_LINK100#
PCI_AD[0..31]
GBE1_MDI-[0..3]
PCI_FRAME#
GBE0_LINK1000#
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
PCI_IDSEL0
PCI_IDSEL1
PCI_IDSEL2
PCI_SERR#
PCI_PERR#
GBE0_LINK1000#
PCI_TRDY#
PCI_STOP#
PCI_IRQC#
GBE1_MDI+[0..3]
PCI_IRQA#
PCI_IRQB#
PCI_IRDY#
GBE0_ACT#
GBE0_ACT#
PCI_PAR
LD3.3V_[0..31]
USB_D+[0..3]
USB_D+[0..3] USB_D-[0..3]
VCC3.3
VCC5 Front Panel I/O USB_D-[0..3]
RXD_232_SP10
RXD_232_SP10 TXD_232_SP10
C VCC5 TXD_232_SP10 BIOS C
RXD_232_SP11
RXD_232_SP11 TXD_232_SP11
VCC3.3 TXD_232_SP11
Actel FPGA
USB_EN#[0..3] VCC3.3
GBE1_LINK1000#
GND_EARTH USB_EN#[0..3]
GBE1_LINK100#
USB_FLAG#[0..3]
USB_FLAG#[0..3] PERIPH_RESET# LD3.3V_[0..7]
GBE1_MDI+0
GBE1_MDI+1
GBE1_MDI+2
GBE1_MDI+3
BUF_PCI_RESET#
PCI_TRDY#
PCI_SERR#
PCI_STOP#
PCI_FRAME#
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
PCI_DEVSEL#
PCI_PERR#
PCI_IDSEL0
PCI_IRDY#
PCI_IRQA#
USB_0_1_OC#
USB_2_3_OC#
USB_4_5_OC#
USB_6_7_OC#
PCI_PAR
PCI_AD[0..31]
PCI_CLK
GBE1_MDI-0
GBE1_MDI-1
GBE1_MDI-2
GBE1_MDI-3
GBE1_ACT#
DGND TEST_SWITCH# PERIPH_RESET# IDE_A_A[0..2] LD3.3V_[0..7]
AGND1
TEST_SWITCH#
PWR_OK
PWR_OK
ACTIVITY_LED_CATHODE#
IDE_A_IOW#
IDE_A_IOWG#
SPI_BIOS_WP#
SPI_BIOS_WP# BIOS
ACTIVITY_LED_CATHODE# VCC3.3
AGND1 OTEMP#
EXT_SYS_RESET#
OTEMP#
EXT_SYS_RESET#
LD3.3V_[0..31]
IDE_B_A[0..2]
IDE_B_IOW#
BOARD_REV_ID#
SLB_SCL
BOARD_REV_ID# JUR EEPROM
IDE_B_IOWG# SLB_SCL
42 Front Panel I/O LA[2..24]
LA[2..24]
SLB_SDA
SLB_SDA ID DGND
LD[0..31]
LD[0..31] SPI_BIOS_WP#
GBE1_MDI+0 NVRAM_CS0#
GBE1_MDI+1 NVRAM_CS1# NVRAM_CS0# BOARD_REV_ID#
GBE1_MDI+2 NVRAM_WE# NVRAM_CS1# FPGA_SLA_SCL 51 BIOS/EPROM/ID
NVRAM_WE# SLA_SCL
I2C - BACKPLANE
GBE1_MDI+3 NVRAM_OE# I2C - BACKPLANE FPGA_SLA_SDA EXAR PCI UARTS
GBE1_MDI-0 LBE_0# NVRAM_OE# SLA_SDA
GBE1_MDI-1 LBE_1# LBE_0# SLAD_SCL#
I2C - BACKPLANE
GBE1_MDI-2
GBE1_MDI-3
LBE_2#
LBE_3#
LBE_1#
LBE_2# Actel FPGA SLAD_SCL#
SLAD_SDA#
I2C - BACKPLANE SLAD_SDA# PCI_AD[0..31]
PCI_C/BE0# PCI_AD[0..31]
GBE1_LINK100# NVRAM_ADV# LBE_3# PCI_C/BE1# PCI_C/BE0#
GBE1_LINK1000#
GBE1_ACT#
NVRAM_WAIT#
NVRAM_CLK
NVRAM_ADV#
NVRAM_WAIT#
TXD_TTL_SP[0..4]
RXD_TTL_SP[0..4]
PCI_C/BE2#
PCI_C/BE3#
PCI_C/BE1#
PCI_C/BE2# EXAR PCI UARTS &
NVRAM_CRE# NVRAM_CLK
NVRAM_CRE#
TXD_TTL_SP[6..11]
RXD_TTL_SP[6..11]
PCI_FRAME#
PCI_CLK
PCI_C/BE3#
PCI_FRAME# PCI32/33 CLK BUFFERS TXD_TTL_EXAR_SP5
PCI_IRDY# PCI_CLK TXD_TTL_EXAR_SP5
NVRAM/BATTERY PCI_IRDY#
VCC3.3 PCI_TRDY# RXD_TTL_EXAR_SP5
RXD_TTL_EXAR_SP[6..11]
TXD_TTL_EXAR_SP[6..11]
I2C - JURISDICTION CHIP PCI_TRDY# RXD_TTL_EXAR_SP5
PCI_DEVSEL#
BUF_HOP_SENSOR_SPARE
PWR_OK SLB_SCL I2C - JURISDICTION CHIP BUF_PCI_RESET# PCI_DEVSEL# RTS_TTL_EXAR_SP5#
ACFAIL# SLB_SDA BUF_PCI_RESET# RTS_TTL_EXAR_SP5#
PLAYERSW/DOORS_OE#
VCC3.3SBY PCI_STOP#
LA[2..24] PCI_STOP#
BUF_FPGA_SPARE_IN
USB_FLAG#[4..7]
BUF_SPI_MISO_P[0..3]
PCI_SERR#
BUF_HOP_COIN_OUT
BUF_HANDLE_OPTIC
VCC3.3 LD[0..31] USB_FLAG#[0..3] USB_FLAG#[4..7] PCI_SERR#
BUF_COIN_CREDIT0
BUF_COIN_CREDIT1
BUF_COIN_CHUTE0
BUF_COIN_CHUTE1
PCI_PAR
BUF_RXD_TTL_SP5
FPGA_SPARE_OUT
BUF_COIN_SENSE
NVRAM_CS0# PCI_PAR
BUF_AC_DETECT
VCC1.8 PCI_IRQB#
0X10C_OUT_CLK
SPI_MOSI_P[0..3]
VCC3.3 VCC3.3
0X104_OUT_CLK
NVRAM_CS1# VCC3.3 PCI_IRQB# VCC3.3
BUF_HOP_FULL
SPI_SCK_P[0..3]
BUF_COIN_TILT
iBUTTON1_OUT
iBUTTON2_OUT
PCI_IRQC#
RTS_TTL_SP5#
SPI_CS_P[0..3]
iBUTTON1_OE
iBUTTON2_OE
TXD_TTL_SP5
VCC3.3SBY NVRAM_WE# PCI_IRQC#
iBUTTON1_IN
iBUTTON2_IN
VCC1.8 PCI_IDSEL1
METER[0..7]
NVRAM_OE# ID_TAG VCC1.8 PCI_IDSEL1
0X100_OE#
0X110_OE#
PCI_IDSEL2
VBATT LBE_0# PCI_CLK0 PCI_IDSEL2 DGND
VCC1.8
NVRAM LBE_1#
LBE_2#
SOFT_PWR_OFF VCC1.5 VCC1.5
PCI_PERR# PCI_CLK0
PCI_PERR#
LBE_3# DGND
Doors
Game Doors + Misc Inputs
VBATT NVRAM_ADV# 60_PCI UART Hierarchy
VCC3.3
NVRAM_WAIT#
BUF_FPGA_SPARE_IN
BUF_AC_DETECT
RTS_TTL_SP5#
RTS_TTL_EXAR_SP5#
BUF_RXD_TTL_SP5
FPGA_SPARE_OUT
BUF_HOP_COIN_OUT
BUF_HANDLE_OPTIC
0X104_OUT_CLK
RXD_TTL_EXAR_SP5
BUF_COIN_SENSE
TXD_TTL_SP5
TXD_TTL_EXAR_SP5
NVRAM_CLK
BUF_HOP_FULL
BUF_COIN_CREDIT0
BUF_COIN_CREDIT1
PLAYERSW/DOORS_OE#
0X100_OE#
iBUTTON1_OUT
iBUTTON2_OUT
BUF_COIN_CHUTE0
BUF_COIN_CHUTE1
59 Actel FPGA
iBUTTON1_OE
iBUTTON2_OE
DGND NVRAM_CRE
BUF_COIN_TILT
iBUTTON1_IN
iBUTTON2_IN
BATT_LOW0#
0X10C_OUT_CLK
BATT_LOW0# VCC3.3
0X110_OE#
BATT_LOW1#
SPI_MOSI_P[0..3]
SPI_CS_P[0..3]
METER[0..7]
BATT_LOW1#
SPI_SCK_P[0..3]
LD3.3V_[16..31]
PWR_OK LD3.3V_[16..31]
LOGIC_DOOR_SW0
PLAYERSW/DOORS_OE#
DOOR_SW[0..11]
B 52 NVRAM/Battery PRSNT#_SLOT0 B
PRSNT#_SLOT0 Serial Transceivers
PEG_ENABLE#
PEG_ENABLE#
TEST_SWITCH#
VCC12_AUX VCC3.3SBY I/O Buffers
Power and Control
VCC5SBY VCC3.3 VCC1.5
DGND
BUF_HOP_FULL
BUF_COIN_CREDIT0
BUF_COIN_CREDIT1
BUF_COIN_CHUTE0
BUF_COIN_CHUTE1
0X100_OE#
TXD_TTL_SP5
BUF_RXD_TTL_SP5
RTS_TTL_SP5#
TXD_TTL_EXAR_SP5
RXD_TTL_EXAR_SP5
RTS_TTL_EXAR_SP5#
PLAYERSW/DOORS_OE#
0X110_OE#
FPGA_SPARE_IN
BUF_FPGA_SPARE_IN
iBUTTON1_IN
iBUTTON2_IN
BUF_HANDLE_OPTIC
iBUTTON1_OE
iBUTTON2_OE
BUF_COIN_SENSE
0X104_OUT_CLK
0X10C_OUT_CLK
SPI_MOSI_P[0..3]
SPI_SCK_P[0..3]
SPI_CS_P[0..3]
METER[0..7]
BUF_AC_DETECT
BUF_FPGA_SPARE_OUT
FPGA_SPARE_OUT
iBUTTON1_OUT
iBUTTON2_OUT
BUF_HOP_COIN_OUT
BUF_COIN_TILT
VCC12 VCC5 VCC1.8 SUS_S3# BATT_LOW0# TXD_TTL_SP[0..4]
VCC1.5 SUS_S3# BATT_LOW1# TXD_TTL_SP[0..4]
LD3.3V_[0..23] 54 Game Doors RXD_TTL_SP[0..4]
VCC1.8 LD3.3V_[28..31] LD3.3V_[0..23] RXD_TTL_SP[0..4]
PWR_OK ACFAIL# LD3.3V_[28..31] SLAD_SDA# TXD_TTL_SP[6..11]
VCC3.3 ACFAIL# SLAD_SCL# TXD_TTL_SP[6..11]
PWR_OK BUF_SLA_SDA RXD_TTL_SP[6..11]
VCC3.3SBY OTEMP# OTEMP# BUF_SLA_SCL RXD_TTL_SP[6..11]
SLA_SDA
VCC5 PS_ON# SLA_SCL
PS_ON# RXD_232_SP0
VCC5SBY
Power and Control ID_TAG USB_EN#[0..3] I/O Buffers CD_DET1#
CD_DET2#
RXD_232_SP1
RXD_232_SP2
VCC12 ID_TAG RXD_232_SP3 VCC12 VEE12
VCC12_AUX BUF_PERIPHERAL_RESET#
BUF_DOOR_MODE
BUF_PCI_RESET#
RXD_232_SP4
RXD_232_SP6 Serial
HOP_SENSOR_SPARE
BUF_SPI_MOSI_P[0..3]
BUF_PLYRLAMP[0..15]
BUF_SPI_SCK_P[0..3]
AC_FAIL# RXD_232_SP7
BUF_TWRLAMP[0..3]
Transceivers
BUF_COIN_DIV_DIR
BUF_SPI_CS_P[0..3]
VCC5
BUF_TXD_TTL_SP5
BUF_RTS_TTL_SP5
BUF_COIN_DIV_EN
BUF_HOP_ENABLE
BUF_COIN_INHIBIT
BUF_HANDLE_SOL
VEE12
BUF_BVAL_MRST#
VEE12 PERIPH_RESET# RXD_232_SP8

BUF_HOP_BRAKE
BUF_HOP_PHASE
BUF_PRN_MRST#
USB_EN#[4..7]
BUF_BVAL_LAMP
PLAYERSW[0..15]
BUF_METER[0..7]
BUF_HOP_MODE
SPI_MISO_P[0..3]
BUF_PRN_LAMP
COIN_DIV_FLAG
HOP_COIN_OUT
USB_EN#[4..7] RXD_232_SP9
HANDLE_OPTIC
METER_SENSE
COIN_CREDIT0
COIN_CREDIT1
COIN_DIV_LED
PWRBTN#
COIN_CHUTE0
COIN_CHUTE1
RXD_TTL_SP5
THRMTRIP# BUF_ACFAIL# RXD_232_SP10
COIN_SENSE
KEY_SW[0..3]
ASPARE[0..2]
DGND AC_DETECT VCC5 VCC5 RXD_232_SP11 VCC12

HOP_FULL
COIN_TILT
SOFT_PWR_OFF BUF_iBUTTON1
GND_EARTH SOFT_PWR_OFF BUF_iBUTTON2 VCC3.3 VCC3.3
TXD_232_SP0 VCC5
BUF_PERIPHERAL_RESET#
DOOR_BAT_LOW# DGND TXD_232_SP1

53 Power and Control TXD_232_SP2
BUF_FPGA_SPARE_OUT
TXD_232_SP3 VEE12
HOP_SENSOR_SPARE
TXD_232_SP4
BUF_TWRLAMP[0..3]
BUF_PLYRLAMP[0..15]
BUF_COIN_DIV_DIR
55 I/O Buffer Hierarchy
BUF_TXD_TTL_SP5
BUF_RTS_TTL_SP5
LOGIC_DOOR_SW0
BUF_SPI_SCK_P[0..3]
BUF_COIN_DIV_EN
BUF_HOP_ENABLE
BUF_HANDLE_SOL
BUF_BVAL_MRST#
TXD_232_SP6
DOOR_BAT_LOW#
BUF_HOP_BRAKE
BUF_HOP_PHASE
BUF_PRN_MRST#
BUF_SPI_CS_P[0..3]
PLAYERSW[0..15]
BUF_METER[0..7]
BUF_BVAL_LAMP
BUF_HOP_MODE
SPI_MISO_P[0..3]
FPGA_SPARE_IN
DOOR_SW[0..11]
BUF_PRN_LAMP
COIN_DIV_FLAG
HOP_COIN_OUT
RXD_232_SP0
RXD_232_SP1
RXD_232_SP2
RXD_232_SP3
RXD_232_SP4
RXD_232_SP6
RXD_232_SP7
RXD_232_SP8
RXD_232_SP9
TXD_232_SP7 DGND
TXD_232_SP0
TXD_232_SP1
TXD_232_SP2
TXD_232_SP3
TXD_232_SP4
TXD_232_SP6
TXD_232_SP7
TXD_232_SP8
TXD_232_SP9
HANDLE_OPTIC
BUF_iBUTTON1
BUF_iBUTTON2
METER_SENSE
COIN_CREDIT0
COIN_CREDIT1
COIN_DIV_LED
COIN_CHUTE0
COIN_CHUTE1
RXD_TTL_SP5
TXD_232_SP8
COIN_INHIBIT
BUF_ACFAIL#
DOOR_MODE
KEY_SW[0..3]
COIN_SENSE
ASPARE[0..2]
BP_SLA_SDA
USB_FLAG#4
USB_FLAG#5
BP_SLA_SCL
AC_DETECT
TXD_232_SP9
HOP_FULL
COIN_TILT
USB_EN#5
USB_EN#4
PWRBTN#
USB_D+4
USB_D+5
TXD_232_SP10
USB_D-4
USB_D-5
TXD_232_SP11
VCC3.3 VCC5
VCC5SBY VCC12 Backplane Connectors 50 Serial Tranceivers

BUF_PERIPHERAL_RESET#
BUF_ACFAIL#
BUF_iBUTTON1
BUF_iBUTTON2
DOOR_BAT_LOW#
HOP_FULL
BUF_PRN_MRST#
BUF_BVAL_MRST#
BUF_HANDLE_SOL
COIN_CREDIT0
COIN_CREDIT1
COIN_CHUTE0
COIN_CHUTE1
BUF_TXD_TTL_SP5
RXD_TTL_SP5
BUF_RTS_TTL_SP5
LOGIC_DOOR_SW0
PWRBTN#
SLA_SCL
USB_D+4
USB_D-4
USB_D+5
USB_D-5
USB_FLAG#4
USB_FLAG#5
USB_EN#5
USB_EN#4
RXD_232_SP0
RXD_232_SP1
RXD_232_SP2
RXD_232_SP3
RXD_232_SP4
RXD_232_SP6
RXD_232_SP7
RXD_232_SP8
RXD_232_SP9
TXD_232_SP0
TXD_232_SP1
TXD_232_SP2
TXD_232_SP3
TXD_232_SP4
TXD_232_SP6
TXD_232_SP7
TXD_232_SP8
TXD_232_SP9
COIN_DIV_FLAG
FPGA_SPARE_IN
HANDLE_OPTIC
BUF_COIN_DIV_EN
BUF_COIN_DIV_DIR
COIN_DIV_LED
ASPARE[0..2]
BUF_HOP_MODE
BUF_HOP_BRAKE
BUF_HOP_PHASE
BUF_HOP_ENABLE
HOP_SENSOR_SPARE
PLAYERSW[0..15]
BUF_PLYRLAMP[0..15]
BUF_PRN_LAMP
KEY_SW[0..3]
BUF_TWRLAMP[0..3]
BUF_BVAL_LAMP
BUF_METER[0..7]
METER_SENSE
COIN_SENSE
SPI_MISO_P[0..3]
BUF_SPI_SCK_P[0..3]
BUF_SPI_CS_P[0..3]
DOOR_MODE
DOOR_SW[0..11]
SLA_SDA
BUF_FPGA_SPARE_OUT
S/PDIF_OUT
AC_DETECT
HOP_COIN_OUT
COIN_INHIBIT
COIN_TILT
VCC12
VCC5
VCC5SBY
VCC3.3
A A
VEE12 VEE12
DGND
Backplane Connectors
48 Backplane Connectors
Title
Alpha 2 iMPU, Marvell Block Diagram
Size Document Number Rev

PCA212268-2-1 A
Date: Thursday, April 14, 2011 Sheet 2 of 62

5 4 3 2 1
SMBus
Channel A Channel B HW-Monitor

DDR3 SO-DIMM DDR3 SO-DIMM ADT7475
Clock Gen
XDP CK505
debug port
DDR3
iTPM SPI SPI Flash

Intel Intel GS45 x4 DMI @2GB/s
Intel ICH9M
CANTIGA SMBus
PENRYN FSB 667/800/1060
(Southbridge)
processor (Northbridge) ControllerLink 0
Ethernet
I2C_INT
MAC LPC Bus (33MHz)
1x USB
PCIe x16 / SDVOx2 / HDMI / DP
1x PCIexpress x1
JIDA
optional instead of GbEthernet

IMVP-VI+ EEPROM
Analog VGA / CRT
1x PCIexpress x1
LVDS 2ch x 24-bit
Core supply JM20335
5x PCIexpress x1
PCI Bus
82567
(GbE PHY) Watchdog
GPIO / Misc
8x USB 2.0
HD-Audio
4x SATA
IDE
TV out
PATA
Flash
10/100/1000 Mbit/s
optional as
Slave
COM express connector

I2C_EXT
LPC Bus (33MHz)

CPLD Microcontroller LPC Bus (33MHz)
(optional)
I2C_INT
SMBus
Power Management Chipset control & SYS Mgmt signals
ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

TECHNOLOGIES
NEVADA. THIS INFORMATION IS DISCLOSED IN ALPHA 2 iMPU, MARVELL
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED ETXe-PC Chipset Block Diagram
PROD. APP.
PCA212268-2-1 1/1 1/1 3 62
supply rail naming conventions:
VCORE_S0....variable CPU Core voltage, active in S0-S2
Vxxx_S0.....voltage is xxx and is active in the states S0-S2
Vxxx_S3.....voltage is xxx and is active in the states S0-S2 and S3
Vxxx_S5.....voltage is xxx and is active in the states S0-S2, S3, S4 and S5
Vxxx_S6.....voltage is xxx and is active in the states S0-S2, S3, S4, S5 and S6
TECHNOLOGIES
Vxxx_G3.....voltage is xxx and is active in all states SAME IS PROECTEDTO THE EXTENT PERMITTED TITLE
Vxxx_M......voltage is xxx and is active in the M states if AMT is enabled UNDER THE LAWS OF THE UNITED STATES AND ENGR.
V_IN_xxx....voltage is xxx and is sourced from the input connector NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED ETXe-PC Power Distribution
PROD. APP.
THE EXPRESS CONSENT OF BALLY. THIS PRINT
Overview
MATL. APP.
PCA212268-2-1 1/1 1/1 4 62
TECHNOLOGIES
NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED ETXe-PC Power On
PROD. APP.
Timing Diagram
MATL. APP.
PCA212268-2-1 1/1 1/1 5 62
DDR3 Channel A SMBus
Temp-diode
DDR3 Channel A
Temp-diode
HW-Monitor PM_THRM#
ADT7475 OD I/O
+internal Temp-diode
PM_THERMD_GMCH
PM_THERMD_CPU
0R resistor
Temp-diode (Q52)
TMMBT3904
Intel Penryn Intel GS45 Intel ICH9M

CPU CANTIGA (Southbridge)
OD I/O OD Output OD Output OD Output Input Input
PM_THRM#
0R resistor Output
(=PROCHOT in S0, else high-Z)
PM_THRMTRIP# EXT_THRMTRIP#
levelshifter Input
0R resistor Input
CPLD
H_PROCHOT# levelshifter CPLD_PROCHOT#
Input
MCH_TSATN#
0R resistor TSATN#
levelshifter
(optional)
IMVP-VI+ VRHOT#
Core supply OD Output

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Thermal Diagram
PROD. APP.
PCA212268-2-1 1/1 1/1 6 62
CLK_XDP (166/200/266 MHz)
XDP
CLK_CPU_BCLK (166/200/266 MHz)

CPU
Penryn
CLK_MEM_DDRA0
CLK_MCH_BCLK (166/200/266 MHz) (sel frequency differential)
CLK_MEM_DDRA1 DDR3
CLK_DPLL_REF_SS (100 MHz) (sel frequency differential) SODIMM A
CLK_DPLL_REF (96 MHz)
GMCH
Cantiga CLK_MEM_DDRB0
CLK_PCIE_PEG (100 MHz) GS45 (sel frequency differential)
CLK_MEM_DDRB1
DDR3
(sel frequency differential) SODIMM B
CLK_PCIE_ICH (100 MHz)

CLK_GBE_ICH9
CLK_PCIE_SATA (100 MHz)
Crystal CK505 GbE
14.318 MHz Crystal Boazman
Clock Gen CLK_USB_48M (48 MHz)
25.0 MHz
CLK_ICH_14M318 (14.318 MHz)

ICH9M
Crystal USB2PATA
12.0 MHz
Bridge
CLK_SUS_32K (32 kHz)

Crystal RTC
32.768 kHz
OpAmp
ca. 120Hz CPLD
CLK_PCI_CPLD_33M (33 MHz)
CLK_PCIE_CON (100 MHz)
CLK_PCI_33M_EXT (33 MHz) COMexpress

Connector
CLK_LPC_33M_EXT (33 MHz)

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED ETXe-PC Clock Distribution
PROD. APP.
PCA212268-2-1 1/1 1/1 7 62
8,11 H_A#[35..3] 8,11 H_D#[63..0]
U32A U32B H_D#[63..0] 8,11
H_A#3 P2 M4 H_D#0 F40 AP44 H_D#32
V4 A[3]# ADS# J5 H_ADS# 11 G43 D[0]# D[32]# AR43
H_A#4 H_D#1 H_D#33
W1 A[4]# BNR# L5 H_BNR# 11 E43 D[1]# D[33]# AH40
H_A#5 H_BPRI# 11 H_D#2 H_D#34
H_A#6 T4 A[5]# BPRI# H_D#3 J43 D[2]# D[34]# AF40 H_D#35
A[6]# V1.05_S0 D[3]# D[35]#
ADDR GROUP 0
H_A#7 AA1 N5 H_DEFER# 11 H_D#4 H40 AJ43 H_D#36
H_A#8 AB4 A[7]# DEFER# F38 H_D#5 H44 D[4]# D[36]# AG41 H_D#37
CONTROL
A[8]# DRDY# H_DRDY# 11 D[5]# D[37]#
DATA GROUP 0
H_A#9 T2 J1 H_D#6 G39 AF44 H_D#38
A[9]# DBSY# H_DBSY# 11 D[6]# D[38]#
DATA GROUP 2
H_A#10 AC5 H_D#7 E41 AH44 H_D#39
A[10]# R644 D[7]# D[39]#
H_A#11 AD2 M2 H_D#8 L41 AM44 H_D#40
A[11]# BR0# H_BREQ# 11 R1%56R2S02 D[8]# D[40]#
H_A#12 AD4 H_D#9 K44 AN43 H_D#41
H_A#13 AA5 A[12]# B40 H_IERR# TP21 H_D#10 N41 D[9]# D[41]# AM40 H_D#42
H_A#14 AE5 A[13]# IERR# D8 rnd_1mm ! LAYOUTNOTE2 H_D#11 T40 D[10]# D[42]# AK40 H_D#43
A[14]# INIT# H_INIT# 17 D[11]# D[43]#
H_A#15 AB2 TP22 TP with GND 0,1" away H_D#12 M40 AG43 H_D#44
H_A#16 AC1 A[15]# N1 rnd_1mm H_D#13 G41 D[12]# D[44]# AP40 H_D#45
A[16]# LOCK# H_LOCK# 11 D[13]# D[45]#
11 H_ADSTB#0 Y4 H_RS#[2..0] 11 H_D#14 M44 AN41 H_D#46
ADSTB[0]# G5 GND H_D#15 L43 D[14]# D[46]# AL41 H_D#47
11 H_REQ#[4..0] RESET# H_CPURST# 11 D[15]# D[47]#
H_REQ#0 R1 K2 H_RS#0 11 H_DSTB#0_N K40 AK44 H_DSTB#2_N 11
H_REQ#1 R5 REQ[0]# RS[0]# H4 H_RS#1 J41 DSTBN[0]# DSTBN[2]# AL43
REQ[1]# RS[1]# 11 H_DSTB#0_P DSTBP[0]# DSTBP[2]# H_DSTB#2_P 11
H_REQ#2 U1 K4 H_RS#2 11 H_DINV#0 P40 AJ41 H_DINV#2 11
H_REQ#3 P4 REQ[2]# RS[2]# L1 DINV[0]# DINV[2]#
REQ[3]# TRDY# H_TRDY# 11
H_REQ#4 W5 8,11 H_D#[63..0] H_D#[63..0] 8,11
REQ[4]# H2 H_D#16 P44 AV38 H_D#48
8,11 H_A#[35..3] HIT# H_HIT# 11 V1.05_S0 D[16]# D[48]#
H_A#17 AN1 F2 H_D#17 V40 AT44 H_D#49
AK4 A[17]# HITM# H_HITM# 11 V44 D[17]# D[49]# AV40
H_A#18 H_D#18 H_D#50
H_A#19 AG1 A[18]# AY8 XDP_BPM#0 H_D#19 AB44 D[18]# D[50]# AU41 H_D#51
A[19]# BPM[0]# D[19]# D[51]#
ADDR GROUP 1
H_A#20 AT4 BA7 XDP_BPM#1 H_D#20 R41 AW41 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
DATA GROUP 1
H_A#21 AK2 BA5 XDP_BPM#2 R348 H_D#21 W41 AR41 H_D#53
A[21]# BPM[2]# D[21]# D[53]#
XDP/ITP SIGNALS
DATA GROUP 3
H_A#22 AT2 AY2 XDP_BPM#3 R1%51R1S02 H_D#22 N43 BA37 H_D#54
H_A#23 AH2 A[22]# BPM[3]# AV10 XDP_PRDY# H_D#23 U41 D[22]# D[54]# BB38 H_D#55
H_A#24 AF4 A[23]# PRDY# AV2 XDP_PREQ# H_D#24 AA41 D[23]# D[55]# AY36 H_D#56
H_A#25 AJ5 A[24]# PREQ# AV4 XDP_TCK H_D#25 AB40 D[24]# D[56]# AT40 H_D#57
H_A#26 AH4 A[25]# TCK AW7 XDP_TDI H_D#26 AD40 D[25]# D[57]# BC35 H_D#58
H_A#27 AM4 A[26]# TDI AU1 XDP_TDO ! LAYOUTNOTE3 ! LAYOUTNOTE4 H_D#27 AC41 D[26]# D[58]# BC39 H_D#59
H_A#28 AP4 A[27]# TDO AW5 XDP_TMS place close to CPU H_GTLREF: Zo=55 Ohm, H_D#28 AA43 D[27]# D[59]# BA41 H_D#60
H_A#29 AR5 A[28]# TMS AV8 XDP_TRST# H_D#29 Y40 D[28]# D[60]# BB40 H_D#61
with stup length <200mils max length 0.5"
H_A#30 AJ1 A[29]# TRST# J7 XDP_DBR# H_D#30 Y44 D[29]# D[61]# BA35 H_D#62
H_A#31 AL1 A[30]# DBR# V1.05_S0 H_D#31 T44 D[30]# D[62]# AU43 H_D#63 ! LAYOUTNOTE5
H_A#32 AM2 A[31]# U43 D[31]# D[63]# AY40 COMP0 and COMP2: Zo=27.4 Ohm
A[32]# R262 11 H_DSTB#1_N DSTBN[1]# DSTBN[3]# H_DSTB#3_N 11
H_A#33 AU5 THERMAL V1.05_S0 11 H_DSTB#1_P W43 AY38 H_DSTB#3_P 11 COMP1 and COMP3: Zo=55 Ohm
H_A#34 AP2 A[33]# R676 R43 DSTBP[1]# DSTBP[3]# BC37
A[34]# R1%68R1S02 11 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 11 at each trace length shorter than 0.5"
H_A#35 AR1 D38 H_PROCHOT# 32 R1%1K0S02
AN5 A[35]# PROCHOT# BB34 PM_THERMDA_CPU_R R359 R1%0R0S02 H_GTLREF AW43 AE43 H_COMP0 R667 R1%27R4S02
11 H_ADSTB#1 ADSTB[1]# THERMDA PM_THERMDA_CPU 23 GTLREF COMP[0]
BD34 PM_THERMDC_CPU_R R358 R1%0R0S02 PM_THERMDC_CPU 23 R261 E37 AD44 H_COMP1 R662 R1%54R9S02
C7 THERMDC R675 R263
DNI
D40 TEST1 COMP[1] AE1 H_COMP2 R664 R1%27R4S02
17 H_A20M# A20M# DNI
TEST2 COMP[2]
17 H_FERR#
D4 B10 PM_THRMTRIP# 12,17 R1%2K00S02 R264 C43 MISC AF2 H_COMP3 R671 R1%54R9S02
F10 FERR# THERMTRIP# DNI
H_TEST4 AE41 TEST3 COMP[3]
17 H_IGNNE# IGNNE# ! TEST4 ! LAYOUTNOTE7
LAYOUTNOTE6 R690 AY10 G7 H_DPRSTP# 12,17,32 TP10
F8 PM_THRMTRIP# should connect GND C717
DNI
AC43 TEST5 DPRSTP# B8 place TP3 w/o stub rnd_1mm GND
17 H_STPCLK# STPCLK# DNI R1%1K0S02 TEST6 DPSLP# H_DPSLP# 17
17 H_INTR
C9 H CLK to ICH9 and GMCH without stub C100N02V16 C41 H_DPWR# 11
LINT0 GND DPWR#
ICH
17 H_NMI
C5 A35 CLK_CPU_BCLK_P 16
A37 E7 H_PWRGD 17
LINT1 BCLK[0] ! 16 CPU_BSEL0 BSEL[0] PWRGOOD
17 H_SMI# E5 C35 CLK_CPU_BCLK_N 16 LAYOUTNOTE8 C37 D10 H_CPUSLP# 11
SMI# BCLK[1] place C603 close to pin AE41 GND 16 CPU_BSEL1 B38 BSEL[1] small SLP# BD10 R645
16 CPU_BSEL2 BSEL[2] form factor PSI# PSI# 32
V2 MH1 max length 0.5" R1%1K0S02
RSVD01 MH1
RESERVED
Y2 UPENRYN_SFF_ES H_PWRGD_XDP
AG5 RSVD02 MH2
AL5 RSVD03
SKT
MH2 !LAYOUTNOTE9
J9 RSVD04 MH3 place R740 w/o stub
F4 RSVD05 MTG MH3
H8 RSVD06 HOLES MH4
max length 0.5"
RSVD07 MH4
small form factor
UPENRYN_SFF_ES
GND
V1.05_S0
XDP
J16
14 8 XDP_BPM#0
PROC_VTT BPM0# 7 XDP_BPM#1 ! LAYOUTNOTE10
C787 BPM1# 5 XDP_BPM#2 place near CPU
C100N02V16 BPM2# 4 XDP_BPM#3 and connector(con.)
H_PWRGD_XDP 10 BPM3# V1.05_S0
PWRGOOD 24 XDP_TCK R357 CPU R1%51R1S02
GND TCK0 20 XDP_TDI R355 CPU R1%51R1S02
11 TDI 18 XDP_TDO R353con. R1%51R1S02
22 NC1 TDO 21 XDP_TMS R356 CPU R1%51R1S02
NC2 TMS 19 XDP_TRST# R354 CPU R1%51R1S02
TRST# R18 was changed in demoboard FernHill to 51.1R
25 12 CLK_XDP_P 16
all other PU/PDs at XDP are 54.9R
26 SHLD1 BCLK0 13
SHLD2 BCLK1 CLK_XDP_N 16 GND
1 XDP_PREQ#
3 PREQ# 2 XDP_PRDY#
6 GND0 PRDY# R352 R1%1K0S02
GND1 DNI V3.3_S0
9 16 XDP_DBR# R351 R1%0R0S02
GND2 DBR# SYS_RESET# 18,35
17
23 GND3 15 XDP_RESET# R350 H_CPURST#
GND4 RESET#
R1%121RS02
XXDPSFF24
GND R349
V1.05_S0 DNI
R1%51R1S02

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED CPU (Penryn)
PROD. APP.
PCA212268-2-1 1/1 1/1 8 62
VCORE VCORE
VCORE V1.05_S0
CPU Decoupling ! LAYOUTNOTE11
U32C Place two rows of 8x 22uF INSIDE socket cavity (north-south)
F32 AH26 Place two rows of 8x 22uF OUTSIDE socket cavity (north-south)
G33 VCC[001] VCC[079] AK30 U32D
H32 VCC[002] VCC[080] AK28 D20 U37 VCORE
J33 VCC[003] VCC[081] AM30 F20 VCC_157 VCCP_010 V38
K32 VCC[004] VCC[082] AM28 H20 VCC_158 VCCP_011 W37
L33 VCC[005] VCC[083] AP30 K18 VCC_159 VCCP_012 AA37
M32 VCC[006] VCC[084] AP28 K16 VCC_160 VCCP_013 AB38 C771 C774 C760 C784 C781 C782 C783 C775 C724 C770 C767 C773
N33 VCC[007] VCC[085] AK26 M18 VCC_161 VCCP_014 AC37 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
P32 VCC[008] VCC[086] AM26 M16 VCC_162 VCCP_015 AE37 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
R33 VCC[009] VCC[087] AP26 K20 VCC_163 VCCP_016 AF38 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
T32 VCC[010] VCC[088] AT30 M20 VCC_164 VCCP_017 AG37
U33 VCC[011] VCC[089] AT28 P18 VCC_165 VCCP_018 AJ37
V32 VCC[012] VCC[090] AV30 P16 VCC_166 VCCP_019 AK38 VCORE GND
W33 VCC[013] VCC[091] AV28 T18 VCC_167 VCCP_020 AL37
Y32 VCC[014] VCC[092] AY30 T16 VCC_168 VCCP_021 AN37
AA33 VCC[015] VCC[093] AY28 V18 VCC_169 VCCP_022 AP38
AB32 VCC[016] VCC[094] AT26 V16 VCC_170 VCCP_023 B32 C750 C733 C772 C764 C756 C747 C738 C740 C758 C765 C757 C766
AC33 VCC[017] VCC[095] AV26 P20 VCC_171 VCCP_024 C33 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
AD32 VCC[018] VCC[096] AY26 T20 VCC_172 VCCP_025 D32 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
AE33 VCC[019] VCC[097] BB30 V20 VCC_173 VCCP_026 E35 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
AF32 VCC[020] VCC[098] BB28 Y18 VCC_174 VCCP_027 E33
AG33 VCC[021] VCC[099] BD30 Y16 VCC_175 VCCP_028 F34
AH32 VCC[022] VCC[100] BD28 AB18 VCC_176 VCCP_029 G35 VCORE GND
AJ33 VCC[023] VCC_101 BB26 AB16 VCC_177 VCCP_030 F36
AK32 VCC[024] VCC_102 BD26 AD18 VCC_178 VCCP_031 H36
AL33 VCC[025] VCC_103 B22 AD16 VCC_179 VCCP_032 J35
AM32 VCC[026] VCC_104 B24 Y20 VCC_180 VCCP_033 L35 C686 C698 C697 C705 C712 C720 C722 C728 C684 C687 C702 C703
AN33 VCC[027] VCC_105 D22 AB20 VCC_181 VCCP_034 N35 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
AP32 VCC[028] VCC_106 D24 AD20 VCC_182 VCCP_035 K36 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
AR33 VCC[029] VCC_107 F24 AF18 VCC_183 VCCP_036 R35 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
POWER
AT34 VCC[030] VCC_108 F22 AF16 VCC_184 VCCP_037 U35
AT32 VCC[031] VCC_109 H24 AH18 VCC_185 VCCP_038 P36
AU33 VCC[032] VCC_110 H22 AH16 VCC_186 VCCP_039 V36 VCORE GND
AV32 VCC[033] VCC_111 K24 AF20 VCC_187 VCCP_040 W35
AY32 VCC[034] VCC_112 K22 AH20 VCC_188 VCCP_041 AA35
BB32 VCC[035] VCC_113 M24 AK18 VCC_189 VCCP_042 AC35
BD32 VCC[036] VCC_114 M22 AK16 VCC_190 VCCP_043 AB36 C710 C713 C727 C726 C685 C695 C696 C704 C711 C719 C721 C729
B28 VCC[037] VCC_115 P24 AM18 VCC_191 VCCP_044 AE35 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
B30 VCC[038] VCC_116 P22 AM16 VCC_192 VCCP_045 AG35 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
B26 VCC[039] VCC_117 T24 AP18 VCC_193 VCCP_046 AJ35 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
D28 VCC[040] VCC_118 T22 AP16 VCC_194 VCCP_047 AF36
D30 VCC[041] VCC_119 V24 AK20 VCC_195 VCCP_048 AL35
F30 VCC[042] VCC_120 V22 AM20 VCC_196 VCCP_049 AN35 VCORE GND
POWER
F28 VCC[043] VCC_121 Y24 AP20 VCC_197 VCCP_050 AK36

H30 VCC[044] VCC_122 Y22 AT18 VCC_198 VCCP_051 AP36
H28 VCC[045] VCC_123 AB24 AT16 VCC_199 VCCP_052 B12
D26 VCC[046] VCC_124 AB22 AV18 VCC_200 VCCP_053 B14 + C779 + C778 + C780
F26 VCC[047] VCC_125 AD24 AV16 VCC_201 VCCP_054 C13 220uF 220uF 220uF
H26 VCC[048] VCC_126 AD22 AY18 VCC_202 VCCP_055 D12 2V 2V 2V
K30 VCC[049] VCC_127 AF24 AY16 VCC_203 VCCP_056 D14
K28 VCC[050] VCC_128 AF22 AT20 VCC_204 VCCP_057 E13
M30 VCC[051] VCC_129 AH24 AV20 VCC_205 VCCP_058 F14
M28 VCC[052] VCC_130 AH22 AY20 VCC_206 VCCP_059 F12 GND
K26 VCC[053] VCC_131 AK24 BB18 VCC_207 VCCP_060 G13
M26 VCC[054] VCC_132 AK22 BB16 VCC_208 VCCP_061 H14
P30 VCC[055] VCC_133 AM24 BD18 VCC_209 VCCP_062 H12
P28 VCC[056] VCC_134 AM22 BD16 VCC_210 VCCP_063 J13
T30 VCC[057] VCC_135 AP24 BB20 VCC_211 VCCP_064 K14
T28 VCC[058] VCC_136 AP22 BD20 VCC_212 VCCP_065 K12
V30 VCC[059] VCC_137 AT24 AM14 VCC_213 VCCP_066 L13 V1.05_S0
V28 VCC[060] VCC_138 AT22 AP14 VCC_214 VCCP_067 L11
P26 VCC[061] VCC_139 AV24 AT14 VCC_215 VCCP_068 M14
T26 VCC[062] VCC_140 AV22 AV14 VCC_216 VCCP_069 N13
V26 VCC[063] VCC_141 AY24 AY14 VCC_217 VCCP_070 N11 C701 C709 C718 C730 C725 C714 C688 C699 C706 C723 C683 C694
Y30 VCC[064] VCC_142 AY22 V1.05_S0 BB14 VCC_218 VCCP_071 K10 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
Y28 VCC[065] VCC_143 BB24 BD14 VCC_219 VCCP_072 P14 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
AB30 VCC[066] VCC_144 BB22 VCC_220 VCCP_073 P12 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
AB28 VCC[067] VCC_145 BD24 J11 VCCP_074 R13
AD30 VCC[068] VCC_146 BD22 E11 VCCP_001 VCCP_075 R11
small form factor
AD28 VCC[069] VCC_147 B16 G11 VCCP_002 VCCP_076 T14 ! LAYOUTNOTE12 GND
Y26 VCC[070] VCC_148 B18 J37 VCCP_003 VCCP_077 U13 V1.05_S0 Place inside CPU center
VCC[071] VCC_149 VCCP_004 VCCP_078
small form factor
AB26 B20 K38 U11 cavity in 2 rows

AD26 VCC[072] VCC_150 D16 L37 VCCP_005 VCCP_079 V14
AF30 VCC[073] VCC_151 D18 N37 VCCP_006 VCCP_080 V12
AF28 VCC[074] VCC_152 F18 P38 VCCP_007 VCCP_081 W13 C737+
AH30 VCC[075] VCC_153 F16 R37 VCCP_008 VCCP_082 W11 C330U2V5POS
AH28 VCC[076] VCC_154 H18 VCCP_009 VCCP_083
AF26 VCC[077] VCC_155 H16 UPENRYN_SFF_ES
VCC[078] VCC_156
UPENRYN_SFF_ES GND

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED CPU Power 1
PROD. APP.
PCA212268-2-1 1/1 1/1 9 62
V1.05_S0 U32F U32G
AM34 C23 W17 M6
U32E AP34 VSS[080] VSS[159] C25 AA19 VSS_238 VSS_317 P8
P10 B42 AM36 VSS[081] VSS[160] E25 AA17 VSS_239 VSS_318 P6
V10 VCCP_084 VSS[001] F44 AR35 VSS[082] VSS[161] E23 AC19 VSS_240 VSS_319 T8
Y14 VCCP_085 VSS[002] D44 AU35 VSS[083] VSS[162] E21 AC17 VSS_241 VSS_320 T6
AA13 VCCP_086 VSS[003] D42 AV34 VSS[084] VSS[163] G25 AE19 VSS_242 VSS_321 V8
AA11 VCCP_087 VSS[004] F42 AW35 VSS[085] VSS_164 G23 AE17 VSS_243 VSS_322 V6
AB14 VCCP_088 VSS[005] H42 AW33 VSS[086] VSS_165 G21 AG19 VSS_244 VSS_323 U5
AB12 VCCP_089 VSS[006] K42 AY34 VSS[087] VSS_166 J25 AG17 VSS_245 VSS_324 Y8
AC13 VCCP_090 VSS[007] M42 AT36 VSS[088] VSS_167 J23 AJ19 VSS_246 VSS_325 Y6
AC11 VCCP_091 VSS[008] P42 AV36 VSS[089] VSS_168 J21 AJ17 VSS_247 VSS_326 AB8
AD14 VCCP_092 VSS[009] T42 BA33 VSS[090] VSS_169 L25 AL19 VSS_248 VSS_327 AB6
AB10 VCCP_093 VSS[010] V42 BC33 VSS[091] VSS_170 L23 AL17 VSS_249 VSS_328 AD8
HS3 AE13 VCCP_094 VSS[011] Y42 BB36 VSS[092] VSS_171 L21 AN19 VSS_250 VSS_329 AD6
PENRYN_CPU_HEATSINK AE11 VCCP_095 VSS[012] AB42 BD36 VSS[093] VSS_172 N25 AN17 VSS_251 VSS_330 AF8
451-042 AF14 VCCP_096 VSS[013] AD42 C27 VSS[094] VSS_173 N23 AR19 VSS_252 VSS_331 AF6
AF12 VCCP_097 VSS[014] AF42 C29 VSS[095] VSS_174 N21 AR17 VSS_253 VSS_332 AH8
AG13 VCCP_098 VSS[015] AH42 C31 VSS[096] VSS_175 R25 AU19 VSS_254 VSS_333 AH6
AG11 VCCP_099 VSS[016] AK42 E29 VSS[097] VSS_176 R23 AU17 VSS_255 VSS_334 AK8
AH14 VCCP_100 VSS[017] AM42 E27 VSS[098] VSS_177 R21 AW19 VSS_256 VSS_335 AK6
AJ13 VCCP_101 VSS[018] AP42 G29 VSS[099] VSS_178 U25 AW17 VSS_257 VSS_336 AM8
AJ11 VCCP_102 VSS[019] AY44 G27 VSS[100] VSS_179 U23 BA19 VSS_258 VSS_337 AM6
AF10 VCCP_103 VSS[020] AV44 E31 VSS[101] VSS_180 U21 BA17 VSS_259 VSS_338 AP8
AK14 VCCP_104 VSS[021] AT42 G31 VSS[102] VSS_181 W25 BC19 VSS_260 VSS_339 AP6
AK12 VCCP_105 VSS[022] AV42 J29 VSS[103] VSS_182 W23 BC17 VSS_261 VSS_340 AT8
AL13 VCCP_106 VSS[023] AY42 J27 VSS[104] VSS_183 W21 C11 VSS_262 VSS_341 AT6
AL11 VCCP_107 VSS[024] BA43 L29 VSS[105] VSS_184 AA25 C15 VSS_263 VSS_342 AU9
AN13 VCCP_108 VSS[025] BB42 L27 VSS[106] VSS_185 AA23 E15 VSS_264 VSS_343 AV6
AN11 VCCP_109 VSS[026] C39 N29 VSS[107] VSS_186 AA21 G15 VSS_265 VSS_344 AU7
AP12 VCCP_110 VSS[027] E39 N27 VSS[108] VSS_187 AC25 H10 VSS_266 VSS_345 AW9
AR13 VCCP_111 VSS[028] G37 J31 VSS[109] VSS_188 AC23 M12 VSS_267 VSS_346 AY6
AR11 VCCP_112 VSS[029] H38 L31 VSS[110] VSS_189 AC21 J15 VSS_268 VSS_347 BA9
POWER
AK10 VCCP_113 VSS[030] J39 N31 VSS[111] VSS_190 AE25 L15 VSS_269 VSS_348 BB6
AP10 VCCP_114 VSS[031] L39 R29 VSS[112] VSS_191 AE23 N15 VSS_270 VSS_349 BC9
AU13 VCCP_115 VSS[032] M38 R27 VSS[113] VSS_192 AE21 M10 VSS_271 VSS_350 BD6
AU11 VCCP_116 VSS[033] N39 U29 VSS[114] VSS_193 AG25 T12 VSS_272 VSS_351 B4
POWER
L9 VCCP_117 VSS[034] R39 U27 VSS[115] VSS_194 AG23 R15 VSS_273 VSS_352 C3
L7 VCCP_118 VSS[035] T38 R31 VSS[116] VSS_195 AG21 U15 VSS_274 VSS_353 E3
N9 VCCP_119 VSS[036] U39 U31 VSS[117] VSS_196 AJ25 W15 VSS_275 VSS_354 G3
N7 VCCP_120 VSS[037] W39 W29 VSS[118] VSS_197 AJ23 T10 VSS_276 VSS_355 J3
R9 VCCP_121 VSS[038] Y38 W27 VSS[119] VSS_198 AJ21 Y12 VSS_277 VSS_356 L3
R7 VCCP_122 VSS[039] AA39 W31 VSS[120] VSS_199 AL25 AD12 VSS_278 VSS_357 N3
U9 VCCP_123 VSS[040] AC39 AA29 VSS[121] VSS_200 AL23 AA15 VSS_279 VSS_358 R3
U7 VCCP_124 VSS[041] AD38 AA27 VSS[122] VSS_201 AL21 AC15 VSS_280 VSS_359 U3
POWER
W9 VCCP_125 VSS[042] AE39 AC29 VSS[123] VSS_202 AN25 Y10 VSS_281 VSS_360 W3
W7 VCCP_126 VSS[043] AG39 AC27 VSS[124] VSS_203 AN23 AD10 VSS_282 VSS_361 AA3
AA9 VCCP_127 VSS[044] AH38 AA31 VSS[125] VSS_204 AN21 AH12 VSS_283 VSS_362 AC3
AA7 VCCP_128 VSS[045] AJ39 AC31 VSS[126] VSS_205 AR25 AE15 VSS_284 VSS_363 AE3
AC9 VCCP_129 VSS[046] AL39 AE29 VSS[127] VSS_206 AR23 AG15 VSS_285 VSS_364 AG3
AC7 VCCP_130 VSS[047] AM38 AE27 VSS[128] VSS_207 AR21 AJ15 VSS_286 VSS_365 AJ3
AE9 VCCP_131 VSS[048] AN39 AG29 VSS[129] VSS_208 AU25 AH10 VSS_287 VSS_366 AL3
AE7 VCCP_132 VSS[049] AR39 AG27 VSS[130] VSS_209 AU23 AM12 VSS_288 VSS_367 AN3
AG9 VCCP_133 VSS[050] AR37 AJ29 VSS[131] VSS_210 AU21 AL15 VSS_289 VSS_368 AR3
AG7 VCCP_134 VSS[051] AT38 AJ27 VSS[132] VSS_211 AW25 AN15 VSS_290 VSS_369 AU3
AJ9 VCCP_135 VSS[052] AU39 AE31 VSS[133] VSS_212 AW23 AR15 VSS_291 VSS_370 AW3
AJ7 VCCP_136 VSS[053] AU37 AG31 VSS[134] VSS_213 AW21 AM10 VSS_292 VSS_371 BA3
V1.5_S0 AL9 VCCP_137 VSS[054] AW39 AJ31 VSS[135] VSS_214 BA25 AT12 VSS_293 VSS_372 BC3
AL7 VCCP_138 VSS[055] AW37 AL29 VSS[136] VSS_215 BA23 AV12 VSS_294 VSS_373 D2
FB56 V1.5_S0_H AN9 VCCP_139 VSS[056] BA39 AL27 VSS[137] VSS_216 BA21 AW13 VSS_295 VSS_374 E1
LCB47R03 + AN7 VCCP_140 VSS[057] BC41 AN29 VSS[138] VSS_217 BC25 AW11 VSS_296 VSS_375 G1
C672 C673 AR9 VCCP_141 VSS[058] BD40 AN27 VSS[139] VSS_218 BC23 AY12 VSS_297 VSS_376 AW1
C10U03 C10NS02 AR7 VCCP_142 VSS[059] BD38 AL31 VSS[140] VSS_219 BC21 AU15 VSS_298 VSS_377 BA1
! LAYOUTNOTE13 A33 VCCP_143 VSS[060] B36 AN31 VSS[141] VSS_220 C17 AW15 VSS_299 VSS_378 BB2
place Cs near pin B34, D34 A13 VCCP_144 VSS[061] H34 AR29 VSS[142] VSS_221 C19 AT10 VSS_300 VSS_379 A41
VCCP_145 VSS[062] D36 AR27 VSS[143] VSS_222 E19 BA13 VSS_301 VSS_380 A39
GND VSS[063] K34 AR31 VSS[144] VSS_223 E17 BA11 VSS_302 VSS_381 A29
B34 VSS[064] M34 AU29 VSS[145] VSS_224 G19 BB12 VSS_303 VSS_382 A27
D34 VCCA[01] VSS[065] M36 AU27 VSS[146] VSS_225 G17 BC11 VSS_304 VSS_383 A31
VCCA[02] VSS[066] P34 AW29 VSS[147] VSS_226 J19 BA15 VSS_305 VSS_384 A25
32 CPU_VID[6..0] VSS[067] VSS[148] VSS_227 VSS_306 VSS_385
CPU_VID0 BD8 T34 AW27 J17 BC15 A23
CPU_VID1 BC7 VID[0] VSS[068] V34 AU31 VSS[149] VSS_228 L19 B6 VSS_307 VSS_386 A21
VCORE CPU_VID2 BB10 VID[1] VSS[069] T36 AW31 VSS[150] VSS_229 L17 D6 VSS_308 VSS_387 A19
small form factor

VID[2] VSS[070] VSS[151] VSS_230 VSS_309 VSS_388
small form factor

CPU_VID3 BB8 Y34 BA29 N19 E9 A17
CPU_VID4 BC5 VID[3] VSS[071] AB34 BA27 VSS[152] VSS_231 N17 F6 VSS_310 VSS_389 A11
R689 CPU_VID5 BB4 VID[4] VSS[072] AD34 BC29 VSS[153] VSS_232 R19 G9 VSS_311 VSS_390 A15
R1%100RS02 CPU_VID6 AY4 VID[5] VSS[073] Y36 BC27 VSS[154] VSS_233 R17 H6 VSS_312 VSS_391 A7
VID[6] VSS[074] AD36 BA31 VSS[155] VSS_234 U19 K8 VSS_313 VSS_392 A5
BD12 VSS[075] AF34 BC31 VSS[156] VSS_235 U17 K6 VSS_314 VSS_393 A9
32 VCCSENSE VCCSENSE VSS[076] VSS[157] VSS_236 VSS_315 VSS_394
BC13 AH34 C21 W19 M8 BD4
32 VSSSENSE VSSSENSE VSS[077] VSS[158] VSS_237 VSS_316 VSS_395
AH36
small VSS[078] AK34 UPENRYN_SFF_ES UPENRYN_SFF_ES
! LAYOUTNOTE14 R688 form factor VSS[079]
Route VCCSENSE and VSSSENSE traces at R1%100RS02 UPENRYN_SFF_ES GND GND
GND GND
27.4 Ohms with 50 mil spacing.
Place PU and PD within 1 inch of CPU.

GND GND

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED CPU Power 2
PROD. APP.
PCA212268-2-1 1/1 1/1 10 62
8 H_D#[63..0] U26A H_A#[35..3] 8
L15 H_A#3
H_D#0 J7 H_A#_3 B14 H_A#4
H_D#1 H6 H_D#_0 H_A#_4 C15 H_A#5
H_D#2 L11 H_D#_1 H_A#_5 D12 H_A#6
H_D#3 J3 H_D#_2 H_A#_6 F14 H_A#7
H_D#4 H4 H_D#_3 H_A#_7 G17 H_A#8
H_D#5 G3 H_D#_4 H_A#_8 B12 H_A#9
H_D#6 K10 H_D#_5 H_A#_9 J15 H_A#10
H_D#7 K12 H_D#_6 H_A#_10 D16 H_A#11
H_D#8 L1 H_D#_7 H_A#_11 C17 H_A#12
H_D#9 M10 H_D#_8 H_A#_12 D14 H_A#13
H_D#10 M6 H_D#_9 H_A#_13 K16 H_A#14
H_D#11 N11 H_D#_10 H_A#_14 F16 H_A#15
H_D#12 L7 H_D#_11 H_A#_15 B16 H_A#16
H_D#_12 H_A#_16 20 M_A_DQ[63..0] 21 M_B_DQ[63..0]
H_D#13 K6 C21 H_A#17
H_D#14 M4 H_D#_13 H_A#_17 D18 H_A#18 U26D U26E
H_D#15 K4 H_D#_14 H_A#_18 J19 H_A#19 M_A_DQ0 AP46 BC21 M_B_DQ0 AP54 BJ13
P6 H_D#_15 H_A#_19 J21 AU47 SA_DQ_0 SA_BS_0 BJ21 M_A_BS0 20 AM52 SB_DQ_0 SB_BS_0 BK12 M_B_BS0 21
H_D#16 H_A#20 M_A_DQ1 M_B_DQ1
W9 H_D#_16 H_A#_20 B18 AT46 SA_DQ_1 SA_BS_1 BJ41 M_A_BS1 20 AR55 SB_DQ_1 SB_BS_1 BK38 M_B_BS1 21
H_D#_17 H_A#_21 SA_DQ_2 SA_BS_2 M_A_BS2 20 SB_DQ_2 SB_BS_2 M_B_BS2 21
H_D#18 V6 D22 H_A#22 M_A_DQ3 AU49 M_B_DQ3 AV54
H_D#19 V2 H_D#_18 H_A#_22 G19 H_A#23 M_A_DQ4 AR45 SA_DQ_3 BH22 M_B_DQ4 AM54 SB_DQ_3
P10 H_D#_19 H_A#_23 J17 AN49 SA_DQ_4 SA_RAS# BK20 M_A_RAS# 20 AN53 SB_DQ_4 BE21
H_D#_20 H_A#_24 SA_DQ_5 SA_CAS# M_A_CAS# 20 SB_DQ_5 SB_RAS# M_B_RAS# 21
H_D#21 W7 L21 H_A#25 M_A_DQ6 AV50 BL15 M_B_DQ6 AT52 BH14
H_D#_21 H_A#_25 SA_DQ_6 SA_WE# M_A_WE# 20 SB_DQ_6 SB_CAS# M_B_CAS# 21
H_D#22 N9 L19 H_A#26 M_A_DQ7 AP50 M_B_DQ7 AU53 BK14
H_D#_22 H_A#_26 SA_DQ_7 SB_DQ_7 SB_WE# M_B_WE# 21
H_D#23 P4 G21 H_A#27 M_A_DQ8 AW47 M_B_DQ8 AW53
H_D#_23 H_A#_27 SA_DQ_8 M_A_DM[7..0] 20 SB_DQ_8
H_D#24 U9 D20 H_A#28 M_A_DQ9 BD50 M_B_DQ9 AY52
V4 H_D#_24 H_A#_28 K22 AW49 SA_DQ_9 BB52 SB_DQ_9 M_B_DM[7..0] 21
H_D#25 H_A#29 M_A_DQ10 M_B_DQ10
H_D#26 U1 H_D#_25 H_A#_29 F18 H_A#30 M_A_DQ11 BA49 SA_DQ_10 AT50 M_A_DM0 M_B_DQ11 BC53 SB_DQ_10
H_D#27 W3 H_D#_26 H_A#_30 K20 H_A#31 M_A_DQ12 BC49 SA_DQ_11 SA_DM_0 BB50 M_A_DM1 M_B_DQ12 AV52 SB_DQ_11 AP52 M_B_DM0
H_D#28 V10 H_D#_27 H_A#_31 F20 H_A#32 M_A_DQ13 AV46 SA_DQ_12 SA_DM_1 BB46 M_A_DM2 M_B_DQ13 AW55 SB_DQ_12 SB_DM_0 AY54 M_B_DM1
H_D#29 U7 H_D#_28 H_A#_32 F22 H_A#33 M_A_DQ14 BA47 SA_DQ_13 SA_DM_2 BE39 M_A_DM3 M_B_DQ14 BD52 SB_DQ_13 SB_DM_1 BJ49 M_B_DM2
H_D#30 W11 H_D#_29 H_A#_33 B20 H_A#34 M_A_DQ15 AY50 SA_DQ_14 SA_DM_3 BB12 M_A_DM4 M_B_DQ15 BC55 SB_DQ_14 SB_DM_2 BJ43 M_B_DM3
H_D#31 U11 H_D#_30 H_A#_34 A19 H_A#35 M_A_DQ16 BF46 SA_DQ_15 SA_DM_4 BE7 M_A_DM5 M_B_DQ16 BF54 SB_DQ_15 SB_DM_3 BH12 M_B_DM4
H_D#_31 H_A#_35 SA_DQ_16 SA_DM_5 SB_DQ_16 SB_DM_4
A
H_D#32 AC11 M_A_DQ17 BC47 AV10 M_A_DM6 M_B_DQ17 BE51 BD2 M_B_DM5
H_D#33 AC9 H_D#_32 F10 M_A_DQ18 BF50 SA_DQ_17 SA_DM_6 AR9 M_A_DM7 M_B_DQ18 BH48 SB_DQ_17 SB_DM_5 AY2 M_B_DM6
H_D#_33 H_ADS# H_ADS# 8 SA_DQ_18 SA_DM_7 SB_DQ_18 SB_DM_6
H_D#34 Y4 A15 M_A_DQ19 BF48 M_B_DQ19 BK48 AJ3 M_B_DM7
B
H_D#_34 H_ADSTB#_0 H_ADSTB#0 8 SA_DQ_19 SB_DQ_19 SB_DM_7
H_D#35 Y10 C19 M_A_DQ20 BC43 AR47 M_B_DQ20 BE53
HOST
H_D#_35 H_ADSTB#_1 H_ADSTB#1 8 SA_DQ_20 SA_DQS_0 M_A_DQS0_P 20 SB_DQ_20

H_D#36 AB6 C9 M_A_DQ21 BE49 BA45 M_B_DQ21 BH52 AR53
MEMORY
AA9 H_D#_36 H_BNR# B8 H_BNR# 8 BA43 SA_DQ_21 SA_DQS_1 BE45 M_A_DQS1_P 20 BK46 SB_DQ_21 SB_DQS_0 BA53 M_B_DQS0_P 21
H_D#37 M_A_DQ22 M_B_DQ22
H_D#_37 H_BPRI# H_BPRI# 8 SA_DQ_22 SA_DQS_2 M_A_DQS2_P 20 SB_DQ_22 SB_DQS_1 M_B_DQS1_P 21
H_D#38 AB10 C11 M_A_DQ23 BE47 BC41 M_B_DQ23 BJ47 BH50
H_D#_38 H_BREQ# H_BREQ# 8 SA_DQ_23 SA_DQS_3 M_A_DQS3_P 20 SB_DQ_23 SB_DQS_2 M_B_DQS2_P 21
MEMORY
H_D#39 AA1 E5 M_A_DQ24 BF42 BC13 M_B_DQ24 BL45 BK42
AC3 H_D#_39 H_DEFER# D6 H_DEFER# 8 BC39 SA_DQ_24 SA_DQS_4 BB10 M_A_DQS4_P 20 BJ45 SB_DQ_24 SB_DQS_3 BH8 M_B_DQS3_P 21
AC7 H_D#_40 H_DBSY# AH10 H_DBSY# 8 BF44 SA_DQ_25 SA_DQS_5 BA7 M_A_DQS5_P 20 BL41 SB_DQ_25 SB_DQS_4 BB2 M_B_DQS4_P 21
AD12 H_D#_41 HPLL_CLK AJ11 CLK_MCH_BCLK_P 16 BF40 SA_DQ_26 SA_DQS_6 AN7 M_A_DQS6_P 20 BH44 SB_DQ_26 SB_DQS_5 AV2 M_B_DQS5_P 21
H_D#_42 HPLL_CLK# CLK_MCH_BCLK_N 16 SA_DQ_27 SA_DQS_7 M_A_DQS7_P 20 SB_DQ_27 SB_DQS_6 M_B_DQS6_P 21
H_D#43 AB4 G11 M_A_DQ28 BB40 AR49 M_B_DQ28 BH46 AM2
Y6 H_D#_43 H_DPWR# H2 H_DPWR# 8 BE43 SA_DQ_28 SA_DQS#_0 AW45 M_A_DQS0_N 20 BK44 SB_DQ_28 SB_DQS_7 AT54 M_B_DQS7_P 21
H_D#_44 H_DRDY# H_DRDY# 8 SA_DQ_29 SA_DQS#_1 M_A_DQS1_N 20 SB_DQ_29 SB_DQS#_0 M_B_DQS0_N 21
H_D#45 AD10 C7 M_A_DQ30 BF38 BC45 M_B_DQ30 BK40 BB54
H_D#_45 H_HIT# H_HIT# 8 SA_DQ_30 SA_DQS#_2 M_A_DQS2_N 20 SB_DQ_30 SB_DQS#_1 M_B_DQS1_N 21
H_D#46 AA11 F8 M_A_DQ31 BE41 BA41 M_B_DQ31 BJ39 BJ51
H_D#_46 H_HITM# H_HITM# 8 SA_DQ_31 SA_DQS#_3 M_A_DQS3_N 20 SB_DQ_31 SB_DQS#_2 M_B_DQS2_N 21
H_D#47 AB2 A11 M_A_DQ32 BA15 BA13 M_B_DQ32 BK10 BH42
H_D#_47 H_LOCK# H_LOCK# 8 SA_DQ_32 SA_DQS#_4 M_A_DQS4_N 20 SB_DQ_32 SB_DQS#_3 M_B_DQS3_N 21
H_D#48 AD4 D8 M_A_DQ33 BE11 BA11 M_B_DQ33 BH10 BK8
AE7 H_D#_48 H_TRDY# H_TRDY# 8 BE15 SA_DQ_33 SA_DQS#_5 BA9 M_A_DQS5_N 20 BK6 SB_DQ_33 SB_DQS#_4 BC3 M_B_DQS4_N 21
SYSTEM
H_D#_49 SA_DQ_34 SA_DQS#_6 M_A_DQS6_N 20 SB_DQ_34 SB_DQS#_5 M_B_DQS5_N 21
H_D#50 AD2 M_A_DQ35 BF14 AN9 M_B_DQ35 BH6 AW3
AD6 H_D#_50 BB14 SA_DQ_35 SA_DQS#_7 M_A_DQS7_N 20 BJ9 SB_DQ_35 SB_DQS#_6 AN3 M_B_DQS6_N 21
H_D#_51 SA_DQ_36 SB_DQ_36 SB_DQS#_7 M_B_DQS7_N 21
SYSTEM
H_D#52 AE3 M_A_DQ37 BC15 BC23 M_A_A0 M_B_DQ37 BL11
H_D#53 AG9 H_D#_52 L9 M_A_DQ38 BE13 SA_DQ_37 SA_MA_0 BF22 M_A_A1 M_B_DQ38 BG5 SB_DQ_37 BJ15 M_B_A0
H_D#_53 H_DINV#_0 H_DINV#0 8 SA_DQ_38 SA_MA_1 SB_DQ_38 SB_MA_0
H_D#54 AG7 N7 M_A_DQ39 BF16 BE31 M_A_A2 M_B_DQ39 BJ5 BJ33 M_B_A1
H_D#55 AE11 AA7 M_A_DQ40 BF10 BC31 M_A_A3 M_B_DQ40 BG3 BH24 M_B_A2
! LAYOUTNOTE15 AK6 H_D#_55 H_DINV#_2 AG3 H_DINV#2 8 BC11 SA_DQ_40 SA_MA_3 BH26 BF4 SB_DQ_40 SB_MA_2 BA17
H_D#56 M_A_DQ41 M_A_A4 M_B_DQ41 M_B_A3
H_RCOMP trace should be H_D#57 AF6 M_A_DQ42 BF8 BJ35 M_A_A5 M_B_DQ42 BD4 BF36 M_B_A4
10mil wide with 20mil spacing H_D#58 AJ9 H_D#_57 K2 M_A_DQ43 BG7 SA_DQ_42 SA_MA_5 BB34 M_A_A6 M_B_DQ43 BA3 SB_DQ_42 SB_MA_4 BH36 M_B_A5
H_D#_58 H_DSTBN#_0 H_DSTB#0_N 8 SA_DQ_43 SA_MA_6 SB_DQ_43 SB_MA_5
H_D#59 AH6 N3 H_DSTB#1_N 8 M_A_DQ44 BC7 BH32 M_A_A7 M_B_DQ44 BE5 BF34 M_B_A6
V1.05_S0 H_D#60 AF12 H_D#_59 H_DSTBN#_1 AA3 M_A_DQ45 BC9 SA_DQ_44 SA_MA_7 BB26 M_A_A8 M_B_DQ45 BF2 SB_DQ_44 SB_MA_6 BK34 M_B_A7
H_D#_60 H_DSTBN#_2 H_DSTB#2_N 8 SA_DQ_45 SA_MA_8 SB_DQ_45 SB_MA_7
H_D#61 AH4 AF4 H_DSTB#3_N 8 M_A_DQ46 BD6 BF32 M_A_A9 M_B_DQ46 BB4 BJ37 M_B_A8
H_D#_61 H_DSTBN#_3 SA_DQ_46 SA_MA_9 SB_DQ_46 SB_MA_8
DDR
H_D#62 AJ7 M_A_DQ47 BF12 BA21 M_A_A10 M_B_DQ47 AY4 BH40 M_B_A9
R614 H_D#63 AE9 H_D#_62 L3 M_A_DQ48 AV6 SA_DQ_47 SA_MA_10 BG25 M_A_A11 M_B_DQ48 BA1 SB_DQ_47 SB_MA_9 BH16 M_B_A10
H_D#_63 H_DSTBP#_0 H_DSTB#0_P 8 SA_DQ_48 SA_MA_11 SB_DQ_48 SB_MA_10
R1%221RS02 M2 H_DSTB#1_P 8 M_A_DQ49 BB6 BH34 M_A_A12 M_B_DQ49 AP2 BK36 M_B_A11
H_DSTBP#_1 SA_DQ_49 SA_MA_12 SB_DQ_49 SB_MA_11
DDR
Y2 H_DSTB#2_P 8 M_A_DQ50 AW7 BH18 M_A_A13 M_B_DQ50 AU1 BH38 M_B_A12
H_SWING B6 H_DSTBP#_2 AF2 M_A_DQ51 AY6 SA_DQ_50 SA_MA_13 BE25 M_A_A14 M_B_DQ51 AT2 SB_DQ_50 SB_MA_12 BJ11 M_B_A13
H_SWING H_DSTBP#_3 H_DSTB#3_P 8 SA_DQ_51 SA_MA_14 SB_DQ_51 SB_MA_13
R615 H_RCOMP D4 M_A_DQ52 AT10 M_B_DQ52 AT4 BL37 M_B_A14
H_RCOMP H_REQ#[4..0] 8 SA_DQ_52 SB_DQ_52 SB_MA_14
C592 J13 H_REQ#0 M_A_DQ53 AW11 M_B_DQ53 AV4
R1%100RS02
R223 H_REQ#_0 L13 AU11 SA_DQ_53 AU3 SB_DQ_53

C100N02V16 H_REQ#1 M_A_DQ54 M_B_DQ54
R1%24R9S02 H_REQ#_1 SA_DQ_54 SB_DQ_54
C13 H_REQ#2 M_A_DQ55 AW9 M_B_DQ55 AR3
H_REQ#_2 G13 H_REQ#3 M_A_DQ56 AR11 SA_DQ_55 M_B_DQ56 AN1 SB_DQ_55
H_REQ#_3 SA_DQ_56 M_A_A[14..0] 20 SB_DQ_56 M_B_A[14..0] 21
J11 G15 H_REQ#4 M_A_DQ57 AT6 M_B_DQ57 AP4
8 H_CPURST# H_CPURST# H_REQ#_4 SA_DQ_57 SB_DQ_57
G9 M_A_DQ58 AP6 M_B_DQ58 AL3
GND 8 H_CPUSLP# H_CPUSLP# F4 H_RS#[2..0] 8 AL7 SA_DQ_58 AJ1 SB_DQ_58
H_RS#0 M_A_DQ59 M_B_DQ59
H_RS#_0 F2 H_RS#1 M_A_DQ60 AR7 SA_DQ_59 M_B_DQ60 AK4 SB_DQ_59
! LAYOUTNOTE16 H_RS#_1 G7 H_RS#2 M_A_DQ61 AT12 SA_DQ_60 M_B_DQ61 AM4 SB_DQ_60
place C100N close H_AVREF L17 H_RS#_2 M_A_DQ62 AM6 SA_DQ_61 M_B_DQ62 AH2 SB_DQ_61
to pin B6 of GMCH K18 H_AVREF M_A_DQ63 AU7 SA_DQ_62 M_B_DQ63 AK2 SB_DQ_62
H_DVREF small form factor SA_DQ_63 small form factor SB_DQ_63 small form factor
V1.05_S0 UGS45_CANTIGA_SFF UGS45_CANTIGA_SFF UGS45_CANTIGA_SFF
! LAYOUTNOTE17
R610 short pins L17 and K18
R1%1K0S02 below GMCH package
R608
R1%2K00S02
GND

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED GMCH (Cantiga) Host & Memory
PROD. APP.
PCA212268-2-1 1/1 1/1 11 62
V3.3_S0
V1.05_M
U26B U26C
BB32 R151 R155
J43 SA_CK_0 BA25 CLK_MEM_DDRA0_P 20
R1%2K21S02
RSVD1 SA_CK_1 CLK_MEM_DDRA1_P 20
L43 BA33 R557
RSVD2 SB_CK_0 CLK_MEM_DDRB0_P 21
J41 BA23 V3.3_S0 D38 R1%49R9S02
L41 RSVD3 SB_CK_1 CLK_MEM_DDRB1_P 21 C37 L_BKLT_CTRL U45 PEG_COMP
AN11 RSVD4 BA31 R136 LVDS_CLKCTL K38 L_BKLT_EN PEG_COMPI T44 ! LAYOUTNOTE18
RSVD5 SA_CK#_0 CLK_MEM_DDRA0_N 20 L_CTRL_CLK PEG_COMPO
AM10 BC25 R1%10K0S02 place PU within 0.5" of GMCH
DDR CLK/CONTROL/COMPENSATION
RSVD6 SA_CK#_1 CLK_MEM_DDRA1_N 20
AK10 BC33 R137 R1%10K0S02 LVDS_DATACTL L37
AL11 RSVD7 SB_CK#_0 BB24 CLK_MEM_DDRB0_N 21 J37 L_CTRL_DATA D52
F12 RSVD8 SB_CK#_1 CLK_MEM_DDRB1_N 21 27 LVDS_DDC_CLK L35 L_DDC_CLK PEG_RX#_0 G49 PEG_RX_0_N 2,38,39
RSVD9 27 LVDS_DDC_DATA L_DDC_DATA PEG_RX#_1 PEG_RX_1_N 2,38,39
RSVD
BC35 R1%100KS02 K54
SA_CKE_0 M_CKE_A0 20 R148 PEG_RX#_2 PEG_RX_2_N 2,38,39
BE33 H50
SA_CKE_1 M_CKE_A1 20 GND PEG_RX#_3 PEG_RX_3_N 2,38,39
C27 BE37 B36 M52
RSVD14 SB_CKE_0 M_CKE_B0 21 27 LVDS_VDD_EN L_VDD_EN PEG_RX#_4 PEG_RX_4_N 2,38,39
D30 BC37 R125 LVDS_IBG F50 N49
RSVD15 SB_CKE_1 M_CKE_B1 21 LVDS_IBG PEG_RX#_5 PEG_RX_5_N 2,38,39
R1%2K37S02 TP6 LVDS_VBG H46 P54
LVDS_VBG PEG_RX#_6 PEG_RX_6_N 2,38,39
V1.05_S0 J9 BK18 rnd_1mm P44 V46
RSVD17 SA_CS#_0 M_CS#_A0 20 LVDS_VREFH PEG_RX#_7 PEG_RX_7_N 2,38,39
BK16 K46 Y50
AW42 SA_CS#_1 BE23 M_CS#_A1 20 V1.5_SYS_MEM D46 LVDS_VREFL PEG_RX#_8 V52 PEG_RX_8_N 2,38,39
RSVD20 SB_CS#_0 M_CS#_B0 21 GND 27 LVDS_A_CLK_N LVDSA_CLK# PEG_RX#_9 PEG_RX_9_N 2,38,39
BC19 B46 W49
SB_CS#_1 M_CS#_B1 21 V1.5_SYS_MEM 27 LVDS_A_CLK_P LVDSA_CLK PEG_RX#_10 PEG_RX_10_N 2,38,39
LVDS
R1%1K02S02 BB20 D44 AB54
DNI
DNI
DNI 27 LVDS_B_CLK_N PEG_RX_11_N 2,38,39

BE19 RSVD22 BJ17 R1%1K0S02 B44 LVDSB_CLK# PEG_RX#_11 AD46
RSVD23 SA_ODT_0 M_ODT_A0 20 27 LVDS_B_CLK_P LVDSB_CLK PEG_RX#_12 PEG_RX_12_N 2,38,39
R104
R105
R103
BF20 BJ19 C2U2S03V6 R161 AC55

BF18 RSVD24 SA_ODT_1 BC17 M_ODT_A1 20 C10NS02 G45 PEG_RX#_13 AE49 PEG_RX_13_N 2,38,39
RSVD25 SB_ODT_0 M_ODT_B0 21 27 LVDS_A_DATA0_N LVDSA_DATA#_0 PEG_RX#_14 PEG_RX_14_N 2,38,39
BE17 F46 AF54
SB_ODT_1 M_ODT_B1 21 C121 C122 27 LVDS_A_DATA1_N LVDSA_DATA#_1 PEG_RX#_15 PEG_RX_15_N 2,38,39
ME_JTAG_TCK AN45 R207 R160 G41
GRAPHICS
TP3 AP44 ME_JTAG_TCK BL25 27 LVDS_A_DATA2_N C45 LVDSA_DATA#_2 E51
rnd_1mm ME_JTAG_TDI M_RCOMP_P R1%80R6S02 R1%3K01S02
TP4 ME_JTAG_TDI SM_RCOMP 27 LVDS_A_DATA3_N LVDSA_DATA#_3 PEG_RX_0 PEG_RX_0_P 2,38,39
rnd_1mm ME_JTAG_TDO AT44 BK26 M_RCOMP_N R188 F48
TP5 ME_JTAG_TDO SM_RCOMP# PEG_RX_1 PEG_RX_1_P 2,38,39
rnd_1mm ME_JTAG_TMS AN47 R1%80R6S02 F44 J55
TP2 ME_JTAG_TMS C128 C127 27 LVDS_A_DATA0_P LVDSA_DATA_0 PEG_RX_2 PEG_RX_2_P 2,38,39
rnd_1mm BK32 M_RCOMP_VOH G47 J49
SM_RCOMP_VOH GND 27 LVDS_A_DATA1_P LVDSA_DATA_1 PEG_RX_3 PEG_RX_3_P 2,38,39
R106 R1%2K21S02 BL31 M_RCOMP_VOL R166 F40 M54
DNI
SM_RCOMP_VOL 27 LVDS_A_DATA2_P A45 LVDSA_DATA_2 PEG_RX_4 M50 PEG_RX_4_P 2,38,39
R1%1K0S02
C2U2S03V6 C10NS02 27 LVDS_A_DATA3_P LVDSA_DATA_3 PEG_RX_5 PEG_RX_5_P 2,38,39
K26 BC51 P52
GND 16 MCH_BSEL0 CFG_0 SM_VREF R108 R1%1K0S02 GND PEG_RX_6 PEG_RX_6_P 2,38,39
G23 AY37 V1.5_SYS_MEM B40 U47
16 MCH_BSEL1 G25 CFG_1 SM_PWROK BH20 SM_PWROK 35 DNI 27 LVDS_B_DATA0_N A41 LVDSB_DATA#_0 PEG_RX_7 AA49 PEG_RX_7_P 2,38,39
M_REXT
16 MCH_BSEL2 CFG_2 SM_REXT DDR_VREF 20,21,30 27 LVDS_B_DATA1_N LVDSB_DATA#_1 PEG_RX_8 PEG_RX_8_P 2,38,39
J25 BA37 F42 V54
CFG_3 SM_DRAMRST# DDR3_DRAMRST# 20,21 27 LVDS_B_DATA2_N LVDSB_DATA#_2 PEG_RX_9 PEG_RX_9_P 2,38,39
L25 R1%1K0S02 D48 V50
DNI
CFG_4 27 LVDS_B_DATA3_N LVDSB_DATA#_3 PEG_RX_10 PEG_RX_10_P 2,38,39
MCH_CFG5 L27 B42 R107 AB52
F24 CFG_5 DPLL_REF_CLK D42 CLK_DPLL_REF_P 16 D40 PEG_RX_11 AC47 PEG_RX_11_P 2,38,39
MCH_CFG6
CFG_6 DPLL_REF_CLK# CLK_DPLL_REF_N 16 27 LVDS_B_DATA0_P LVDSB_DATA_0 PEG_RX_12 PEG_RX_12_P 2,38,39
CFG
MCH_CFG7 D24 B50 C41 AC53
CFG_7 DPLL_REF_SSCLK CLK_DPLL_REF_SS_P 16 27 LVDS_B_DATA1_P LVDSB_DATA_1 PEG_RX_13 PEG_RX_13_P 2,38,39
PCI-EXPRESS
D26 D50 G43 AD50
CFG_8 CLK DPLL_REF_SSCLK# CLK_DPLL_REF_SS_N 16 GND 27 LVDS_B_DATA2_P LVDSB_DATA_2 PEG_RX_14 PEG_RX_14_P 2,38,39
PEG_LANE_RV# J23 B48 AF52
CFG_9 27 LVDS_B_DATA3_P LVDSB_DATA_3 PEG_RX_15 PEG_RX_15_P 2,38,39
MCH_CFG10 B26 R49 R215
! LAYOUTNOTE19 A23 CFG_10 PEG_CLK P50 CLK_PCIE_PEG_P 16 L47 SDVOB_RED_N
R1%499RS02 C480
CFG_11 PEG_CLK# CLK_PCIE_PEG_N 16 PEG_TX#_0 PEG_TX_0_N 2,38,39
PM_DPRSLPVR: refer to the Montevina MCH_CFG12 C23 F52 SDVOB_GRN_N C483
CFG_12 GND PEG_TX#_1 PEG_TX_1_N 2,38,39
design guide for topology information MCH_CFG13 B24 AG55 DMI_RX3_N R598 R1%75RS02 J27 P46 SDVOB_BLUE_N C479
B22 CFG_13 DMI_RXN_0 AL49 ICH_DMI_TX3_N 18 E27 TVA_DAC PEG_TX#_2 H54 SDVOB_CLK_N PEG_TX_2_N 2,38,39
DMI_RX2_N R587 R1%75RS02 C96
K24 CFG_14 DMI_RXN_1 AH54 ICH_DMI_TX2_N 18 G27 TVB_DAC PEG_TX#_3 L55 SDVOC_RED_N PEG_TX_3_N 2,38,39
DMI_RX1_N R595 R1%75RS02 C98
C25 CFG_15 DMI_RXN_2 AL47 ICH_DMI_TX1_N 18 TVC_DAC PEG_TX#_4 T46 SDVOC_GRN_N PEG_TX_4_N 2,38,39
MCH_CFG16 DMI_RX0_N C477
CFG_16 DMI_RXN_3 ICH_DMI_TX0_N 18 PEG_TX#_5 PEG_TX_5_N 2,38,39
TV
L23 F26 R53 SDVOC_BLUE_N C99
L33 CFG_17 AG53 GND TVA_RTN PEG_TX#_6 U49 SDVOC_CLK_N PEG_TX_6_N 2,38,39
V3.3_S0 DMI_RX3_P C474
CFG_18 DMI_RXP_0 ICH_DMI_TX3_P 18 PEG_TX#_7 PEG_TX_7_N 2,38,39
MCH_CFG19 K32 AK50 DMI_RX2_P T54 PEG_TX_8_C_N C102
CFG_19 DMI_RXP_1 ICH_DMI_TX2_P 18 GND PEG_TX#_8 PEG_TX_8_N 2,38,39
MCH_CFG20 K34 AH52 DMI_RX1_P Y46 PEG_TX_9_C_N C472
CFG_20 DMI_RXP_2 ICH_DMI_TX1_P 18 PEG_TX#_9 PEG_TX_9_N 2,38,39
AL45 DMI_RX0_P R579 R1%0R0S02 B34 AB46 PEG_TX_10_C_N C470
DMI_RXP_3 ICH_DMI_TX0_P 18 TV_DCONSEL_0 PEG_TX#_10 PEG_TX_10_N 2,38,39
R128 R127 R583 R1%0R0S02 D34 W53 PEG_TX_11_C_N C104
AG49 TV_DCONSEL_1 PEG_TX#_11 Y54 PEG_TX_12_C_N PEG_TX_11_N 2,38,39
DMI_TX3_N
DMI
R1%10K0S02 R1%10K0S02 R1%0R0S02 C105

DMI_TXN_0 ICH_DMI_RX3_N 18 PEG_TX#_12 PEG_TX_12_N 2,38,39
R143 J35 AJ49 DMI_TX2_N AC49 PEG_TX_13_C_N C468
18 PM_SYNC# F6 PM_SYNC# DMI_TXN_1 AJ47 ICH_DMI_RX2_N 18 GND PEG_TX#_13 AF46 PEG_TX_14_C_N PEG_TX_13_N 2,38,39
R234 DMI_TX1_N C466
8,17,32 H_DPRSTP# PM_DPRSTP# DMI_TXN_2 ICH_DMI_RX1_N 18 PEG_TX#_14 PEG_TX_14_N 2,38,39
PM
J39 AG47 DMI_TX0_N AD54 PEG_TX_15_C_N C107

23 PM_EXT_TS0# PM_EXT_TS#_0 DMI_TXN_3 ICH_DMI_RX0_N 18 PEG_TX#_15 PEG_TX_15_N 2,38,39
L39
20,21 TS#_DIMM_AB PM_EXT_TS#_1
AY39 AF50 DMI_TX3_P J29 J47 SDVOB_RED_P C481
35 DELAY_VR_PWRGOOD PWROK DMI_TXP_0 ICH_DMI_RX3_P 18 2,42,45 CRT_BLUE CRT_BLUE PEG_TX_0 PEG_TX_0_P 2,38,39
R235 MCH_RSTIN# BB18 AH50 DMI_TX2_P R580 R1%150RS02 F54 SDVOB_GRN_P C482
17,24,25,35 ICH_PLTRST# K28 RSTIN# DMI_TXP_1 AJ45 ICH_DMI_RX2_P 18 G29 PEG_TX_1 N47 SDVOB_BLUE_P PEG_TX_1_P 2,38,39
R1%100RS02 DMI_TX1_P C478
8,17 PM_THRMTRIP# THERMTRIP# DMI_TXP_2 ICH_DMI_RX1_P 18 2,42,45 CRT_GREEN CRT_GREEN PEG_TX_2 PEG_TX_2_P 2,38,39
K36 AG45 DMI_TX0_P R584 R1%150RS02 H52 SDVOB_CLK_P C95
18 PM_DPRSLPVR DPRSLPVR DMI_TXP_3 ICH_DMI_RX0_P 18 PEG_TX_3 PEG_TX_3_P 2,38,39
R147 F30 L53 SDVOC_RED_P C97
32 PM_DPRSLPVR_MVP 2,42,45 CRT_RED CRT_RED PEG_TX_4 PEG_TX_4_P 2,38,39
VGA
R1%499RS02 G33 MCH_GFX_VID0 R585 R1%150RS02 R47 SDVOC_GRN_P C476
GFX_VID_0 PEG_TX_5 PEG_TX_5_P 2,38,39
G37 MCH_GFX_VID1 E29 R55 SDVOC_BLUE_P C100
GFX_VID_1 CRT_IRTN PEG_TX_6 PEG_TX_6_P 2,38,39
GRAPHICS
V3.3_S0 A7 F38 MCH_GFX_VID2 T50 SDVOC_CLK_P C475

NC_1 GFX_VID_2 GND PEG_TX_7 PEG_TX_7_P 2,38,39
A49 F36 MCH_GFX_VID3 CRT_DDC_CLK_3V D36 T52 PEG_TX_8_C_P C101
NC_2 GFX_VID_3 CRT_DDC_CLK PEG_TX_8 PEG_TX_8_P 2,38,39
A52 G35 MCH_GFX_VID4 CRT_DDC_DATA_3V C35 W47 PEG_TX_9_C_P C473
A54 NC_3 GFX_VID_4 J33 CRT_DDC_DATA PEG_TX_9 AA47 PEG_TX_10_C_P PEG_TX_9_P 2,38,39
SDVO_CTRLCLK R163 CRT_HSYNC_R C471
DNI R1%2K21S02 NC_4 MCH_GFX_VID[4..0] 31 CRT_HSYNC PEG_TX_10 PEG_TX_10_P 2,38,39
VID
DDPC_CTRLCLK R165 B54 G39 CRT_IREF D32 W55 PEG_TX_11_C_P C103

DNI R1%2K21S02 D55 NC_5 GFX_VR_EN MCH_GFX_VR_EN 31,35 G31 CRT_TVO_IREF PEG_TX_11 Y52 PEG_TX_12_C_P PEG_TX_11_P 2,38,39
SDVO_CTRLDATA R162 V1.05_M CRT_VSYNC_R C106
DNI R1%2K21S02 NC_6 CRT_VSYNC PEG_TX_12 PEG_TX_12_P 2,38,39
DDPC_CTRLDATA R168 G55 AK52 AB50 PEG_TX_13_C_P C469
DNI R1%2K21S02 NC_7 CL_CLK MCH_CL_CLK0 18 PEG_TX_13 PEG_TX_13_P 2,38,39
MCH_CFG20 R140 BE55 AK54 AE47 PEG_TX_14_C_P C467
DNI R1%4K02S02 NC_8 CL_DATA MCH_CL_DATA0 18 PEG_TX_14 PEG_TX_14_P 2,38,39
NC
MCH_CFG19 R145 BH55 AW40 R111 R84 R87 AD52 PEG_TX_15_C_P C108
R1%4K02S02 NC_9 CL_PWROK CL_PWROK 18,35 PEG_TX_15 PEG_TX_15_P 2,38,39
BK55 AL53 R1%1K0S02 R1%30R1S02 R1%30R1S02
ME
R185 NC_10 CL_RST# MCH_CL_RST0# 18 C100N02V16
R1%499RS02
MCH_CFG5 BK54 AL55 MCH_CLVREF R152 small form factor
DNI R1%2K21S02 NC_11 CL_VREF
BL54 V3.3_S0 R1%1K02S02 UGS45_CANTIGA_SFF
NC_12
R110
MCH_CFG6 R204 BL52 F34 DDPC_CTRLCLK C100N02V16
R1%2K21S02 BL49 NC_13 DDPC_CTRLCLK F32 DDPC_CTRLDATA C109 V3.3_S0 V5.0_S0
MCH_CFG7 R209 BL7 NC_14 DDPC_CTRLDATA B38 R156 GND
MISC
DNI R1%2K21S02 BL4 NC_15 SDVO_CTRLCLK A37 SDVO_CTRLCLK 2,38,39 3 2

R1%10K0S02 GND
R1%2K21S02 CRT_DDC_CLK_3V
R603 NC_16 SDVO_CTRLDATA SDVO_CTRLDATA 2,38,39 R1%2K21S02
PEG_LANE_RV# BL2 C31 BS138
R1%2K21S02 NC_17 CLKREQ# MCH_CLKREQ# 16 Q35
BK2 K42 R493 R499 R497 R505 V3.3_S0
DNI
NC_18 ICH_SYNC# MCH_ICH_SYNC# 18 BS138
DNI
MCH_CFG16 R205 BK1 R1%2K21S02
DNI R1%2K21S02 NC_19 ! R510
BH1 D10 MCH_TSATN# LAYOUTNOTE21 R1%2K21S02
1
BE1 NC_20 TSATN# place C72 R1%2K21S02
R186 NC_21 V1.05_S0 2,42,45 CRT_DDC_CLK
MCH_CFG10 G1 C29 close to GMCH 2,42,45 CRT_DDC_DATA
3 2 CRT_DDC_DATA_3V
DNI R1%2K21S02 NC_22 HDA_BCLK B30 R1%56R2S02 BS138
R214 HDA_RST# D28 Q37
MCH_CFG12 R597 V3.3_S0 V5.0_S0
DNI R1%2K21S02 HDA_SDI BS138
2
A27
HDA
R210 HDA_SDO CRT_VSYNC 2,42,45 R511

MCH_CFG13 small form factor B28 1 R589 R93 R92
R1%2K21S02
1
DNI
HDA_SYNC V3.3_S0
R1%2K21S02 R1%0R0S02 R1%0R0S02 CRT_HSYNC 2,42,45
DNI
Q50 V3.3_S0 R1%2K21S02
UGS45_CANTIGA_SFF
TMMBT3904
3
U16
GND R588 C92
8 1 GND
23,35 TSATN# VCCB VCCA
R1%10K0S02 C100N02V16
R88
CRT_VSYNC_R2 7 B1 A1 2 CRT_VSYNC_O
R1%30R1S02
R85
CRT_HSYNC_R2 6 B2 A2 3 CRT_HSYNC_O
R1%30R1S02
DIR 5
4
GND GND
GND U74LVC2T45VSSOP
TECHNOLOGIES
Pinname function LOW HIGH XOR/ALLZ/Clock Un-gating
MCH_CFG_5 DMI X2 Select DMIx2 DMIx4(default) MCH_CFG_13 MCH_CFG_12 function
ENG. APP.
MCH_CFG_6 iTPM Host Interface enabled(default) disabled 0 0 reserved CONFIDENCE AND IS NOT TO BE COPIED,
MCH_CFG_7 ME Crypto TLS AMT with no confid. AMT with confidentiality(default) 1 0 XOR mode enabled REPRODUCED, REVEALED TO OR APPROPRIATED GMCH Graphics & Misc.
PROD. APP.
MCH_CFG_9 PEG lane reverse normal operation (default) 0 1 All-Z mode enabled BY OTHERS, IN PART OR IN WHOLE, WITHOUT
MCH_CFG_16 FSB dynamic ODT disabled enabled (default) 1 1 normal operation(default) THE EXPRESS CONSENT OF BALLY. THIS PRINT MATL. APP.
MCH_CFG_19 DMI lane reversal normal reversed (default) IS LOANED ONLY AND RECIPIENT COVENANTS DWG. SIZE DWG. NO. REV.
MCH_CFG_20 DP concurrent PCIe DP or PCIe(default) DP (SDVO/DP/iHDMI)+PCIe via PEGport IT WILL NOT BE USED IN ANY MANNER
NOTE: Q.A. APP. C PCA212268-2-1 A
MCH_CFG_10 PCIe loopback enabled disabled (default) DETRIMENTAL TO THE INTEREST OF BALLY, AND
only one of CFG10/CFG12/CFG13 can be enabled at any time
PCA212268-2-1 1/1 1/1 12 62
V1.5_SYS_MEM V1.05_M
VCCGFXCORE
U26G U26F
T32
VCC_SM_BB36 BB36 VCC_AXG_NCTF_1 U31 AT41
VCC_SM_BE35 BE35 VCC_SM_1 VCC_AXG_NCTF_2 T31 AR41 VCC_1
AW34 VCC_SM_2 VCC_AXG_NCTF_3 R31 AN41 VCC_2
AW32 VCC_SM_3 VCC_AXG_NCTF_4 U29 AJ41 VCC_3
+ BK30 VCC_SM_4 VCC_AXG_NCTF_5 T29 AH41 VCC_4
C519 C518 C537 C526 C525 BH30 VCC_SM_5 VCC_AXG_NCTF_6 R29 AD41 VCC_5
C516
BF30 VCC_SM_6 VCC_AXG_NCTF_7 U28 AC41 VCC_6
VCC_SM_7 VCC_AXG_NCTF_8 VCC_7
C100N02V16
BD30 U27 Y41
C100N02V16
C100N02V16
C330U2V5POS
C22US05V6
C22US05V6
BB30 VCC_SM_8 VCC_AXG_NCTF_9 T27 W41 VCC_8
AW30 VCC_SM_9 VCC_AXG_NCTF_10 R27 AT40 VCC_9
GND BL29 VCC_SM_10 VCC_AXG_NCTF_11 U25 AM40 VCC_10
BJ29 VCC_SM_11 VCC_AXG_NCTF_12 T25 AL40 VCC_11
BG29 VCC_SM_12 VCC_AXG_NCTF_13 R25 VCC_12
BE29 VCC_SM_13 VCC_AXG_NCTF_14 U24 AJ40
C538 VCC_SM_BC29 BC29 VCC_SM_14 VCC_AXG_NCTF_15 U22 AH40 VCC_13
C100N02V16 BA29 VCC_SM_15 VCC_AXG_NCTF_16 T22 AG40 VCC_14
AY29 VCC_SM_16 VCC_AXG_NCTF_17 R22 AE40 VCC_15
GND BK28 VCC_SM_17 VCC_AXG_NCTF_18 U21 AD40 VCC_16
BH28 VCC_SM_18 VCC_AXG_NCTF_19 T21 AC40 VCC_17
BF28 VCC_SM_19 VCC_AXG_NCTF_20 R21 AA40 VCC_18
VCC CORE
BD28 VCC_SM_20 VCC_AXG_NCTF_21 AM19 Y40 VCC_19
BB28 VCC_SM_21 VCC_AXG_NCTF_22 AL19 AN35 VCC_20
BL27 VCC_SM_22 VCC_AXG_NCTF_23 AH19 AM35 VCC_21
BJ27 VCC_SM_23 VCC_AXG_NCTF_24 AG19 AJ35 VCC_22
BG27 VCC_SM_24 VCC_AXG_NCTF_25 AE19 AH35 VCC_23
BE27 VCC_SM_25 VCC_AXG_NCTF_26 AD19 AD35 VCC_24
VCC SM
BC27 VCC_SM_26 VCC_AXG_NCTF_27 AC19 AC35 VCC_25
VCC_SM_27 VCC_AXG_NCTF_28 VCC_26
VCC GFX NCTF

BA27 W19 W35
AY27 VCC_SM_28 VCC_AXG_NCTF_29 U19 AM34 VCC_27
AW26 VCC_SM_29 VCC_AXG_NCTF_30 AM18 AL34 VCC_28
C133 VCC_SM_BF24 BF24 VCC_SM_30 VCC_AXG_NCTF_31 AL18 AJ34 VCC_29
C135 VCC_SM_BL19 BL19 VCC_SM_31 VCC_AXG_NCTF_32 AJ18 AH34 VCC_30
C140 VCC_SM_BB16 BB16 VCC_SM_32 VCC_AXG_NCTF_33 AH18 AG34 VCC_31
VCC_SM_33 VCC_AXG_NCTF_34 AG18 ! LAYOUTNOTE22 Cavity Capacitors AE34 VCC_32
GND C100N02V16 VCC_AXG_NCTF_35 AE18 AD34 VCC_33
VCCGFXCORE place close to the GMCH
VCC_AXG_NCTF_36 AD18 VCC_34
Cavity Capacitors VCC_AXG_NCTF_37 AC18 AC34
W32 VCC_AXG_NCTF_38 AA18 + + AA34 VCC_35 V1.05_M
VCC_AXG_1 VCC_AXG_NCTF_39 C642 C490 VCC_36
AG31 Y18
VCC_AXG_2 VCC_AXG_NCTF_40 C220U4VESR C515 C510 C523 C511
AE31 W18 Y34
C605 C559 C546 C544 C532 C560 C533 VCC_AXG_3 VCC_AXG_NCTF_41 VCC_37
POWER
AD31 U18 W34 AT38
C22US05V6
C220N02V10
C220N02V10
C100N02V16
AC31 VCC_AXG_4 VCC_AXG_NCTF_42 T18 AM32 VCC_38 VCC_NCTF_1 AR38
VCC_AXG_5 VCC_AXG_NCTF_43 GND VCC_39 VCC_NCTF_2
C10US03V4
C1U02V6
C1U02V6
C22US05V6
C470N02V6
C100N02V16
C100N02V16
AA31 R18 AL32 AN38

Y31 VCC_AXG_6 VCC_AXG_NCTF_44 AJ32 VCC_40 VCC_NCTF_3 AM38
GND W31 VCC_AXG_7 AH32 VCC_41 VCC_NCTF_4 AL38
AH29 VCC_AXG_8 AE32 VCC_42 VCC_NCTF_5 AG38
AG29 VCC_AXG_9 AD32 VCC_43 VCC_NCTF_6 AE38
AE29 VCC_AXG_10 AA32 VCC_44 VCC_NCTF_7 AA38
AD29 VCC_AXG_11 AJ16 AM31 VCC_45 VCC_NCTF_8 Y38
AC29 VCC_AXG_12 VCC_AXG_62 AH16 AL31 VCC_46 VCC_NCTF_9 W38
AA29 VCC_AXG_13 VCC_AXG_63 AD16 AJ31 VCC_47 VCC_NCTF_10 U38
Y29 VCC_AXG_14 VCC_AXG_64 AC16 AH31 VCC_48 VCC_NCTF_11 T38
W29 VCC_AXG_15 VCC_AXG_65 AA16 AM29 VCC_49 VCC_NCTF_12 R38
AH28 VCC_AXG_16 VCC_AXG_66 U16 AL29 VCC_50 VCC_NCTF_13 AT37
AG28 VCC_AXG_17 VCC_AXG_67 T16 ! LAYOUTNOTE23 AM28 VCC_51 VCC_NCTF_14 AR37
AE28 VCC_AXG_18 VCC_AXG_68 R16 place close to the GMCH AL28 VCC_52 VCC_NCTF_15 AN37
VCC GFX
AA28 VCC_AXG_19 VCC_AXG_69 AM15 AJ28 VCC_53 VCC_NCTF_16 AM37
AH27 VCC_AXG_20 VCC_AXG_70 AL15 AM27 VCC_54 VCC_NCTF_17 AL37
AG27 VCC_AXG_21 VCC_AXG_71 AJ15 + C643 + C622 AL27 VCC_55 VCC_NCTF_18 AJ37
AE27 VCC_AXG_22 VCC_AXG_72 AH15 C330U2V5POS C330U2V5POS AM25 VCC_56 VCC_NCTF_19 AH37
AD27 VCC_AXG_23 VCC_AXG_73 AG15 AL25 VCC_57 VCC_NCTF_20 AG37
AC27 VCC_AXG_24 VCC_AXG_74 AE15 AJ25 VCC_58 VCC_NCTF_21 AE37
AA27 VCC_AXG_25 VCC_AXG_75 AA15 AM24 VCC_59 VCC_NCTF_22 AD37
Y27 VCC_AXG_26 VCC_AXG_76 Y15 N36 VCC_60 VCC_NCTF_23 AC37
W27 VCC_AXG_27 VCC_AXG_77 W15 GND VCC_61 VCC_NCTF_24 AA37
VCC NCTF
AH25 VCC_AXG_28 VCC_AXG_78 U15 VCC_NCTF_25 Y37
AD25 VCC_AXG_29 VCC_AXG_79 T15 VCC_NCTF_26 W37
AC25 VCC_AXG_30 VCC_AXG_80 VCC_NCTF_27 U37
W25 VCC_AXG_31 VCC_NCTF_28 T37
AJ24 VCC_AXG_32 VCC_NCTF_29 R37
AH24 VCC_AXG_33 VCC_NCTF_30 AT35
AG24 VCC_AXG_34 VCC_NCTF_31 AR35
AE24 VCC_AXG_35 VCC_NCTF_32 U35
AD24 VCC_AXG_36 VCC_NCTF_33 AT34
AC24 VCC_AXG_37 VCC_NCTF_34 AR34
AA24 VCC_AXG_38 VCC_NCTF_35 U34
Y24 VCC_AXG_39
VCC_AXG_40 POWER VCC_NCTF_36
VCC_NCTF_37
T34
3
W24 R34
Q47 1 AM22 VCC_AXG_41 VCC_NCTF_38
PM_THERMDA_GMCH 23 VCC_AXG_42
MMBT3904 AL22
TMMBT3904 VCC_AXG_43
PM_THERMDC_GMCH 23
AJ22
2
AH22 VCC_AXG_44
VCC GFX
AG22 VCC_AXG_45
! LAYOUTNOTE24 AE22 VCC_AXG_46
place Q52 on bottom layer directly under U26 AD22 VCC_AXG_47
AC22 VCC_AXG_48
AA22 VCC_AXG_49 AU45 VCCSM_LF1
AM21 VCC_AXG_50 VCC_SM_LF1 BF52 VCCSM_LF2
VCC SM LF
AL21 VCC_AXG_51 VCC_SM_LF2 BB38 VCCSM_LF3

AJ21 VCC_AXG_52 VCC_SM_LF3 BA19 VCCSM_LF4
AH21 VCC_AXG_53 VCC_SM_LF4 BE9 VCCSM_LF5
AD21 VCC_AXG_54 VCC_SM_LF5 AU9 VCCSM_LF6 small form factor
AC21 VCC_AXG_55 VCC_SM_LF6 AL9 VCCSM_LF7 UGS45_CANTIGA_SFF
AA21 VCC_AXG_56 VCC_SM_LF7
Y21 VCC_AXG_57
W21 VCC_AXG_58 C150 C151 C152 C137 C509 C484 C485
AM16 VCC_AXG_59
AL16 VCC_AXG_60
VCC_AXG_61
C100N02V16
C100N02V16
C220N02V10
C220N02V10
C470N02V6
C1U02V6
C1U02V6
AG13
31 VCC_AXG_SENSE_P VCC_AXG_SENSE GND
AE13
31 VSS_AXG_SENSE_N VSS_AXG_SENSE small form factor
! LAYOUTNOTE25 UGS45_CANTIGA_SFF
route as diff-pair

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED GMCH Power 1
PROD. APP.
PCA212268-2-1 1/1 1/1 13 62
! LAYOUTNOTE26
Caps used with V3.3_TVDAC_S0 V1.05_S0
should be within 250 mils of edge of GMCH U26H
V3.3_S0 R13
FB47 VTT_1 T12 +
VTT_2 C576 C583 C593 C596 C633
V3.3_TVDAC_S0 J31 R11
VCCA_CRT_DAC VTT_3 C470N02V6 C2U2S03V6 C4U7S03V4 C4U7S03V4 C220U4VESR
C551 C534 T10
LCB180R03 VTT_4
C100N02V16 C10NS02 R9
VTT_5 T8
GND L31 VTT_6 R7 GND
VCCA_DAC_BG VTT_7
CRT
C552 C541 C528 M33 T6
V1.05_M C100US10V6X5R C100N02V16 C10NS02 VSSA_DAC_BG VTT_8 R5
VTT_9 T4
VTT_10 R3
L13 GND VTT_11
L10UH10_450MA V1.05_M_DPLLA J45 T2
VCCA_DPLLA VTT_12 R1
L12 VTT_13
VTT
L10UH10_450MA V1.05_M_DPLLB L49
VCCA_DPLLB
FB51
PLL
LCB120R03A500 V1.05_M_AHPLL AF10
VCCA_HPLL
FB50 LCB120R03A500 V1.05_M_MPLL AE1 K30 V3.3_TVDAC_S0
VCCA_MPLL VCCA_TV_DAC
TV
C594 C540 C550
R625 R624 C100N02V16 C100N02V16 C10NS02
R1%1RS02
R1%1RS02
V1.5_S0
A PEG A LVDS
+ C493 C496 + C489 C492 C588 C569 V1.8_S3_TXLVDS U43
C627 U41 VCCA_LVDS1 A31 GND
C504 VCCA_LVDS2 VCC_HDA
HDA
C22US05V6
C1NS02
V44
VSSA_LVDS GND
C220U4VESR
C100N02V16
C220U4VESR
C100N02V16
C4U7S03V4
C100N02V16
V1.5_S0 filter placeholer
GND FB45 R577
N34 V1.5_QDAC_S0
GND GND VCCD_QDAC
D TV/CRT
AJ43 LCB180R03 R1%0R0S02
VCCA_PEG_BG C520 C513 C512
C501 C100N02V16 N32
VCCD_TVDAC C10NS02 C100N02V16 DNI C10US03V4
V1.05_M C514
C100US10V6X5R
FB44 V1.05_M_PEGPLL GND AG43
LCB220R03_2 VCCA_PEG_PLL GND GND
R563 C502 V1.5_S0 GND
R1%1RS02 C100N02V16 AW24 V1.5_LDO_QDAC_S0 FB46
AU24 VCCA_SM_1 LCB47R03
VCCA_SM_2 C527 C530
AW22
GND VCCA_SM_3 C10NS02 C100N02V16
+ C487 AU22
C10U03 AU21 VCCA_SM_4
AW20 VCCA_SM_5
GND
AU19
AW18
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
POWER GND
A SM
R613 0 V1.05_M_A_SM AU18
AW16 VCCA_SM_9 V1.05_M
C581 C563 C545 AU16 VCCA_SM_10
C557 VCCA_SM_11
C22US05V6 C22US05V6 C1U02V6 AT16
C611 C4U7S03V4 AR16 VCCA_SM_12
NI
C100US10V6X5R VCCA_SM_13 L16
AU15 V1.05_M_AXF
GND AT15 VCCA_SM_14 L100NH10
GND AR15 VCCA_SM_15
VCCA_SM_16 C568
AW14 M25 C542
VCCA_SM_17 VCC_AXF_1 N24 C10US03V4
C1U02V6
VCC_AXF_2
AXF
AT24 M23
AR24 VCCA_SM_NCTF_1 VCC_AXF_3 V1.5_SYS_MEM
AT22 VCCA_SM_NCTF_2 GND
VCCA_SM_NCTF_3 L14
AR22 V1.5_S3_SMCK
AT21 VCCA_SM_NCTF_4 L1UH05
AR21 VCCA_SM_NCTF_5 BK24 C543 R586
VCCA_SM_NCTF_6 VCC_SM_CK_1
SM CK
AT19 BL23 C100N02V16 + C549
VCCA_SM_NCTF_7 VCC_SM_CK_2 R1%1RS02
AR19 BJ23 C10U03
AT18 VCCA_SM_NCTF_8 VCC_SM_CK_3 BK22
AR18 VCCA_SM_NCTF_9 VCC_SM_CK_4 V1.8_S3
VCCA_SM_NCTF_10
GND filter placeholer
T41 V1.8_S3_TXLVDS R564 0 V1.05_S0
R604 0 V1.05_M_A_SM_CK AU27 VCC_TX_LVDS C503 NI
AU28 VCCA_SM_CK_4 C33 C1NS02 C488
C539 VCCA_SM_CK_3 VCC_HV_1
1
C558 C531 AU29 A33
C4U7S03V4 AU31 VCCA_SM_CK_2 VCC_HV_2
DNI C22US05V6 C100N02V16 V3.3_S0 D55
VCCA_SM_CK_1 GND R578
HV
AT31 3
V1.05_S0_SD DBAT54C
AR31 VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2 R1%10R0S02
A CK
AT29 AB44 C529 C100N02V16
GND AR29 VCCA_SM_CK_NCTF_3 VCC_PEG_1 Y44 V1.05_M
2
AT28 VCCA_SM_CK_NCTF_4 VCC_PEG_2 AC43 GND
VCCA_SM_CK_NCTF_5 VCC_PEG_3
PEG
AR28 AA43
AT27 VCCA_SM_CK_NCTF_6 VCC_PEG_4 C521 C491 + C486
AR27 VCCA_SM_CK_NCTF_7 C4U7S03V4 C22US05V6 C220U4VESR
VCCA_SM_CK_NCTF_8
AM44 V1.05_M
VCC_DMI_1 AN43
V1.05_M VCC_DMI_2 AL43 GND
FB52 VCC_DMI_3
DMI
V1.05_M_DHPLL AH12 C517
LCB120R03A500 VCCD_HPLL C100N02V16
C564 V1.05_M_PEGPLL AE43
C100N02V16 V1.8_S3 VCCD_PEG_PLL
C494 GND
K14 VTTLF_CAP1
GND C100N02V16 VTTLF1
LVDS
VTTLF
M46 Y12 VTTLF_CAP2
L45 VCCD_LVDS_1 VTTLF2 P2 VTTLF_CAP3
GND VCCD_LVDS_2 VTTLF3 C153 C149 C148
C495
C1U02V6 small form factor
UGS45_CANTIGA_SFF
C470N02V6
GND GND C470N02V6
C470N02V6

TECHNOLOGIES
ENG. APP.
PROD. APP.
PCA212268-2-1 1/1 1/1 14 62
U26J
U26I
AN25 AM8
BA55 C43 AG25 VSS_199 VSS_300 AK8
AU55 VSS_1 VSS_100 A43 AE25 VSS_200 VSS_301 AH8
AN55 VSS_2 VSS_101 BD42 AA25 VSS_201 VSS_302 AF8
AJ55 VSS_3 VSS_102 H42 Y25 VSS_202 VSS_303 AD8
AE55 VSS_4 VSS_103 BG41 E25 VSS_203 VSS_304 AB8
AA55 VSS_5 VSS_104 AY41 A25 VSS_204 VSS_305 Y8
U55 VSS_6 VSS_105 AU41 BD24 VSS_205 VSS_306 V8
N55 VSS_7 VSS_106 AM41 AN24 VSS_206 VSS_307 P8
BD54 VSS_8 VSS_107 AL41 AL24 VSS_207 VSS_308 M8
BG53 VSS_9 VSS_108 AG41 H24 VSS_208 VSS_309 K8
AJ53 VSS_10 VSS_109 AE41 BG23 VSS_209 VSS_310 H8
AE53 VSS_11 VSS_110 AA41 AY23 VSS_210 VSS_311 BJ7
AA53 VSS_12 VSS_111 R41 E23 VSS_211 VSS_312 E7
U53 VSS_13 VSS_112 M41 BD22 VSS_212 VSS_313 BF6
N53 VSS_14 VSS_113 E41 BB22 VSS_213 VSS_314 BC5
J53 VSS_15 VSS_114 BD40 AN22 VSS_214 VSS_315 BA5
G53 VSS_16 VSS_115 AU40 Y22 VSS_215 VSS_316 AW5
E53 VSS_17 VSS_116 AR40 W22 VSS_216 VSS_317 AU5
K52 VSS_18 VSS_117 AN40 H22 VSS_217 VSS_318 AR5
BG51 VSS_19 VSS_118 W40 BL21 VSS_218 VSS_319 AN5
BA51 VSS_20 VSS_119 U40 BG21 VSS_219 VSS_320 AL5
AW51 VSS_21 VSS_120 T40 AY21 VSS_220 VSS_321 AJ5
AU51 VSS_22 VSS_121 R40 AN21 VSS_221 VSS_322 AG5
AR51 VSS_23 VSS_122 K40 AG21 VSS_222 VSS_323 AE5 HS1
AN51 VSS_24 VSS_123 H40 AE21 VSS_223 VSS_324 AC5 GS45 HeatSink
AL51 VSS_25 VSS_124 BL39 M21 VSS_224 VSS_325 AA5 4 1
AJ51 VSS_26 VSS_125 BG39 E21 VSS_225 VSS_326 W5 P4 P1
AG51 VSS_27 VSS_126 BA39 A21 VSS_226 VSS_327 U5
AE51 VSS_28 VSS_127 E39 BD20 VSS_227 VSS_328 N5 3 2
AC51 VSS_29 VSS_128 C39 H20 VSS_228 VSS_329 L5 P3 P2
AA51
W51
VSS_30
VSS_31
VSS_32
VSS_129
VSS_130
VSS_131
A39
BD38
BG19
AY19
VSS_229
VSS_230
VSS_231
VSS VSS_330
VSS_331
VSS_332
J5
G5 GND GND
U51 AU38 M19 C5
R51
N51
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
H38
BG37
E19
BD18
VSS_232
VSS_233
VSS_234
VSS_333
VSS_334
VSS_335
BH4
BE3
L51 AU37 N18 U3 HS_CLIP1
J51 VSS_36 VSS_135 M37 H18 VSS_235 VSS_336 E3 HEATSINK_CLIP
G51 VSS_37 VSS_136 E37 BL17 VSS_236 VSS_337 BC1 451-017
C51 VSS_38 VSS_137 BD36 BG17 VSS_237 VSS_338 AW1
BK50 VSS_39 VSS_138 AW36 AY17 VSS_238 VSS_339 AR1
AM50 VSS_40 VSS_139 H36 M17 VSS_239 VSS_340 AL1 HS_CLIP2
K50 VSS_41 VSS_140 BL35 E17 VSS_240 VSS_341 AG1 HEATSINK_CLIP
BG49 VSS_42 VSS_141 BG35 A17 VSS_241 VSS_342 AC1 451-017
E49 VSS_43 VSS_142 AY35 BD16 VSS_242 VSS_343 W1
C49 VSS_44 VSS_143 AU35 AN16 VSS_243 VSS_344 N1
BD48 VSS_45 VSS_144 AL35 AG16 VSS_244 VSS_345 J1
BB48 VSS_46 VSS_145 AG35 AE16 VSS_245 VSS_346 AU43
AY48 VSS_47 VSS_146 AE35 Y16 VSS_246 VSS_347 BB42
AV48 VSS_48 VSS_147 AA35 W16 VSS_247 VSS_348 AW38
AT48 VSS_49 VSS_148 Y35 N16 VSS_248 VSS_349 BA35
AP48 VSS_50 VSS_149 M35 H16 VSS_249 VSS_350 L29
AM48 VSS_51 VSS_150 E35 BG15 VSS_250 VSS_351 N28
AK48 VSS_52 VSS_151 A35 AY15 VSS_251 VSS_352 N22
AH48 VSS_53 VSS_152 BD34 AN15 VSS_252 VSS_353 N20
AF48 VSS_54 VSS_153 AU34 AD15 VSS_253 VSS_354 N14
AD48 VSS_55 VSS_154 AN34 AC15 VSS_254 VSS_355 AL13
AB48 VSS_56 VSS_155 H34 R15 VSS_255 VSS_356 B10
Y48 VSS_57 VSS_156 BL33 M15 VSS_256 VSS_357 AN13
V48 VSS_58 VSS_157 BG33 E15 VSS_257 VSS_358
T48 VSS_59 VSS_158 AY33 BD14 VSS_258 N42
P48 VSS_60 VSS_159 E33 H14 VSS_259 VSS_359 N40
M48 VSS_61 VSS_160 BD32 BL13 VSS_260 VSS_360 N38
K48 VSS_62 VSS_161 AU32 BG13 VSS_261 VSS_361 M39
H48 VSS_63 VSS_162 AN32 AY13 VSS_262 VSS_362
BL47 VSS_64 VSS_163 AG32 AU13 VSS_263
BG47 VSS_65 VSS_164 AC32 AR13 VSS_264 AJ38
E47 VSS_66 VSS_165 Y32 AJ13 VSS_265 VSS_NCTF_1 AH38
C47 VSS_67 VSS_166 H32 AC13 VSS_266 VSS_NCTF_2 AD38
A47 VSS_68 VSS_167 B32 AA13 VSS_267 VSS_NCTF_3 AC38
BD46 VSS_69 VSS_168 BJ31 W13 VSS_268 VSS_NCTF_4 T35
AY46 VSS_70 VSS_169 BG31 U13 VSS_269 VSS_NCTF_5 R35
VSS_71 VSS_170 VSS_270 VSS_NCTF_6
VSS NCTF
AM46 AY31 M13 AT32
AK46 VSS_72 VSS_171 AN31 E13 VSS_271 VSS_NCTF_7 AR32
AH46 VSS_73 VSS_172 M31 A13 VSS_272 VSS_NCTF_8 U32
BG45 VSS_74 VSS_173 E31 BD12 VSS_273 VSS_NCTF_9 R32
AE45 VSS_75 VSS_174 N30 AV12 VSS_274 VSS_NCTF_10 T28
AC45 VSS_76 VSS_175 H30 AP12 VSS_275 VSS_NCTF_11 R28
AA45 VSS_77 VSS_176 AN29 AM12 VSS_276 VSS_NCTF_12 AT25
W45 VSS_78 VSS_177 AJ29 AK12 VSS_277 VSS_NCTF_13 AR25
R45 VSS_79 VSS_178 M29 AB12 VSS_278 VSS_NCTF_14 T24
N45 VSS_80 VSS_179 A29 V12 VSS_279 VSS_NCTF_15 R24
E45 VSS_81 VSS_180 AW28 P12 VSS_280 VSS_NCTF_16 AN19
BD44 VSS_82 VSS_181 AN28 H12 VSS_281 VSS_NCTF_17 AJ19
BB44 VSS_83 VSS_182 AD28 BG11 VSS_282 VSS_NCTF_18 AA19
AV44 VSS_84 VSS_183 AC28 AG11 VSS_283 VSS_NCTF_19 Y19
AK44 VSS_85 VSS_184 Y28 E11 VSS_284 VSS_NCTF_20 T19
AH44 VSS_86 VSS_185 W28 BD10 VSS_285 VSS_NCTF_21 R19
AF44 VSS_87 VSS_186 H28 AY10 VSS_286 VSS_NCTF_22 AN18
AD44 VSS_88 VSS_187 F28 AP10 VSS_287 VSS_NCTF_23
K44 VSS_89 VSS_188 AN27 H10 VSS_288
H44 VSS_90 VSS_189 AJ27 BL9 VSS_289
BL43 VSS_91 VSS_190 M27 BG9 VSS_290 GND
BG43 VSS_92 VSS_191 BF26 E9 VSS_291
AY43 VSS_93 VSS_192 BD26 A9 VSS_292 BL55
AR43 VSS_94 VSS_193 N26 BD8 VSS_293 VSS_SCB_1 BL1
VSS_95 VSS_194 VSS_294 VSS_SCB_2
VSS SCB
W43 H26 BB8 A55
R43 VSS_96 VSS_195 BJ25 AY8 VSS_295 VSS_SCB_3 D1
M43 VSS_97 VSS_196 AY25 AV8 VSS_296 VSS_SCB_4 B55
E43 VSS_98 VSS_197 AU25 AT8 VSS_297 VSS_SCB_5 B2
VSS_99 VSS_198 AP8 VSS_298 VSS_SCB_6 A4
small form factor VSS_299 VSS_SCB_7
UGS45_CANTIGA_SFF
GND GND small form factor GND
GND UGS45_CANTIGA_SFF

TECHNOLOGIES
ENG. APP.
PROD. APP.
PCA212268-2-1 1/1 1/1 15 62
! LAYOUTNOTE27
place each 100nF cap as close as possible to each VDD_IO pin V1.05_M
place the 10uF caps on the VDD_IO plane.
FB49
LCB47R03
C10US03V4 V1.05_M_CLKGEN
C618 C570 C138 C143

C600 C573 C615 C590 C591 C595 C604
C100N02V16
V3.3_S5
GND
FB48 C100N02V16
V3.3_M_CLKGEN U27
LCB47R03 56 45
33 VDD_CPU_I/O PCI_STOP# 44 PM_STPPCI# 18
C609 C589 C630 C623 C624 C619 43 VDD_SRC0_I/O CPU_STOP# PM_STPCPU# 18
52 VDD_SRC1_I/O 58 CLK_MCH_R_P RN17C 3 6 RN0RVF0804
GND VDD_SRC2_I/O CPU1_MCH CLK_MCH_BCLK_P 11
19 57 CLK_MCH_R_N RN17D 4 5 RN0RVF0804
27 VDD_I/O CPU1_MCH# CLK_MCH_BCLK_N 11
VDD_PLL3_I/O 61 CLK_CPU_R_P RN17A 1 8 RN0RVF0804
CPU0 CLK_CPU_BCLK_P 8
C644 C606 23 60 CLK_CPU_R_N RN17B 2 7 RN0RVF0804
VDD_PLL3 CPU0# CLK_CPU_BCLK_N 8
C4U7S03V4 C4U7S03V4 62
9 VDD_CPU 54 CLK_ITP_R_P RN15A 1 8 RN0RVF0804
GND 4 VDD_PCI SRC8/CPU_ITP 53 CLK_XDP_P 8
Y4 CLK_ITP_R_N RN15B 2 7 RN0RVF0804
VDD_REF SRC8#/CPU_ITP# CLK_XDP_N 8
Q14M318SMDF_BS 46
16 VDD_SRC 29 CLK_3GPLL_R_N RN14C 3 6 RN0RVF0804
! VDD_48 SRC2# 28 CLK_PCIE_PEG_N 12
1 2 LAYOUTNOTE28 CLK_3GPLL_R_P RN14D 4 5 RN0RVF0804
SRC2 CLK_PCIE_PEG_P 12
14M318 place crystal within 0,5" to CK505
XTAL_OUT 2 51
XTAL_IN 3 XTAL_OUT SRC7/CLKREQ_F# 50 CLK_SATA_OE_R# R219 R1%475RS02
17 XTAL_IN SRC7#/CLKREQ_E# CLK_SATA_OE# 18
C156 C157 R237 R1%33R2S02 CLK_USB48_BSEL0
18 CLK_USB_48M USB/FS_A 40
C33PS02 C33PS02
CLK_BSEL0 R232 R1%2K21S02 CLK_BSEL1 64 SRC11/CLKREQ_H# 39
FSB/TEST_MODE SRC11#/CLKREQ_G#
GND CLK_BSEL2 R255 R1%10K0S02 CLK_ICH_14M318_R 5 35 CLK_PCIE0_R_N RN12C 3 6 RN0RVF0804
REF/FSC/TEST_SEL SRC4# 34 CLK_PCIE0_N 2,38,40
R241 R1%33R2S02 CLK_PCIE0_R_P RN12D 4 5 RN0RVF0804
18 CLK_ICH_14M318 SRC4 CLK_PCIE0_P 2,38,40
R242 R1%475RS02 MCH_CLKREQ_R# 8 32 CLK_PCIE1_R_N RN14A 1 8 RN0RVF0804
12 MCH_CLKREQ# PCI0/CLKREQ_A# SRC3#/CLKREQ_D# 31 CLK_PCIE1_N 2,38,41
CLK_PCIE1_R_P RN14B 2 7 RN0RVF0804
10 SRC3/CLKREQ_C# CLK_PCIE1_P 2,38,41
R243 R1%22R1S02 CLK_PCI_33M_EXT_R
2,60 CLK_PCI_33M_EXT PCI1/CLKREQ_B# 38
V3.3_S0 R245 R1%10K0S02 CLK_PCIE2_R_N RN12A 1 8 RN0RVF0804
DNI
SRC9# CLK_PCIE2_N 2,38,39
R244 R1%22R1S02 CLK_PCI_CPLD_33M_R 11 37 CLK_PCIE2_R_P RN12B 2 7 RN0RVF0804
35 CLK_PCI_CPLD_33M PCI2 SRC9 CLK_PCIE2_P 2,38,39
R246 R1%22R1S02 CLK_LPC_33M_EXT_R 12 42 CLK_PCIE_ICH_R_N RN13C 3 6 RN0RVF0804
2,47 CLK_LPC_33M_EXT PCI3 SRC10# CLK_PCIE_ICH_N 18
41 CLK_PCIE_ICH_R_P RN13D 4 5 RN0RVF0804
SRC10 CLK_PCIE_ICH_P 18
R248 R1%22R1S02 SEL_LCDCLK# 13
17 CLK_PCI_33M_ICH PCI4/SEL_LCDCLK# 47 CLK_PCIESATA_R_N RN13B 2 7 RN0RVF0804
R249 14 SRC6# 48 CLK_PCIE_SATA_N 17
V3.3_S0 CLK_PCI_33M_ICH_R CLK_PCIESATA_R_P RN13A 1 8 RN0RVF0804
PCIF5/ITP_EN SRC6 CLK_PCIE_SATA_P 17
7
R1%10K0S02 18,20,21,23 SMB_CLK 6 SCL 24 DREFSSCLK_R_P RN16B 2 7 RN0RVF0804
18,20,21,23 SMB_DATA SDA LCDCLK/27M CLK_DPLL_REF_SS_P 12
R247 25 DREFSSCLK_R_N RN16A 1 8 RN0RVF0804
LCDCLK#/27M_SS CLK_DPLL_REF_SS_N 12
R1%10K0S02 15
18 VSS_PCI 21 CLK_DPLL_REF_R_N RN16C 3 6 RN0RVF0804
VSS_48 SRC0#/DOT_96# CLK_DPLL_REF_N 12
22 20 CLK_DPLL_REF_R_P RN16D 4 5 RN0RVF0804
26 VSS_I/O SRC0/DOT_96 CLK_DPLL_REF_P 12
30 VSS_PLL3
GND 36 VSS_SRC0 63
59 VSS_SRC1 CKPWRGD/PD# CLK_PWRGD 18
49 VSS_CPU
1 VSS_SRC2 55
65 VSS_REF NC
GND_PAD
UCK505_QFN64
RN15D 4 5 RN0RVF0804
GND
RN15C 3 6 RN0RVF0804
! LAYOUTNOTE30
BSEL[2..0] -> Refer to Topology 4A, B, C
V1.05_S0 of Montevina Platform Design Guide
Place for CPU Driven BSEL
R1%1K0S02
R1%1K0S02
R1%1K0S02
R637 R635 R633 Do not place for manually selected BSEL BSEL2 BSEL1 BSEL0 Host Clock Freq. FSB Freq.
DNI
DNI
DNI
0 1 1 166 667
0 1 0 200 800
CLK_BSEL0 RN19A 1 8 RN0RVF0804 0 0 0 266 1067
CPU_BSEL0 8
CLK_BSEL1 RN19B 2 7 RN0RVF0804 others RSVD
CPU_BSEL1 8
CLK_BSEL2 RN19C 3 6 RN0RVF0804
4 5 CPU_BSEL2 8
RN19D RN0RVF0804
RN20A 1 8 RN1KVF0804
MCH_BSEL0 12
RN20B 2 7 RN1KVF0804
MCH_BSEL1 12
RN20C 3 6 RN1KVF0804
4 5 MCH_BSEL2 12
RN20D RN1KVF0804
R1%1K0S02
R1%1K0S02
R1%1K0S02
R260 R258 R257
DNI
DNI
DNI
GND

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Clock Generator CK505
PROD. APP.
PCA212268-2-1 1/1 1/1 16 62
V3.3_G3_RTC
C139
R224
C1U02V6
R1%20K0S02
GND
C136 V3.3_G3_RTC
R218
C1U02V6
DNI
R1%0R0S02
0R = clear ME RTC registers
2,37,59,60,61,62 PCI_AD[31..0] U28B
GND R238 A11 G4
PCI_AD0 PCI_REQ0#
PCI_AD1 B12 AD0 REQ0# E1 PCI_GNT0#
C145
R233
R1%20K0S02
PCI_AD2 A10 AD1 PCI GNT0# A9 PCI_REQ1#
DNI
C1U02V6 AD2 REQ1#/GPIO50
R1%0R0S02 PCI_AD3 C12 E12
0R = clear CMOS PCI_AD4 A8 AD3 GNT1#/GPIO51 B11 PCI_REQ2#
PCI_AD5 A12 AD4 REQ2#/GPIO52 C10 PCI_GNT2#
GND C142 C10PS02 Q32K768SMD_UM_9P PCI_AD6 E10 AD5 GNT2#/GPIO53 D6 PCI_REQ3#
N_ICH_RTX1 PCI_AD7 C11 AD6 REQ3#/GPIO54 C6
Y3 PCI_AD8 B9 AD7 GNT3#/GPIO55
R227 AD8
U28A PCI_AD9 D8 D10 PCI_C/BE0# 2,59,60,61,62
R5%10MS02 LPC_AD[3..0] 2,35,47 AD9 C/BE0#
F25 H3 LPC_AD0 PCI_AD10 A4 A5 PCI_C/BE1# 2,59,60,61,62
32K768_UM_9p N_ICH_RTX2 G25 RTCX1 FWH0/LAD0 J3 LPC_AD1 V1.05_S0 PCI_AD11 E8 AD10 C/BE1# E6
RTCX2 FWH1/LAD1 AD11 C/BE2# PCI_C/BE2# 2,59,60,61,62
C144 C10PS02 K5 LPC_AD2 PCI_AD12 A3 C9 PCI_C/BE3# 2,59,60,61,62
GND FWH2/LAD2 AD12 C/BE3#
LPC
RTC_RST# G24 L3 LPC_AD3 PCI_AD13 D9
SRTC_RST# C24 RTCRST# FWH3/LAD3 R1%56R2S02 PCI_AD14 C8 AD13 C3
SRTCRST# AD14 IRDY# PCI_IRDY# 2,59,60,61,62
RTC
R208 R1%1M0S02 INTRUDER# C23 J2 PCI_AD15 C2 B1 PCI_PAR 2,59,60,61,62
INTRUDER# FWH4/LFRAME# LPC_FRAME# 2,35,47 ! D7 AD15 PAR T3
R277 LAYOUTNOTE31 PCI_AD16
DNI
DNI
AD16 PCIRST# PCI_RST# 37
R217 R1%332KS02 ICH_INTVRMEN E25 H1 LPC_DRQ0# H_DPRSTP# should be routed from ICH9M to MVP-6, PCI_AD17 B3 A7 PCI_DEVSEL# 2,59,60,61,62
D25 INTVRMEN LDRQ0# J1 R276 D11 AD17 DEVSEL# D4
LPC_DRQ1# then to GMCH and CPU (in this order exactly) PCI_AD18 PCI_PERR# 2,59,60,61,62
LAN100_SLP LDRQ1#/GPIO23 PCI_AD19 B6 AD18 PERR# C5 PCI_LOCK#
H_DPRSTP# 8,12,32 AD19 PLOCK#
G22 N3 KBD_A20GATE PCI_AD20 D5 H5 PCI_SERR# 2,35,59,60,61,62
22 CLK_GBE_ICH9 GLAN_CLK A20GATE AB23 H_DPSLP# 8 D3 AD20 SERR# A6
PCI_AD21 PCI_STOP# 2,59,60,61,62
A20M# H_A20M# 8 V1.05_S0 AD21 STOP#
D14 PCI_AD22 F4 A2 PCI_TRDY# 2,59,60,61,62
22 GBE0_PHY_RSTSYNC LAN_RSTSYNC ! LAYOUTNOTE32 AD22 TRDY#
AE23 PCI_AD23 E3 B8 PCI_FRAME# 2,59,60,61,62
A14 DPRSTP# AE24 R254 place series Resistor within 2" of ICH PCI_AD24 E4 AD23 FRAME#
22 GBE0_PHY_RDX0 LAN_RXD0 DPSLP# AD24
LAN / GLAN
D12 R1%56R2S02 place pullup R close to series R without stub PCI_AD25 B2 A21
22 GBE0_PHY_RDX1 B14 LAN_RXD1 AD25 R253 C4 AD25 PLTRST# B5 ICH_PLTRST# 12,24,25,35
H_FERR#_R PCI_AD26
22 GBE0_PHY_RDX2 LAN_RXD2 FERR# H_FERR# 8 AD26 PCICLK CLK_PCI_33M_ICH 16
R1%56R2S02 PCI_AD27 C1 T1
D13 AE22 PCI_AD28 D1 AD27 PME# V3.3_S0
22 GBE0_PHY_TXD0 LAN_TXD0 CPUPWRGD H_PWRGD 8 AD28
22 GBE0_PHY_TXD1
C13 PCI_AD29 E2
A13 LAN_TXD1 AD23 PCI_AD30 J4 AD29
22 GBE0_PHY_TXD2 LAN_TXD2 IGNNE# H_IGNNE# 8 AD30
PCI_AD31 H2 R212 R216 R220
AD31
CPU
R170 D15 AE21 R1%8K25S02 R622 R1%2K21S02 R1%2K21S02
GPIO56 INIT# H_INIT# 8
INTR
AD24
H_INTR 8
Interrupt I/F R1%8K25S02
V1.5_S0_PCIE_ICH H22 L1 KBD_RST# V1.05_S0 INT_IRQA# F1 G3 WDT_IRQ# 35
R626 GND GLAN_COMPI RCIN# PIRQA# PIRQE#/GPIO2
R1%24R9S02 GBE0_COMP H21 2,59 INT_IRQB# F5 G1 ICH_GPIO3
GLAN_COMPO AD21 ! LAYOUTNOTE33 F2 PIRQB# PIRQF#/GPIO3 F3
NMI H_NMI 8 2,60,61 INT_IRQC# PIRQC# PIRQG#/GPIO4 I2C_CLK_INT 22,35
RN21B 7 2 HDA_BIT_CLK_ICH AE7 AC21 place R130 within 2" of ICH 2,60,62 INT_IRQD# C7 H4
2,46 HDA_BIT_CLK 5 4 AB7 HDA_BIT_CLK SMI# H_SMI# 8 PIRQD# PIRQH#/GPIO5 I2C_DATA_INT 22,35
RN21D HDA_SYNC_ICH R252 place R129 within 2" of series R w/o stub
2,46 HDA_SYNC HDA_SYNC AC25 R1%56R2S02 small form factor
STPCLK# H_STPCLK# 8 place Q65 within 2" of series R w/o stub
RN21C 6 3 HDA_RST#_ICH AA7 UICH9M_SFF
2,46 HDA_RST# HDA_RST# AC23 R251
AB6 THRMTRIP# PM_THRMTRIP# 8,12
2,46 HDA_SDIN0 HDA_SDIN0 R1%54R9S02
AE6 AC22
IHDA
HDA_SDIN1 TP11 Q12
AC6
HDA_SDIN2 TMMBT3904
2
AA5 V1.05_S0
HDA_SDIN3 R250
AD12 1
SATA4RXN SATA_RX4_N 24
RN21A 8 1 HDA_SDOUT_ICH AC7 AE12 R1%2K21S02
2,46 HDA_SDOUT HDA_SDOUT SATA4RXP SATA_RX4_P 24
RN33RVF0402
AB12 MMBT3904 V3.3_S0
SATA_TX4_N 24
3
AD8 SATA4TXN AA12
AB8 HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_TX4_P 24
R256 R1%10K0S02
R269 HDA_DOCK_RST#/GPIO34 AC11
V3.3_S0 SATA5RXN SATA_RX5_N 25
R1%10K0S02 AC9 AD11 EXT_THRMTRIP# 2,35
2,26 ATA_LED# SATALED# SATA5RXP SATA_RX5_P 25
AB10
SATA5TXN SATA_TX5_N 25
C160 SATA_RX0_C_N AE14 AA10
2,49 SATA_RX0_N SATA0RXN SATA5TXP SATA_TX5_P 25
C161 SATA_RX0_C_P AD14
2,49 SATA_RX0_P SATA0RXP
C163 SATA_TX0_C_N AC15 AC16
SATA
2,49 SATA_TX0_N AD15 SATA0TXN SATA_CLKN AB16 CLK_PCIE_SATA_N 16

C162 SATA_TX0_C_P
2,49 SATA_TX0_P SATA0TXP SATA_CLKP CLK_PCIE_SATA_P 16
C166 SATA_RX1_C_N AD13 AD10
2,49 SATA_RX1_N AC13 SATA1RXN SATARBIAS# AE10
C165 SATA_RX1_C_P SATA_RBIAS_PN
2,49 SATA_RX1_P SATA1RXP SATARBIAS
C168 SATA_TX1_C_N AA14
2,49 SATA_TX1_N SATA1TXN
C167 SATA_TX1_C_P AB14
2,49 SATA_TX1_P SATA1TXP small form factor R270
C10NS02
UICH9M_SFF R1%24R9S02
! LAYOUTNOTE34
! LAYOUTNOTE35 short pins AD10, AE10 and place
distance between ICH and cap between P- and 24R9 within 500mils to them
N-signal should be identical for the same pair GND V3.3_S0
ICH9M pullups
KBD_RST# R229 R1%10K0S02
KBD_A20GATE R239 R1%10K0S02
V3.3_S0 PCI_FRAME# RN11B 2 7 RN8K2VF0804

PCI_IRDY# RN10D 4 5 RN8K2VF0804
if Firmwarehub should be PCI_TRDY# RN11A 1 8 RN8K2VF0804
selected to be flashed PCI_STOP# RN11D 4 5 RN8K2VF0804
PCI_GNT2# GPIO3 shoud be low, else high R230 PCI_SERR# RN11C 3 6 RN8K2VF0804
V3.3_S0 R1%10K0S02 PCI_DEVSEL# RN10C 3 6 RN8K2VF0804
ICH_GPIO3 1 2 PCI_RST# PCI_PERR# RN10A 1 8 RN8K2VF0804
R169 PCI_LOCK# RN10B 2 7 RN8K2VF0804
DNI
R1%1K0S02 D57 PCI_REQ0# RN8B 2 7 RN8K2VF0804
3
R265 R266 V3.3_S0 DBAT54A PCI_REQ1# RN8D 4 5 RN8K2VF0804
DNI
DNI
R1%1K0S02 R1%1K0S02 PCI_REQ2# RN8C 3 6 RN8K2VF0804
1
PCI_REQ3# RN8A 1 8 RN8K2VF0804
GND HDA_SYNC_ICH HDA_SDOUT_ICH 5 BSS84
INT_IRQA# RN9A 1 8 RN8K2VF0804
2 VCC 4 2 3 PCI_GNT0# INT_IRQB# RN9B 2 7 RN8K2VF0804
ICH_TP3 18
INT_IRQC# RN9C 3 6 RN8K2VF0804
R198 1 o INT_IRQD# RN9D 4 5 RN8K2VF0804
DNI
2,18,47 BIOS_DISABLE# #OE

R1%1K0S02 GND Q51 R628
U96
TBSS84 R1%1K0S02
U74VHC1GT125
3
LPC_DRQ0# R222 R1%10KS02

GND
GND LPC_DRQ1# R225 R1%10KS02
GND

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED ICH9 1
PROD. APP.
PCA212268-2-1 1/1 1/1 17 62
ICH9M SMB, GPIO, Clocks, V3.3_S0 ICH9M PCIe, DMI, SPI, USB
Ctrl Link, Power MGT
RN18D
RN18C
RN18A
RN18B
8
5
7
6
RN10KVF0804
U28C U28D
1
4
2
3
SMB_CLK_S5 C18 AE19 T25 V25
C15 SMBCLK SATA0GP/GPIO21 AA18 BIOS_DISABLE# 2,17,47 2,38,40 PCIE_RX1_N T24 PERN1 DMI0RXN V24 ICH_DMI_RX0_N 12
SMB_DATA_S5
PEG_ENABLE# 2,38,39,54 2,38,40 PCIE_RX1_P ICH_DMI_RX0_P 12
SATA
GPIO
SMBDATA SATA1GP/GPIO19 PERP1 DMI0RXP
Direct Media Interface

LINKALERT# B21 AE20 C158 PCIE_TX1_C_N R24 U24
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 2,38,40 PCIE_TX1_N PETN1 DMI0TXN ICH_DMI_TX0_N 12
R600 SMLINK0 E18 AA20 C155 PCIE_TX1_C_P R23 U23
DNI
SMLINK0 SATA5GP/GPIO37 CPLD_TDO_ICH 35 2,38,40 PCIE_TX1_P PETP1 DMI0TXP ICH_DMI_TX0_P 12
R596 SMLINK1 A24
DNI
SMLINK1 SMB K1 C100N02V16 P25 W23
R1%0R0S02 CLK14 CLK_ICH_14M318 16 2,38,41 PCIE_RX2_N PERN2 DMI1RXN ICH_DMI_RX1_N 12
Clocks
C20 AB5 P24 W24
2,38,41 WAKE1# RI# CLK48 CLK_USB_48M 16 2,38,41 PCIE_RX2_P PERP2 DMI1RXP ICH_DMI_RX1_P 12
V3.3_S5 C147 PCIE_TX2_C_N P21 V21
2,38,41 PCIE_TX2_N PETN2 DMI1TXN ICH_DMI_TX1_N 12
T5 R3 C154 PCIE_TX2_C_P P22 V22
2,35,47 PM_SUS_STAT# SUS_STAT#/LPCPD# SUSCLK CLK_SUS_32K 35 2,38,41 PCIE_TX2_P PETP2 DMI1TXP ICH_DMI_TX1_P 12
C25
8,35 SYS_RESET# SYS_RESET# C100N02V16
D18 N23 Y24
SLP_S3# PM_SLP_S3# 31,34,35 PERN3 DMI2RXN ICH_DMI_RX2_N 12
PCI-Express
R202 L2 B20 N24 Y25
12 PM_SYNC# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S4# 34,35 22 PCIE_GBE0_RX_N PERP3 DMI2RXP ICH_DMI_RX2_P 12
R1%1K02S02 D16 M21 Y21
SLP_S5# PM_SLP_S5# 35 22 PCIE_GBE0_RX_P PETN3 DMI2TXN ICH_DMI_TX2_N 12
A23 M22 Y22
23 SMB_ALERT# SMBALERT#/GPIO11 22 PCIE_GBE0_TX_N PETP3 DMI2TXP ICH_DMI_TX2_P 12
R1%0R0S02
R1%0R0S02
R1%0R0S02 E14
S4_STATE#/GPIO26 PM_S4_STATE# 35 TP32 22 PCIE_GBE0_TX_P
R194 PM_STPPCI_R# B15 rnd_1mm M25 AB24
SYS GPIO
16 PM_STPPCI# STP_PCI#/GPIO15 PM_ICH_PWROK 35 PERN4 DMI3RXN ICH_DMI_RX3_N 12
C100N02V16
C100N02V16
R200 PM_STPCPU_R# A20 D23 M24 AB25
16 PM_STPCPU# STP_CPU#/GPIO25 PWROK TP33 L24 PERP4 DMI3RXP AA23 ICH_DMI_RX3_P 12
R1%0R0S02 R211 R1%10K0S02 rnd_1mm V3.3_S5
M5 M1 L23 PETN4 DMI3TXN AA24 ICH_DMI_TX3_N 12
2,47 PM_CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR 12 TP34 PETP4 DMI3TXP ICH_DMI_TX3_P 12
rnd_1mm
C21 C16 PM_BATLOW# GND NI K24 T21
2,38,39,40 PCIE_WAKE# WAKE# BATLOW# ! PERN5 DMI_CLKN CLK_PCIE_ICH_N 16
Power MGT
L4 LAYOUTNOTE36 R786 0 R787 K25 T22
2,35,47 LPC_SERIRQ AD20 SERIRQ U4 K21 PERP5 DMI_CLKP CLK_PCIE_ICH_P 16
V3.3_S0 place Cs and Rs with shared 4.7K V1.5_S0_PCIE_ICH
23,35 PM_THRM# THRM# PWRBTN# CPLD_PWRBTN# 35 PETN5
R619
R621
pin close together (no stub) K22 AB21
R180 PETP5 DMI_ZCOMP R627
2 3 VR_PWRGD_CLKEN B24 D22 Q82 AB22 DMI_IRCOMP_R
VRMPWRGD LAN_RST# PM_LAN_RST# 22,35 DMI_IRCOMP
C617
C612
Q11 R1%100KS02 MMBT3906 PCIE_RX6_R_N H24
R1%10K0S02 PERN6/GLAN_RXN R1%24R9S02
BSS84 R192 A19 D19 ICH_RSMRST# 3 2 PCIE_RX6_R_P H25 AE2 USB0_N 2,42,43
TP12 RSMRST# PM_RSMRST# 35 J24 PERP6/GLAN_RXP USBP0N AD1
TBSS84 PCIE_TX6_C_N USB0_P 2,42,43
GND EXT_GPI0 AE16 U1 PCIE_TX6_C_P J23 PETN6/GLAN_TXN USBP0P AD3
CLK_PWRGD 16 USB1_N 2,42,43
1
1
EXT_GPI1 AE18 GPIO1 CK_PWRGD R174 RSM_RST_BASE_PU R1%15R0S02 PETP6/GLAN_TXP USBP1N AD4
32,35 VR_PWRGD_CLKEN# GPIO6 USBP1P USB1_P 2,42,43
EXT_GPI2 AD18 T4 R1%10K0S02 22 SPI_CLK R616 SPI_CLK_R E24 AC2 USB2_N 2,42,43
GPIO7 CLPWROK CL_PWROK 12,35 SPI_CLK USBP2N
1
B25 22 SPI_CS0# R611 SPI_CS0#_R E23 AC3 USB2_P 2,42,43
35 ICH_GPIO8_CPLD GPIO8 SPI_CS0# USBP2P
36 EXCD0_CPPE#
C14 B23 22 SPI_CS1# R623 SPI_CS1#_R F23 AC5 USB3_N 2,42,43
GPIO12 SLP_M# PM_SLP_M# 34,35 SPI_CS1#/GPIO58/CLGPIO6 USBP3N
36 EXCD1_CPPE# D20 3 D69 AB4 USB3_P 2,42,43
AE17 GPIO13 C22 GND R1%15R0S02 F22 USBP3P AB2
NI V3.3_S5 BAV99W 22 SPI_SI R620 SPI_SI_R USB4_N 2,48
35 WDTKICK K3 GPIO17 CL_CLK0 A18 MCH_CL_CLK1 MCH_CL_CLK0 12 G23 SPI_MOSI USBP4N AB1
R268
ICH_GPIO20_RSVD
35 CPLD_TDI_ICH
AC8 GPIO18 CL_CLK1 TP8
rnd_1mm
22 SPI_SO SPI_MISO SPI USBP4P AA3
USB4_P 2,48
V3.3_S0 USB5_N 2,48
1 2
EXT_GPI3 AC19 GPIO20 E22 RSM_RST_ISO P4 USBP5N AA2
R1%100KS02 SCLOCK/GPIO22 CL_DATA0 MCH_CL_DATA0 12 2,59 USB_01_OC# OC0#/GPIO59 USBP5P USB5_P 2,48
Controller Link
D17 B18 MCH_CL_DATA1 R602 N4 Y1
35 CPLD_TMS_ICH GPIO27 CL_DATA1 TP9 OC1#/GPIO40 USBP6N
GPIO
E20 rnd_1mm R1%3K24S02 N1 Y2

V3.3_S5 M4 GPIO28 F21 CL_VREF0_ICH RSM_RST_ISO_A 3 D70
2,59 USB_23_OC#
P5 OC2#/GPIO41 USB
USBP6P W2
16 CLK_SATA_OE# SATACLKREQ#/GPIO35 CL_VREF0 OC3#/GPIO42 USBP7N
AB18 A17 CL_VREF1_ICH BAV99W P1 W3
AC18 SLOAD/GPIO38 CL_VREF1 C579 2,59 USB_45_OC# P2 OC4#/GPIO43 USBP7P V1
EN_SMB_EXT R606
AB19 SDATAOUT0/GPIO39 C17 C100N02V16 M3 OC5#/GPIO29 USBP8N V2
R1%453RS02
MCH_CL_RST0# 12
2
R196 ICH_GPIO49_EC AC20 SDATAOUT1/GPIO48 CL_RST0# B17 RSM_RST_ISO_B M2 OC6#/GPIO30 USBP8P Y5
R1%1K02S02 A16 GPIO49 CL_RST1# MCH_CL_RST1# NI ICH_OC8# P3 OC7#/GPIO31 USBP9N Y4
GPIO57/CLGPIO5 A22 TP7 GND R1 OC8#/GPIO44 USBP9P U3
ICH_TPM_PRESENT rnd_1mm R788 R789 ICH_OC9#
MEM_LED/GPIO24 CPLD_TCK_ICH 35 OC9#/GPIO45 USBP10N
K4 E16 2.2K 2.2K ICH_OC10# R4 U2
SPKR GPIO10/SUS_PWR_ACK SUS_PWR_ACK 35 OC10#/GPIO46 USBP10P
R173 AB20 A15 V3.3_S5 R2 V4
12 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT ICH_GPIO14_CPLD 35 OC11#/GPIO47 USBP11N
DNI
MISC
R1%100KS02 C19 D21 ICH_OC11# V5

17 ICH_TP3 TP3 WOL_EN/GPIO9 LAN_WOL_EN 34,35 USBP11P
1
2
6
4
1
2
6
4
AB17 V3.3_S5 AE5
To use internal TPM, TP13 AC17 TP8 AD5 USBRBIAS
rnd_1mm R607
GND ICH_TPM_PRESENT TP12 TP9 GND GND USBRBIAS#
R176
R280
R274
R273
R197
rnd_1mm AD17 R1%3K24S02 small form factor

must be set high (lt. INTEL) TP11 TP10 small form factor
rnd_1mm UICH9M_SFF
8
7
3
5
8
RN22A 7
RN22B 3
5
UICH9M_SFF
RN23C
RN23D
R1%10K0S02 R601 R267
RN23A
RN23B
RN22C
RN22D
USB drive strength set using R433
C580 R1%453RS02 22.6
R228
V3.3_S0 C100N02V16
GND 2,46 HDA_SPKR DNI
R1%1K0S02 RN10KVF0804 RN10KVF0804

GND GND ! LAYOUTNOTE37
R1%0R0S02 V3.3_SMBUS_M V3.3_S5 Short pins AE5, AD5 and place R267 within 500mils to them.
Possibly use ICH_GPIO3 instead of ICH_GPIO49_EC?? R575 Avoid routing next to clock/high speed signals.
V3.3_S5
V3.3_S0 R576 DNI
Q46
1
R570 T2N7002 R1%10K0S02 R560
R571
R1%10K0S02 2N7002 R561 R1%10K0S02
R1%10K0S02
2 3 SMB_CLK_S5
16,20,21,23 SMB_CLK
2 3 SMB_DATA_S5
16,20,21,23 SMB_DATA
Q45
No Reboot Strap (HDA_SPKR) T2N7002
2N7002
LOW = default V3.3_SMBUS_M
1
HIGH = no reboot V3.3_S5
EN_SMB_EXT
V3.3_S5 Q42
1
R566 R565 2N7002
R1%10K0S02 R1%10K0S02 T2N7002
R593 R590 iTPM enable Strap 2 3 SMB_CLK_S5

DNI
DNI
2,38,39,40 SMB_CK
R1%10K0S02 R1%10K0S02 R173=NO_STUFF for discrete TPM and
R173=STUFF for iTPM enable
PM_STPPCI#
PM_STPCPU# V3.3_S5 2 3 SMB_DATA_S5
2,38,39,40 SMB_DAT
V3.3_S5 SPI_SI_R R617 DNI
R1%20K0S02 Q41
PM_LAN_RST# R612 R1%10K0S02 2N7002
T2N7002
1
LAN_WOL_EN R178 R1%10K0S02 V3.3_S0
WAKE1# R177 R1%10K0S02 EN_SMB_EXT
PCIE_WAKE# R201 R1%1K02S02 CLK_SATA_OE# R231 R1%10K0S02
PM_THRM# R282 R1%8K25S02
PM_BATLOW# R172 R1%8K25S02 LPC_SERIRQ R226 R1%10K0S02
LINKALERT# R179 R1%10K0S02 PM_CLKRUN# R236 R1%8K25S02
SMLINK0 R175 R1%10K0S02 EXT_GPI0 R279 R1%10K0S02
SMLINK1 R203 R1%10K0S02 EXT_GPI1 R271 R1%10K0S02
EXT_GPI2 R272 R1%10K0S02
SUS_PWR_ACK R171 R1%10K0S02 EXT_GPI3 R281 R1%10K0S02
ICH_GPIO14_CPLD R195 DNI
R1%10K0S02
ICH_GPIO8_CPLD R213 R1%10K0S02 ICH_GPIO49_EC R275 DNI
R1%10K0S02
EXCD0_CPPE# R193 R1%10K0S02

GPIO49 (DMI Termination Voltage)
should be high at rising edge of PWROK
for mobile applications
TECHNOLOGIES
EXCD1_CPPE# R199 R1%10K0S02 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
GPIO49 has a 20k internal pull-up TITLE
SAME IS PROECTEDTO THE EXTENT PERMITTED
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED ICH9 2
PROD. APP.
PCA212268-2-1 1/1 1/1 18 62
V3.3_G3_RTC
U28E V1.05_S0
B4 U5 U28F
B7 VSS[001] VSS[107] U10 V5.0_S0 G17 L11 V1.05_S0_ICH C100N02V16 FB53
B10 VSS[002] VSS[108] W11 C599 C597 VCCRTC VCC1_05[01] L12 + C130 LCB10R02
VSS[003] VSS[109] C598 VCC1_05[02]
B13 U14 V3.3_S0 C1U02V6 C100N02V16 G7 L13 C620 C628 C629 330u
DNI
VSS[004] VSS[110] C100N02V16 V5REF VCC1_05[03] C621
B16 W16 L14 C22NS02 C22NS02 2.5 V
VSS[005] VSS[111] R618 VCC1_05[04]
B19 U21 U7 L15 V1.5_S0
VSS[006] VSS[112] R1%100RS02 V5REF_SUS VCC1_05[05]
2
B22 U22 M11
D2 VSS[007] VSS[113] U25 GND J19 VCC1_05[06] M15
D24 VSS[008] VSS[114] V3 D56
3 K18 VCC1_5_B[01] VCC1_05[07] N11 GND L17
V5.0_S0_V5REF VCCDMIPLL
E5 VSS[009] VSS[115] V8 V5.0_S5 C587 K19 VCC1_5_B[02] VCC1_05[08] N15 C631 C634 L1U0H05
VSS[010] VSS[116] DBAT54C VCC1_5_B[03] VCC1_05[09]
E7 V19 C1U02V6 L18 P11 C10NS02 C10US03V4
E9 VSS[011] VSS[117] V23 V3.3_S5 L19 VCC1_5_B[04] VCC1_05[10] P15
1
VSS[012] VSS[118] VCC1_5_B[05] VCC1_05[11]
VCCA3GP
E11 W1 M18 R11
CORE
E13 VSS[013] VSS[119] W4 R259 GND M19 VCC1_5_B[06] VCC1_05[12] R12 V1.05_S0
VSS[014] VSS[120] VCC1_5_B[07] VCC1_05[13] GND
2
E15 W5 R1%100RS02 N18 R13
E17 VSS[015] VSS[121] W7 N19 VCC1_5_B[08] VCC1_05[14] R14 VCC_DMIPLL FB54
E19 VSS[016] VSS[122] W9 D19
3 P18 VCC1_5_B[09] VCC1_05[15] R15
V5.0_S5_V5REF_SUS C640 LCB10R02
E21 VSS[017] VSS[123] W15 R18 VCC1_5_B[10] VCC1_05[16] C1U02V6
VSS[018] VSS[124] DBAT54C VCC1_5_B[11]
F24 W19 C159 T18
G2 VSS[019] VSS[125] W21 C1U02V6 T19 VCC1_5_B[12] V1.05_S0
1
G5 VSS[020] VSS[126] W22 U18 VCC1_5_B[13] P19
G10 VSS[021] VSS[127] W25 V1.5_S0 V1.5_S0_PCIE_ICH U19 VCC1_5_B[14] VCCDMIPLL GND
G13 VSS[022] VSS[128] Y3 VCC1_5_B[15] T17 C648 C645 C649
G16 VSS[023] VSS[129] Y23 GND FB55 C100N02V16 VCC_DMI[1] U17 C100N02V16 C100N02V16 C4U7S03V4
G19 VSS[024] VSS[130] AA1 LCB300R03 VCC_DMI[2]
G21 VSS[025] VSS[131] AA4 INTEL: 330Ohm C614 C665 V16
DNI
H10 VSS[026] VSS[132] AA6 C626 V_CPU_IO[1] U16 V3.3_S0
H12 VSS[027] VSS[133] AA8 C671 C661 C10US03V4 V_CPU_IO[2] GND
H18 VSS[028] VSS[134] AA11 V18
H23 VSS[029] VSS[135] AA13 C100US10V6X5R C22US05V6 VCC3_3[01]
VSS[030] VSS[136] C656
J5 AA15 AE9
VSS[031] VSS[137] GND VCC3_3[02] C100N02V16
J9 AA16
J10 VSS[032] VSS[138] AA17
J11 VSS[033] VSS[139] AA19 GND
J12 VSS[034] VSS[140] AA21 AA9
VSS[035] VSS[141] VCC3_3[03] C602
J13 AA22 V14
VCCP_CORE
VSS[036] VSS[142] VCC3_3[04] C100N02V16
J15 AA25 W14
J21 VSS[037] VSS[143] AB3 VCC3_3[05]
J22 VSS[038] VSS[144] AB9
J25 VSS[039] VSS[145] AB11 G8 GND
K2 VSS[040] VSS[146] AB13 V1.5_S0 VCC3_3[06] H7
VSS[041] VSS[147] VCC3_3[07] C646 C647
K9 AB15 H8
DNI
VSS[042] VSS[148] VCC3_3[08] C100N02V16 C100N02V16
K10 AC24
PCI
VSS[043] VSS[149] L18
K11 AC1 V1.5_S0_SATAPLL
K12 VSS[044] VSS[150] AC4 L10UH05 GND
K13 VSS[045] VSS[151] AC10 C651 C652
VSS[046] VSS[152] C603 C639
K15 AC12 C10US03V4 C100N02V16
DNI
VSS[047] VSS[153] C100N02V16 C100N02V16
K17 AC14 AD7
K23 VSS[048] VSS[154] AD2 VCCHDA
L5 VSS[049] VSS[155] AD6 HS2 W17 V10
L9 VSS[050] VSS[156] AD9 ICH9 HeatSink GND VCCSATAPLL VCCSUSHDA GND
L10 VSS[051] VSS[157] AD16 4 1 U13 T7
L16 VSS[052] VSS[158] AD19 P4 P1 V13 VCC1_5_A[01] VCCSUS1_05[1] H15 C664
L17 VSS[053] VSS[159] AD22 W13 VCC1_5_A[02] VCCSUS1_05[2] C100N02V16
C632 C654
VSS[054] VSS[160] VCC1_5_A[03]
ARX
L21 AE3 3 2 C1U02V6 C100N02V16 H16 VCCSUS1_5_ICH_1 V3.3_V1.5_HDA_S5
L22 VSS[055] VSS[161] AE4 P3 P2 VCCSUS1_5[1]
L25 VSS[056] VSS[162] AE11 V7 GND R634
VCCSUS1_5_ICH_2
VSS
M9 VSS[057] VSS[163] AE13 GND GND VCCSUS1_5[2] DNI
VSS[058] VSS[164] GND C660 C586 C663 R1%0R0S02

M10 AE15
DNI
DNI
VSS[059] VSS[165] C100N02V16 C100N02V16 C100N02V16 GND
M12 V17 G14 R636
VSS[060] VSS[166] VCCSUS3_3[01]
VCCPSUS
M13 AE8 HS_CLIP3 U12 G15 R1%0R0S02
M14 VSS[061] VSS[167] V9 HEATSINK_CLIP V12 VCC1_5_A[04] VCCSUS3_3[02] H14 V3.3_S5 GND
VSS[062] VSS[168] VCC1_5_A[05] VCCSUS3_3[03] GND Voltage divider, to
M16 J16 451-017 C635 C641 W12
M17 VSS[063] VSS[169] C1U02V6 C100N02V16 VCC1_5_A[06] R592 V3.3_S5 support HDA voltages
VSS[064] with V1.5_S5
ATX
M23
VSS[065] R1%0R0S02
N2 HS_CLIP4 W8
N5 VSS[066] HEATSINK_CLIP VCCSUS3_3[04]
N9 VSS[067] GND 451-017 GND J7
N10 VSS[068] VCCSUS3_3[05] J8
VSS[069] VCCSUS3_3[06] C625 C616 C610
N12 W10 K7
VSS[070] VCC1_5_A[07] VCCSUS3_3[07] C22NS02 C100N02V16 C100N02V16
N13 C601 C607 C637 K8
N14 VSS[071] C1U02V6 C1U02V6 C100N02V16 U15 VCCSUS3_3[08] L7
N16 VSS[072] V15 VCC1_5_A[08] VCCSUS3_3[09] L8
N17 VSS[073] VCC1_5_A[09] VCCSUS3_3[10] M7
N21 VSS[074] W18 VCCSUS3_3[11] M8 GND
N22 VSS[075] GND VCC1_5_A[10] VCCSUS3_3[12] N7
N25 VSS[076] G9 VCCSUS3_3[13] N8
P9 VSS[077] H9 VCC1_5_A[11] VCCSUS3_3[14] P7
VCCPUSB
P10 VSS[078] VCC1_5_A[12] VCCSUS3_3[15] P8
P12 VSS[079] V11 VCCSUS3_3[16]
VSS[080] C636 VCC1_5_A[13]
P13 U11
P14 VSS[081] C100N02V16 VCC1_5_A[14]
P16 VSS[082]
P17 VSS[083] U8 G18 VCCCL1_05_INT_ICH
P23 VSS[084] GND VCCUSBPLL VCCCL1_05
R5 VSS[085] T9 H17 VCCCL1_5_INT_ICH
VSS[086] VCC1_5_A[15] VCCCL1_5 C571
USB CORE
R7 U9
DNI
C582
R8 VSS[087] C638 VCC1_5_A[16] J14 V3.3_S5 C567 C100N02V16
DNI
C1U02V6
R9 VSS[088] C100N02V16 VCCCL3_3[1] K14 C100N02V16
R10 VSS[089] VCCCL3_3[2]
R16 VSS[090]
R17 VSS[091] VCCLAN1_05_INT_ICH GND G11 GND
R19 VSS[092] V3.3_S5 H11 VCCLAN1_05[1]
R21 VSS[093] A1 C585 VCCLAN1_05[2]
VSS[094] VSS_NCTF[01] C100N02V16
R22 A25 G12
R25 VSS[095] VSS_NCTF[02] AE1 V1.5_S0 H13 VCCLAN3_3[1]
T2 VSS[096] VSS_NCTF[03] AE25 C613 VCCLAN3_3[2]
VSS[097] VSS_NCTF[04] GND C100N02V16 L15
T8 VCCGLANPLL J17
T10 VSS[098] L1UH07 V1.5_S0_PCIE_ICH VCCGLANPLL
VSS[099]
GLAN POWER
T11 C584 C572 H19
T12 VSS[100] GND GND C10US03V4 C2U2S03V6 J18 VCCGLAN1_5[1]
T13 VSS[101] VCCGLAN1_5[2]
T14 VSS[102] C608 V3.3_S0
T15 VSS[103] C10US03V4
T16 VSS[104] GND K16
T23 VSS[105] VCCGLAN3_3 small form factor
VSS[106] small form factor UICH9M_SFF
UICH9M_SFF GND
GND

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED ICH9 Power
PROD. APP.
PCA212268-2-1 1/1 1/1 19 62
Bottom SO-DIMM Socket with 4 mm Height
11 M_A_A[14..0]
J12A
M_A_DQ[63..0] 11
M_A_A0 98 5 M_A_DQ0 LAYOUTNOTE38 V1.5_SYS_MEM
M_A_A1 97 A0 DQ00 7 M_A_DQ1 ! J12B
M_A_A2 96 A1 DQ01 15 M_A_DQ2 place these caps near SODIMM_A
M_A_A3 95 A2 DQ02 17 M_A_DQ3 75 44
M_A_A4 92 A3 DQ03 4 M_A_DQ4
near SODIMM_A 76 VDD1 VSS16 48
M_A_A5 91 A4 DQ04 6 M_A_DQ5 81 VDD2 VSS17 49
M_A_A6 90 A5 DQ05 16 M_A_DQ6 C10US03V4 82 VDD3 VSS18 54
M_A_A8 89 A7 DQ07 21 M_A_DQ8 C578 + 88 VDD5 VSS20 60
A8 DQ08 C555 C536 C500 C548 C524 C498 VDD6 VSS21
M_A_A9 85 23 M_A_DQ9 C330U2V5POS 93 61
M_A_A11 84 A10/AP DQ10 35 M_A_DQ11 99 VDD8 VSS23 66
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ13 GND 105 VDD10 VSS25 72
R573DNI TP_A15_DIMM_A 78 A14 DQ14 36 M_A_DQ15 111 VDD12 VSS27 128
A15 DQ15 39 M_A_DQ16 112 VDD13 VSS28 133
R1%10KS02 DQ16 VDD14 VSS29
109 41 M_A_DQ17 117 134
GND 11 M_A_BS0 BA0 DQ17 VDD15 VSS30
108 51 M_A_DQ18 118 138
11 M_A_BS1 79 BA1 DQ18 53 123 VDD16 VSS31 139
M_A_DQ19
11 M_A_BS2 114 BA2 DQ19 40 124 VDD17 VSS32 144
M_A_DQ20 V3.3_S5
12 M_CS#_A0 S0# DQ20 VDD18 VSS33
121 42 M_A_DQ21 145
12 M_CS#_A1 S1# DQ21 VSS34
101 50 M_A_DQ22 199 150
12 CLK_MEM_DDRA0_P CK0 DQ22 VDDSPD VSS35
103 52 M_A_DQ23 151
12 CLK_MEM_DDRA0_N 102 CK0# DQ23 57 C655 77 VSS36 155
M_A_DQ24
12 CLK_MEM_DDRA1_P CK1 DQ24 C100N02V16 C650 NC1 VSS37
104 59 M_A_DQ25 122 156
12 CLK_MEM_DDRA1_N CK1# DQ25 C2U2S03V6 NC2 VSS38
NOTE: 73 67 M_A_DQ26 125 161
12 M_CKE_A0 74 CKE0 DQ26 69 over temperature alarm NCTEST VSS39 162
SO-DIMM_A SPD address is 0xA0 M_A_DQ27
12 M_CKE_A1 115 CKE1 DQ27 56 12,21,30 DDR_VREF GND 198 VSS40 167
SO-DIMM_A TS address is 0x30 M_A_DQ28
11 M_A_CAS# 110 CAS# DQ28 58 12,21 TS#_DIMM_AB 30 EVENT# VSS41 168
M_A_DQ29
11 M_A_RAS# RAS# DQ29 C447 C454 12,21 DDR3_DRAMRST# RESET# VSS42
113 68 M_A_DQ30 172
11 M_A_WE# 197 WE# DQ30 70 C100N02V16 C2U2S03V6 VSS43 173
SA0_DIMM_A M_A_DQ31
SA1_DIMM_A 201 SA0 DQ31 129 M_A_DQ32 1 VSS44 178
202 SA1 DQ32 131 M_A_DQ33 GND 126 VREF_DQ VSS45 179
16,18,21,23 SMB_CLK SCL DQ33 VREF_CA VSS46
200 141 M_A_DQ34 184
16,18,21,23 SMB_DATA SDA DQ34 C566 C575 VSS47
143 M_A_DQ35 2 185
116 DQ35 130 C100N02V16 C2U2S03V6 3 VSS1 VSS48 189
R629 R631 M_A_DQ36
12 M_ODT_A0 ODT0 DQ36 VSS2 VSS49
R1%10KS02 R1%10KS02 120 132 M_A_DQ37 8 190
12 M_ODT_A1 ODT1 DQ37 140 GND 9 VSS3 VSS50 195
M_A_DQ38
11 M_A_DM[7..0] DQ38 VSS4 VSS51
M_A_DM0 11 142 M_A_DQ39 13 196
M_A_DM1 28 DM0 DQ39 147 M_A_DQ40 14 VSS5 VSS52
M_A_DM2 46 DM1 DQ40 149 M_A_DQ41 19 VSS6 V0.75_S3
M_A_DM3 63 DM2 DQ41 157 M_A_DQ42 20 VSS7 GND
GND M_A_DM4 136 DM3 DQ42 159 M_A_DQ43 25 VSS8 203
M_A_DM5 153 DM4 DQ43 146 M_A_DQ44 26 VSS9 VTT1 204
M_A_DM6 170 DM5 DQ44 148 M_A_DQ45 31 VSS10 VTT2 C668 C659 C669 C662
M_A_DM7 187 DM6 DQ45 158 M_A_DQ46 !
LAYOUTNOTE39 32 VSS11 C1US02
DM7 DQ46 160 M_A_DQ47 V1.5_SYS_MEM
place these caps near Command 37 VSS12 G1
12 DQ47 163 M_A_DQ48 and Control signals of SODIMM_A 38 VSS13 G1 G2
11 M_A_DQS0_P DQS0 DQ48 VSS14 G2
29 165 M_A_DQ49 43
11 M_A_DQS1_P DQS1 DQ49 VSS15
47 175 M_A_DQ50 C506 C556 C508 C562
11 M_A_DQS2_P 64 DQS2 DQ50 177 M_A_DQ51 C100N02V16 XSODIMM_DDR3_RVS_4MM0
11 M_A_DQS3_P DQS3 DQ51 GND GND ! LAYOUTNOTE40
137 164 M_A_DQ52
11 M_A_DQS4_P 154 DQS4 DQ52 166 M_A_DQ53 place these caps close
11 M_A_DQS5_P DQS5 DQ53
171 174 M_A_DQ54 to VTT1 and VTT2
11 M_A_DQS6_P DQS6 DQ54 GND
188 176 M_A_DQ55
11 M_A_DQS7_P 10 DQS7 DQ55 181 M_A_DQ56
11 M_A_DQS0_N DQS#0 DQ56
27 183 M_A_DQ57
45 191 M_A_DQ58
62 193 M_A_DQ59
135 180 M_A_DQ60
11 M_A_DQS4_N 152 DQS#4 DQ60 182 M_A_DQ61
XSODIMM_DDR3_RVS_4MM0

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED DDR3 SO-DIMM A
PROD. APP.
PCA212268-2-1 1/1 1/1 20 62
Top SO-DIMM Socket with 8 mm Height
11 M_B_A[14..0] M_B_DQ[63..0] 11
J11A
M_B_A0 98 5 M_B_DQ0
M_B_A1 97 A0 DQ00 7 M_B_DQ1
M_B_A2 96 A1 DQ01 15 M_B_DQ2
M_B_A3 95 A2 DQ02 17 M_B_DQ3
M_B_A4 92 A3 DQ03 4 M_B_DQ4 V1.5_SYS_MEM
M_B_A5 91 A4 DQ04 6 M_B_DQ5 J11B
M_B_A6 90 A5 DQ05 16 M_B_DQ6
M_B_A7 86 A6 DQ06 18 M_B_DQ7 75 44
M_B_A8 89 A7 DQ07 21 M_B_DQ8 ! LAYOUTNOTE41 76 VDD1 VSS16 48
M_B_A9 85 A8 DQ08 23 M_B_DQ9 place these caps near SODIMM_B 81 VDD2 VSS17 49
M_B_A10 107 A9 DQ09 33 M_B_DQ10 82 VDD3 VSS18 54
M_B_A11 84 A10/AP DQ10 35 M_B_DQ11
near SODIMM_B C10US03V4 87 VDD4 VSS19 55
M_B_A12 83 A11 DQ11 22 M_B_DQ12 88 VDD5 VSS20 60
M_B_A13 119 A12/BC# DQ12 24 M_B_DQ13 93 VDD6 VSS21 61
M_B_A14 80 A13 DQ13 34 M_B_DQ14 C577 + 94 VDD7 VSS22 65
A14 DQ14 C553 C535 C499 C547 C522 C497 VDD8 VSS23
R574 TP_A15_DIMM_B 78 36 M_B_DQ15 C330U2V5POS 99 66
DNI
A15 DQ15 39 M_B_DQ16 100 VDD9 VSS24 71
R1%10KS02 DQ16 VDD10 VSS25
109 41 M_B_DQ17 105 72
GND 11 M_B_BS0 108 BA0 DQ17 51 106 VDD11 VSS26 127
M_B_DQ18
11 M_B_BS1 79 BA1 DQ18 53 GND 111 VDD12 VSS27 128
M_B_DQ19
11 M_B_BS2 BA2 DQ19 VDD13 VSS28
114 40 M_B_DQ20 112 133
12 M_CS#_B0 S0# DQ20 VDD14 VSS29
121 42 M_B_DQ21 117 134
12 M_CS#_B1 S1# DQ21 VDD15 VSS30
101 50 M_B_DQ22 118 138
12 CLK_MEM_DDRB0_P 103 CK0 DQ22 52 123 VDD16 VSS31 139
M_B_DQ23
12 CLK_MEM_DDRB0_N CK0# DQ23 VDD17 VSS32
V3.3_S5 102 57 M_B_DQ24 V3.3_S5 124 144
12 CLK_MEM_DDRB1_P CK1 DQ24 VDD18 VSS33
104 59 M_B_DQ25 145
12 CLK_MEM_DDRB1_N 73 CK1# DQ25 67 199 VSS34 150
M_B_DQ26
R632 12 M_CKE_B0 74 CKE0 DQ26 69 VDDSPD VSS35 151
M_B_DQ27
R1%10KS02 12 M_CKE_B1 115 CKE1 DQ27 56 C658 C653 77 VSS36 155
M_B_DQ28
11 M_B_CAS# CAS# DQ28 C100N02V16 C2U2S03V6 NC1 VSS37
110 58 M_B_DQ29 122 156
11 M_B_RAS# 113 RAS# DQ29 68 125 NC2 VSS38 161
M_B_DQ30
11 M_B_WE# WE# DQ30 over temperature alarm NCTEST VSS39
SA0_DIMM_B 197 70 M_B_DQ31 162
SA1_DIMM_B 201 SA0 DQ31 129 M_B_DQ32 GND 198 VSS40 167
SA1 DQ32 12,20,30 DDR_VREF 12,20 TS#_DIMM_AB EVENT# VSS41
202 131 M_B_DQ33 30 168
16,18,20,23 SMB_CLK SCL DQ33 C565 C574 12,20 DDR3_DRAMRST# RESET# VSS42
200 141 M_B_DQ34 172
16,18,20,23 SMB_DATA SDA DQ34 143 C100N02V16 C2U2S03V6 VSS43 173
M_B_DQ35
R630 116 DQ35 130 M_B_DQ36 1 VSS44 178
12 M_ODT_B0 120 ODT0 DQ36 132 GND 126 VREF_DQ VSS45 179
R1%10KS02 M_B_DQ37
12 M_ODT_B1 ODT1 DQ37 VREF_CA VSS46
140 M_B_DQ38 184
11 M_B_DM[7..0] DQ38 VSS47
M_B_DM0 11 142 M_B_DQ39 2 185
DM0 DQ39 C446 C453 VSS1 VSS48
M_B_DM1 28 147 M_B_DQ40 3 189
GND DM1 DQ40 C100N02V16 C2U2S03V6 VSS2 VSS49
M_B_DM2 46 149 M_B_DQ41 8 190
M_B_DM3 63 DM2 DQ41 157 M_B_DQ42 9 VSS3 VSS50 195
NOTE: DM3 DQ42 VSS4 VSS51
SO-DIMM_B SPD address is 0xA4 M_B_DM4 136 159 M_B_DQ43 13 196
M_B_DM5 153 DM4 DQ43 146 M_B_DQ44 GND 14 VSS5 VSS52
SO-DIMM_B TS address is 0x34 DM5 DQ44 VSS6
M_B_DM6 170 148 M_B_DQ45 19 V0.75_S3
M_B_DM7 187 DM6 DQ45 158 M_B_DQ46 20 VSS7 GND
DM7 DQ46 160 M_B_DQ47 25 VSS8 203
12 DQ47 163 M_B_DQ48 26 VSS9 VTT1 204
11 M_B_DQS0_P DQS0 DQ48 VSS10 VTT2
29 165 M_B_DQ49 31 C667 C670 C657 C666
11 M_B_DQS1_P 47 DQS1 DQ49 175 ! 32 VSS11
M_B_DQ50 LAYOUTNOTE42
11 M_B_DQS2_P DQS2 DQ50 VSS12
64 177 M_B_DQ51 place these caps near Command 37 G1 C1US02
11 M_B_DQS3_P 137 DQS3 DQ51 164 38 VSS13 G1 G2
M_B_DQ52 V1.5_SYS_MEM and Control signals of SODIMM_B
11 M_B_DQS4_P DQS4 DQ52 VSS14 G2
154 166 M_B_DQ53 43
11 M_B_DQS5_P DQS5 DQ53 VSS15
171 174 M_B_DQ54
11 M_B_DQS6_P 188 DQS6 DQ54 176 M_B_DQ55 <ERP_KEM_DEG>
11 M_B_DQS7_P DQS7 DQ55 GND ! LAYOUTNOTE43
10 181 M_B_DQ56 C505 C561 C507 C554
11 M_B_DQS0_N DQS#0 DQ56
27 183 M_B_DQ57 C100N02V16 place these caps close
11 M_B_DQS1_N DQS#1 DQ57 GND
45 191 M_B_DQ58 to VTT1 and VTT2
62 193 M_B_DQ59
11 M_B_DQS3_N 135 DQS#3 DQ59 180 M_B_DQ60
11 M_B_DQS4_N 152 DQS#4 DQ60 182 GND
M_B_DQ61
11 M_B_DQS5_N 169 DQS#5 DQ61 192 M_B_DQ62
186 194 M_B_DQ63
<ERP_KEM_DEG>

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED DDR3 SO-DIMM B
PROD. APP.
PCA212268-2-1 1/1 1/1 21 62
! LAYOUTNOTE44 Gigabit Ethernet PHY V1.8_LAN_SW_M
place caps close to LAN PHY

(82567 has internal termination) V3.3_S5 V3.3_LAN_M
U10 R15
C81 PCIE_GBE0_TX_C_P 52 26 R528 R1%0R0S02
18 PCIE_GBE0_RX_P GLAN_TXP MDI_N_0 GBE0_MDI0_N 2,42,43
C82 PCIE_GBE0_TX_C_N 53 27 R1%0R0S02
18 PCIE_GBE0_RX_N GLAN_TXN MDI_P_0 GBE0_MDI0_P 2,42,43
C100N02V16 C383 C437 C400 C430
55 22 R665 placeholder for
2,42,43 GBE0_CTREF
18 PCIE_GBE0_TX_P GLAN_RXP MDI_N_1 GBE0_MDI1_N 2,42,43 LCB47R03 or similar C10US03V4
56 23 C100N02V16
18 PCIE_GBE0_TX_N GLAN_RXN MDI_P_1 GBE0_MDI1_P 2,42,43
C35
R1%33R2S02 20 C1NS02
45 MDI_N_2 21 GBE0_MDI2_N 2,42,43 DNI
R74 CLK_GBE_ICH9_R
17 CLK_GBE_ICH9 JKCLK MDI_P_2 GBE0_MDI2_P 2,42,43 GND
50
17 GBE0_PHY_RSTSYNC JRSTSYNC 16
42 MDI_N_3 17 GBE0_MDI3_N 2,42,43 GND
17 GBE0_PHY_TXD0 JTXD_0 MDI_P_3 GBE0_MDI3_P 2,42,43
17 GBE0_PHY_TXD1
43
44 JTXD_1 3
17 GBE0_PHY_TXD2 JTXD_2 VDDO_33_3 V3.3_LAN_M
V3.3_LAN_M 46
47 VDDO_33_46 28
R68 17 GBE0_PHY_RDX0 48 JRXD_0 AVDD_33_28
2,42,43 GBE0_ACT# 17 GBE0_PHY_RDX1 JRXD_1
49 5 V1.0_LAN_SW_M
R1%0R0S02 R62 17 GBE0_PHY_RDX2 JRXD_2 DVDD_10_5
3
8 V3.3_LAN_M
BOAZ
DNI
R1%10K0S02 DVDD_10_8
BS138 33
DNI DVDD_10_33 38
Q9 DVDD_10_38
BS138
1
PU evtl optional
GBE0_LED_LNK#_ACT 4
2 LED_0 man 11
R508
R1%5K1S02
! LAYOUTNOTE45
2,42,43 GBE0_LINK1000# LED_1 AVDD_18_11 V1.8_LAN_SW_M
not to violate ETXexpr spec 1 14 place at least 13x13mm
2,42,43 GBE0_LINK100#
2
LED_2 AVDD_18_14
3
19 pad for pin4 of TBCP69
V3.3_LAN_M AVDD_18_19 18 1
GND R24 AVDD_18_18
GBE0_RSET15 24 V1.8_LAN_SW_M
RSET AVDD_18_24 25 Q2
R1%4K99S02 TBCP69
2
4
AVDD_18_25 41 C10NS02X7R
R43 AVDD_18_41
R44 GND GBE0_ATEST_P12 54
R1%1K0S02 !
LAYOUTNOTE46
DNI
GBE0_ATEST_N 13 IEEE_TEST_P AVDD_18_54 32 C396 C405
IEEE_TEST_N AVDD_18_32 C55 C436 C425 C429 C401 C399 C398 C397
keep ATEST tracks as short as possible R1%0R0S02 30
GBE0_DIS_REG10 34 AVDD_18_30
DIS_REG10 29 GBE0_CTRL_18
37 CTRL18 31 GBE0_CTRL_10 C10US03V4 C100N02V16
18,35 PM_LAN_RST# LAN_DISABLE_N CTRL10
R53
GND
DNI
R1%1K0S02 GBE0_BOAZ_TEST_EN 36 51
TEST_EN RESERVED_NC
JTAG_TRST
! LAYOUTNOTE47
JTAG_TDO
JTAG_TMS
JTAG_TCK
CLK_ETH_25M_X2 9
JTAG_TDI
GND XTAL2 R39 !
R55 10 57 LAYOUTNOTE48 place caps close to LAN PHY
Y1 CLK_ETH_25M_X1 XTAL1 GND_PAD place at least 13x13mm
R1%10K0S02 R1%5K1S02
3
pad for pin4 of TBCP69
Q25M0SMDF_BS 1
GND
25M_50PPM U82567_GBEPHY V1.0_LAN_SW_M
GND C62 C56 Q10
35
40
39
7
6
C27PS02 C27PS02 TBCP69
2
4
R56
DNI
DNI
DNI
DNI
R1%1K02S02
GND C419 C410 C421 C80 C420
V3.3_LAN_M V1.0 regulator STUFF NO STUFF
! LAYOUTNOTE49 Internal R219 R218, R221,Q10
R54
R67
R57
place XTAL close to LAN PHY External(default) R218, R221,Q10 R219 C10US03V4 C100N02V16
GND
less than 19MM
GND
R1%200RS02
BIOS SPI FLASH JIDA EEPROM

V3.3_S5
SOCKETED SPI0_HOLD# R455

Note: SKT_U54A (SMT) and SKT_U54B (thru-hole)
3.3k
use a dual footprint and only one can NI
physically be populated at a time. SKT_U54A SKT_U54B V3.3_S5
SKT_CHUPOND_AP-ACA SKT_ENPLAS_OTS
1 16 1 16
HOLD SCK HOLD SCK
2 15 2 15 SPI1_HOLD# R412
VCC SI VCC SI
3.3k V3.3_S0
SPI_SKT_P3 3 14 SPI_SKT_P14 SPI_SKT_P3 3 14 SPI_SKT_P14 U48
U54 NC_P3 NC_P15 C835 NC_P3 NC_P15 S4 U_AT25DF641
1
SPI_EEPROM SPI_SKT_P4 4 13 SPI_SKT_P13 100nF SPI_SKT_P4 4 13 SPI_SKT_P13 SHUNT 1 16
NC_P4 NC_P14 NC_P4 NC_P14 JP4 HOLD SCK
1032-2071 JUMPER NI
NI SPI_SKT_P5 5 12 SPI_SKT_P12 SPI_SKT_P5 5 12 SPI_SKT_P12 2 15 R131
DNI
NC_P5 NC_P13 NC_P5 NC_P13 VCC SI R1%10K0S02 V3.3_S0
2
SPI_SKT_P6 6 11 SPI_SKT_P11 SPI_SKT_P6 6 11 SPI_SKT_P11 3 14 NI
NC_P6 NC_P12 NC_P6 NC_P12 C803 NC_P3 NC_P15 U22
7 10 7 10 100nF 4 13 6 8
CE VSS CE VSS NC_P4 NC_P14 17,35 I2C_CLK_INT 5 SCL VCC
R409
8 9 8 9 5 12 17,35 I2C_DATA_INT SDA
3.3k NI
SO WP SO WP NC_P5 NC_P13 3 C903
NI R772 0 Ohm 6 11 2 A3 7 100nF
GND GND NC_P6 NC_P12 A1 WP
N_ICH_JIDA 1 4
R773 0 Ohm SPI_CE_A# 7 10 A0 GND
18 SPI_CS0# CE VSS NI U24C04-A
R456 GND GND
SPI_SO_R 8 9 R130
18 SPI_SO SO WP
15.0 R1%0R0S02
GND
NI R774 0 Ohm
NI R404 SPI1_WP#
GND
18 SPI_CS1# R775 0 Ohm SPI_CE_B# 3.3k
GND
18 SPI_SI
18 SPI_CLK
SPI_BIOS_WP# R722 2K SPI0_WP# R416 3.3k
2^,59 SPI_BIOS_WP#
GND
NI R723 2K V3.3_S5
D1000 D1001 D1002 D1003 D1004 D1005

2 2 2 2 2 2 PERTAINING TO THE ARTICLE SHOWN ON THIS
TECHNOLOGIES
3 3 3 3 3 3 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
C1000 C1001 C1002 C1003 C1004 C1005 SAME IS PROECTEDTO THE EXTENT PERMITTED TITLE
1 1 1 1 1 1 100nF 100nF 100nF 100nF 100nF 100nF UNDER THE LAWS OF THE UNITED STATES AND ENGR.
ENG. APP.
BAT54SW BAT54SW BAT54SW BAT54SW BAT54SW BAT54SW CONFIDENCE AND IS NOT TO BE COPIED,
REPRODUCED, REVEALED TO OR APPROPRIATED Gigabit Ethernet 1, SPI BIOS
PROD. APP.
JIDA EEPROM
MATL. APP.
PCA212268-2-1 1/1 1/1 22 62
Fan Control
VCC12 V3.3_S0
R401 R408
0 0
NI VCC12
2
V3.3_S0 V3.3_S0
PF1
POLY_FUSE
1.5A
1036-4695
1
1
2
V3.3_S5 V3.3_S0 1812
V3.3_S0 VCC12
3
R399 R400 VCORE D32
0 0 U38 BAT54SW D33 D59
3
1
2
NI UADT7475 R403 R402 1035-5790 BAT54SW BAT54C
14 R382 R386 R389 R395 R381 10k 10k 1035-5790 231-005
VCCP
VCC_ADT7475 3 10k 10k 10k 10k 10k NI NI NI
VCC
2
18,35 PM_THRM# R380 0 9 D31 D28
THERM#/TACH4/GPIO/SMBALERT#
C270 BAT54SW BAT54SW
3
100nF 8 PM_THERMDA_CPU 13 1035-5790 1035-5790 CPU Fan
8 PM_THERMDC_CPU 12 D1+
13 PM_THERMDA_GMCH
11 D1- 6 FAN_1_TACH_B R385 0 FAN_1_TACH_A R387 221 J15
13 PM_THERMDC_GMCH 10 D2+ TACH1 7 TACH2_PU FAN_1_GND 1
D2- TACH2 4
FAN_2_TACH_B R388 0 FAN_2_TACH_A R390 221 FAN_V12 2
TACH3
16 FAN_1_TACH 3
16,18,20,21 SMB_DATA
1 SDA 15 FAN_1_PWM_A R410 221 FAN_1_PWM 4
16,18,20,21 SMB_CLK SCL PWM1/XTO 5
SMB_ALERT_A#
PWM2/SMBALERT# 8
2 FAN_2_PWM_A R383 221 1032-4207
GND PWM3
2,35,42,44,55,57 OTEMP# NI R384 0
2
4
1032-2577
12,35 TSATN# NI R372 0 R407 R406 1 Q28
4.7k 4.7k NDT3055L R639
NI NI 1035-5312 0
3
NI
Enclosure Fan
R375 0 For 3-wire J14

18 SMB_ALERT# fans, install FAN_2_GND 1
NI R376 0 FETs and FAN_V12 2
12 PM_EXT_TS0# remove jumpers. FAN_2_TACH 3
FAN_2_PWM 4
1032-4207
2
4
1 Q23
NDT3055L R638
1035-5312 0
3
NI

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Fan Controller
PROD. APP.
PCA212268-2-1 1/1 1/1 23 62
5 4 3 2 1
D D
V1.2_PATA_S0 V3.3_S0
U100
IC_88SA8052B1
56 44
41 VDD_3 VDDIO_2 4
9 VDD_2 VDDIO_1
C911 C912 C913 C914 C915 VDD_1 C916 C917 C918
2.2uF 0.1uF 0.1uF 0.1uF 2.2uF 0.1uF 0.1uF 2.2uF
V3.3_S0
C111 0.01uF FB57

17 SATA_TX4_P
29 V3.3_PATA_S0_A 1 2
C110 0.01uF SATA_TX4_C_P 27 VAA2 24
17 SATA_TX4_N RX+ VAA1
SATA_TX4_C_N 28 10-Ohms@100MHz
RX- C919 C920 C921 C922
SATA_RX4_C_P 32 0.01uF 0.1uF 0.001uF 2.2uF
C910 0.01uF SATA_RX4_C_N 31 TX+
C 17 SATA_RX4_P TX- C
C909 0.01uF V3.3_S0 AGND_SATA_A AGND_SATA_A AGND_SATA_A AGND_SATA_A
17 SATA_RX4_N
NI R792 10k SATA_A_T8 52 16
T8 H_RESET# IDE_RESET# 2,25,26,35,47
NI NI NI R793 10k SATA_A_T7 40
R834 R835 R794 10k SATA_A_T6 39 T7
T6 IDE_A_D[15..0] 26
49.9 49.9 NI R795 10k SATA_A_T5 38
NI R797 10k SATA_A_T4 36 T5 61 IDE_A_D15
SATA - PATA BRIDGE (STD)

NI R796 10k SATA_A_T3 37 T4 H_DD[15] 63 IDE_A_D14
R798 10k SATA_A_T2 35 T3 H_DD[14] 1 IDE_A_D13
Must be placed with no stubs to TX4 traces. T0 H_DD[11] 10 IDE_A_D10
H_DD[10] IDE_A_A[2..0] 2,26,59
12 IDE_A_D9
V3.3_S0 H_DD[9] 14 IDE_A_D8 IDE_A_D7
H_DD[8] 15 IDE_A_D7
H_DD[7] IDE_A_CS#[3..1] 26
NI R801 10k CNFG2_A 20 13 IDE_A_D6
R802 10k CNFG1_A 19 CNFG2 H_DD[6] 11 IDE_A_D5 R804
R803 10k CNFG0_A 18 CNFG1 H_DD[5] 7 IDE_A_D4 10k
CNFG0 H_DD[4] 5 IDE_A_D3
H_DD[3] 2 IDE_A_D2
NI R853 10k LDO_A_EN 42 H_DD[2] 64 IDE_A_D1
V3.3_S0 LDO_EN H_DD[1] 62 IDE_A_D0
H_DD[0] V3.3_S0
UAI_A 43 49 IDE_A_A2
TP35 UAI H_DA[2]
UAO_A 45 51 IDE_A_A1
TP36 UAO H_DA[1] 50
R806 IDE_A_A0
H_DA[0] R805
10k
47 IDE_A_CS#3 4.7K
H_CS1# 48 IDE_A_CS#1
ATAIOSEL_A 21 H_CS0#
ATAIOSEL 54
H_DMACK# IDE_A_DMA_ACK# 26
3
59 IDE_A_IOW_R# R847 0
H_DIOW# IDE_A_IOW# 2,59
17 58
12,17,25,35 ICH_PLTRST# RST# H_DIOR# 55 IDE_A_IOR# 26
Q83
H_IORDY IDE_A_IORDY 26
1 2N7002 60
B 2,26,55,57 CD_DET1# C923 H_DMARQ 53 IDE_A_DMA_REQ 26 B
H_INTRQ IDE_A_INTRQ 26
SATA_XTL_IN_A 22
2
XTLIN/OSC 46 IDE_A_PDIAG# V3.3_S0

H_PDIAG#
2
22pF R808 R809

AGND_SATA_A Y5 NI FB58 5.6k 10k
20MHz R851 30 1 2 NI
1032-4474 10MEG VSS2 25 R841
C924 VSS1 10-Ohms@100MHz 10k
1
SATA_XTL_OUT_A 23 AGND_SATA_A
XTLOUT
22pF 57
AGND_SATA_A GND_2 8
R810 6.04k SATA-PATA_ISET_A 26 GND_1
ISET 65 R807
GND_PAD
10k
AGND_SATA_A 981-167

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED SATA - PATA Bridge A
PROD. APP.
PCA212268-2-1 1/1 1/1 24 62
5 4 3 2 1
5 4 3 2 1
D D
V1.2_PATA_S0 V3.3_S0
U102
IC_88SA8052B1
56 44
41 VDD_3 VDDIO_2 4
9 VDD_2 VDDIO_1
C927 C928 C929 C930 C931 VDD_1 C932 C933 C934
2.2uF 0.1uF 0.1uF 0.1uF 2.2uF 0.1uF 0.1uF 2.2uF
V3.3_S0
C942 0.01uF FB59

17 SATA_TX5_P
29 V3.3_PATA_S0_B 1 2
C941 0.01uF SATA_TX5_C_P 27 VAA2 24
17 SATA_TX5_N RX+ VAA1
SATA_TX5_C_N 28 10-Ohms@100MHz
RX- C935 C936 C937 C938
SATA_RX5_C_P 32 0.01uF 0.1uF 0.001uF 2.2uF
C944 0.01uF SATA_RX5_C_N 31 TX+
C 17 SATA_RX5_P TX- C
C943 0.01uF V3.3_S0 AGND_SATA_B AGND_SATA_B AGND_SATA_B AGND_SATA_B
17 SATA_RX5_N
NI R813 10k SATA_B_T8 52 16
T8 H_RESET# IDE_RESET# 2,24,26,35,47
NI NI NI R814 10k SATA_B_T7 40
R838 R839 R815 10k SATA_B_T6 39 T7
T6 IDE_B_D[15..0] 26
49.9 49.9 NI R816 10k SATA_B_T5 38
NI R818 10k SATA_B_T4 36 T5 61 IDE_B_D15
SATA - PATA BRIDGE (STD)

NI R817 10k SATA_B_T3 37 T4 H_DD[15] 63 IDE_B_D14
R819 10k SATA_B_T2 35 T3 H_DD[14] 1 IDE_B_D13
Must be placed with no stubs to TX5 traces. T0 H_DD[11] 10 IDE_B_D10
H_DD[10] IDE_B_A[2..0] 2,26,59
12 IDE_B_D9
V3.3_S0 H_DD[9] 14 IDE_B_D8 IDE_B_D7
H_DD[8] 15 IDE_B_D7
H_DD[7] IDE_B_CS#[3..1] 26
NI R822 10k CNFG2_B 20 13 IDE_B_D6
R823 10k CNFG1_B 19 CNFG2 H_DD[6] 11 IDE_B_D5 R824
R825 10k CNFG0_B 18 CNFG1 H_DD[5] 7 IDE_B_D4 10k
CNFG0 H_DD[4] 5 IDE_B_D3
H_DD[3] 2 IDE_B_D2
NI R854 10k LDO_B_EN 42 H_DD[2] 64 IDE_B_D1
V3.3_S0 LDO_EN H_DD[1] 62 IDE_B_D0
H_DD[0] V3.3_S0
UAI_B 43 49 IDE_B_A2
TP37 UAI H_DA[2]
UAO_B 45 51 IDE_B_A1
TP38 UAO H_DA[1] 50
R827 IDE_B_A0
H_DA[0] R826
10k
47 IDE_B_CS#3 4.7K
H_CS1# 48 IDE_B_CS#1
ATAIOSEL_B 21 H_CS0#
ATAIOSEL 54
H_DMACK# IDE_B_DMA_ACK# 26
3
59 IDE_B_IOW_R# R848 0
H_DIOW# IDE_B_IOW# 2,59
17 58
12,17,24,35 ICH_PLTRST# RST# H_DIOR# 55 IDE_B_IOR# 26
Q84
H_IORDY IDE_B_IORDY 26
1 2N7002 60
B 2,26,55,57 CD_DET2# C939 H_DMARQ 53 IDE_B_DMA_REQ 26 B
H_INTRQ IDE_B_INTRQ 26
SATA_XTL_IN_B 22
2
XTLIN/OSC 46 IDE_B_PDIAG# V3.3_S0

H_PDIAG#
2
22pF R829 R830

AGND_SATA_B Y6 NI FB60 5.6k 10k
20MHz R852 30 1 2 NI
1032-4474 10MEG VSS2 25 R842
C940 VSS1 10-Ohms@100MHz 10k
1
SATA_XTL_OUT_B 23 AGND_SATA_B
XTLOUT
22pF 57
AGND_SATA_B GND_2 8
R831 6.04k SATA-PATA_ISET_B 26 GND_1
ISET 65 R828
GND_PAD
10k
AGND_SATA_B 981-167

Bally
A BALLY TECHNOLOGIES, INC A
D. LEBLANC 4/14/2011 6601 SOUTH BERMUDA ROAD
TECHNOLOGIES LAS VEGAS, NEVADA 89119
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED SATA - PATA Bridge B
PROD. APP.
PCA212268-2-1 1/1 1/1 25 62
5 4 3 2 1
5 4 3 2 1
VCC3.3
CompactFlash
Operating System - Top Side
R51
2.2K
EJ1
J6
GND 50
2^,24,57 CD_DET1#
25
IDE_A_D10 49
IOCS16# 24
IDE_A_D9 48
IDE_A_D2 23
D IDE_A_D8 47 D
IDE_A_D1 22
IDE_A_PDIAG 46 50 25
IDE_A_D0 21
IDE_A_DASP 45
IDE_A_A0 20
44
Top Side View

IDE_A_A1 19
43
IDE_A_A2 18
42
A03 17
41
A04 16 J6 Pad View
24 IDE_A_DMA_ACK# VS2# 40
24 IDE_A_DMA_REQ A05 15 (Normal)
24 IDE_A_IORDY CSEL# 39
A06 14
2,24,25,26,35,47 IDE_RESET# VCC 38
VCC3.3
VCC 13
VCC3.3 37
A07 12
NI R843 10k C57 C406 M_WE# 36
100nF 10uF A08 11
R844 10k 35
A09 10
34 26
1
ATA SEL# 9
24 IDE_A_INTRQ
R849 0 IDE_A_IOWG_R# VS1 33
2,59 IDE_A_IOWG# A10 8
24 IDE_A_IOR#
IDE_A_CS#3 32
IDE_A_CS#1 7
IDE_A_D15 31
IDE_A_D7 6
IDE_A_D14 30
24 IDE_A_CS#[3..1]
IDE_A_D6 5
C IDE_A_D13 29 CF Card C
IDE_A_D5 4
IDE_A_D12 28 25 1
IDE_A_D4 3
IDE_A_D11 27 50 26
IDE_A_D3 2
26
2,24,59 IDE_A_A[2..0] GND 1
24 IDE_A_D[15..0]
50-Pin Normal Ejector Normal
MOLEX
53856-5070
2^,44 ACTIVITY_LED_CATHODE#
3
3
NI
D10 D71
BAT54ALT1G BAT54ALT1G VCC3.3
CompactFlash
2
1
2,17 SATA_ACT#
R515
Game/Personality - Bottom Side
2.2K
EJ2
J26
GND 50
2^,25,57 CD_DET2#
25
IDE_B_D10 49
B B
IOCS16# 24
IDE_B_D9 48
IDE_B_D2 23
IDE_B_D8 47
IDE_B_D1 22
IDE_B_PDIAG 46
IDE_B_D0 21
IDE_B_DASP 45
IDE_B_A0 20
44
Bottom Side View

IDE_B_A1 19
43
IDE_B_A2 18
42
A03 17 SCR1 SCR2
41
A04 16
25 IDE_B_DMA_ACK# VS2# 40
25 IDE_B_DMA_REQ A05 15
25 IDE_B_IORDY CSEL# 39
A06 14 CF Screw CF Screw
2,24,25,26,35,47 IDE_RESET# VCC 38
VCC3.3
VCC 13
VCC3.3 37 NUT1 NUT2
A07 12
NI R845 10k C404 C59 WE# 36
100nF 10uF A08 11
R846 10k 35
A09 10 CF Nut CF Nut
34
ATA SEL# 9
25 IDE_B_INTRQ
R850 0 IDE_B_IOWG_R# VS1 33
2,59 IDE_B_IOWG# A10 8
25 IDE_B_IOR# 32
IDE_B_CS#3
IDE_B_CS#1 7
IDE_B_D15 31 ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE
Bally
A BALLY TECHNOLOGIES, INC A
IDE_B_D7 6 PERTAINING TO THE ARTICLE SHOWN ON THIS
IDE_B_D14 30 SHEET IS THE EXCLUSIVE PROPERTY OF BALLY
D. LEBLANC 4/14/2011 6601 SOUTH BERMUDA ROAD
25 IDE_B_CS#[3..1] TECHNOLOGIES LAS VEGAS, NEVADA 89119
IDE_B_D6 5 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
IDE_B_D13 29 SAME IS PROECTEDTO THE EXTENT PERMITTED TITLE
IDE_B_D5 4 UNDER THE LAWS OF THE UNITED STATES AND ENGR.
IDE_B_D12 28 NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
IDE_B_D4 3 ENG. APP.
IDE_B_D11 27 Compact Flash Connectors
REPRODUCED, REVEALED TO OR APPROPRIATED
IDE_B_D3 2 PROD. APP.
26 BY OTHERS, IN PART OR IN WHOLE, WITHOUT
2,25,59 IDE_B_A[2..0] THE EXPRESS CONSENT OF BALLY. THIS PRINT
GND 1 MATL. APP.
25 IDE_B_D[15..0] IT WILL NOT BE USED IN ANY MANNER
50-Pin Reverse Ejector Reverse Q.A. APP. C PCA212268-2-1 A
MOLEX DETRIMENTAL TO THE INTEREST OF BALLY, AND
53927-5019 MUST BE RETURNEDTO BALLY ON DEMAND. ORCAD FILE DWG. SCALE PLOT SCALE SHEET OF
PCA212268-2-1 1/1 1/1 26 62
5 4 3 2 1
5 4 3 2 1
V3.3_S0 V3.3_S0
FB43
PLLVCCFB
120 OHM @ 100MHz V3.3_DAC
1
500mA C438
C422 C434 C427 C402 C435 C449 C450 10uF
100nF 10nF 1nF 10nF 10nF 100nF 100nF X5R 16V
1
V3.3_S0 V3.3_S0 0805
C411 C424 C414
100nF 100nF 100nF
2
CRT2_RED 2,42,45
1
NI
R521 R514 C403 C442 C443
10k 0 1nF 10nF 100nF U11
CRT2_GREEN 2,42,45
1
ADV7125
LVDS_VDD_EN# R516 0 NI C432 C431 C433 13
10nF 10nF 10nF 29 VAA1
CRT2_BLUE 2,42,45
2
VAA2
3
D U14 30 D
1 Q38 V3.3_S0 DS90CF388A VAA3
12 LVDS_VDD_EN 13 8 41
2N7002 TTL_R0
NI 23 VCC1 R10 9 TTL_R1 42 R0
2
33 VCC2 R11 10 TTL_R2 43 R1

45 VCC3 R12 11 TTL_R3 44 R2
56 VCC4 R13 12 TTL_R4 45 R3
R71 R52 66 VCC5 R14 14 TTL_R5 46 R4
0 0 VCC6 R15 15 TTL_R6 47 R5
81 R16 17 TTL_R7 48 R6
93 LVDSVCC1 R17 R7
DS90_PD#
LVDSVCC2 18 TTL_G0 3 V3.3_S0 V3.3_S0
DS90_R_FDE
2 G10 19 TTL_G1 4 G0 34
DS90_PLLSEL
PLLVCC1 G11 20 TTL_G2 5 G1 IOR 33
NI NI 75 G12 21 TTL_G3 6 G2 IOR
R65 R42 74 CNTLE/NC G13 22 TTL_G4 7 G3 32
CNTLF/NC G14 G4 IOG
1
10k 10k 24 TTL_G5 8 ADV7125 31 C456 C455 NI C457 C458
78 G15 26 TTL_G6 9 G5 Video DAC IOG 100nF 100nF U17 100nF 100nF
77 PD G16 27 TTL_G7 10 G6 28 74ABT16374
2
5 R_FDE G17 G7 IOB 27
PLLSEL 28 TTL_B0 16 IOB 7 31
99 B10 29 TTL_B1 17 B0 18 VCC1 VCC3 42
12 LVDS_A_DATA0_N 98 A0M B11 30 18 B1 VCC2 VCC4
TTL_B2 0 R541 TTL_VSYNC TTL_HSYNC R537 0
12 LVDS_A_DATA0_P A0P B12 31 19 B2
R45 100 TTL_B3 R28 R29 R30
97 B13 32 TTL_B4 20 B3 150 150 150 47 36
12 LVDS_A_DATA1_N A1M B14 B4 D0 D8
96 34 TTL_B5 21 NI 0 R540 VSYNC_DLY_1 2 13 HSYNC_DLY_1 R547 0 NI
12 LVDS_A_DATA1_P A1P B15 36 22 B5 O0 O8
R520 100 TTL_B6
95 B16 37 TTL_B7 23 B6 46 35
12 LVDS_A_DATA2_N A2M B17 B7 D1 D9
94 NI 0 R552 VSYNC_DLY_2 3 14 HSYNC_DLY_2 R536 0 NI
12 LVDS_A_DATA2_P A2P O1 O9
R46 100 70 TTL_VSYNC NI R525 0 DAC_BLANK# 11
90 VSync 71 TTL_HSYNC DAC_COMP_SYNC 12 BLANK 1 44 33
12 LVDS_A_DATA3_N 89 A3M Hsync SYNC GND1 2 5 D2 D10 16
NI 0 R539 VSYNC_DLY_3 HSYNC_DLY_3 R546 0 NI
12 LVDS_A_DATA3_P A3P DS90CF388A GND2 O2 O10
R47 100 69 TTL_DE R770 33 DAC_CLK 24 14
87 LVDS Receiver DE CLOCK GND3 15 43 32
12 LVDS_B_DATA0_N 86 A4M 42 1 2 100nF 35 GND4 25 6 D3 D11 17
TTL_CLK V3.3_DAC C61 DAC_COMP NI 0 R551 VSYNC_DLY_4 HSYNC_DLY_4 R535 0 NI
12 LVDS_B_DATA0_P A4P CLKOUT COMP GND5 O3 O11
R518 100 U99 V3.3_S0 DAC_VREF 36 26
C 85 73 V3.3_S0 NC7SZ86 DAC_RSET 37 VREF GND6 39 41 30 C
12 LVDS_B_DATA1_N A5M STOPCLK RSET GND7 D4 D12
84 1 5 DS90_STOPCLK# 38 40 NI 0 R538 VSYNC_DLY_5 8 19 HSYNC_DLY_5 R545 0 NI
12 LVDS_B_DATA1_P A5P A VCC PSAVE GND8 O4 O12
1
R48 100 38
83 R20 39 C902 1032-4288 40 29
12 LVDS_B_DATA2_N A6M R21 D5 D13
82 40 2 100nF NI 0 R550 VSYNC_DLY_6 9 20 HSYNC_DLY_6 R534 0 NI
12 LVDS_B_DATA2_P
2
R517 100 A6P R22 41 B O5 O13
80 R23 43 38 27
12 LVDS_B_DATA3_N 79 A7M R24 46 3 4 11 D6 D14 22
DAC_CLK_A NI 0 R549 VSYNC_DLY_7 HSYNC_DLY_7 R544 0 NI
12 LVDS_B_DATA3_P A7P R25 GND Y O6 O14
R49 100 47
R527 0 LVDS_CLK_N 92 R26 48 1015-2777 37 26
12 LVDS_A_CLK_N 91 CLKM R27 12 D7 D15 23
R531 0 LVDS_CLK_P NI 0 R548 VSYNC_DLY_8 HSYNC_DLY_8 R543 0 NI
12 LVDS_A_CLK_P CLKP 49 O7 O15
R519 100
NI R526 0 1 G20 50
12 LVDS_B_CLK_N PLLGND1 G21
NI R530 0 3 51 R771 33 SH_REG_CLK 48 4
12 LVDS_B_CLK_P PLLGND2 G22 52 25 CP1 GND1 10
76 G23 53 CP2 GND2 15
88 LVDSGND1 G24 55 NI NI GND3 21
100 LVDSGND2 G25 57 U13 V3.3_S0 U95 V3.3_S0 V3.3_S0 1 GND4 28
LVDSGND3 G26 58 NC7SZ86 NC7SZ86 24 OE1 GND5 34
4 G27 1 5 1 5 OE2 GND6 39
GND1 A VCC A VCC GND7
1
6 59 NI NI 45
7 GND2 B20 60 C76 V3.3_S0 C439 R542 GND8
16 GND3 B21 61 2 100nF 2 100nF 0
2
25 GND4 B22 62 B B
35 GND5 B23 64
44 GND6 B24 65 3 4 3 4
54 GND7 B25 67 GND Y GND Y
63 GND8 B26 68 1015-2777 1015-2777
72 GND9 B27 V3.3_S0 V5.0_S0
CRT2_HSYNC_A
CRT2_VSYNC_A
GND10 R64
1032-2592 0 R23 0 NI 0 R22
V3.3_S0
1
C392 C46
R512 1k 100nF 100nF
U5
2
D50 8 1
B VCCB VCCA B
V5.0_S0 U3 V3.3_DAC AD1580
1
1
3 2 C409 30.1 R25 CRT2_HSYNC_B 7 B1 A1 2CRT2_HSYNC_O 30.1 R37
Vin Vout1 3 CRT2_HSYNC 2,42,45
C13 1uF
1
100nF 6.6V X5R 2
2
1 4 R7 0402
GND Vout2 0 V3.3_S0 1.225V 30.1 R34 CRT2_VSYNC_B 6 B2 A2 3CRT2_VSYNC_O 30.1 R12
TAB CRT2_VSYNC 2,42,45
2
1032-4298
LD1117AS33 DIR 5
R507 560 4
GND
1
C30 R523
10uF 10k U74LVC2T45VSSOP
16V X5R
2
0805
3
DS90_STOPCLK 1 Q39 V3.3_S0 V5.0_S0

2N7002 NI
R522
2
R26 R31 R14 R10
1
2.21k 2.21k 2.21k 2.21k
2 3
12 LVDS_DDC_CLK CRT2_DDC_CLK 2,42,45
Q4
BSS138LT1
241-036
1
2 3
12 LVDS_DDC_DATA CRT2_DDC_DATA 2,42,45
Q5
A BSS138LT1 ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE A
241-036 PERTAINING TO THE ARTICLE SHOWN ON THIS
TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED LVDS/Analog Video Bridge
PROD. APP.
Secondary Analog Video Port: Max THE EXPRESS CONSENT OF BALLY. THIS PRINT MATL. APP.
resolution limited to WXGA IS LOANED ONLY AND RECIPIENT COVENANTS DWG. SIZE DWG. NO. REV.
(1366x768@60Hz), giving max dot IT WILL NOT BE USED IN ANY MANNER Q.A. APP.
clock (pixel clock) of 85 MHz
PCA212268-2-1 1/1 1/1 27 62
5 4 3 2 1
Voltage Regulator for V3.3_S5
TP15
rnd_1mm
V3.3_S5
L1
U25
L25IHLP1R5A9_KOMBI
D15 R184
1 10 R164
D_DFLS230L C125 C220N03_25V RT_V3.3_S5
BD RT
C126 R1%47KS02 R1%102KS02
BOOST_V3.3_S5 2 9
BOOST V_C
V5.0_S5 GND C220N03_25V GND
V3.3_S5_SW 3 8 FB_V3.3_S5
SW FB R182
R181
4 7 BIAS_V3.3_S5 R1%165KS02
V_IN BIAS
GND_PAD
R1%0R0S02
+ C146 C141 C134 5 6 PG_V3.3_S5_R
C132 RUN/SS PG C120 C123
100uF 10uF 10uF
RUN_V3.3_S5
C1US05V25 C22US05V6 C1U02V6
35V 35V
ULT3481DFN10
GND GND
11
R191
S6 support BOM option R167 R189 R190 R1%10K0S02
DNI
NI R187 DNI R1%100KS02 R1%19K1S02 R1%0R0S02 R1%0R0S02
35 EN_V5.0_V3.3_S5
from CPLD R183 R1%100KS02
V5.0_S5 PG_V3.3_S5 35
C129 C124 to CPLD
C131
C220PS02X7R C100PS02X7R
C220NS03_X5R
GND
voltage Regulator for V1.5_S0 Voltage Regulator for V1.2_PATA_S0

TP19
rnd_1mm
V1.5_S0
V3.3_S0
L2
L25IHLP1R5A9_KOMBI
D18 U29
D_DFLS230L V3.3_S0
C176 R283 R286
C220N03_25V 1 10 RT_V1.5_S0
BD RT V3.3_S0
C175 R1%47KS02 R1%102KS02
BOOST_V1.5_S0 2 9
BOOST V_C GND
V_IN_12 GND C220N03_25V 3 8
V1.5_S0_SW FB_V1.5_S0 R287 C925
SW FB R1%19K1S02 R811
R285 1uF, 16V
4 7 BIAS_V1.5_S0 R812 U101 10k V1.2_PATA_S0
V_IN BIAS
GND_PAD
C206 C193 10k 1032-4024

C184 R1%0R0S02 C164
+ C220 10uF 10uF 5 6 PG_V1.5_S0_R
C1US05V25 RUN/SS PG C22US05V6 C169
100uF 35V 35V 3 4
RUN_V1.5_S0
C1U02V6 VIN VOUT

1 6
GND_PAD
EN_V3.3_V1.5_V1.05_S0 V1.2_PATA_EN V1.2_PATA_PG
ULT3481DFN10 EN PG C926
GND R296
11
R290 R291 2 5 1uF, 16V

DNI
GND R1%100KS02 GND NC

R284 R1%0R0S02 R1%0R0S02
R288 R1%1K0S02 R1%19K1S02
29,35 EN_V3.3_V1.5_V1.05_S0
from CPLD MIC5248
PG_V1.5_S0 35
7
V5.0_S5 R289 DNI
R1%100KS02
to CPLD
C171 C170
C185
C220PS02X7R C100PS02X7R
C220NS03_X5R
GND
TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED VREG V3.3_S5, V1.5_S0,
PROD. APP.
V1.2_PATA_S0
MATL. APP.
PCA212268-2-1 1/1 1/1 28 62
power regulator for V1.05_S0 and V1.05_M
V5.0_S5
C735
C716 C736 C715 C1U02V6 C691
Rton on V5.0_S5 not causes any problems V5.0_S5 C100N02V16 C100N02V16 C1U02V6 C1U02V6
on functionality or quality of SC416
R670 V_IN_DUAL_DDR3
V3.3_S5 AGND_SC416 GND
R1%499KS02 U33
(25)
TON_USC416 10 3 D21
TON VDD1 16 DMBRM130LT
C221 VDD2
R666 C330PS02 C203 C675 C188 C678 + C190
R309 C183
R1%10K0S02 2 BST1_USC416 BST1_USC416_R 10uF 10uF 10uF 10uF 100uF
BST1 C100NS03V25
35V 35V 35V 35V
AGND_SC416 R1%0R0S02
5
6
7
8
PG_V1.05_M PG_V1.05_M 22 C216
35 PG_V1.05_M PGD1 TP18
PG_V1.05_S0 21 C100N02V16
PGD2 GND rnd_1mm
Q53
C218 5 24 R310 4
DH1_USC416 DH1_USC416_R UBSC042N03S
C100N02V16 V1.05_M 34,35 EN_V1.05_V3.3_M 14 EN1 DH1
28,35 EN_V3.3_V1.5_V1.05_S0 EN2 R1%0R0S02
C330U2V5POS
L3
1
2
3
7 1 LX1_+V1.05_S0 V1.05_M
AGND_SC416 VOUT1 LX1 L25IHLP4R7A5
5
6
7
8
V3.3_S5 C214 C217 23 ILIM1_USC416 R312
C100N02V16 R314 C22PS02 ILM1 + + +
DNI R1%8K25S02 D20
R1%4K02S02 Q52
R313 R308 D10BQ60 C179 C180 C178
FB1_USC416 8 4 DL1_USC416 DL1_USC416_R 4 UBSC042N03S
FB1 DL1 C174 C173 C172
R672 R1%10KS02 R1%0R0S02
R1%10K0S02
AGND_SC416
1
2
3
C10US05V16
PG_V1.05_S0 V5.0_S5
35 PG_V1.05_S0 V1.05_S0 GND
C222
C100N02V16
12
VOUT2 V_IN_GFX
C739
C232 C228 C226 D23
C1U02V6
C100N02V16 C100N02V16 R320 C22PS02 DMBRM130LT (26)
AGND_SC416 DNI
DNI
R1%4K02S02
FB2_USC416 11 17 BST2_USC416 R323 BST2_USC416_R
FB2 BST2 GND + C256
C745 C238 C235 C749
R319 R1%0R0S02 TP24
5
6
7
8
C231 C263 10uF 10uF 10uF 10uF 100uF
AGND_SC416 R1%10KS02 rnd_1mm
C100N02V16 C100NS03V25 35V 35V 35V 35V
Q62
19 DH2_USC416 R321 DH2_USC416_R 4 UBSC042N03S
DH2
R1%0R0S02 GND
SS1_USC416 6 C330U2V5POS
L7
1
2
3
SS2_USC416 13 SS1 18 LX2_+V1.05_S0
SS2 LX2 V1.05_S0
C215 C230 L25IHLP4R7A5
5
6
7
8
C1U02V6 C10NS02 25 20 ILIM2_USC416 R318
GND (PAD) ILM2 + + +
R1%8K25S02 D27
Q66
9 15 R322 4 D10BQ60 C257 C759 C252 C239 C744 C233
DL2_USC416 DL2_USC416_R UBSC042N03S
STARPOINT2 RTN (AGND) DL2
R1%0R0S02
USC416
1
2
3
C10US05V16
GND AGND_SC416 GND
power regulator for V1.8_S3 (LVDS)
V1.8_S3 V3.3_S5
V3.3_S5
U21
1 8
VIN VOUT R138
R1%10K0S02
2 7
35 EN_V1.8_S3 EN POR
from CPLD PG_V1.8_S3 35
CBYP 3 6
CBYP NC C115 to CPLD
R139
CPOR 4 5 C1U02V6
R1%10K0S02 CPOR GND 9 because of internal 100k pullup
C114 C116 GND_PAD high level will be ca 3.16V
C1U02V6 C100N02V16 C117
UISL9001A ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE
GND
C10NS02
GND
TECHNOLOGIES
GND ENGR.
UNDER THE LAWS OF THE UNITED STATES AND
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Regulators V1.05_S0, V1.05_M
PROD. APP.
PCA212268-2-1 1/1 1/1 29 62
Protection (OVP/UVP/discharge) R433
OVP Discharge SKIP# (Pulse Skipping Enable) R1%10K0S02
SKIP#_VDDR
R442 Enabled Enabled R660 Enabled (Default) ! LAYOUTNOTE53 V_IN_DUAL
None Enabled Disabled R661 Disabled V_IN_DUAL_DDR3 place caps close to FET
R445 Disabled Enabled AGND_DDR
R434 <insert 2nd line here>
DNI
R450 Disabled Disabled (24) L8
R1%10K0S02
AVDD_VDDR
L25IHLP1R5A9
C322 + C269
REF_VDDR C307 C305 C312 C809 C820 C813
C1U02V6
C302 10uF 10uF 10uF 10uF 10uF 10uF 100uF
R437 C842 V5.0_S5 C100NS03V25 35V 35V 35V 35V 35V 35V
DNI
C839
R1%10K0S02 C220N02V10 SS_VDDR
AGND_DDR
R739 R740
DNI
C4N7S02 R734
R1%10K0S02 R1%10K0S02
AGND_DDR
R442 R1%10RS02 GND
DDR_SHDNB#
D35
3
REF_VDDR R1%0R0S02 C317 1 DBAT54A
2
28
25
17
26
22
AGND_DDR C10US05V16
3
U56
R453 R452 R454 BST_VDDR_R TP29
DNI
DNI
TPO
VIN
AVDD
VDD
SS
REF
SKIP#
GND
5
6
7
8
R1%10K0S02 R1%10K0S02 R1%100KS02 C314 rnd_1mm
R421 C220N03
ILIM_VDDR 4 20 BST_VDDR
ILIM BST Q68 V1.5_SYS_MEM
R1%0R0S02
TON_VDDR 1 18 DH_VDDR_R DH_VDDR 4 UBSC042N03S
TON DH L11
2 19 R426 C1U02V6
OVP_VDDR LX_VDDR C22US05V6
51
62
73
OVP/UVP LX
8
L50IHLPR82A25
Switching Frequency R450 27 21
DDR_SHDNB# DL_VDDR_R
R451 600kHz
DNI
SHDN# UMAX8632 DL C805 C804 + +
Q67
R446 450kHz R1%0R0S02 7 23 R425 4 C279 C282 C793
R448 R447 R449 DL_VDDR UBSC042N03S D36
DNI
DNI
none (default) 300kHz R1%10K0S02 R1%10K0S02 R1%23K7S02 STBY# PGND1 D10BQ60 C799 C801
R1%0R0S02
R443 200kHz 5 15
GND
1
2
3
V3.3_S5 POK1 FB AVDD_VDDR
6 16 C10US03V4 C330U2V5POS
AGND_DDR POK2 OUT GND
VTTREF
R424
PGND2
DNI
!
VTTR
R1%10K0S02 LAYOUTNOTE54
VTTS
GND
VTTI
34,35 EN_V1.5_S3
TAB
VTT
FB_VDDR place caps close to inductor L14
R738 in the order shown here
R737 R1%10K0S02 R427
10
24
29
11
12
14
13
R1%10K0S02 R1%11K3S02 R428
35 PG_V1.5_S3 R1%10K0S02
C328
C100N02V16
GND AGND_DDR
AGND_DDR C319 DNI C315

R731 C10US03V4 C100N02V16
VTTR_VDDR R423
VTT_MAX8632
12,20,21 DDR_VREF
R1%22R1S02
R1%0R0S02
C321
C1U02V6 GND
VTTREF_VDDR
C316 diodes to secure the maximum ratings
C100N02V16
of the switching pins of MAX8632
V0.75_S3
AGND_DDR
DNI
BST_VDDR1 2DH_VDDR_R
R446 LX_VDDR D66
3
LRZ1206 DBAT54A
! LAYOUTNOTE55 C320 C832 1

BST_VDDR DNI
2 DL_VDDR_R
place starpoint in exposed pad (TAB pin) STARPOINT4 C10US03V4 C10US03V4
in the middle of UMAX8632 footprint C323 D67
3
C10US03V4 DBAT54A
AGND_DDR GND
GND
! LAYOUTNOTE56
place diodes close to U22
and 50A design for VCORE_S0

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Regulator V1.5_SYS_MEM
PROD. APP.
DDR3
MATL. APP.
PCA212268-2-1 1/1 1/1 30 62
V_IN_GFX V_IN_12
L6
+ C245 L25IHLP1R5A9
C250 C223 C761 C731
C219 10uF 10uF 10uF 10uF 100uF
C100NS03V25 35V 35V 35V 35V
GND
VREF_VR_GFX V5.0_S5
R301
R1%90K9S02
C690 D60
3
C1NS02 C186 DBAT54A
HYS_VR_GFX 1 2
C1U02V6
20
R300 C202 U30
AGND_GFX GND DNI C224 TP23
R306 R1%110KS02 C100PS02
V5
R292 C182 C2N2S02 rnd_1mm
R1%90K9S02 8 24 BST_VR_GFX_R BST_VR_GFX
VREF BST
5
6
7
8
R1%0R0S02 C1US03V16 VCCGFXCORE
Q17 R316
DNI
AGND_GFX R293
6 23 TG_VR_GFX_R TG_VR_GFX UBSC042N03S R1%22R6S02
HYS TG 4 L4
C680 R1%0R0S02
R305
C100PS02
R1%110KS02 CLSET_VR_GFX 7 22 DRN_VR_GFX
C225 L25IHLP1R0A11
51
62
73
CLSET DRN
8
+
DNI C2N2S02 C177 C189 C187
AGND_GFX 16 21 R294 Q18 C330U2V5POS C10US03V4 C1US05V25
RAMP_VR_GFX BG_VR_GFX_R BG_VR_GFX
RAMP BG UBSC042N03S
4 D25
R1%0R0S02 R317
D10BQ60
DNI
R1%22R6S02
C204 R663 GND
V3.3_S0 R297 R1%10K0S0218 15 CS_VR_GFX_P
C1NS02 R299 R1%16K2S02
1
2
3
PGD CS+
R1%10K0S02 35 PG_MCH_GFX_VR GND R659 CS_VR_GFX_P_R
GFX_VR_EN 17 14 CS_VR_GFX_N R1%249RS02 V1.05_S0
EN CS- R654
R653 C707 C692 R295
DNI
R1%18K2S02
R1%249KS02 C100PS02 LRZ1206
AGND_GFX 1 13 C22NS02
MCH_GFX_VID4 FB_VR_GFX_P R652
VID4 FB+ R1%249RS02
C681
2 11 VCCGFXCORE C100PS02
MCH_GFX_VID3 FB_VR_GFX_N Shunt R601 should be
VID3 FB- ! LAYOUTNOTE57 capable to support 8-9A
R781 R1%0R0S02 place parts close to U12 and route
18,34,35 PM_SLP_S3# DNI R307 AGND_GFX
MCH_GFX_VID2 3 10 ERROUT_GFX ERROUT_GFX_R C210 VREF_VR_GFX differential without stubs at Caps
VID2 ERROUT R651
R1%8K06S02 C207 C560PS02
R302 R1%10R0S02
R782 R1%0R0S02 MCH_GFX_VID1 4 19
12,35 MCH_GFX_VR_EN VID1 PMON C47PS02
R1%10R0S02 C208
C100PS02
R298 MCH_GFX_VID0 5 12 SS_USC472B
VID0 SS
AGND
100K
GND
AGND_GFX
C689 VCC_AXG_SENSE_P 13
R303
USC472B C10NS02 VSS_AXG_SENSE_N 13
9
GND 25 R1%10R0S02
R304
AGND_GFX C700
R1%10R0S02
C100PS02
12 MCH_GFX_VID[4..0] STARPOINT1
AGND_GFX
! LAYOUTNOTE58
AGND_GFX GND
place parts close to U12 and route VCC_AXG_SENSE_P
and VSS_AXG_SENSE_N differential without stubs at C358/C361
diodes to secure the maximum ratings

of the switching pins of SC472B
1
BST_VR_GFX_R DNI 2TG_VR_GFX_R
D61
3
DRN_VR_GFX DBAT54A
DNI
1
BST_VR_GFX_R 2 BG_VR_GFX_R
D58
3
DBAT54A
GND
! LAYOUTNOTE59
place diodes close to U12
and 50A design for VCORE_S0

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Regulator VCCGFXCORE
PROD. APP.
PCA212268-2-1 1/1 1/1 31 62
NI NI NI
C287 C286 C285 C283 C284 C289 C290 C288 C300
10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
35V 35V 35V 35V 35V 35V 35V 35V 35V
V5.0_S5
R685 GND
VCC_5V_MAX8771
V_IN_12
R1%10RS02
C753 C754 C769
C100N02V16 C2U2S03V6 C2U2S03V6 DH1_VR C200 C199 C198 C197 C196 C195 C201 C194
D26 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
DNI DMBRM130LT 35V 35V 35V 35V 35V 35V 35V 35V
L10
GND
L25IHLP1R5A9
19
25
AGND_CORE
U35
GND
VCC
VDD
R343 R364 C260
7 30 BST1_VR V_IN_12_CORE
TIME BST1
5
6
7
8
V_IN_12_CORE R1%71K5S02 NI NI
R1%0R0S02 C220N03 C274 C273
5
6
7
8
C255 9 DNI + C205 + C280 D34
CCV C2N2S02 DNI C2N2S02
C470PS02X7R DNI 100uF 100uF DSMBJ22A
R342 29 DH1_VR 4 SMBJ22CA
DH1 Q27
R1%200KS02 C251 11 R393 4 R392
DNI
DNI
REF UBSC042N03S Q26
C220N02V10 R1%22R6S02 R1%22R6S02 L9
UBSC042N03S
5 1
6 2
7 3
28 LX1_VCCCORE VCORE_PH1
AGND_CORE GND
5 1
6 2
7 3
LX1
8
RTON_VRCORE 8 L50IHLPR82A25
RTON C265 C264
8
DNI
C2N2S02 DNI C2N2S02
10 CPU_VID[6..0] 31 26 4 D29
CPU_VID0 DL1_VR_R
D0 DL1 Q20 4 D10BQ60
R369 R368 LAYOUTNOTE60
DNI
DNI
C258 UBSC042N03S Q19 !
CPU_VID1 32 R1%22R6S02 R1%22R6S02
C100N02V16 UBSC042N03S
1
2
3
D1 make 35A design for phase1
1
2
3
DNI
CPU_VID2 33 27 values of R531 and R542 and 50A design for VCORE_S0
D2 low < 0.33V PGND1 will change if just 1 phase
high > 0.67V GND
CPU_VID3 34 R363 or another CPU is used
DNI
D3 GND
R1%0R0S02
CPU_VID4 35 TP25
D4 16 R330 R360 rnd_1mm
CS1_VR_R2_P CS1_VR_R1_P
CSP1
2
4
CPU_VID5 36
D5 R1%100RS02 R1%0R0S02
LAYOUTNOTE61 R347 R346
Shunt
DNI
37 C248 C241 ! VCORE
CPU_VID6 R1%0R0S02 R1%1MR12
D6 C2N2S02 C2N2S02 R329
route CS1_VR_x_P, CS12_VR_N and CS2_VR_x_P
35 EN_VCORE_S0 R1%10RS02
1
3
DNI
R365 10k 38 differential and as short as possible
from CPLD SHDN 15 CS12_VR_R_N
CSN12
AGND_CORE
2
4
+ C246 + C262
12 PM_DPRSLPVR_MVP C249 R328
39 C242 values of R536 and R543 R334 R338 330u 330u
Shunt
DNI
8 PSI# DPRSLPVR C2N2S02 R1%10RS02 will change if just 1 phase
C2N2S02 R1%0R0S02 R1%1MR12 2.5 V 2.5 V
V3.3_S0 NI DNI R1%100RS02 or another CPU is used
C261 R332
1
3
V3.3_S0 R366 14 CS2_VR_R2_P R327 CS2_VR_R1_P
C2N2S02 CSP2
DNI R1%100KS02 D24 DMBRM130LT V5.0_S5
DNI R1%0R0S02 GND
DH2_VR
20 R335
R361 BST2_VR V_IN_12_CORE (+ at page 10: 4x C330U2V5POS)
AGND_CORE BST2
5
6
7
8
5
6
7
8
R684 R1%10K0S02 3 C247
DNI
PSI R1%0R0S02 C211 C2N2S02

R1%10K0S02 C220N03 R326
DNI
DNI DNI C2N2S02 C209 DNI C276 C275 C212 C213
2 R1%0R0S02
35 PG_VCORE_S0 PWRGD 21 4 4
to CPLD DH2_VR Q13 C10US05V16
DH2 Q14 C1US05V25
PHASEGD_CORE 17
PHASEGD UBSC042N03S UBSC042N03S GND
R315
DNI
DNI
R344 R311
1
2
3
1
2
3
VCC_5V_MAX8771 THRM_VRCORE 6 R1%22R6S02
C752 DNI THRM R1%22R6S02
C2N2S02 R1%18K2S02 22 L5
C259 LX2_VCCCORE VCORE_PH2
RT1 LX2
T
C1N0S02_X7R L50IHLPR82A25
R5%470KS02NTC
5
6
7
8
5
6
7
8
DNI
AGND_CORE C229 C227
R705
DNI C2N2S02 DNI C2N2S02
R1%10K0S02 AGND_CORE D22
V3.3_S0
24 DL2_VR_R 4 4
R700 DL2 Q15 Q16 D10BQ60
VRHOT# 5 R324
DNI
35 EC_VRHOT# DNI
VRHOT UBSC042N03S UBSC042N03S
R1%22R6S02
DNI
R1%0R0S02 C254
1
2
3
1
2
3
C2N2S02 DNI
4 23 R325
! LAYOUTNOTE62 POUT PGND2
place R276,R336 R345 R1%22R6S02
and Q66 without stub R1%0R0S02
GND GND
V3.3_S0
R698
R1%68R1S02
V1.05_S0 R677 ! LAYOUTNOTE63
13 VSSSENSE_R
R367 GNDS place parts close to UMAX8771 and route VCCSENSE_x
8 H_PROCHOT# C236 R1%100RS02
R1%2K21S02 and VSSSENSE_x differential without stub at C390/C392/C477 LAYOUTNOTE64
to CPU C1N0S02_X7R diodes to secure the maximum ratings !
18
TMMBT3904 GND
2
1 of the switching pins of MAX8771 place diodes close to U13

Q61 18,35 VR_PWRGD_CLKEN# CLKEN AGND_CORE
V1.05_S0 1 to ICH & CPLD and 50A design for VCORE_S0
R339 R331 VSSSENSE 10
MMBT3904 12 VCCSENSE_R2 VCCSENSE_R1
R693 FB VCCSENSE 10
R1%2K37S02 C237 BST1_VR 1 DNI 2DH1_VR BST2_VR1 DNI 2 DH2_VR
R1%2K21S02 R1%100RS02
3
40
8,12,17 H_DPRSTP# DPRSTP R333 C4N7S02
D65 D62
DNI
R686 R1%100RS02
3
V3.3_S0 LX1_VCCCORE DBAT54A LX2_VCCCORE DBAT54A
C240
GND_BACK
R1%10K0S02 AGND_CORE VCORE

VCCSENSE_RC C4N7S02
DNI
DNI DNI
VCC3.3 10 C253 C470PS02X7R R341 R1%20K0S02 BST1_VR 1 2 DL1_VR_R BST2_VR1 2 DL2_VR_R
CCI
35 CPLD_PROCHOT#
R340 R1%0R0S02 D64 D63
3
DNI
to CPLD UMAX8771 DBAT54A DBAT54A
41
GND GND
C181
100nF
GND
STARPOINT3
High-speed bypass caps for H_DPRSTP#

where the return plane transitions
between VCC3.3 and DGND. AGND_CORE GND
LAYOUTNOTE65
!
place starpoint close to UMAX8771
VCCSENSE_x and VSSSENSE_x differential

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Regulator VCORE
PROD. APP.
PCA212268-2-1 1/1 1/1 32 62
Generation of V3.3_RTC Vin Voltage Power Good Switches for V_IN_DUAL_12_S3
V_IN_DUAL
V3.3_S5 TP26
rnd_1mm
V3.3_S5 TP16 V_IN_12 V_IN_12 V5.0_S5 TP17 TP20
rnd_1mm rnd_1mm rnd_1mm
V5.0_S5 V_IN_12
V3.3_G3_RTC R374 R373 R397 V_IN_5.0_S5_TO_V_IN_12
1
to RTCpin@ICH9M R371 R396 R1%10K0S02 R1%10K0S02 R1%10K0S02

D30 Q22A Q22B
R1%51K1S02 R1%75K0S02 U37
3 7 UBSO303P UBSO303P
6
D17 1 8 8 1 3 5
VCC3 COMP3
R1%100KS02
DMMDB1204 2 7
R1%51K1S02
TP31 VCC5 COMP5 PG_V5.0_S5 35 D_DFLS230L
3 6 to CPLD C272
2
rnd_1mm 4 VCCA RST# 5 over 8.5V (real 7,4V) 1uF

C266 GND COMPA PG_V_IN_12 35
DNI
R370
R394
R379 to CPLD 16V
C10PS02
4
3
R1%10K0S02 ULTC1727 SMT
V_BAT R391 C267 C908
R1%11K8S02 C10PS02 10nF Q21
R221 from ETXexpress Over_18.5V 1 BS138
connector R398
R1%1K0S02 V3.3_S5 R1%51K1S02
2
GND
GND
3
R378
R1%33K2S02
Q25
1 BS138
2
3
GND
Q24
1 BS138
35 SW_S0_S3
from CPLD
2
R377
R1%10K0S02
GND
GND

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED V5.0_S5, V_IN_12 Power Good,
PROD. APP.
V_IN_DUAL
MATL. APP.
PCA212268-2-1 1/1 1/1 33 62
VCORE V1.05_S0 V1.5_S0 V1.8_S3 V3.3_S0 V5.0_S0
R647 R674 R648 R655 R668 R673

R1%47R02 R1%470R02 R1%47R02 R1%47R02 R1%100R02 R1%100R02
3
Q54 Q60 Q55 Q56 Q57 Q59
1 2N7002 1 2N7002 1 2N7002 1 2N7002 1 2N7002 1 2N7002
V5.0_S5
2
GND GND GND GND GND GND
R669
R1%10K0S02
V0.75_S3
3
V1.5_SYS_MEM
Q58
R657 1 2N7002
18,31,35 PM_SLP_S3# DNI
R1%0R0S02 R707 R708
V1.05_M V3.3_S5
R1%100R02 R1%100R02
2
R656 V3.3_S5
2,35,53 PM_SLP_S3_EXT#
R1%0R0S02 GND
3
R559 R572
R1%47R02 R1%470R02 R558 V5.0_S5 Q63 Q64
R1%100R02 1 2N7002 1 2N7002
3
R713
2
3
R1%10K0S02
Q44 Q49
GND GND
V5.0_S5 1 2N7002 1 2N7002 Q40
1 2N7002 PM_SLP_S4_DIS
2
3
2
R582
R704
R1%10K0S02 Q65
R568 R1%0R0S02 1
GND GND GND 2N7002
R1%100KS02 18,35 PM_SLP_S4# DNI
30,35 EN_V1.5_S3
2
R703
3
R562 R1%0R0S02
R702
35 EN_V3.3_WOL_M# DNI
Q48 R1%0R0S02 R1%0R0S02
R567 1 2N7002
18,35 PM_SLP_M# DNI
3
R1%0R0S02
GND
2
R569 Q43
29,35 EN_V1.05_V3.3_M
R1%0R0S02 1 2N7002
18,35 LAN_WOL_EN
GND
2
GND

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Discharge Switches
PROD. APP.
PCA212268-2-1 1/1 1/1 34 62
TLC3702 CPLD
R150 DNI 0 6
-
7 R154 DNI 0
R146 0 5 + V3.3_S5
DNI U23B
UTLC3702 D13
GND DBAT54A
Unused Gate
G3
G9
CPLD_TDI_CON1 2
C8
C4
E9
E3
J4
J8
C448 C461 C462 V3.3_S5
U20 GND
C2U2S03V6 C100N02V16 C100N02V16
CPLD_TDI
VCCINT
VCCINT
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
33
CPLD_TCK K1
TCK D52 DNI
R1%10K0S02
R1%10K0S02
CPLD_TDI J2 V3.3_S0 2 1
R1%1K0S02
TDI R80 CPLD_TDI_ICH 18
NI R81 R1%0R0S02 CPLD_TDO K2
18 CPLD_TDO_ICH TDO GND R1%2K00S02
CPLD_TMS J1 DBAT54A
R1%0R0S02 TMS
1 2
=GPIO10 R115
R72
R73
R82
R83
SUS_PWR_ACK_GPIO B1 L3 IDE_RESET# 2,24,25,26,47
1
CPLD_TMS_CON 2
18 SUS_PWR_ACK IO_B1_0 IO_B1_19
R158 47k D16 C2 K4 D12
18 ICH_GPIO8_CPLD
3
V3.3_S5 DBAT54C
active in S5
C1 IO_B1_1 IO_B1_20 L4 CPLD_TMS DBAT54A CPLD_TDI
29 PG_V1.05_M
33
V3.3_S5 D3 IO_B1_2 IO_B1_21 K5 DELAY_VR_PWRGOOD 12 CPLD_TMS
active in S5 18 DNI
ICH_GPIO14_CPLD D2 IO_B1_3 IO_B1_22 L5 ICH_PLTRST# 12,17,24,25 D512 1 CPLD_TDO
8,18 SYS_RESET# D1 IO_B1_4 IO_B1_23 L6 PM_S4_STATE# 18 CPLD_TMS_ICH 18
CPLD_TCK
2,36,42,44 EXT_SYS_RESET# IO_B1_5 IO_B1_24 PM_LAN_RST# 18,22
8
R144 TLC3702
ca. 120Hz
E2 J5 DBAT54A
2,36,37,47 CB_RESET# IO_B1_6 GNDINT GND
2.2k 2 F2 K6
-
1 R141 18 CLK_SUS_32K E1 IO_B1_7/GCLK0 IO_B1_26 J7 PM_SLP_S4# 18,34 1 2
CPLD_CLK CPLD_TCK_CON
IO_B1_8/GCLK1 VCCINT V3.3_S5
3 + R1%0R0S02 F1 J6 D14
U23A 2,18,47 PM_SUS_STAT# IO_B1_9 IO_B1_28 EXT_THRMTRIP# 2,17
G1 L7 CPLD_TCK DBAT54C
18,31,34 PM_SLP_S3# CPLD_PROCHOT# 32
33
C118 UTLC3702 G2 IO_B1_10 IO_B1_29 K7 DNI
C119 18 PM_SLP_S5# SW_S0_S3 33 D532
4
R142 F3 IO_B1_11 IO_B1_30 L8 1

DNI C100NS03 18,34 PM_SLP_M# H1 IO_B1_12 DEV_OE/IO_B1_31 K8 CPLD_PWRBTN# 18 CPLD_TCK_ICH 18
6.2k
GND 2,34,53 PM_SLP_S3_EXT# IO_B1_13 #DEV_CLR/IO_B1_32 EXT_PWRBTN# 2,36,48,53
H3 L9 DBAT54C
31 PG_MCH_GFX_VR IO_B1_14 IO_B1_33 EXT_PWR_OK 2,42,44,52,53,55,58,59
C100PS03 H2 K9
18 PM_RSMRST# L1 IO_B1_15 IO_B1_34 L10 VR_PWRGD_CLKEN# 18,32
GND 18 PM_ICH_PWROK IO_B1_16 IO_B1_35 CL_PWROK 12,18
L2 K10
29 PG_V1.05_S0 IO_B1_17 IO_B1_36 EN_V3.3_WOL_M# 34
K3 L11
33 PG_V_IN_12 IO_B1_18 IO_B1_37 MCH_GFX_VR_EN 12,31
12,23 TSATN# NI R98 0 J10 B9 I2C_CLK_EXT

J11 IO_B2_0 IO_B2_21 A9 I2C_DATA_EXT
2,53,59 SOFT_PWR_OFF
NI R777 0 H9 IO_B2_1
IO_B2_2
IO_B2_22
IO_B2_23
B8
EN_V1.5_S3 30,34
CPLD Programming Interface
H10 A8
18,34 LAN_WOL_EN IO_B2_3 IO_B2_24 EN_V1.8_S3 29
2,23,42,44,55,57 OTEMP# R100 0 H11 B7
G10 IO_B2_4 IO_B2_25 A7 EN_V3.3_V1.5_V1.05_S0 28,29
WDTO_PIC# J9
IO_B2_5 IO_B2_26 EN_V1.05_V3.3_M 29,34 R86
PIC_RST# F9 C6 1 V3.3_S5_CON V3.3_S5
R102 R1%0R0S02 F10 IO_B2_6 IO_B2_27 B6 2 CPLD_TDI_CON
CPLD PUs / PDs 16 CLK_PCI_CPLD_33M G11 IO_B2_7/GCLK2 IO_B2_28 C7 EN_V5.0_V3.3_S5 28 3 R1%0R0S02
V3.3_S5 2,17,47 LPC_AD[3..0] 18,23 PM_THRM# CPLD_PM_THRM# CPLD_TCK_CON
F11 IO_B2_8/GCLK3 VCCINT A6 V3.3_S5 4
LPC_AD0 CPLD_TMS_CON
E11 IO_B2_9 IO_B2_30 C5 EN_VCORE_S0 32 5
LPC_AD1 CPLD_TDO
IO_B2_10 GNDINT GND
R95 PM_SLP_S3_EXT# LPC_AD2 E10 A5 6 MCCI_DATA_OUT
D9 IO_B2_11 IO_B2_32 B5 PG_VCORE_S0 32 7
R1%10K0S02 LPC_AD3 MCCI_DATA_IN
IO_B2_12 IO_B2_33 PG_V5.0_S5 33
R99 SYS_RESET# 2,17,47 LPC_FRAME# D11 A4 PM_PSON# 8 MCCI_RST
R1%10K0S02 D10 IO_B2_13 IO_B2_34 B4 9 MCCI_CLK
2,18,47 LPC_SERIRQ IO_B2_14 IO_B2_35 PG_V3.3_S5 28
V3.3_S0 MCCI_RST C11 A3 CPLD_SPARE_IO_0 R123 0 10 MCCI_INT
MCCI_CLK C10 IO_B2_15 IO_B2_36 B3 CPLD_SPARE_IO_1 R124
DNI
0 11 MCCI_FREEZ
R101 EXT_SYS_RESET# MCCI_DATA_OUT B11 IO_B2_16 IO_B2_37 A2
DNI
12
EXT_PWRBTN# and EXT_SYS_RESET# IO_B2_17 IO_B2_38 PG_V1.8_S3 29
DNI R1%10K0S02 should have no pullups on baseboard MCCI_DATA_IN B10 B2
A11 IO_B2_18 IO_B2_39 A1 PG_V1.5_S3 30
R120 I2C_CLK_EXT EXT_SYS_RESET# has CPLD internal PU MCCI_INT
IO_B2_19 IO_B2_40 PG_V1.5_S0 28 GND
R1%2K21S02 MCCI_FREEZ A10 K11 SM_PWROK_U
R121 I2C_DATA_EXT IO_B2_20 IO_B2_41
R119
GNDINT
GNDINT
R1%2K21S02 R96
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
17,22 I2C_CLK_INT DNI
R1%12K1S02
17,22 I2C_DATA_INT DNI
V3.3_S5 R118 R1%0R0S02 SM_PWROK 12
to support WDT in CPLD to connect I2C_INT and
R79 EXT_PWRBTN# <ERP_KEM_DEG> V3.3_S5 R91
G4
E8
E4
H5
H7
G8
D7
D5
I2C_EXT through CPLD
R1%20K0S02 WDT_R_IRQ# DNI
WDTO_PIC# UEPM570M100 R1%10K0S02
to support the S6 state the EXT_PWRBTN# R109 R1%0R0S02

should be connected to the V3.3_DUAL_S6 ! LAYOUTNOTE67
place R755 into footprint of U17 GND GND
R783
1
near U16 R1%10K0S02 Q81
2N7002
2 3 PS_ON#
PS_ON# 2^,53
Watchdog
V3.3_S0
7,59,60,61,62 PCI_SERR# R581 DNI
R1%100RS02 D54 DBAT54S

1 2 V3.3_S5
DNI DNI C904
100nF
3
to cause a NMI
with the WDT U24
R149 WDT_R_IRQ# 2 1
17 WDT_IRQ# DNI NMI VCC
R1%10K0S02 I2C_CLK_INT 6 3
SCL DNI TRG WDTKICK 18
I2C_DATA_INT 7 4 ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE
V3.3_S0 R159 DNI
WDTO_PIC#
R1%10K0S02
5 SDA
RSTO
RSTI
GND
8
GND
TECHNOLOGIES
W509P113 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
R153 PIC_RST# UNDER THE LAWS OF THE UNITED STATES AND ENGR.
V3.3_S5 DNI
R1%10K0S02 NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
ENG. APP.
R157 EC_PIC_RST#
REPRODUCED, REVEALED TO OR APPROPRIATED CPLD, Watchdog
PROD. APP.
32 EC_VRHOT# DNI BY OTHERS, IN PART OR IN WHOLE, WITHOUT
R1%0R0S02 THE EXPRESS CONSENT OF BALLY. THIS PRINT MATL. APP.
PCA212268-2-1 1/1 1/1 35 62
5 4 3 2 1
VCC3.3 VCC3.3 VCC3.3

TP1
SYS_RESET# 2^,17,35,47 LPC_AD[0..3] LPC_AD[3..0] 2,17,35,47
R591 R594
1
4.7K 4.7K LPC_AD0
R97 LPC_AD1
4.7K LPC_AD2
LPC_AD3
EXCD0_CPPE# 18
D EXCD1_CPPE# 18 D
2^,35,44 EXT_SYS_RESET# EXT_SYS_RESET# 2,35,42,44 2^,17,35,47 LPC_FRAME# LPC_FRAME# 2,17,35,47
2^,35,37,47 CB_RESET# CB_RESET# 2,35,37,47 2^,16,47 LPC_CLK CLK_LPC_33M_EXT 2,16,47
2^,18,35,47 LPC_SERIRQ LPC_SERIRQ 2,18,35,47
GBE0_MDI+0
2^,22,43 GBE0_MDI+0 GBE0_MDI0_P 2,22,42,43
GBE0_MDI-0 2^,18,39,40 SMB_CK
2^,22,43 GBE0_MDI-0 GBE0_MDI0_N 2,22,42,43 SMB_CK 2,18,38,39,40
GBE0_MDI+1 2^,18,39,40 SMB_DAT
2^,22,43 GBE0_MDI+1 GBE0_MDI1_P 2,22,42,43 SMB_DAT 2,18,38,39,40
GBE0_MDI-1
2^,22,43 GBE0_MDI-1 GBE0_MDI1_N 2,22,42,43
GBE0_MDI+2
2^,22,43 GBE0_MDI+2 GBE0_MDI2_P 2,22,42,43
GBE0_MDI-2
2^,22,43 GBE0_MDI-2 GBE0_MDI2_N 2,22,42,43
GBE0_MDI+3 2^,17,49 SATA0_TX+
2^,22,43 GBE0_MDI+3 GBE0_MDI3_P 2,22,42,43 SATA_TX0_P 2,17,49
GBE0_MDI-3 2^,17,49 SATA0_TX-
2^,22,43 GBE0_MDI-3 GBE0_MDI3_N 2,22,42,43 SATA_TX0_N 2,17,49
2^,22,43 GBE0_ACT# GBE0_ACT# 2^,17,49 SATA0_RX+

GBE0_ACT# 2,22,42,43 SATA_RX0_P 2,17,49
2^,43 GBE0_LINK100# GBE0_LINK100# 2^,17,49 SATA0_RX-
GBE0_LINK100# 2,22,42,43 SATA_RX0_N 2,17,49
2^,43 GBE0_LINK1000# GBE0_LINK1000#
GBE0_LINK1000# 2,22,42,43
2^,22,43 GBE0_CTREF GBE0_CTREF
GBE0_CTREF 2,22,42,43 2^,17,49 SATA1_TX+ SATA_TX1_P 2,17,49
2^,17,49 SATA1_TX- SATA_TX1_N 2,17,49
2^,17,49 SATA1_RX+ SATA_RX1_P 2,17,49

2^,18,46 PC_SPEAKER PC_SPEAKER
HDA_SPKR 2,18,46 2^,17,49 SATA1_RX- SATA_RX1_N 2,17,49
2^,17,46 AC_SDOUT AC_SDOUT 2^,17,26 SATA_ACT#

HDA_SDOUT 2,17,46 ATA_LED# 2,17,26
2^,17,46 AC_SDIN0 AC_SDIN0 HDA_SDIN0 2,17,46
2^,17,46 AC_BITCLK AC_BITCLK
HDA_BIT_CLK 2,17,46
2^,17,46 AC_SYNC AC_SYNC VCC5SBY
HDA_SYNC 2,17,46
2^,17,46 AC_RESET# AC_RESET#
HDA_RST# 2,17,46
R78
2^,18,40,41 PCIE_TX+[0..1] 10K
2^,18,40,41 PCIE_TX-[0..1]
PCIE_TX+0 2^,35,53 PWRBTN#
PCIE_TX1_P 2,18,38,40 EXT_PWRBTN# 2,35,48,53
PCIE_TX+1
PCIE_TX2_P 2,18,38,41
PCIE_TX-0
C PCIE_TX1_N 2,18,38,40 C
PCIE_TX-1 2^,35,59 SOFT_PWR_OFF
PCIE_TX2_N 2,18,38,41 SOFT_PWR_OFF 2,35,53,59
2^,18,40,41 PCIE_RX+[0..1]
2^,18,40,41 PCIE_RX-[0..1] 2^,35,44,53,59 PWR_OK EXT_PWR_OK 2,35,42,44,52,53,55,58,59

PCIE_RX+0
PCIE_RX1_P 2,18,38,40
PCIE_RX+1 2^,18,41 WAKE1#
PCIE_RX2_P 2,18,38,41 WAKE1# 2,18,38,41
PCIE_RX-0
PCIE_RX1_N 2,18,38,40
PCIE_RX-1 2^,18,47 BIOS_DISABLE#
PCIE_RX2_N 2,18,38,41 BIOS_DISABLE# 2,17,18,47
2^,23,35,44,57 OTEMP# OTEMP# 2,23,35,42,44,55,57

2^,16,39,40,41 CLK_PCIE+[0..2]
2^,17,35 THRMTRIP# EXT_THRMTRIP# 2,17,35

CLK_PCIE+0
CLK_PCIE0_P 2,16,38,40
2^,16,39,40,41 CLK_PCIE-[0..2] CLK_PCIE+1 2^,34,35,53 SUS_S3#
CLK_PCIE1_P 2,16,38,41 PM_SLP_S3_EXT# 2,34,35,53
CLK_PCIE+2
CLK_PCIE2_P 2,16,38,39
2^,18,35,47 SUS_STAT# PM_SUS_STAT# 2,18,35,47
CLK_PCIE-0
CLK_PCIE0_N 2,16,38,40
CLK_PCIE-1
CLK_PCIE1_N 2,16,38,41
CLK_PCIE-2
CLK_PCIE2_N 2,16,38,39
2^,12,45 VGA_RED CRT_RED 2,12,42,45
2^,12,45 VGA_GRN CRT_GREEN 2,12,42,45
2^,12,45 VGA_BLU CRT_BLUE 2,12,42,45
2^,12,45 VGA_HSYNC CRT_HSYNC 2,12,42,45
2^,12,45 VGA_VSYNC CRT_VSYNC 2,12,42,45
2^,18,39,40 WAKE0# WAKE0#

PCIE_WAKE# 2,18,38,39,40
2^,12,45 VGA_I2C_CLK CRT_DDC_CLK 2,12,42,45
2^,12,45 VGA_I2C_DAT CRT_DDC_DATA 2,12,42,45
2^,27,45 VGA2_I2C_CLK CRT2_DDC_CLK 2,27,42,45

USB_D+[0..5] 2^,27,45 VGA2_I2C_DAT CRT2_DDC_DATA 2,27,42,45
B B
2^,18,43 USB_D+[0..3] USB_D+0 2^,27,45 VGA2_RED

USB0_P 2,18,42,43 CRT2_RED 2,27,42,45
2^,18,48 USB_D+4 USB_D+1 2^,27,45 VGA2_GRN
USB1_P 2,18,42,43 CRT2_GREEN 2,27,42,45
2^,18,48 USB_D+5 USB_D+2 2^,27,45 VGA2_BLU
USB2_P 2,18,42,43 CRT2_BLUE 2,27,42,45
USB_D+3 2^,27,45 VGA2_HSYNC
USB3_P 2,18,42,43 CRT2_HSYNC 2,27,42,45
USB_D+4 2^,27,45 VGA2_VSYNC
USB4_P 2,18,48 CRT2_VSYNC 2,27,42,45
USB_D+5
USB_D-[0..5] USB5_P 2,18,48
VCC5 V5.0_S0
USB_D-0
USB0_N 2,18,42,43
2^,18,43 USB_D-[0..3] USB_D-1
USB1_N 2,18,42,43
2^,18,48 USB_D-4 USB_D-2
USB2_N 2,18,42,43
2^,18,48 USB_D-5 USB_D-3
USB3_N 2,18,42,43
USB_D-4
USB4_N 2,18,48
USB_D-5
USB5_N 2,18,48
VCC3.3 V3.3_S0
2^,18,59 USB_4_5_OC# USB_45_OC# 2,18,59

2^,18,59 USB_2_3_OC# USB_23_OC# 2,18,59
2^,18,59 USB_0_1_OC# USB_01_OC# 2,18,59
VBATT
VCC5SBY V_BAT
V5.0_S5
GND
C338 C339
10uF 10nF

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED ETXe-PC Hierarchy Connections 1
PROD. APP.
PCA212268-2-1 1/1 1/1 36 62
5 4 3 2 1
5 4 3 2 1
2^,17,59,61,62 PCI_AD[0..31] PCI_AD[31..0] 2,17,59,60,61,62
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
2^,24,26,59 IDE_A_A[0..2] IDE_A_A[2..0] 2,24,26,59 PCI_AD4
PCI_AD5
PCI_AD6
IDE_A_A0 PCI_AD7
IDE_A_A1 PCI_AD8
IDE_A_A2 PCI_AD9
PCI_AD10
PCI_AD11
D PCI_AD12 D
2^,24,59 IDE_A_IOW# IDE_A_IOW# 2,24,59
IDE_A_IOWG# 2,26,59 PCI_AD13
2^,26,59 IDE_A_IOWG#
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
2^,25,26,59 IDE_B_A[0..2] IDE_B_A[2..0] 2,25,26,59 2^,59 PCI_IDSEL0 R599 100 PCI_AD20 PCI_AD18
2^,61 PCI_IDSEL1 R605 100 PCI_AD21 PCI_AD19
2^,62 PCI_IDSEL2 R609 100 PCI_AD22 PCI_AD20
IDE_B_A0 PCI_AD21
IDE_B_A1 PCI_AD22
IDE_B_A2 PCI_AD23
PCI_AD24
PCI_AD25
2^,25,59 IDE_B_IOW# IDE_B_IOW# 2,25,59 PCI_AD26
IDE_B_IOWG# 2,26,59 PCI_AD27
2^,26,59 IDE_B_IOWG#
PCI_AD28
PCI_AD29
PCI_AD30
2^,24,25,26,35,47 IDE_RESET# IDE_RESET# 2,24,25,26,35,47 PCI_AD31
2^,17,59,61,62 PCI_C/BE0# PCI_C/BE0# 2,17,59,60,61,62

2^,17,59,61,62 PCI_C/BE1# PCI_C/BE1# 2,17,59,60,61,62
2^,17,59,61,62 PCI_C/BE2# PCI_C/BE2# 2,17,59,60,61,62
2^,17,59,61,62 PCI_C/BE3# PCI_C/BE3# 2,17,59,60,61,62
2^,17,35,59,61,62 PCI_SERR# PCI_SERR# 2,17,35,59,60,61,62
2^,17,59,61,62 PCI_PERR# PCI_PERR# 2,17,59,60,61,62
2^,17,59,61,62 PCI_PAR PCI_PAR 2,17,59,60,61,62
2^,12,39 PEG_+TX[0..15] 2^,17,59,61,62 PCI_DEVSEL# PCI_DEVSEL# 2,17,59,60,61,62

2^,17,59,61,62 PCI_FRAME# PCI_FRAME# 2,17,59,60,61,62
2^,17,59,61,62 PCI_IRDY# PCI_IRDY# 2,17,59,60,61,62
PEG_+TX0 2^,17,59,61,62 PCI_TRDY# PCI_TRDY# 2,17,59,60,61,62
C PEG_TX_0_P 2,12,38,39 C
PEG_+TX1
PEG_TX_1_P 2,12,38,39
PEG_+TX2 2^,17,59 PCI_IRQA# INT_IRQB# 2,17,59
PEG_TX_2_P 2,12,38,39
PEG_+TX3 2^,17,61 PCI_IRQB# INT_IRQC# 2,17,60,61
PEG_TX_3_P 2,12,38,39
PEG_+TX4 2^,17,62 PCI_IRQC# INT_IRQD# 2,17,60,62
PEG_TX_4_P 2,12,38,39
PEG_+TX5
PEG_TX_5_P 2,12,38,39
PEG_+TX6 2^,16,60 PCI_CLK
PEG_TX_6_P 2,12,38,39 CLK_PCI_33M_EXT 2,16,60
PEG_+TX7
PEG_TX_7_P 2,12,38,39
PEG_+TX8 2^,17,59,61,62 PCI_STOP# PCI_STOP# 2,17,59,60,61,62
PEG_TX_8_P 2,12,38,39
PEG_+TX9
PEG_TX_9_P 2,12,38,39
PEG_+TX10 2^,18,47 PCI_CLKRUN# PM_CLKRUN# 2,18,47
PEG_TX_10_P 2,12,38,39
PEG_+TX11
PEG_TX_11_P 2,12,38,39
PEG_+TX12
PEG_TX_12_P 2,12,38,39
PEG_+TX13
PEG_TX_13_P 2,12,38,39
PEG_+TX14
PEG_TX_14_P 2,12,38,39
PEG_+TX15 VCC3.3
PEG_TX_15_P 2,12,38,39
2^,12,39 PEG_-TX[0..15] VCC3.3

R94
C89
4.7K 10nF
PEG_-TX0 R240
PEG_TX_0_N 2,12,38,39
PEG_-TX1 U18 4.7K
PEG_TX_1_N 2,12,38,39
1
5
PEG_-TX2
PEG_TX_2_N 2,12,38,39
PEG_-TX3
PEG_TX_3_N 2,12,38,39
PEG_-TX4 2^,47,58,59,61,62 BUF_PCI_RESET# 4 2 PCI_RST# 17
PEG_TX_4_N 2,12,38,39
PEG_-TX5
PEG_TX_5_N 2,12,38,39
PEG_-TX6
PEG_TX_6_N 2,12,38,39
PEG_-TX7 NC7SZ125
PEG_TX_7_N 2,12,38,39
3
PEG_-TX8
PEG_TX_8_N 2,12,38,39
PEG_-TX9
PEG_TX_9_N 2,12,38,39
PEG_-TX10
PEG_TX_10_N 2,12,38,39
PEG_-TX11 R790 0 Ohm
PEG_TX_11_N 2,12,38,39
PEG_-TX12
PEG_TX_12_N 2,12,38,39
PEG_-TX13 2^,39,40,41 PCIE_RESET#
PEG_TX_13_N 2,12,38,39
PEG_-TX14
PEG_TX_14_N 2,12,38,39
PEG_-TX15 NI R791 0 Ohm CB_RESET# 2,35,36,47
PEG_TX_15_N 2,12,38,39
B B
2^,12,39 PEG_+RX[0..15] VCC12_AUX
PEG_+RX0 V_IN_12
PEG_RX_0_P 2,12,38,39
PEG_+RX1
PEG_RX_1_P 2,12,38,39
PEG_+RX2
PEG_RX_2_P 2,12,38,39
PEG_+RX3
PEG_RX_3_P 2,12,38,39
PEG_+RX4 C818 C819 C814 C815 C808 C807 C827 C828
PEG_RX_4_P 2,12,38,39 10nF
PEG_+RX5 10uF 10uF 10nF 10uF 10uF 10nF 10nF
PEG_RX_5_P 2,12,38,39
PEG_+RX6
PEG_RX_6_P 2,12,38,39
PEG_+RX7
PEG_RX_7_P 2,12,38,39
PEG_+RX8
PEG_RX_8_P 2,12,38,39
PEG_+RX9
PEG_RX_9_P 2,12,38,39
PEG_+RX10
PEG_RX_10_P 2,12,38,39
PEG_+RX11
PEG_RX_11_P 2,12,38,39
PEG_+RX12
PEG_RX_12_P 2,12,38,39
PEG_+RX13
PEG_RX_13_P 2,12,38,39
PEG_+RX14
PEG_RX_14_P 2,12,38,39
PEG_+RX15
PEG_RX_15_P 2,12,38,39
2^,12,39 PEG_-RX[0..15] C234 C746 C762 C791 C748 C755 C792

10uF 10uF 10uF 10uF 10nF 10nF 10nF
PEG_-RX0
PEG_RX_0_N 2,12,38,39
PEG_-RX1
PEG_RX_1_N 2,12,38,39
PEG_-RX2
PEG_RX_2_N 2,12,38,39
PEG_-RX3
PEG_RX_3_N 2,12,38,39
PEG_-RX4
PEG_RX_4_N 2,12,38,39
PEG_-RX5
PEG_RX_5_N 2,12,38,39
PEG_-RX6
PEG_RX_6_N 2,12,38,39
PEG_-RX7
PEG_RX_7_N 2,12,38,39
PEG_-RX8
PEG_RX_8_N 2,12,38,39
PEG_-RX9 C693 C313 C679 C708 C306 C816 C677
A PEG_RX_9_N 2,12,38,39 10nF 10nF A
PEG_-RX10 10uF 10uF 10uF 10nF 10nF ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE
PEG_-RX11
PEG_-RX12
PEG_RX_10_N
PEG_RX_11_N
PEG_RX_12_N
2,12,38,39
2,12,38,39
2,12,38,39
TECHNOLOGIES
PEG_-RX13 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
PEG_RX_13_N 2,12,38,39
PEG_-RX14 SAME IS PROECTEDTO THE EXTENT PERMITTED TITLE
PEG_RX_14_N 2,12,38,39 ENGR.
PEG_-RX15 UNDER THE LAWS OF THE UNITED STATES AND
PEG_RX_15_N 2,12,38,39
ENG. APP.
2^,12,39 SDVO_CLK SDVO_CTRLCLK 2,12,38,39 REPRODUCED, REVEALED TO OR APPROPRIATED ETXe-PC Hierarchy Connections 2
PROD. APP.
2^,18,39 PEG_ENABLE# PEG_ENABLE# 2,18,38,39,54 THE EXPRESS CONSENT OF BALLY. THIS PRINT MATL. APP.
2^,12,39 SDVO_DATA SDVO_CTRLDATA 2,12,38,39 IT WILL NOT BE USED IN ANY MANNER Q.A. APP. C PCA212268-2-1 A
DETRIMENTAL TO THE INTEREST OF BALLY, AND
PCA212268-2-1 1/1 1/1 37 62
5 4 3 2 1
5 4 3 2 1
D D
PCIe Graphics Interface PCIe Single Lane PCIe Gigabit Ethernet
PCIE_TX+0 PCIE_TX+1
PEG_+TX[0..15] PCIE_TX+0 PCIE_TX+1
2^,12 PEG_+TX[0..15] PEG_+TX[0..15]
PEG_-TX[0..15] PCIE_TX-0 PCIE_TX-1
2^,12 PEG_-TX[0..15] PEG_-TX[0..15] PCIE_TX-0 PCIE_TX-1 GBE1_MDI+0 GBE1_MDI+0 2^,41!,43!
PEG_-RX[0..15] CLK_PEG+ PCIE_RX+0 CLK_PCIE+0 PCIE_RX+1
2^,12 PEG_-RX[0..15] PEG_+RX[0..15] PEG_-RX[0..15] PCIE_RX+0 PCIE_RX+1 GBE1_MDI-0 GBE1_MDI-0 2^,41!,43!
2^,12 PEG_+RX[0..15] PEG_+RX[0..15] PCIE_RX-0 PCIE_RX-1
CLK_PEG- PCIE_RX-0 CLK_PCIE-0 PCIE_RX-1 GBE1_MDI+1 GBE1_MDI+1 2^,41!,43!
2^,18,39!,40! WAKE0# WAKE0#

WAKE0# CLK_PCIE+1 GBE1_MDI-1 GBE1_MDI-1 2^,41!,43!
VCC3.3 VCC12 WAKE0#
WAKE0#
CLK_PCIE-1 GBE1_MDI+2 GBE1_MDI+2 2^,41!,43!
2^,12 SDVO_CLK VCC3.3SBY
SDVO_CLK PCIE_RESET# WAKE1#
VCC12 PCIE_RESET# 2^,18 WAKE1# WAKE1# GBE1_MDI-2 GBE1_MDI-2 2^,41!,43!
VCC12 VCC3.3SBY
2^,12,39! SDVO_DATA PCIE_RESET#
SDVO_DATA PCIE_RESET# GBE1_MDI+3 GBE1_MDI+3 2^,41!,43!
PRSNT#_SLOT0
VCC3.3 VCC3.3SBY PRSNT#SLOT0
GBE1_MDI-3 GBE1_MDI-3 2^,41!,43!
2^,18 SMB_CK SMB_CK
SMB_CK SMB_CK VCC3.3SBY VCC12
VCC12 VCC3.3 SMB_CK GBE1_ACT# GBE1_ACT# 2^,43!
2^,18,39!,40! SMB_DAT SMB_DAT VCC3.3 GBE1_LINK1000# 2^,43!

C SMB_DAT SMB_DAT GBE1_LINK1000# C
VCC3.3 DGND SMB_DAT
VCC12 GBE1_LINK100# GBE1_LINK100# 2^,43!
2^,37! PCIE_RESET# PCIE_RESET#
PCIE_RESET#
VCC3.3SBY VCC3.3
2^,18,54! PEG_ENABLE# PEG_ENABLE# 40 PCIe Single Lane VCC3.3SBY

DGND
DGND
39 PCIe Graphics Interface 41 PCIe Gigabit Ethernet
2^,16 CLK_PCIE+[0..2]
CLK_PCIE+0
2^,16 CLK_PCIE-[0..2] CLK_PCIE+1
CLK_PCIE+2
CLK_PCIE-0
CLK_PCIE-1 VCC12 VCC3.3 VCC3.3SBY
CLK_PCIE-2
2^,18 PCIE_TX+[0..1]
PCIE_TX+0
2^,23,39!,40!,41!,46!,48!,50!,53! VCC12
PCIE_TX+1
2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39!,40!,41!,43!,44!,45,46!,47!,48!,51!,52!,53!,54!,56!,57!,58!,59!,60!,61!,62! VCC3.3
2^,18 PCIE_RX+[0..1]
2^,39!,40!,41!,47!,52!,53! VCC3.3SBY
PCIE_RX+0
PCIE_RX+1
B B
2^,18 PCIE_TX-[0..1] 2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39!,40!,41!,43!,44!,45,46!,47!,48!,49!,50!,51!,52!,53!,54!,56!,57!,58!,59!,60!,61!,62! DGND

PCIE_TX-0
PCIE_TX-1
2^,18 PCIE_RX-[0..1]
PCIE_RX-0
PCIE_RX-1
2^,54! PRSNT#_SLOT0 PRSNT#_SLOT0

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED PCI Express Hierarchy
PROD. APP.
PCA212268-2-1 1/1 1/1 38 62
5 4 3 2 1
5 4 3 2 1
D D
VCC12 VCC12 VCC3.3 VCC3.3

J13
B1 A1 R38 0 Ohm
B2 12V_0 PRSNT1#_0 A2 R553
12,38^ PEG_+TX[0..15] R529
B3 12V_1 12V_3 A3 4.7K 4.7K
PEG_+TX0 B4 RSVD_0 12V_4 A4 R524 0 Ohm
PEG_+TX1 B5 GND_0 GND_1 A5
18,38^ SMB_CK SMCLK TCK
PEG_+TX2 18,38^,40 SMB_DAT B6 A6
PEG_+TX3 B7 SMDAT TDI A7
PEG_+TX4 B8 GND_2 TDO A8
VCC3.3 3.3V_0 TMS 8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38^,40,41,43,44,45,46,47,48,51,52,53,54,56,57,58,59,60,61,62
PEG_+TX5 B9 A9 VCC3.3
PEG_+TX6 B10 TRST# 3.3V_1 A10
VCC3.3SBY 3.3Vaux 3.3V_2
PEG_+TX7 18,38^,40 WAKE0#
B11 A11 PCIE_RESET# 37,38^ VCC3.3
PEG_+TX8 B12 WAKE# PERST# A12
PEG_+TX9 B13 RSVD_1 GND_3 A13
GND_4 REFCLK+ CLK_PEG+ 16,38^
PEG_+TX10 PEG_+TX15 B14 A14 CLK_PEG- 16,38^
PEG_+TX11 PEG_-TX15 B15 PET0+ REFCLK- A15
PEG_+TX12 B16 PET0- GND_5 A16 PEG_+RX15
GND_6 PER0+ VCC3.3
PEG_+TX13 12,38^ SDVO_CLK R126 0 Ohm SDVO_CLK_R B17 A17 PEG_-RX15
PEG_+TX14 B18 PRSNT2#_0 PER0- A18
PEG_+TX15 PEG_+TX14 B19 GND_7 GND_8 A19
PEG_-TX14 B20 PET1+ RSVD_3 A20 + C85
B21 PET1- GND_9 A21 PEG_+RX14 100uF C84
B22 GND_10 PER1+ A22 PEG_-RX14 10V 10nF
12,38^ PEG_-TX[0..15] GND_11 PER1-
PEG_+TX13 B23 A23
PEG_-TX0 PEG_-TX13 B24 PET2+ GND_12 A24
PEG_-TX1 B25 PET2- GND_13 A25 PEG_+RX13
PEG_-TX2 B26 GND_14 PER2+ A26 PEG_-RX13 C441 C83
PEG_-TX3 PEG_+TX12 B27 GND_15 PER2- A27 22uF 10nF
PEG_-TX4 PEG_-TX12 B28 PET3+ GND_16 A28 25V
C PEG_-TX5 B29 PET3- GND_17 A29 PEG_+RX12 C
PEG_-TX6 B30 GND_18 PER3+ A30 PEG_-RX12
PEG_-TX7 R129 0 Ohm SDVO_DATA_R B31 RSVD_2 PER3- A31
12,38^ SDVO_DATA PRSNT2#_1 GND_19
PEG_-TX8 B32 A32
PEG_-TX9 PEG_+TX11 B33 GND_20 RSVD_4 A33
PEG_-TX10 PEG_-TX11 B34 PET4+ RSVD_5 A34 VCC12
PEG_-TX12 B36 GND_22 PER4+ A36 PEG_-RX11
PEG_-TX13 PEG_+TX10 B37 GND_23 PER4- A37
PEG_-TX14 PEG_-TX10 B38 PET5+ GND_24 A38
B40 GND_26 PER5+ A40 PEG_-RX10
PEG_+TX9 B41 GND_27 PER5- A41
PET6+ GND_28 23,38^,40,41,46,48,50,53 VCC12
12,38^ PEG_+RX[0..15] PEG_-TX9 B42 A42
B43 PET6- GND_29 A43 PEG_+RX9
PEG_+RX0 B44 GND_30 PER6+ A44 PEG_-RX9
PEG_+RX1 PEG_+TX8 B45 GND_31 PER6- A45 C428 C48 C49
PEG_+RX2 PEG_-TX8 B46 PET7+ GND_32 A46 22uF 10nF 10nF
PEG_+RX3 B47 PET7- GND_33 A47 PEG_+RX8 25V
PEG_+RX4 R206 0 Ohm B48 GND_34 PER7+ A48 PEG_-RX8
PEG_+RX5 B49 PRSNT2#_2 PER7- A49 + C72
PEG_+RX6 PEG_+TX7 B50 GND_35 GND_36 A50 220uF C50 C51
PEG_+RX7 PEG_-TX7 B51 PET8+ RSVD_6 A51 25V 10nF 10nF
PEG_+RX8 B52 PET8- GND_37 A52 PEG_+RX7
PEG_+RX10 PEG_+TX6 B54 GND_39 PER8- A54
PEG_+RX11 PEG_-TX6 B55 PET9+ GND_40 A55
PEG_+RX12 B56 PET9- GND_41 A56 PEG_+RX6
PEG_+RX14 PEG_+TX5 B58 GND_43 PER9- A58
PEG_+RX15 PEG_-TX5 B59 PET10+ GND_44 A59
GND_46 PER10+ 8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38^,40,41,43,44,45,46,47,48,49,50,51,52,53,54,56,57,58,59,60,61,62
B61 A61 PEG_-RX5
PEG_+TX4 B62 GND_47 PER10- A62
12,38^ PEG_-RX[0..15] PET11+ GND_48
PEG_-TX4 B63 A63 VCC3.3SBY
PEG_-RX0 B64 PET11- GND_49 A64 PEG_+RX4
B PEG_-RX1 B65 GND_50 PER11+ A65 PEG_-RX4 B
PEG_-RX2 PEG_+TX3 B66 GND_51 PER11- A66
PET12+ GND_52 38^,40,41,47,52,53 VCC3.3SBY
PEG_-RX3 PEG_-TX3 B67 A67
PEG_-RX5 B69 GND_54 PER12+ A69 PEG_-RX3
PET13+ GND_56 DGND
PEG_-RX7 PEG_-TX2 B71 A71 C90
PEG_-RX8 B72 PET13- GND_57 A72 PEG_+RX2 100nF
PEG_-RX11 PEG_-TX1 B75 PET14+ GND_60 A75
PEG_-RX15 PEG_-TX0 B79 PET15+ GND_64 A79
R278 0 Ohm B81 GND_66 PER15+ A81 PEG_-RX0
18,38^,54 PEG_ENABLE# PRSNT2#_3 PER15-
B82 A82
RSVD_7 GND_67
MOLEX
1032-0923 PCIe x 16 - 2x82

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED PCI Express Graphics Slot
PROD. APP.
PCA212268-2-1 1/1 1/1 39 62
5 4 3 2 1
5 4 3 2 1
D D
VCC12
23,38^,39,41,46,48,50,53 VCC12
C39 C52 C53 C54

10uF 10nF 10nF 10nF
VCC12 VCC12
C C
J8
R36
A1 B1
PRSNT1#_0 12V_0
0 Ohm A2 B2
12V_3 12V_1
A3 B3
VCC3.3 12V_4 RSVD_0
8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38^,39,41,43,44,45,46,47,48,51,52,53,54,56,57,58,59,60,61,62
A4 B4
GND_1 GND_0
VCC3.3
A5 B5 SMB_CK 18,38^
TCK SMCLK
A6 B6 SMB_DAT 18,38^,39
TDI SMDAT VCC3.3
+ C94 VCC3.3 A7 B7
220uF C91 C87 TDO GND_2
16V 10nF 10nF A8 B8 VCC3.3SBY
TMS 3.3V_0
A9 B9
3.3V_1 TRST#
A10 B10
3.3V_2 3.3Vaux
37,38^ PCIE_RESET# A11 B11 WAKE0# 18,38^,39

PERST# WAKE#
A12 B12 VCC3.3
GND_3 RSVD_1
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38^,39,41,43,44,45,46,47,48,49,50,51,52,53,54,56,57,58,59,60,61,62 VCC3.3SBY 16,38^ CLK_PCIE+0

A13 B13
REFCLK+ GND_4
16,38^ CLK_PCIE-0
A14 B14 PCIE_TX+0 18,38^
REFCLK- PET0+ R114
38^,39,41,47,52,53 VCC3.3SBY
A15 B15 PCIE_TX-0 18,38^ 10K
GND_5 PET0-
18,38^ PCIE_RX+0 A16 B16

PER0+ GND_6
DGND
C86 18,38^ PCIE_RX-0
A17 B17 PRSNT#SLOT0 38^,54
B 100nF PER0- PRSNT2#_0 B
A18 B18
GND_8 GND_7
Molex PCIe X1 Conn.

87715-9006

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED PCI Express x1 Slot
PROD. APP.
PCA212268-2-1 1/1 1/1 40 62
5 4 3 2 1
5 4 3 2 1
VCC12 VCC3.3 VCC3.3SBY
D R41 D
2.2K
2
1 D11
Wake On LAN
IRLML2803 MBR0520LT1G
Q36
R33
100K - DNI
3
VCC3.3
VDD3.3_GBE R18 0 Ohm - DNI
U8
3
FB22 180Z@100MHz
VDD3.3A_GBE 2 1 CTRL_V1.8_GBE R16 CTRL_V1.8_GBE_R 1 Q3
59 AVDD33_1 VCTRL18 0 Ohm BCX51
AVDD33_2
2
C384 C391 5 VDD1.8A_GBE
C 100nF 100nF AVDD18_1 8 C
AVDD18_2 11
AVDD18_3 14 C945 C386 C385 C378 C380
16 AVDD18_4 10nF 100nF 100nF 100nF 100nF
37 VDD33_1 Keep power traces as
46 VDD33_2 short and wide as possible.
C68 C43 C417 C78 C407 53 VDD33_3 22 VDD1.8E_GBE R35 0 Ohm
22uF 100nF 100nF 100nF 100nF VDD33_4 EVDD18_1 28
EVDD18_2
C395 C408 C47 C946
100nF 100nF 4.7uF 22uF
25
EGND_1
3
31 63 CTRL_V1.5_GBE R27 CTRL_V1.5_GBE_R 1 Q6
EGND_2 VCTRL15 0 Ohm BCX51
R21 2.49K 1% 15
2
RSET_GBE 64 VDD15_1 21
RSET VDD15_2 32 VDD1.5_GBE
VDD15_3 33
26 VDD15_4 38
16,38^ CLK_PCIE+1 REFCLK_P VDD15_5
16,38^ CLK_PCIE-1
27 C38 C390 C418 C79 C416 C74
REFCLK_N 41 100nF 100nF 100nF 100nF 100nF 22uF
23 VDD15_6 43
18,38^ PCIE_TX+1 HSIP VDD15_7
18,38^ PCIE_TX-1
24 49
VDD3.3_GBE C65 PCIE_RX+1_C 29 HSIN VDD15_8 52
18,38^ PCIE_RX+1 HSOP VDD15_9
100nF 58
VDD15_10 C77 C415 C423 C412 C394
18,38^ PCIE_RX-1 C66 PCIE_RX-1_C 30 100nF 100nF 100nF 100nF 100nF
R70 100nF HSON
1K 37,38^ PCIE_RESET# 20
PERST#
4
MDIN0 GBE1_MDI-0 38^,43
ISOLATE_GBE# 36 3
19 ISOLATE# MDIP0 GBE1_MDI+0 38^,43
18,38^ WAKE1# LANWAKE# 7
B MDIN1 6 GBE1_MDI-1 38^,43 B
R840 VDD3.3_GBE U9
MDIP1 GBE1_MDI+1 38^,43
15K Differential Pairs should be separated by
2 3 CLK25M_GBE 60 10 at least 50 mils to minimize cross-talk
GND OUT CKTAL1 MDIN2 9 GBE1_MDI-2 38^,43
4 1 R66 10K 61 MDIP2 GBE1_MDI+2 38^,43 coupled from other pairs. Avoid using vias
Vcc EOH VDD3.3_GBE CKTAL2 on the differential pairs.
13
MDIN3 GBE1_MDI-3 38^,43
CWX813-25.0M 12
MDIP3 GBE1_MDI+3 38^,43
C413
10nF EEDO 45
EEDI 47 EEDO
EESK 48 EEDI 57
EESK LED0 GBE1_ACT# 38^,43
EECS 44 56 GBE1_LINK100# 38^,43
EECS LED1 55
LED2 54
LED3 GBE1_LINK1000# 38^,43
VCC12 VCC3.3 VCC3.3SBY 17
18 NC_1
34 NC_2
35 NC_3 62 GVDD_GBE
23,38^,39,40,46,48,50,53 NC_4 GVDD
VDD3.3_GBE 39
R532 3.6K 40 NC_5
VCC12 NC_6
42
50 NC_7 65
51 NC_8 EXP_PAD
8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38^,39,40,43,44,45,46,47,48,51,52,53,54,56,57,58,59,60,61,62 U15 NC_9
VCC3.3
1 8
2 CS VCC 7
3 SK NC 6
RTL8111B-GR C393 C389
38^,39,40,47,52,53 DI ORG
4 5 1uF 100nF
DO GND C440
VCC3.3SBY
100nF Place RTL8111B as close
CAT93C46VI-GT3 as possible to the RJ45
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38^,39,40,43,44,45,46,47,48,49,50,51,52,53,54,56,57,58,59,60,61,62 connector/magnetics.
DGND
TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED PCI Express Gigabit Ethernet 2
PROD. APP.
PCA212268-2-1 1/1 1/1 41 62
5 4 3 2 1
5 4 3 2 1
D D
FRONT I/O - USB + ETHERNET AUDIO/VIDEO/SERIAL/MISC?
2^,22,43! GBE0_MDI+0 GBE0_MDI+0 GBE1_MDI+0 GBE1_MDI+0 2^,12

2^,41!,43! VGA_RED VGA_RED
TXD_232_SP10 TXD_232_SP10 2^,50!
2^,22,43! GBE0_MDI-0 GBE0_MDI-0 GBE1_MDI-0 GBE1_MDI-0 2^,41!,43!
2^,12 VGA_GRN VGA_GRN
2^,22,43! GBE0_MDI+1 GBE0_MDI+1 GBE1_MDI+1 GBE1_MDI+1 2^,41!,43! RXD_232_SP10 RXD_232_SP10 2^,50!
2^,22,43! GBE0_MDI-1 GBE0_MDI-1 GBE1_MDI-1 GBE1_MDI-1 2^,41!,43!2^,12 VGA_BLU VGA_BLU

TXD_232_SP11 TXD_232_SP11 2^,50!
2^,22,43! GBE0_MDI+2 GBE0_MDI+2 GBE1_MDI+2 GBE1_MDI+2 2^,41!,43!
2^,12 VGA_HSYNC VGA_HSYNC
2^,22,43! GBE0_MDI-2 GBE0_MDI-2 GBE1_MDI-2 GBE1_MDI-2 2^,41!,43! RXD_232_SP11 RXD_232_SP11 2^,50!
2^,22,43! GBE0_MDI+3 GBE0_MDI+3 GBE1_MDI+3 GBE1_MDI+3 2^,12

2^,41!,43! VGA_VSYNC VGA_VSYNC
C 2^,22,43! GBE0_MDI-3 GBE0_MDI-3 GBE1_MDI-3 GBE1_MDI-3 2^,41!,43! TEST_SWITCH# TEST_SWITCH# 2^,54! C
2^,22,43! GBE0_CTREF GBE0_CTREF 2^,12,45! VGA_I2C_DAT VGA_I2C_DAT

ACTIVITY_LED_CATHODE# ACTIVITY_LED_CATHODE# 2^,26!
2^,12 VGA_I2C_CLK VGA_I2C_CLK

2^,22 GBE0_LINK1000# GBE0_LINK1000# GBE1_LINK1000# GBE1_LINK1000# 2^,41! PWR_OK PWR_OK 2^,35,52!,58!,59!
2^,22 GBE0_LINK100# GBE0_LINK100# GBE1_LINK100# GBE1_LINK100# 2^,41!

2^,27 VGA2_RED VGA2_RED EXT_SYS_RESET# EXT_SYS_RESET# 2^,35,36!
2^,22 GBE0_ACT# GBE0_ACT# GBE1_ACT# GBE1_ACT# 2^,41! 2^,27 VGA2_GRN VGA2_GRN
2^,27 VGA2_BLU VGA2_BLU

USB_D+[0..3] VCC5 VCC3.3
2^,18,43! USB_D+[0..3] USB_D+[0..3]
2^,27 VGA2_HSYNC VGA2_HSYNC OTEMP# OTEMP# 2^,23,35
USB_D-[0..3]
2^,18,43! USB_D-[0..3] USB_D-[0..3] VCC5
2^,27 VGA2_VSYNC VGA2_VSYNC
USB_EN#[0..3] VCC3.3 VCC5 VCC3.3
2^,58! USB_EN#[0..3] USB_EN#[0..3]
GND_EARTH
2^,27,45! VGA2_I2C_DAT VGA2_I2C_DAT
USB_FLAG#[0..3]
2^,59! USB_FLAG#[0..3] USB_FLAG#[0..3] DGND
2^,27 VGA2_I2C_CLK VGA2_I2C_CLK VCC5

43 Front I/O - USB / Ethernet
VCC3.3
2^,46! LINE_IN_R LINE_IN_R AGND1
GND_EARTH
2^,46! LINE_IN_L LINE_IN_L
B DGND B
VCC5 VCC3.3 2^,46! MIC_IN_R MIC_IN_R
2^,46! MIC_IN_L MIC_IN_L

2^,12,19,27,34,43!,45,46!,48!,50!,53!,56!,57!,58!
VCC5 AGND1
2^,46! LINE_OUT_R LINE_OUT_R
2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39!,40!,41!,43!,44!,45,46!,47!,48!,51!,52!,53!,54!,56!,57!,58!,59!,60!,61!,62!
VCC3.3
2^,46! LINE_OUT_L LINE_OUT_L
2^,44!,46!
AGND1
2^,43!,44!,45,53! 44 Audio/Video/Serial/Misc
GND_EARTH
2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39!,40!,41!,43!,44!,45,46!,47!,48!,49!,50!,51!,52!,53!,54!,56!,57!,58!,59!,60!,61!,62!
DGND
AGND1

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Front Panel I/O Hierarchy
PROD. APP.
PCA212268-2-1 1/1 1/1 42 62
5 4 3 2 1
5 4 3 2 1
DUAL USB / ETHERNET COMBO 0 - ETX GbE

18,42^ USB_D+[0..3] V3.3_LAN_M V3.3_LAN_M
USB_D+0
USB_D+1
USB_D+2 R8 R9
USB_D+3 J4 330 330
RJ45-2
D 22,42^ GBE0_MDI+0 RJ45-3 RJ45-12 D
22,42^ GBE0_MDI-0
18,42^ USB_D-[0..3]
RJ45-4 RJ45-14
22,42^ GBE0_MDI+1
RJ45-5
22,42^ GBE0_MDI-1
USB_D-0
USB_D-1 RJ45-7
22,42^ GBE0_MDI+2
USB_D-2 RJ45-8
22,42^ GBE0_MDI-2
USB_D-3 RJ45-11 GBE0_ACT# 22,42^
RJ45-9
22,42^ GBE0_MDI+3 RJ45-10 RJ45-13
22,42^ GBE0_MDI-3 GBE0_LINK1000# 22,42^
FB15 220 OHM @ 100MHz RJ45-6 RJ45-15 GBE0_LINK100# 22,42^
42^,58 USB_EN#[0..3]
22,42^ GBE0_CTREF GBE0_CTREF_FB RJ45-1
USB_EN#0
USB_EN#1
USB_EN#2
USB_EN#3 FB4 220 OHM @ 100MHz
VOUT5.0_USB0 VOUT5.0_USB0_FB
VCC5
+ C12 FB37 USB2-1
42^,59 USB_FLAG#[0..3] VCC3.3 VCC3.3 100uF C20 USB_D-0 1 4 USB_D-0_FB USB2-2
10nF USB_D+0 2 3 USB_D+0_FB USB2-3
USB_FLAG#0 USB2-4
USB_FLAG#1 C10 90 OHM COM. MODE
USB_FLAG#2 100nF R5 R6
USB_FLAG#3 10K 10K FB42 USB1-1
USB_D-1 1 4 USB_D-1_FB USB1-2
U2 USB_D+1 2 3 USB_D+1_FB USB1-3
USB1-4
1 8 D45
USB_FLAG#0 90 OHM COM. MODE
GND OC1
M1
M2
M3
M4
M5
M6
M7
M8
2 7 1 6 Dual USB + 10/100/1000Base-TX
IN OUT1
USB_EN#0 3 6 2 5 Bel Fuse Inc.
C EN1 OUT2 C
USB_EN#1 4 5 USB_FLAG#1 3 4 0862-1J1T-43-F
EN2 OC2
ST2042 RCLAMP0504F.TCT
FB3 220 OHM @ 100MHz

+ C11
100uF C19
10nF
VDD3.3_GBE VDD3.3_GBE
VCC5 VCC3.3 DUAL USB / ETHERNET COMBO 1 - CARRIER BOARD GbE
R496 R495
J5 330 330
12,19,27,34,42^,45,46,48,50,53,56,57,58
VCC5
RJ45-2
41,42^ GBE1_MDI+0
RJ45-3 RJ45-12
41,42^ GBE1_MDI-0
8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,42^,44,45,46,47,48,51,52,53,54,56,57,58,59,60,61,62
VCC3.3
RJ45-4 RJ45-14
41,42^ GBE1_MDI+1
RJ45-5
41,42^ GBE1_MDI-1
42^,44,45,53
GND_EARTH
RJ45-7
41,42^ GBE1_MDI+2
RJ45-8
41,42^ GBE1_MDI-2 RJ45-11
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,42^,44,45,46,47,48,49,50,51,52,53,54,56,57,58,59,60,61,62 GBE1_ACT# 41,42^
DGND
RJ45-9
B 41,42^ GBE1_MDI+3 RJ45-10 RJ45-13 B
41,42^ GBE1_MDI-3 GBE1_LINK1000# 41,42^
RJ45-6 RJ45-15 GBE1_LINK100# 41,42^
C23 RJ45-1
10nF
VCC5
+ C3 FB41 USB2-1
VCC3.3 VCC3.3 100uF C8 USB_D-2 1 4 USB_D-2_FB USB2-2
10nF USB_D+2 2 3 USB_D+2_FB USB2-3
USB2-4
C1 90 OHM COM. MODE
100nF R1 R2
10K 10K FB36 USB1-1
USB_D-3 1 4 USB_D-3_FB USB1-2
U1 USB_D+3 2 3 USB_D+3_FB USB1-3
USB1-4
D44
1 8 USB_FLAG#2 90 OHM COM. MODE
GND OC1
M1
M2
M3
M4
M5
M6
M7
M8
2 7 1 6 Dual USB + 10/100/1000Base-TX
IN OUT1
USB_EN#2 3 6 2 5 Bel Fuse Inc.
EN1 OUT2
USB_EN#3 4 5 USB_FLAG#3 3 4 0862-1J1T-43-F
EN2 OC2
ST2042 RCLAMP0504F.TCT

TECHNOLOGIES
+ C2 SAME IS PROECTEDTO THE EXTENT PERMITTED TITLE
100uF C7 UNDER THE LAWS OF THE UNITED STATES AND ENGR.
10nF NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Front Panel USB & Ethernet
PROD. APP.
PCA212268-2-1 1/1 1/1 43 62
5 4 3 2 1
5 4 3 2 1
TEST SWITCH Serial Ports 1 & 2

D D
J1
POWER ACTIVITY
CF/SATA
SW1 A1
SPDT Mom. A2 CD_1
42^,50 RXD_232_SP11 RXD_1
1 42^,50 TXD_232_SP11
A3 VCC3.3 VCC3.3
2 A4 TXD_1 TOP DB-9
42^,54 TEST_SWITCH# DTR_1
3 A5
A6 GND_1
A7 DSR_1
A8 RTS_1 D40 D39
A9 CTS_1
Note: Mount switch RI_1 Green LED Red LED
on bottom of board
B1
B2 CD_2
42^,50 RXD_232_SP10 RXD_2
42^,50 TXD_232_SP10
B3 R488 R487
B4 TXD_2 BOTTOM DB-9 220 220
B5 DTR_2
B6 GND_2 S_GND1
B7 DSR_2 SHL_GND1 S_GND2
B8 RTS_2 SHL_GND2 S_GND3
B9 CTS_2 SHL_GND3 S_GND4
RI_2 SHL_GND4
26,42^ ACTIVITY_LED_CATHODE#
RESET SWITCH DUAL DB-9 CONN R/A

Note: Mount LEDs
Kycon
K42X-E9P/P-A4N
on bottom of board
SW2
SPDT Mom.
C 1 C
35,42^,52,58,59 PWR_OK R784 0 RST_SW# 2

3
35,36,42^ EXT_SYS_RESET# NI R785 0
Note: Mount switch

on bottom of board
C356
100pF
C357
100pF
AUDIO INTERFACE CONN.
J3
3 Audio Vertical Stack R/A TEMP WARNING HOT
FB9 120 OHM @ 100MHz AGND1 AGND1
42^,46 LINE_IN_L LINE_IN_L_FB 35
34
FB8 120 OHM @ 100MHz 33 LINE IN VCC3.3 VCC3.3

42^,46 LINE_IN_R LINE_IN_R_FB 32
BLUE
B LINE_OUT_L_FB 25 D38 D37 B
42^,46 LINE_OUT_L
24 YELLOW LED Red LED
FB7 120 OHM @ 100MHz 23 LINE OUT

42^,46 LINE_OUT_R LINE_OUT_R_FB 22
GREEN
FB28 120 OHM @ 100MHz R490 R489
MIC_IN_L_FB 5 220 220
42^,46 MIC_IN_L
4
FB27 120 OHM @ 100MHz 3 MIC

42^,46 MIC_IN_R MIC_IN_R_FB 2
PINK
1 OTEMP# 23,35,42^ PWR_OK
M2
M1
C9 C6 C5 C4 Kycon Note: Mount LEDs
Audio signals must be 100pF 100pF 100pF 100pF STX-4335-5BGP-S1
kept as far as possible on bottom of board
from digital signals and
clock lines.
AGND1 AGND1 AGND1 AGND1 AGND1
VCC5 VCC3.3
12,19,27,34,42^,43,45,46,48,50,53,56,57,58
VCC5
8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,42^,43,45,46,47,48,51,52,53,54,56,57,58,59,60,61,62
A
VCC3.3 A
42^,43,45,53
GND_EARTH
TECHNOLOGIES
42^,46 SAME IS PROECTEDTO THE EXTENT PERMITTED TITLE
AGND1
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,42^,43,45,46,47,48,49,50,51,52,53,54,56,57,58,59,60,61,62 ENG. APP.
DGND REPRODUCED, REVEALED TO OR APPROPRIATED Front Panel Audio, Serial, Misc.
PROD. APP.
AGND1 MUST BE RETURNEDTO BALLY ON DEMAND. ORCAD FILE DWG. SCALE PLOT SCALE SHEET OF
PCA212268-2-1 1/1 1/1 44 62
5 4 3 2 1
5 4 3 2 1
Analog Video 2 (via LVDS bridge)

VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC5 VCC5
J2B
Dual 15-Pin HD D-Sub
Top Connector
2
5 1
10 6
15 11
D2 D4 D6 D5 SH3
BAT54SW BAT54SW BAT54SW BAT54SW SH4 SH3
3
D SH4 D
GND_G
GREEN
GND_H
GND_R
HSYNC
VSYNC
GND_B
GND_V
SENSE
1
BLUE
RED
SDA
NC1
NC2
SCL
1B
4B
2B
5B
3B
6B
14B
7B
13B
8B
15B
10B
12B
11B
9B
D3 D7 D8
BAT54SW BAT54SW BAT54SW
3
FB19 FB11
27,42^ VGA2_RED
1 2 VGA2_RED_A 1 2 VGA2_RED_B
47-Ohms@100MHz FB20 47-Ohms@100MHz FB14

27,42^ VGA2_GRN 1 2 VGA2_GRN_A 1 2 VGA2_GRN_B
FB21 47-Ohms@100MHz 47-Ohms@100MHz FB13

27,42^ VGA2_BLU 1 2 VGA2_BLU_A 1 2 VGA2_BLU_B
47-Ohms@100MHz FB16 47-Ohms@100MHz

27,42^ VGA2_VSYNC
1 2 VGA2_VSYNC_A
FB17 47-Ohms@100MHz
27,42^ VGA2_HSYNC 1 2 VGA2_HSYNC_A
47-Ohms@100MHz FB18
1 2 VGA2_I2C_CLK_A
27,42^ VGA2_I2C_CLK
FB10 47-Ohms@100MHz
1 2 VGA2_I2C_DAT_A
27,42^ VGA2_I2C_DAT
47-Ohms@100MHz
NI NI
C44 C41 C32 C34 C14 C16 C28 C29 R11 R13
R17 R19 R20 10pF 10pF 22pF 22pF 10pF 10pF 47pF 47pF 2.2K 2.2K
150 150 150 NI NI
C40 C33 C15 C27 C17
C 10pF 22pF 10pF 47pF 47pF C
F1 FB5
VCC5 VCC5_VGA_F 1 2 VCC5_VGA
0.5A 47-Ohms@100MHz
C22
100nF
C21
47pF
Analog Video 1 (native CRT) VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC5 VCC5 J2A
Dual 15-Pin HD D-Sub
Bottom Connector
5 1
2
10 6
15 11
SH1
SH2 SH1
D43 D41 D48 D49 SH2
BAT54SW BAT54SW BAT54SW BAT54SW
GND_G
GREEN
GND_H
GND_R
HSYNC
VSYNC
GND_B
GND_V
SENSE
3
BLUE
RED
SDA
NC1
NC2
SCL
1
2
B B
1A
4A
2A
5A
3A
6A
14A
7A
13A
8A
15A
10A
12A
11A
9A
D42 D47 D46
FB38 FB29 BAT54SW BAT54SW BAT54SW
3
12,42^ VGA_RED
1 2 VGA_RED_A 1 2 VGA_RED_B
47-Ohms@100MHz FB40 47-Ohms@100MHz FB31

12,42^ VGA_GRN 1 2 VGA_GRN_A 1 2 VGA_GRN_B
FB39 47-Ohms@100MHz 47-Ohms@100MHz FB33

12,42^ VGA_BLU 1 2 VGA_BLU_A 1 2 VGA_BLU_B
47-Ohms@100MHz FB32 47-Ohms@100MHz

12,42^ VGA_VSYNC
1 2 VGA_VSYNC_A
FB35 47-Ohms@100MHz
12,42^ VGA_HSYNC
1 2 VGA_HSYNC_A
47-Ohms@100MHz FB34
1 2 VGA_I2C_CLK_A
12,42^ VGA_I2C_CLK
FB30 47-Ohms@100MHz
1 2 VGA_I2C_DAT_A
12,42^ VGA_I2C_DAT
47-Ohms@100MHz
NI NI
C375 C374 C369 C367 C365 C363 C360 C359 R494 R498
R503 R506 R502 10pF 10pF 22pF 22pF 10pF 10pF 47pF 47pF 2.2K 2.2K
150 150 150 NI NI
C379 C368 C364 C361 C362
10pF 22pF 10pF 47pF 47pF

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Front Panel Analog Video
PROD. APP.
PCA212268-2-1 1/1 1/1 45 62
5 4 3 2 1
5 4 3 2 1
V_AVDD5
D D
Note: Locate this resistor as close
C388 as possible to the ALC888 Audio
10uF C387 Codec Chip.
10nF
U7
AGND1 AGND1 FB12 LM7805
2^,48 S/PDIF_OUT VCC12
1 3 V_AVDD5
JDREF R509 20K VIN VOUT
GND
NI
120 OHM @ 100MHz + C26
FB24 C370 C371 C18 C31 C366 100uF
4
VCC3.3 VCC3.3_ALC888 22uF 22uF 10uF 100nF 10uF
25V 25V
48
47
46
45
44
43
42
41
40
39
38
37
120 OHM @ 100MHz AGND1
SPDIFO
PIN37-VREFO
SPDIFI/EAPD
SIDESURR-R
CEN
SURR-R
LFE
JDREF
SIDESURR-L
AVSS2
SURR-L
AVDD2
AGND1 AGND1 AGND1
C71 C73 C69 C70

10uF 10uF 10nF 10nF C25 100uF
1 36 FRONT_R
+
DVDD1 FRONT-R LINE_OUT_R 2^,44
R58 4.7K 2 35 FRONT_L C24 100uF
GPIO0 FRONT-L
R59 4.7K 3 34 SENSE_B R500 100K
+
GPIO1 Sense B V_AVDD5 LINE_OUT_L 2^,44
4 33
DVSS1 DCVOL R491 R492
2^,17 AC_SDOUT AC_SDOUT 5 32 VREFO-R_MIC1 22K - DNI 22K - DNI
SDATA-OUT U6 MIC1-VREFO-R
2^,17 AC_BITCLK R60 33 OHM AC_BITCLK_R 6 31
BIT-CLK ALC888 LINE2-VREFO
NI 7 30
C C426 DVSS2 MIC2-VREFO AGND1 AGND1 C
22pF AC_SDIN0_R 8 29
SDATA-IN LINE1-VREFO
9 28 VREFO-L_MIC1
AGND1 DVDD-IO MIC1-VREFO-L
10 27 VREF_ALC888
R61 33 OHM SYNC VREF
2^,17 AC_SDIN0
11 26
RESET# AVSS1
2^,17 AC_SYNC AC_SYNC 12 25 V_AVDD5 C377 C373

PCBEEP AVDD1 10uF 10nF
2^,17 AC_RESET# AC_RESET#
CD-GND
LINE2-R
LINE1-R
Sense A
LINE2-L
LINE1-L
C372 C376
MIC2-R
MIC1-R
MIC2-L
MIC1-L
10nF 10uF AGND1 AGND1 AGND1 R504 R501
CD-R
CD-L
C67
4.7K 4.7K
V_AVDD5 R50 4.7K PCBEEP_C PCBEEP
AGND1 AGND1
13
14
15
16
17
18
19
20
21
22
23
24
R63 C64 100nF
PC_SPEAKER 3.3nF
LINE1-R
MIC_IN_R_C
LINE1-L
MIC_IN_L_C
SENSE_A RP1
0 Ohm - DNI 1 8 LINE_IN_R LINE_IN_R 2^,44
LINE1-R_C 2 7
AGND1 C36 1uF, 16V 3 6 LINE_IN_L LINE_IN_L 2^,44
R40 R32 4 5
10K 20K
2^,44 MIC_IN_L C45 LINE1-L_C
1uF, 16V C37 1uF, 16V 4.7K
2^,44 MIC_IN_R C42

1uF, 16V AGND1
AGND1 AGND1
VCC5
B R513 Note: Route Audio Input and Output signals over B
SPKR1 a continuous analog ground plane. Audio signals
WT-1205 are single ended with a nominal trace impedance of
0 Ohm R3 33 1 55 Ohms. Partition analog and digital parts into
2 + seperate groups. Place Codec in quiet area of
- of the board.
AGND1 NI
3 D1
2
R4 Q1 3
2^,18 PC_SPEAKER PC_SPEAKER 1 2N7002/SOT
1
100
2
BAT54C
231-005
VCC12 VCC5 VCC3.3
2^,23,39,40,41,48,50,53 VCC12
2^,12,19,27,34,43,45,48,50,53,56,57,58 VCC5
2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,47,48,51,52,53,54,56,57,58,59,60,61,62 VCC3.3

2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,47,48,49,50,51,52,53,54,56,57,58,59,60,61,62 DGND
TECHNOLOGIES
2^,44 AGND1 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Audio Codec
AGND1 PROD. APP.
PCA212268-2-1 1/1 1/1 46 62
5 4 3 2 1
5 4 3 2 1
VCC3.3 VCC3.3SBY
2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,48,51,52,53,54,56,57,58,59,60,61,62 VCC3.3
D D
2^,39,40,41,52,53 VCC3.3SBY
2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,48,49,50,51,52,53,54,56,57,58,59,60,61,62 DGND
LPC BIOS/Firmware Hub

TPM Interface
VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3
R746 R744 R743 R742 C862 VCC3.3 VCC3.3SBY

10K 10K 10K 10K 100nF
VCC3.3
LPC_RESET#
LPC_CLK0 C877 C868 C881
C879 C880 10uF 100nF 100nF
R741 10K 100nF 10uF J22
NI
VCC3.3 R747 3.3K
32
31
30
U63
4
3
2
1
LPC_CLK1 1 2
R745 100 3 4 Keying Plug Installed at Pin 4 of TPM
LCLK
GPI2
GPI3
RST#
NC1
NC11
GPI4
R481 2^,17,35 LPC_FRAME#
VCC3.3 R750 3.3K 5 29 LPC_RESET# 5 6
C C340 6 GPI1 NC10 28 LPC_AD3 7 8 LPC_AD2 C
10nF 7 GPI0 NC9 27 9 10 LPC_AD1
8 WP# NC8 26 LPC_AD0 11 12
R482 U73 3.3K 9 TBL# NC7 25 13 14
ID3 VDD
5
1
4.7K 10 24 IDE_RESET# 2^,24,25,26,35 15 16 LPC_SERIRQ 2^,18,35

RP3 ID2 INIT#
11 23 LPC_FRAME# 17 18 R751 0 Ohm PCI_CLKRUN# 2^,18
2 4 5 4 12 ID1 LFRAME# 22 SUS_STAT# 19 20
2^,17,18 BIOS_DISABLE# ID0 NC6 2^,18,35 SUS_STAT#
6 3 13 21
LAD1
LAD2
LAD3
VSS
NC2
NC3
NC4
NI 7 2 LAD0 NC5 R753
S3 NC7SZ125 8 1 0 Ohm - DNI
3
1
Vertical, Dual Row ,SMT HDR
14
15
16
17
18
19
20
JP3 SHUNT SST49LF160C Molex
JUMPER 56 Ohm, 5% 15-91-2200
2
LPC_AD0
LPC_AD1 U63/SKT1 Socket, PLCC SMT,32 pos., tin, 1.27mm pitch
INSTALL JUMPER ACROSS BOTH LPC_AD2
PINS (1-2) TO DISABLE ETX BIOS LPC_AD3
AND ENABLE THE BASE BOARD Note: Pin 4 on this header must
BIOS. be cut off to accomodate a
keyed receptacle on the TPM.
B B
NI R440 0 Ohm
VCC3.3
NI R441 0 Ohm
VCC3.3
R411
4.7K U55
U46 C292 1 8 R422 33 OHM LPC_CLK0

2^,16 LPC_CLK CLKIN CLKOUT
1 5 10nF
2^,35,36,37 CB_RESET# A VCC 3 R439 33 OHM LPC_CLK1
2 FB26 120 OHM @ 100MHz CLK1
2^,37 BUF_PCI_RESET# B
VCC3.3
6 2
3 4 LPC_RESET# VCC CLK2
GND Y C310 C311 5
100nF 10nF CLK3
74LVC1G08
4 7
GND CLK4
CY2305
2^,17,35 LPC_AD[0..3]
LPC_AD0
LPC_AD1 PERTAINING TO THE ARTICLE SHOWN ON THIS
TECHNOLOGIES
LPC_AD2 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
LPC_AD3 UNDER THE LAWS OF THE UNITED STATES AND ENGR.
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Firmware Hub, TPM socket
PROD. APP.
PCA212268-2-1 1/1 1/1 47 62
5 4 3 2 1
5 4 3 2 1
VCC5 P1C VCC3.3 VCC5 P1B VCC12 P1A

96 Pin DIN R/A 96 Pin DIN R/A 96 Pin DIN R/A
2^,58 BUF_PERIPHERAL_RESET# C32 B32 A32 2^,57 PLAYERSW[0..15]

C31 B31 A31 PLAYERSW0
2^,56 BUF_iBUTTON1
PLAYERSW1
2^,56 BUF_iBUTTON2 C30 B30 A30 PLAYERSW2
PLAYERSW3
D D
C29 B29 AC DETECTION CIRCUIT ON BACKPLANE-AC POWER SW DETECT
A29 PLAYERSW4
2^,56 SLA_SDA 2^,56 AC_DETECT
PLAYERSW5
C28 B28 MOMENTARY PUSHBUTTON INPUT - SOFT ATX ON A28 PLAYERSW6
2^,56 SLA_SCL 2^,35,53 PWRBTN#
PLAYERSW7
C27 2^,58 USB_EN#4 B27 2^,58 USB_EN#5 A27 PLAYERSW8
PLAYERSW9
C26 2^,18 USB_D+4 B26 2^,18 USB_D+5 A26 PLAYERSW10
PLAYERSW11
C25 2^,18 USB_D-4 B25 2^,18 USB_D-5 A25 PLAYERSW12
PLAYERSW13
C24 2^,59 USB_FLAG#4 B24 2^,59 USB_FLAG#5 A24 PLAYERSW14
PLAYERSW15
2^,56 BUF_RTS_TTL_SP5 C23 2^,56 BUF_TXD_TTL_SP5 B23 2^,56 RXD_TTL_SP5 A23
C22 B22 A22

2^,50 TXD_232_SP9 2^,50 TXD_232_SP8 2^,50 TXD_232_SP7
2^,58 BUF_PLYRLAMP[0..15]
C21 B21 A21
2^,50 TXD_232_SP6 2^,50 TXD_232_SP4 2^,50 TXD_232_SP3
BUF_PLYRLAMP0
2^,50 TXD_232_SP2 C20 2^,50 TXD_232_SP1 B20 2^,50 TXD_232_SP0 A20 BUF_PLYRLAMP1
BUF_PLYRLAMP2
2^,50 RXD_232_SP9 C19 2^,50 RXD_232_SP8 B19 2^,50 RXD_232_SP7 A19 BUF_PLYRLAMP3
BUF_PLYRLAMP4
2^,50 RXD_232_SP6 C18 2^,50 RXD_232_SP4 B18 2^,50 RXD_232_SP3 A18 BUF_PLYRLAMP5
BUF_PLYRLAMP6
C17 B17 A17 BUF_PLYRLAMP7
2^,50 RXD_232_SP2 2^,50 RXD_232_SP1 2^,50 RXD_232_SP0
BUF_PLYRLAMP8
DOOR_SW11 C16 DOOR_SW10 B16 DOOR_SW9 A16 BUF_PLYRLAMP9
BUF_PLYRLAMP10
BUF_PLYRLAMP12
BUF_PLYRLAMP14
DOOR_SW2 C13 DOOR_SW1 B13 2^,58 DOOR_MODE A13 BUF_PLYRLAMP15
C12 B12 DOOR_SW0 A12

2^,57 DOOR_BAT_LOW#
C11 SPI_MISO_P1 B11 SPI_MISO_P0 A11
2^,54 LOGIC_DOOR_SW0 2^,54 DOOR_SW[0..11]
SPI_MISO_P2 C10 BUF_SPI_SCK_P0 B10 SPI_MISO_P3 A10 DOOR_SW0
DOOR_SW1
BUF_SPI_SCK_P1 C9 BUF_SPI_SCK_P2 B9 BUF_SPI_SCK_P3 A9 DOOR_SW2
DOOR_SW3
BUF_SPI_MOSI_P2 C8 BUF_SPI_MOSI_P1 B8 BUF_SPI_MOSI_P0 A8 DOOR_SW4
DOOR_SW5
BUF_SPI_CS_P1 C7 BUF_SPI_CS_P0 B7 BUF_SPI_MOSI_P3 A7 DOOR_SW6
DOOR_SW7
C6 BUF_SPI_CS_P3 B6 BUF_SPI_CS_P2 A6 DOOR_SW8
2^,56 BUF_FPGA_SPARE_OUT
DOOR_SW9
ASPARE0 C5 KEY_SW0 B5 KEY_SW2 A5 DOOR_SW10
DOOR_SW11
ASPARE1 C4 KEY_SW1 B4 KEY_SW3 A4
ASPARE2 C3 B3 A3
C C
C2 2^,46 S/PDIF_OUT B2 A2
C1 B1 A1
2^,58 BUF_METER[0..7]
ITW/Pancon ITW/Pancon ITW/Pancon
100-096-053 100-096-053 100-096-053 BUF_METER0
BUF_METER1
BUF_METER2
BUF_METER3
BUF_METER4
BUF_METER5
BUF_METER6
BUF_METER7
2^,58 BUF_TWRLAMP[0..3]
BUF_TWRLAMP0
BUF_TWRLAMP1
BUF_TWRLAMP2
BUF_TWRLAMP3
2^,57 KEY_SW[0..3]
VCC5SBY VEE12 VCC3.3 P2A KEY_SW0
P2C VCC5 VCC12 P2B 96 Pin DIN R/A KEY_SW1
96 Pin DIN R/A 96 Pin DIN R/A KEY_SW2
KEY_SW3
2^,57 HOP_SENSOR_SPARE A32
C32 B32
2^,57 HOP_FULL A31
C31 2^,58 BUF_HANDLE_SOL B31
2^,57 HOP_COIN_OUT A30 2^,56 SPI_MISO_P[0..3]
C30 2^,57 HANDLE_OPTIC B30
2^,58 BUF_HOP_MODE A29 SPI_MISO_P0
2^,56 BUF_ACFAIL# C29 B29 SPI_MISO_P1
A28 SPI_MISO_P2
2^,58 BUF_HOP_BRAKE
C28 B28 SPI_MISO_P3
2^,58 BUF_HOP_PHASE A27
C27 2^,58 BUF_BVAL_MRST# B27
2^,58 BUF_HOP_ENABLE A26
C26 B26
2^,58 BUF_PRN_MRST# 2^,58 BUF_BVAL_LAMP
2^,58 BUF_COIN_DIV_EN A25 2^,56 BUF_SPI_MOSI_P[0..3]
2^,58 BUF_PRN_LAMP C25 2^,58 BUF_COIN_DIV_DIR B25
2^,57 COIN_CREDIT1 A24 BUF_SPI_MOSI_P0
2^,58 COIN_DIV_LED C24 2^,57 COIN_DIV_FLAG B24 BUF_SPI_MOSI_P1
B A23 BUF_SPI_MOSI_P2 B
2^,57 COIN_CHUTE0
2^,57 COIN_CREDIT0 C23 2^,57 COIN_CHUTE1 B23 BUF_SPI_MOSI_P3
2^,58 COIN_INHIBIT A22
2^,57 ASPARE[0..2] 2^,57 COIN_TILT C22 2^,57 COIN_SENSE B22
2^,57 METER_SENSE A21
ASPARE0 2^,56 FPGA_SPARE_IN C21 B21 2^,56 BUF_SPI_CS_P[0..3]
ASPARE1 BUF_METER5 A20
ASPARE2 BUF_METER7 C20 BUF_METER6 B20 BUF_SPI_CS_P0
BUF_METER2 A19 BUF_SPI_CS_P1
BUF_METER4 C19 BUF_METER3 B19 BUF_SPI_CS_P2
PLAYERSW15 A18 BUF_SPI_CS_P3
BUF_METER1 C18 BUF_METER0 B18
PLAYERSW12 A17
PLAYERSW14 C17 PLAYERSW13 B17
PLAYERSW9 A16 2^,56 BUF_SPI_SCK_P[0..3]
PLAYERSW6 A15 BUF_SPI_SCK_P0
PLAYERSW8 C15 PLAYERSW7 B15 BUF_SPI_SCK_P1
PLAYERSW3 A14 BUF_SPI_SCK_P2
PLAYERSW5 C14 PLAYERSW4 B14 BUF_SPI_SCK_P3
PLAYERSW0 A13
A12
C12 B12
BUF_PLYRLAMP15 A11
C11 B11
BUF_PLYRLAMP12 A10
BUF_PLYRLAMP14 C10 BUF_PLYRLAMP13 B10
BUF_PLYRLAMP9 A9
BUF_PLYRLAMP6 A8
BUF_PLYRLAMP8 C8 BUF_PLYRLAMP7 B8 SCR3 SCR4 SCR5 SCR6
BUF_PLYRLAMP3 A7
BUF_PLYRLAMP0 A6
A5
C5 B5 BP Screw BP Screw BP Screw BP Screw
BUF_TWRLAMP0 A4
BUF_TWRLAMP2 C4 BUF_TWRLAMP1 B4
BUF_TWRLAMP3 A3 NUT3 NUT4 NUT5 NUT6
C3 B3
A2
C2 B2
A1
C1 B1 BP Nut BP Nut BP Nut BP Nut
ITW/Pancon
ITW/Pancon ITW/Pancon 100-096-053
100-096-053 100-096-053
VCC12 VCC5SBY
A A
2^,23,39,40,41,46,50,53 VCC12 VCC5 VCC3.3
2^,12,19,27,34,43,45,46,50,53,56,57,58 VCC5
2^,19,28,29,30,31,32,33,34,36,53 VCC5SBY
2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,51,52,53,54,56,57,58,59,60,61,62 VCC3.3
SHEET IS THE EXCLUSIVE PROPERTY OF BALLY D. LEBLANC 4/14/2011 Bally
TECHNOLOGIES
2^,50,53 VEE12 VEE12
NEVADA. THIS INFORMATION IS DISCLOSED IN
ENG. APP.
Alpha 2 iMPU, Marvell
2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,49,50,51,52,53,54,56,57,58,59,60,61,62 DGND REPRODUCED, REVEALED TO OR APPROPRIATED
PROD. APP.
Backplane Connectors
IS LOANED ONLY AND RECIPIENT COVENANTS MATL. APP.
IT WILL NOT BE USED IN ANY MANNER DWG. SIZE DWG. NO. REV.
Q.A. APP.
MUST BE RETURNEDTO BALLY ON DEMAND.
ORCAD FILE DWG. SCALE PLOT SCALE SHEET OF
PCA212268-2-1 1/1 1/1 48 62
5 4 3 2 1
5 4 3 2 1
D D
SATA 1
J17
2^,17 SATA1_TX+ 2 1
3 TX GND_0 4
2^,17 SATA1_TX- TX # GND_1 7
GND_2
C 5 C
2^,17 SATA1_RX- RX #
2^,17 SATA1_RX+ 6 S1
RX SHIELD_1 S2
SHIELD_2
MOLEX
301-142
SATA 0
J18
2^,17 SATA0_TX+ 2 1
3 TX GND_0 4
2^,17 SATA0_TX- TX # GND_1 7
GND_2
2^,17 SATA0_RX-
5
6 RX # S1
2^,17 SATA0_RX+ RX SHIELD_1 S2
SHIELD_2
MOLEX
301-142
B B
VCC3.3 VCC5
VCC5 2^,12,19,27,34,43,45,46,48,50,53,56,57,58
VCC3.3 2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,48,51,52,53,54,56,57,58,59,60,61,62
DGND 2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,50,51,52,53,54,56,57,58,59,60,61,62

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED SATA connectors
PROD. APP.
PCA212268-2-1 1/1 1/1 49 62
5 4 3 2 1
5 4 3 2 1
2^,59,61 RXD_TTL_EXAR_SP[0..4]
RXD_TTL_EXAR_SP0 RXD_TTL_SP0
D D
2^,59,61,62 RXD_TTL_EXAR_SP[6..11]
RXD_TTL_EXAR_SP6 RXD_TTL_SP6 Serial Ports 0, 1, 2 Serial Ports 3, 4, 6
RXD_TTL_EXAR_SP10 RXD_TTL_SP10 VCC12 VCC5 VCC12 VCC5
2^,61 TXD_TTL_EXAR_SP[0..4]
C899 C348 C900 C347
100nF U81 100nF 100nF U80 100nF
TXD_TTL_EXAR_SP0 R709 0 Ohm - DNI TXD_TTL_SP0
TXD_TTL_EXAR_SP1 R697 0 Ohm - DNI TXD_TTL_SP1 1 20 1 20
TXD_TTL_EXAR_SP2 R687 0 Ohm - DNI TXD_TTL_SP2 VDD VCC VDD VCC
TXD_TTL_EXAR_SP3 R695 0 Ohm - DNI TXD_TTL_SP3 2^,48 RXD_232_SP0
2 19 RXD_TTL_SP0 2^,48 RXD_232_SP3
2 19 RXD_TTL_SP3
TXD_TTL_EXAR_SP4 R694 0 Ohm - DNI TXD_TTL_SP4 RA1 RY1 RA1 RY1
2^,48 RXD_232_SP1 3 18 RXD_TTL_SP1 2^,48 RXD_232_SP4 3 18 RXD_TTL_SP4

RA2 RY2 RA2 RY2
2^,48 RXD_232_SP2 4 17 RXD_TTL_SP2 2^,48 RXD_232_SP6 4 17 RXD_TTL_SP6
RA3 RY3 RA3 RY3
2^,61,62 TXD_TTL_EXAR_SP[6..11]
2^,48 TXD_232_SP0
5 16 TXD_TTL_SP0 2^,48 TXD_232_SP3
5 16 TXD_TTL_SP3
DY1 DA1 DY1 DA1
TXD_TTL_EXAR_SP6 R699 0 Ohm - DNI TXD_TTL_SP6 2^,48 TXD_232_SP1
6 15 TXD_TTL_SP1 2^,48 TXD_232_SP4
6 15 TXD_TTL_SP4
TXD_TTL_EXAR_SP7 R710 0 Ohm - DNI TXD_TTL_SP7 DY2 DA2 DY2 DA2
TXD_TTL_EXAR_SP8 R661 0 Ohm - DNI TXD_TTL_SP8 7 14 7 14
TXD_TTL_EXAR_SP9 R643 0 Ohm - DNI TXD_TTL_SP9 RA4 RY4 RA4 RY4
TXD_TTL_EXAR_SP10 R641 0 Ohm - DNI TXD_TTL_SP10 2^,48 TXD_232_SP2
8 13 TXD_TTL_SP2 2^,48 TXD_232_SP6
8 13 TXD_TTL_SP6
TXD_TTL_EXAR_SP11 R658 0 Ohm - DNI TXD_TTL_SP11 DY3 DA3 DY3 DA3
9 12 9 12
RA5 RY5 RA5 RY5
VEE12
10 11 VEE12
10 11
Stuffing option for Exar PCI UARTs. FPGA must VSS GND VSS GND
C be configured to drive it's UART outputs in C
high impedance if Exar UARTs are to be used. C891 C892
GD75232DWR GD75232DWR
100nF 100nF
2^,59 TXD_TTL_SP[0..4]
TXD_TTL_SP0
TXD_TTL_SP1
TXD_TTL_SP2
TXD_TTL_SP3
TXD_TTL_SP4
2^,59 TXD_TTL_SP[6..11]
Serial Ports 7, 8, 9 Serial Ports 10, 11
TXD_TTL_SP6
TXD_TTL_SP7
TXD_TTL_SP8 VCC12 VCC5 VCC12 VCC5
TXD_TTL_SP9
TXD_TTL_SP10
TXD_TTL_SP11
C898 C346 C381 C382

100nF U79 100nF 100nF U4 100nF
2^,59,61 RXD_TTL_SP[0..4] 1 20 1 20
VDD VCC VDD VCC
RXD_TTL_SP0 2^,48 RXD_232_SP7
2 19 RXD_TTL_SP7 2^,44 RXD_232_SP10
2 19 RXD_TTL_SP10
B RXD_TTL_SP1 RA1 RY1 RA1 RY1 B
3 18 RXD_TTL_SP8 2^,44 RXD_232_SP11
3 18 RXD_TTL_SP11
RXD_TTL_SP3 RA2 RY2 RA2 RY2
4 17 RXD_TTL_SP9 4 17
RA3 RY3 RA3 RY3
2^,48 TXD_232_SP7
5 16 TXD_TTL_SP7 2^,44 TXD_232_SP10
5 16 TXD_TTL_SP10
DY1 DA1 DY1 DA1
2^,59,61,62 RXD_TTL_SP[6..11] 2^,48 TXD_232_SP8

6 15 TXD_TTL_SP8 2^,44 TXD_232_SP11
6 15 TXD_TTL_SP11
DY2 DA2 DY2 DA2
RXD_TTL_SP6 7 14 7 14
RXD_TTL_SP8 2^,48 TXD_232_SP9
8 13 TXD_TTL_SP9 8 13
RXD_TTL_SP9 DY3 DA3 DY3 DA3
RXD_TTL_SP10 9 12 9 12
VEE12
10 11 VEE12
10 11
VSS GND VSS GND
C893 GD75232DWR C358 GD75232DWR

100nF 100nF
VCC12 VEE12 VCC5
2^,23,39,40,41,46,48,53 VCC12
A
2^,48,53 VEE12 A
2^,12,19,27,34,43,45,46,48,53,56,57,58 VCC5
TECHNOLOGIES
2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,49,51,52,53,54,56,57,58,59,60,61,62 DGND
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED RS-232 Serial Transceivers
PROD. APP.
PCA212268-2-1 1/1 1/1 50 62
5 4 3 2 1
5 4 3 2 1
D D
Board Rev. Identification Jurisdiction EEPROM (2Kx8)

VCC3.3
VCC3.3
10
5
RP2 NI R465 R462 C335
10K 3.83K 3.83K 100nF
U62
1 8
LD3.3V_[0..7] 2^,57,58,59 A0 VCC
2 7
C 3 A1 WP 6 C
SLB_SCL 2^,59
9
4 A2 SCL 5
U52 GND SDA SLB_SDA 2^,59
NI R724 0 Ohm BOARD_REV0 2 18 LD3.3V_0 24WC16P
I0 O0
R721 0 Ohm BOARD_REV1 4 16 LD3.3V_1
I1 O1
I2 O2
I3 O3 U62/SKT1
I4 O4
I5 O5
I6 O6 8-pin DIP
I7 O7 VCC3.3
1 20
OE1 Vcc
2^,59 BOARD_REV_ID#
19 10
OE2 GND C812
ADDR 0X114 100nF
74LCX244
B B
VCC3.3
2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,48,52,53,54,56,57,58,59,60,61,62 VCC3.3
2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,49,50,52,53,54,56,57,58,59,60,61,62 DGND

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Board Rev. ID, Jurisdiction
PROD. APP.
EEPROM
MATL. APP.
PCA212268-2-1 1/1 1/1 51 62
5 4 3 2 1
5 4 3 2 1
NVRAM Bank 0 - Upperword NVRAM Bank 0 - Lowerword

2^,59 LA[2..24] LD[0..31] 2^,59
2^,33 VBATT
VCC3.3SBY VCC3.3 U51 U59
BH2 LA2 A3 LA2 A3

24.5mm Coin Cell Holder LA3 A4 A0 LA3 A4 A0
D R714 LA4 A5 A1 LA4 A5 A1 D
1 VBATT_CELL0 LA5 B3 A2 LA5 B3 A2
U43 10K A3 A3
2 LA6 B4 LA6 B4
LA7 C3 A4 LA7 C3 A4
Renata 16 11 LA8 C4 A5 LA8 C4 A5
VCC BL BATT_LOW0# 2^,57 NVRAM_CS0# 2^,59 A6 A6
NH5077-LF 1 15 LA9 D4 B6 LD16 LA9 D4 B6 LD0
7 NC1 NC5 13 LA10 H2 A7 DQ0 C5 LD17 LA10 H2 A7 DQ0 C5 LD1
5 VBAT NC4 2 LA11 H3 A8 DQ1 C6 LD18 LA11 H3 A8 DQ1 C6 LD2
PWR_OK# 10 RSTIN NC2 14 LA12 H4 A9 DQ2 D5 LD19 LA12 H4 A9 DQ2 D5 LD3
12 E VOUT 6 VCCB0_1.8 LA13 H5 A10 DQ3 E5 LD20 LA13 H5 A10 DQ3 E5 LD4
4 PFI PFO 3 LA14 G3 A11 DQ4 F5 LD21 LA14 G3 A11 DQ4 F5 LD5
BT1 8 NC3 RST 9 U39 LA15 G4 A12 DQ5 F6 LD22 LA15 G4 A12 DQ5 F6 LD6
CR2477 - 950mAH VSS ECON 1 5 LA16 F3 A13 DQ6 G6 LD23 LA16 F3 A13 DQ6 G6 LD7
A VCC C268 LA17 F4 A14 DQ7 B1 LD24 LA17 F4 A14 DQ7 B1 LD8
2 10nF LA18 E4 A15 DQ8 C1 LD25 LA18 E4 A15 DQ8 C1 LD9
M40SZ100WMQ6 B A16 DQ9 A16 DQ9
C1006 LA19 D3 C2 LD26 LA19 D3 C2 LD10
100nF Tpd = 15nS 3 4 LA20 H1 A17 DQ10 D2 LD27 LA20 H1 A17 DQ10 D2 LD11
GND Y LA21 G2 A18 DQ11 E2 LD28 LA21 G2 A18 DQ11 E2 LD12
LA22 H6 A19 DQ12 F2 LD29 LA22 H6 A19 DQ12 F2 LD13
74AUC1G32 A20 DQ13 A20 DQ13
LA23 E3 F1 LD30 LA23 E3 F1 LD14
U43A Tpd = 2.5nS LA24 J4 A21 DQ14 G1 LD31 LA24 J4 A21 DQ14 G1 LD15
VCC1.8 A22 DQ15 A22 DQ15
15 12
1 VCCi BW 7 VOUT_BATT_3.3SBY_0 VCCB0_1.8 VCCB0_1.8
4 NC1 NC4 16 LBE_3# B2 LBE_1# B2
VBAT NC5 2^,59 LBE_3# UB# 2^,59 LBE_1# UB#
3 13 R717 2^,59 LBE_2# LBE_2# A1 D6 2^,59 LBE_0# LBE_0# A1 D6
PWR_OK# 9 NC2 NC6 2 3.3K NVRAM_OE# A2 LB# VCC E1 NVRAM_OE# A2 LB# VCC E1
CEI VCCo 2^,59 NVRAM_OE# OE# VCCQ OE# VCCQ
6 10 C794 2^,59 NVRAM_WE# NVRAM_WE# G5 E6 NVRAM_WE# G5 E6
5 TOL NC7 14 10nF CE0#1.8 B5 WE# VSS D1 CE0#1.8 B5 WE# VSS D1
8 NC3 RST 11 CE# VSSQ CE# VSSQ
GND CEO NVRAM_WAIT# J1 NVRAM_WAIT# J1
2^,59 NVRAM_WAIT# WAIT WAIT
C301 C796 2^,59 NVRAM_CLK NVRAM_CLK J2 J5 NVRAM_CLK J2 J5
100nF 100nF NVRAM_ADV# J3 CLK RFU1 J6 C800 C810 C802 NVRAM_ADV# J3 CLK RFU1 J6 C834 C850 C855
DS1314S+ 2^,59 NVRAM_ADV# ADV# RFU2 ADV# RFU2
NVRAM_CRE A6 33nF 33nF 330nF NVRAM_CRE A6 33nF 33nF 330nF
2^,59 NVRAM_CRE CRE CRE
U43 AND U43A ARE ALTERNATE PARTS
C INSTALL ONLY ONE C
MT45W8MW16BGX-7013LWT MT45W8MW16BGX-7013LWT
U45 VCCB0_1.8
1
VIN 5
VOUT
VCC3.3SBY 2
GND
U41 C1007 C295 4 C281
1 5 10nF 1uF 3 NC 1uF
NC VCC C277 EN
2 10nF
2^,35,44,53,59 PWR_OK
3
A
GND Y
4 PWR_OK#
LD39015M18R
NVRAM Bank 1 - Upperword NVRAM Bank 1 - Lowerword
74LVC1G14 U53 U61
VCC3.3 LA2 A3 LA2 A3

BH1 LA3 A4 A0 LA3 A4 A0
24.5mm Coin Cell Holder LA4 A5 A1 LA4 A5 A1
VCC3.3SBY LA5 B3 A2 LA5 B3 A2
R715 LA6 B4 A3 LA6 B4 A3
1 VBATT_CELL1 LA7 C3 A4 LA7 C3 A4
U42 10K A5 A5
2 LA8 C4 LA8 C4
LA9 D4 A6 B6 LD16 LA9 D4 A6 B6 LD0
Renata 16 11 LA10 H2 A7 DQ0 C5 LD17 LA10 H2 A7 DQ0 C5 LD1
VCC BL BATT_LOW1# 2^,57 NVRAM_CS1# 2^,59 A8 DQ1 A8 DQ1
NH5077-LF 1 15 LA11 H3 C6 LD18 LA11 H3 C6 LD2
7 NC1 NC5 13 LA12 H4 A9 DQ2 D5 LD19 LA12 H4 A9 DQ2 D5 LD3
5 VBAT NC4 2 LA13 H5 A10 DQ3 E5 LD20 LA13 H5 A10 DQ3 E5 LD4
PWR_OK# 10 RSTIN NC2 14 LA14 G3 A11 DQ4 F5 LD21 LA14 G3 A11 DQ4 F5 LD5
BT2 12 E VOUT 6 VCCB1_1.8 LA15 G4 A12 DQ5 F6 LD22 LA15 G4 A12 DQ5 F6 LD6
CR2477 - 950mAH 4 PFI PFO 3 LA16 F3 A13 DQ6 G6 LD23 LA16 F3 A13 DQ6 G6 LD7
8 NC3 RST 9 U40 LA17 F4 A14 DQ7 B1 LD24 LA17 F4 A14 DQ7 B1 LD8
VSS ECON 1 5 LA18 E4 A15 DQ8 C1 LD25 LA18 E4 A15 DQ8 C1 LD9
B A VCC C271 LA19 D3 A16 DQ9 C2 LD26 LA19 D3 A16 DQ9 C2 LD10 B
2 10nF LA20 H1 A17 DQ10 D2 LD27 LA20 H1 A17 DQ10 D2 LD11
M40SZ100WMQ6 B A18 DQ11 A18 DQ11
C1008 LA21 G2 E2 LD28 LA21 G2 E2 LD12
100nF Tpd = 15nS 3 4 LA22 H6 A19 DQ12 F2 LD29 LA22 H6 A19 DQ12 F2 LD13
GND Y LA23 E3 A20 DQ13 F1 LD30 LA23 E3 A20 DQ13 F1 LD14
LA24 J4 A21 DQ14 G1 LD31 LA24 J4 A21 DQ14 G1 LD15
74AUC1G32 A22 DQ15 A22 DQ15
U42A Tpd = 2.5nS
VCCB1_1.8 VCCB1_1.8
15 12 LBE_3# B2 LBE_1# B2
1 VCCi BW 7 VOUT_BATT_3.3SBY_1 LBE_2# A1 UB# D6 LBE_0# A1 UB# D6
4 NC1 NC4 16 NVRAM_OE# A2 LB# VCC E1 NVRAM_OE# A2 LB# VCC E1
3 VBAT NC5 13 NVRAM_WE# G5 OE# VCCQ E6 NVRAM_WE# G5 OE# VCCQ E6
PWR_OK# 9 NC2 NC6 2 C795 CE1#1.8 B5 WE# VSS D1 CE1#1.8 B5 WE# VSS D1
6 CEI VCCo 10 10nF CE# VSSQ CE# VSSQ
5 TOL NC7 14 NVRAM_WAIT# J1 NVRAM_WAIT# J1
8 NC3 RST 11 NVRAM_CLK J2 WAIT J5 NVRAM_CLK J2 WAIT J5
C299 C797 GND CEO NVRAM_ADV# J3 CLK RFU1 J6 C811 C831 C817 NVRAM_ADV# J3 CLK RFU1 J6 C860 C878 C869
100nF 100nF NVRAM_CRE A6 ADV# RFU2 33nF 33nF 330nF NVRAM_CRE A6 ADV# RFU2 33nF 33nF 330nF
U44 VCCB1_1.8 CRE CRE
DS1314S+
1
VIN 5
VOUT MT45W8MW16BGX-7013LWT MT45W8MW16BGX-7013LWT
U42 AND U42A ARE ALTERNATE PARTS
INSTALL ONLY ONE 2
GND R718
4 49.9 AC TERMINATION, PLACE AT END
3 NC OF CLOCK LINE.
C1009 C293 EN C278
10nF 1uF LD39015M18R 1uF
VCC3.3 VCC1.8
C806
100pF
4,56,57,58,59,60,61,62 VCC3.3 VCC3.3SBY
A RP23 RP25 RP24 RP22 A

2^,39,40,41,47,53 VCC3.3SBY ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE
LA2
LA3
9
10
8
7
LA10
LA11
9
10
8
7
LA18
LA19
9
10
8
7
LBE_1#
LBE_2#
9
10
8
7
TECHNOLOGIES
LA4 11 6 LA12 11 6 LA20 11 6 LBE_3# 11 6 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
2^,53,59 VCC1.8 LA5 12 5 LA13 12 5 LA21 12 5 NVRAM_OE# 12 5 SAME IS PROECTEDTO THE EXTENT PERMITTED TITLE
LA6 13 4 LA14 13 4 LA22 13 4 NVRAM_WE# 13 4 UNDER THE LAWS OF THE UNITED STATES AND ENGR.
LA7 14 3 LA15 14 3 LA23 14 3 NVRAM_CLK 14 3 NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
LA8 15 2 LA16 15 2 LA24 15 2 NVRAM_ADV# 15 2 ENG. APP.
4,56,57,58,59,60,61,62 DGND LA9 16 1 LA17 16 1 LBE_0# 16 1 NVRAM_CRE 16 1 Battery, NVRAM
REPRODUCED, REVEALED TO OR APPROPRIATED
PROD. APP.
4.7K 5% 4.7K 5% 4.7K 5% 4.7K 5% THE EXPRESS CONSENT OF BALLY. THIS PRINT MATL. APP.
PCA212268-2-1 1/1 1/1 52 62
5 4 3 2 1
5 4 3 2 1
VCC12 VCC5 VCC3.3
R436 R429 R419 R458 R464 R470 R457 R463 R469

240 DNI 240 DNI 240 DNI 39 DNI 39 DNI 39 DNI 22 DNI 22 DNI 22 DNI
1.0W 1.0W 1.0W 1.0W 1.0W 1.0W 1.0W 1.0W 1.0W
JUMP FOR USE WITH BALLY TP14 VCC5 VCC3.3 VCC3.3

50mA/resistor 128mA/resistor 150mA/resistor POWER SUPPLIES THAT HAVE AC_FAIL#
ACFAIL DRIVE CAPABILITY.
OPEN FOR STANDARD ATX
1
POWER SUPPLIES. R451
D VCC3.3SBY VCC5SBY 4.7K R445 R435 D
3.3K 3.3K
Soft Power ON/OFF U58
JP1 R443
C836 R732 1 2 1 6 AC_FAIL# 2^,56,59
U97 10nF 10K 1A 1Y
1 5 S1 2 5
2^,35,59 SOFT_PWR_OFF OE VCC JUMPER 330 GND Vcc
2^,34,35 SUS_S3#
2 SHUNT
3 4 PWR_OK 2^,35,52,58,59
A R730 2A 2Y
3
3 4 1 Q71
GND Y
ATX_POWER_OK_R
R727 MMBT3904 74LVC2G07 C327
10K 100nF
74LVC1G125 ATX Power Input
2
10K
R728
TP28 100K
rnd_1mm VCC5 VCC3.3 VCC5 VCC3.3 VCC5SBY VCC12 VCC12_AUX
VCC3.3
U47
VCC1.8 J24 12 V Aux. Power
R418
3 4 VCC1.8 2^,52,59 13 1 R438
VIN VOUT 14 2 J19
TAB 2^,48,50 VEE12 330
15 3 1.5mOhm 2512 DNI
1 R405 PS_ON# 16 4
GND 2^,35 PS_ON#
C298 0 Ohm 17 5 R430 3 1
1uF 18 6 4 2
LD1117ADT18
19 7
ATX_ACFAIL# 20 8 ATX_POWER_OK 1.5mOhm 2512 DNI
21 9 Vert. Dual Row Hdr 2x2
C291 22 10 C309 C297
10uF 23 11 22uF C308 22uF C303 Molex
24 12 25V 100nF 25V 100nF 44472-0451
Vert. Dual Row HDR
1
C + C333 NI + C332 + C324 C
C329 C330 100uF C342 JP2 39-29-9246 100uF C325 100uF C343
10uF 100nF 35V 100nF JUMPER 35V 100nF 35V 100nF
2
S2 C326 C345
TP30 C341 10uF 10uF
rnd_1mm 10uF SHUNT
VCC3.3 VCC1.5 J25
U49
1 1 PWRBTN# 2^,35,36,48
VIN 3 2
VOUT VCC1.5 2^,59
JUMP FOR FORCED
4 POWER SUPPLY ON.
C304 GND OPEN FOR SOFT ON
TAB OPERATION.
330nF C296 PUSH BUTTON PWR SWITCH
LD29080DT15R 10uF Molex
22-23-2021
VCC3.3SBY Crowbar
C833 R729
1uF 1M Ohm VCC12 VCC5 VCC3.3
TP27
VCC3.3SBY
rnd_1mm R735
2
VCC5SBY 249K 1
Q69
U50
4
PMV65XP
C853
3
B 3 2 Q72 Q34 Q32 Q29 B
Vin Vout1 VCC3.3SBY 2^,39,40,41,47,52 R726 R471 R461
1 BSS138 1 FDD8778 1 FDD8778 1 FDD8778
3
1 4 249K 249K 249K
3
C294 GND Vout2 R716 10uF
TAB R725
1uF 0 Ohm Q73
1 249K
LD1117AS33 PWR_OK 2N7002/SOT
R736
3
1M Ohm R483 R478 R467
2
R733 MMBT3904 1 MMBT3904 1 MMBT3904 1

C798 47K Q70 Q33 Q31 Q30
10uF 1 2N7002/SOT 4.99K 4.99K 4.99K
R485 R479 R468
2
0.3 Ohm 0.3 Ohm 0.3 Ohm
2
VCC12 VCC5
VCC12 VCC5 VCC3.3
VCC12_AUX VCC5SBY VCC3.3
Loads for ATX parasitic leakages. MH2 MH9 MH8 MH6 MH5 MH7 MH4 MH10 MH1 MH3
2^,28,31,32,33,37 VCC12_AUX
R444 R460 R459
330 330 330
2^,23,39,40,41,46,48,50 VCC12
1W .25W
VCC3.3 0.170 0.170 0.170 0.170 0.170 0.170 0.170 0.170 0.170 0.170
2^,19,28,29,30,31,32,33,34,36,48 VCC5SBY
Silicon ID Tag
2^,12,19,27,34,43,45,46,48,50,56,57,58 VCC5
R473
3.83K
,39,40,41,43,44,45,46,47,48,51,52,54,56,57,58,59,60,61,62 VCC3.3
U64
TECHNOLOGIES
2^,59 ID_TAG
1 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
I/O TITLE
SAME IS PROECTEDTO THE EXTENT PERMITTED
VCC3.3 3 UNDER THE LAWS OF THE UNITED STATES AND ENGR.
GND
2
2^,43,44,45 GND_EARTH ENG. APP.
VCC CONFIDENCE AND IS NOT TO BE COPIED,
REPRODUCED, REVEALED TO OR APPROPRIATED ATX Power Connector, Crowbar
DS2411R PROD. APP.
C337 BY OTHERS, IN PART OR IN WHOLE, WITHOUT
1,43,44,45,46,47,48,49,50,51,52,54,56,57,58,59,60,61,62 DGND THE EXPRESS CONSENT OF BALLY. THIS PRINT
100nF MATL. APP.
PCA212268-2-1 1/1 1/1 53 62
5 4 3 2 1
5 4 3 2 1
D D
2^,57,58,59 LD3.3V_[16..31]
VCC3.3 VCC3.3
10
10
5
5
RP32 RP33
4.7K 4.7K
U91 U90
18 LD3.3V_16 18 LD3.3V_24
O0 O0
9
RP19 16 LD3.3V_17 RP17 16 LD3.3V_25
DOOR_SW0 8 1 DOOR_SW0_R 2 O1 DOOR_SW7 8 1 DOOR_SW7_R 2 O1
DOOR_SW1 7 2 DOOR_SW1_R 4 I0 14 LD3.3V_18 DOOR_SW8 7 2 DOOR_SW8_R 4 I0 14 LD3.3V_26
DOOR_SW2 6 3 DOOR_SW2_R 6 I1 O2 DOOR_SW9 6 3 DOOR_SW9_R 6 I1 O2
DOOR_SW3 5 4 DOOR_SW3_R 8 I2 12 LD3.3V_19 DOOR_SW10 5 4 DOOR_SW10_R 8 I2 12 LD3.3V_27
I3 O3 I3 O3
330 3 LD3.3V_20 330 3 LD3.3V_28
O4 O4
RP18 5 LD3.3V_21 RP16 5 LD3.3V_29
DOOR_SW4 8 1 DOOR_SW4_R 17 O5 DOOR_SW11 8 1 DOOR_SW11_R 17 O5
C DOOR_SW5 7 2 DOOR_SW5_R 15 I4 7 LD3.3V_22 7 2 15 I4 7 LD3.3V_30 C
DOOR_SW6 6 3 DOOR_SW6_R 13 I5 O6 PRSNT#_SLOT0 6 3 PRSNT#_SLOT0_R 13 I5 O6
I6 2^,40 PRSNT#_SLOT0 I6
2^,44 TEST_SWITCH#
5 4 TEST_SWITCH#_R 11 9 LD3.3V_23 2^,18,39 PEG_ENABLE# PEG_ENABLE# 5 4 PEG_ENABLE#_R 11 9 LD3.3V_31
I7 O7 VCC3.3 I7 O7 VCC3.3
330 330
2^,59 PLAYERSW/DOORS_OE# PLAYERSW/DOORS_OE# 1 20 PLAYERSW/DOORS_OE# 1 20
OE1 Vcc OE1 Vcc
ADDR 0X108 ADDR 0X108
19 10 19 10
OE2 GND C351 OE2 GND C350
100nF 100nF
74LCX244 74LCX244
Logic Door
J7
1 LOGIC_DOOR_SW0
2 LOGIC_DOOR_SW0 2^,48
2-Pin
DOOR SWITCH MAPPING
DOORSW0 = PROCESSOR/LOGIC DOOR
B DOORSW1 = CASHBOX DOOR B
DOORSW2 = CASHBOX PRESENT

DOORSW3 = COIN TRAY PRESENT/SPARE
DOORSW4 = DROP DOOR
DOORSW5 = LOWER DOOR 2^,48 DOOR_SW[0..11]
DOORSW6 = BELLY DOOR
DOOR_SW0
DOORSW7 = UPPER DOOR DOOR_SW1
DOORSW8 = BONUS TOP BOX DOOR DOOR_SW2
DOOR_SW3
DOORSW9 = RCU DOOR DOOR_SW4
DOORSW10 = BONUS RCU DOOR DOOR_SW5
DOORSW11 = TOP BOX DOOR DOOR_SW6
DOOR_SW7
DOOR_SW8
DOOR_SW9
DOOR_SW10
DOOR_SW11
VCC3.3
2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,48,51,52,53,56,57,58,59,60,61,62 VCC3.3
TECHNOLOGIES
2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,49,50,51,52,53,56,57,58,59,60,61,62 DGND NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Game Door, Test Switch,
PROD. APP.
Card Detect
MATL. APP.
PCA212268-2-1 1/1 1/1 54 62
5 4 3 2 1
5 4 3 2 1
Input Buffers Output Buffers

INPUT BUFFERS OUTPUT BUFFERS
BUF_METER[0..7]
BUF_METER[0..7] BUF_METER[0..7] 2^,48!
2^,48! COIN_CHUTE0 COIN_CHUTE0 BUF_HOP_COIN_OUT BUF_HOP_COIN_OUT 2^,59!

BUF_COIN_DIV_EN BUF_COIN_DIV_EN 2^,48!
2^,48! COIN_CHUTE1 COIN_CHUTE1 METER[0..7]
2^,59! METER[0..7] METER[0..7]
2^,52! BATT_LOW0# BATT_LOW0# BUF_COIN_DIV_DIR BUF_COIN_DIV_DIR 2^,48!
BUF_HOP_SENSOR_SPARE BUF_HOP_SENSOR_SPARE 2^,59!
2^,52! BATT_LOW1# BATT_LOW1#
BUF_COIN_INHIBIT BUF_COIN_INHIBIT 2^,48!
D
2^,48! HOP_COIN_OUT HOP_COIN_OUT D
2^,48! HOP_SENSOR_SPARE HOP_SENSOR_SPARE BUF_HOP_FULL BUF_HOP_FULL 2^,59! BUF_BVAL_MRST# BUF_BVAL_MRST# 2^,48!
2^,48! HOP_FULL HOP_FULL 2^,37! BUF_PCI_RESET# BUF_PCI_RESET#

BUF_PRN_MRST# BUF_PRN_MRST# 2^,48!
PLAYERSW[0..15]
2^,48! PLAYERSW[0..15] PLAYERSW[0..15]
BUF_COIN_TILT BUF_COIN_TILT 2^,59!
2^,48! COIN_DIV_FLAG COIN_DIV_FLAG
ASPARE[0..2]
2^,48! ASPARE[0..2] ASPARE[0..2]
2^,59! PERIPH_RESET# PERIPH_RESET# BUF_HOP_ENABLE BUF_HOP_ENABLE 2^,48!
2^,48! HANDLE_OPTIC HANDLE_OPTIC BUF_HANDLE_OPTIC BUF_HANDLE_OPTIC 2^,59!
2^,48! COIN_SENSE COIN_SENSE BUF_HOP_PHASE BUF_HOP_PHASE 2^,48!
2^,48! COIN_TILT COIN_TILT

BUF_COIN_SENSE BUF_COIN_SENSE 2^,59! 2^,35,44!,53!,59! PWR_OK PWR_OK BUF_HOP_BRAKE BUF_HOP_BRAKE 2^,48!
2^,48! COIN_CREDIT0 COIN_CREDIT0
2^,48! COIN_CREDIT1 COIN_CREDIT1 BUF_HOP_MODE BUF_HOP_MODE 2^,48!
2^,48! METER_SENSE METER_SENSE BUF_COIN_CREDIT0 BUF_COIN_CREDIT0 2^,59!

2^,59! 0X104_OUT_CLK 0X104_OUT_CLK BUF_DOOR_MODE BUF_DOOR_MODE 2^,48!
2^,48! DOOR_BAT_LOW# DOOR_BAT_LOW#
USB_EN#[0..3]
2^,23,35 OTEMP# OTEMP# USB_EN#[0..3] USB_EN#[0..3] 2^,43!
BUF_COIN_CREDIT1 BUF_COIN_CREDIT1 2^,59!
KEY_SW[0..3]
2^,48! KEY_SW[0..3] KEY_SW[0..3] USB_EN#[4..7]
2^,59! 0X10C_OUT_CLK 0X10C_OUT_CLK USB_EN#[4..7] USB_EN#[4..7] 2^,48!
2^,26! CD_DET1# CD_DET1#
BUF_PLYRLAMP[0..15]
2^,26! CD_DET2# CD_DET2# BUF_COIN_CHUTE0 BUF_COIN_CHUTE0 2^,59! BUF_PLYRLAMP[0..15] BUF_PLYRLAMP[0..15] 2^,48!
2^,59! PLAYERSW/DOORS_OE# PLAYERSW/DOORS_OE#

LD3.3V_[0..23] BUF_PRNLAMP BUF_PRN_LAMP 2^,48!
C C
BUF_COIN_CHUTE1 BUF_COIN_CHUTE1 2^,59!
VCC3.3 VCC5 BUF_BVAL_LAMP BUF_BVAL_LAMP 2^,48!
VCC5 VCC3.3
2^,59! 0X100_OE# 0X100_OE#
BUF_HANDLE_SOL BUF_HANDLE_SOL 2^,48!
2^,59! 0X110_OE# 0X110_OE# VCC5 VCC5
LD3.3V_[28..31] BUF_TWRLAMP[0..3]
2^,54!,57!,59! LD3.3V_[28..31] LD3.3V_[28..31] VCC3.3 BUF_TWRLAMP[0..3] BUF_TWRLAMP[0..3] 2^,48!
LD3.3V_[0..15] VCC3.3
LD3.3V_[0..15] DGND
COIN_DIV_LED COIN_DIV_LED 2^,48!
DGND
57 Input Buffers
BUF_PERIPHERAL_RESET# BUF_PERIPHERAL_RESET# 2^,48!
2^,51!,54!,57!,58!,59! LD3.3V_[0..23]
LD3.3V_[0..23]
58 Output Buffers
Misc. Comm. Buffers

MISC COMMUNICATIONS I/O
SPI_MOSI_P[0..3] BUF_SPI_MISO_P[0..3]
2^,59! SPI_MOSI_P[0..3] SPI_MOSI_P[0..3] BUF_SPI_MISO_P[0..3] BUF_SPI_MISO_P[0..3] 2^,59!
SPI_SCK_P[0..3]
2^,59! SPI_SCK_P[0..3] SPI_SCK_P[0..3]
SPI_CS_P[0..3] BUF_SPI_CS_P[0..3]
2^,59! SPI_CS_P[0..3] SPI_CS_P[0..3] BUF_SPI_CS_P[0..3] BUF_SPI_CS_P[0..3] 2^,48!
SPI_MISO_P[0..3]
2^,48! SPI_MISO_P[0..3] SPI_MISO_P[0..3]
BUF_SPI_MOSI_P[0..3] BUF_SPI_MOSI_P[0..3] 2^,48!
B
2^,48!,56! SLA_SDA SLA_SDA B
2^,48!,56! SLA_SCL SLA_SCL BUF_SPI_SCK_P[0..3]

BUF_SPI_SCK_P[0..3] BUF_SPI_SCK_P[0..3] 2^,48!
2^,59! SLAD_SDA# SLAD_SDA#
2^,59! SLAD_SCL# SLAD_SCL#

BUF_TXD_TTL_SP5 BUF_TXD_TTL_SP5 2^,48!
2^,61! RTS_TTL_EXAR_SP5# RTS_TTL_EXAR_SP5#

2^,61! TXD_TTL_EXAR_SP5 TXD_TTL_EXAR_SP5 BUF_RXD_TTL_SP5 BUF_RXD_TTL_SP5 2^,59!,61!
2^,59!,61! RXD_TTL_EXAR_SP5 RXD_TTL_EXAR_SP5

2^,48! RXD_TTL_SP5 RXD_TTL_SP5 BUF_RTS_TTL_SP5 BUF_RTS_TTL_SP5 2^,48!
2^,59! RTS_TTL_SP5# RTS_TTL_SP5#

2^,59! TXD_TTL_SP5 TXD_TTL_SP5 BUF_iBUTTON1 BUF_iBUTTON1 2^,48!,56!
2^,59! iBUTTON1_OUT iBUTTON1_OUT

BUF_iBUTTON2 BUF_iBUTTON2 2^,48!,56!
2^,59! iBUTTON1_IN iBUTTON1_IN
2^,59! iBUTTON1_OE iBUTTON1_OE
BUF_ACFAIL# BUF_ACFAIL# 2^,48!
2^,59! iBUTTON2_OUT iBUTTON2_OUT
2^,59! iBUTTON2_IN iBUTTON2_IN
BUF_FPGA_SPARE_OUT BUF_FPGA_SPARE_OUT 2^,48!
2^,59! iBUTTON2_OE iBUTTON2_OE
VCC5 VCC3.3
2^,53! ACFAIL# ACFAIL#
BUF_FPGA_SPARE_IN BUF_FPGA_SPARE_IN 2^,59!
A
2^,59! FPGA_SPARE_OUT FPGA_SPARE_OUT A
,53!,56!,57!,58! VCC5 2^,48! FPGA_SPARE_IN FPGA_SPARE_IN
BUF_SLA_SCL BUF_SLA_SCL 2^,59!
TECHNOLOGIES
2^,48! AC_DETECT TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
AC_DETECT TITLE
!,61!,62! VCC3.3 SAME IS PROECTEDTO THE EXTENT PERMITTED
VCC5 VCC5
BUF_SLA_SDA BUF_SLA_SDA 2^,59! NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
!,61!,62! DGND VCC3.3 ENG. APP.
VCC3.3 CONFIDENCE AND IS NOT TO BE COPIED,
REPRODUCED, REVEALED TO OR APPROPRIATED I/O Buffer Hierarchy
BUF_AC_DETECT 2^,59! PROD. APP.
DGND BUF_AC_DETECT BY OTHERS, IN PART OR IN WHOLE, WITHOUT
56 Misc Communications I/O IT WILL NOT BE USED IN ANY MANNER Q.A. APP.
PCA212268-2-1 1/1 1/1 55 62
5 4 3 2 1
5 4 3 2 1
VCC5
VCC3.3
R765
VCC3.3 4.7K
D R759 D
55^,59 SPI_SCK_P[0..3] BUF_SPI_SCK_P[0..3] 48,55^ 55^,59 iBUTTON1_OE 4.7K

U89 SLA_SDA SLA_SDA 48,55^
3
VCC3.3 R769
SPI_SCK_P0 2 18 BUF_SPI_SCK_P0 U82A 3.83K 1 MMBT3904
A1 Y1 55^,59 SLAD_SDA#
1
SPI_SCK_P1 4 16 BUF_SPI_SCK_P1 14 Q80
SPI_SCK_P2 6 A2 Y2 14 BUF_SPI_SCK_P2 R762 4.7K
2
SPI_SCK_P3 8 A3 Y3 12 BUF_SPI_SCK_P3 2 3
A4 Y4 55^,59 iBUTTON1_OUT BUF_iBUTTON1 48,55^
SPI_CS_P0 11 9 BUF_SPI_CS_P0
SPI_CS_P1 13 A5 Y5 7 BUF_SPI_CS_P1 7
SPI_CS_P2 15 A6 Y6 5 BUF_SPI_CS_P2
SPI_CS_P3 17 A7 Y7 3 BUF_SPI_CS_P3 VCC3.3 74LVC126
A8 Y8 VCC5
VCC3.3 VCC5
55^,59 SPI_CS_P[0..3]
1 20 BUF_SPI_CS_P[0..3] 48,55^
1OE VCC U82B VCC3.3
4
19 10 14
2OE GND C353 R764
100nF 55^,59 iBUTTON1_IN
6 5 4.7K
74ABT244A R758
7 4.7K
SLA_SCL SLA_SCL 48,55^
3
74LVC126
VCC3.3 1 MMBT3904
55^,59 SLAD_SCL# Q79
55^,59 iBUTTON2_OE R761 4.7K
2
VCC3.3 R768
U82C 3.83K
10
14
55^,59 iBUTTON2_OUT
9 8 BUF_iBUTTON2 48,55^
VCC5
7
VCC3.3
55^,59 SPI_MOSI_P[0..3] BUF_SPI_MOSI_P[0..3] 48,55^ VCC3.3 74LVC126
C U67 R763 C
4.7K
SPI_MOSI_P0 2 18 BUF_SPI_MOSI_P0 VCC3.3 R757
SPI_MOSI_P1 4 A1 Y1 16 BUF_SPI_MOSI_P1 U82D
13
A2 Y2 4.7K
SPI_MOSI_P2 6 14 BUF_SPI_MOSI_P2 14 BUF_RTS_TTL_SP5 48,55^
A3 Y3
3
SPI_MOSI_P3 8 12 BUF_SPI_MOSI_P3
11 A4 Y4 9 11 12 C901 1 MMBT3904
55^,59 TXD_TTL_SP5 A5 Y5 BUF_TXD_TTL_SP5 48,55^ 55^,59 iBUTTON2_IN 55^,59 RTS_TTL_SP5# Q78
53,55^ ACFAIL#
13 7 BUF_ACFAIL# 48,55^ 100nF
15 A6 Y6 5 7 R760 4.7K
2
17 A7 Y7 3
A8 Y8 VCC5 74LVC126
1 20
1OE VCC
19 10
2OE GND C889
100nF
74ABT244A
VCC5
10
RP31
4.7K
BUF_SPI_MISO_P[0..3] 55^,59 VCC3.3 VCC3.3
U92
48,55^ SPI_MISO_P[0..3]
18 BUF_SPI_MISO_P0
9
B O0 U76 C896 B
RP21 16 BUF_SPI_MISO_P1 1 8 100nF
SPI_MISO_P0 8 1 2 O1 1OE VCC
SPI_MISO_P1 7 2 4 I0 14 BUF_SPI_MISO_P2 SLA_SDA 2 7
SPI_MISO_P2 6 3 6 I1 O2 1A 2OE
SPI_MISO_P3 5 4 8 I2 12 BUF_SPI_MISO_P3 3 6
I3 O3 55^,59 BUF_SLA_SCL 2Y 1Y BUF_SLA_SDA 55^,59
220 3 BUF_RXD_TTL_SP5 55^,59,61
4 5 SLA_SCL
O4 GND 2A
RP20 5 BUF_AC_DETECT 55^,59 74LVC2G126
8 1 17 O5
48,55^ RXD_TTL_SP5 I4
48,55^ AC_DETECT
7 2 15 7 R486 0 Ohm BUF_FPGA_SPARE_IN 55^,59
6 3 13 I5 O6
48,55^ FPGA_SPARE_IN I6
55^,59 FPGA_SPARE_OUT
5 4 11 9 BUF_FPGA_SPARE_OUT 48,55^
I7 O7 VCC3.3
220
1 20
OE1 Vcc
19 10
OE2 GND C352
100nF
74LCX244
55^,61 RTS_TTL_EXAR_SP5# R682 0 Ohm - DNI RTS_TTL_SP5#
Stuffing option for Exar PCI UARTs. FPGA must
be configured to drive it's UART outputs in
high impedance if Exar UARTs are to be used. R683 0 Ohm - DNI TXD_TTL_SP5
55^,61 TXD_TTL_EXAR_SP5
55^,59,61 RXD_TTL_EXAR_SP5 BUF_RXD_TTL_SP5
VCC5 VCC3.3

12,19,27,34,43,45,46,48,50,53,55^,57,58 VCC5
TECHNOLOGIES
8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,48,51,52,53,54,55^,57,58,59,60,61,62 VCC3.3 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,49,50,51,52,53,54,55^,57,58,59,60,61,62 DGND NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Misc. Communication Buffers
PROD. APP.
PCA212268-2-1 1/1 1/1 56 62
5 4 3 2 1
5 4 3 2 1
VCC5
10
5
RP34
4.7K U93
18 BUF_HOP_COIN_OUT 55^,59
O0
RP13 16 BUF_HOP_SENSOR_SPARE 55^,59
9
8 1 HOP_COIN_OUT_R 2 O1
48,55^ HOP_COIN_OUT I0
48,55^ HOP_SENSOR_SPARE
7 2 HOP_SENSOR_SPARE_R 4 14 BUF_HOP_FULL 55^,59
6 3 HOP_FULL_R 6 I1 O2
48,55^ HOP_FULL I2
48,55^ HANDLE_OPTIC 5 4 HANDLE_OPTIC_R 8 12 BUF_HANDLE_OPTIC 55^,59
D I3 O3 D
330 3 BUF_COIN_TILT 55^,59 VCC3.3
O4
RP12 5 BUF_COIN_CREDIT0 55^,59
8 1 COIN_TILT_R 17 O5
48,55^ COIN_TILT I4
48,55^ COIN_CREDIT0
7 2 COIN_CREDIT0_R 15 7 BUF_COIN_CREDIT1 55^,59
6 3 COIN_CREDIT1_R 13 I5 O6
10
48,55^ COIN_CREDIT1 I6
5
48,55^ COIN_SENSE
5 4 COIN_SENSE_R 11 9 BUF_COIN_SENSE 55^,59
I7 O7 VCC3.3 RP30
330 4.7K
1 20
OE1 Vcc U88
19 10 48,55^ PLAYERSW[0..15] 18 LD3.3V_0
OE2 GND C354 O0
9
100nF RP15 16 LD3.3V_1
VCC3.3 PLAYERSW0 8 1 PLAYERSW0_R 2 O1
74LVT244 I0
PLAYERSW1 7 2 PLAYERSW1_R 4 14 LD3.3V_2
PLAYERSW2 6 3 PLAYERSW2_R 6 I1 O2
PLAYERSW3 5 4 PLAYERSW3_R 8 I2 12 LD3.3V_3
I3 O3
330 3 LD3.3V_4
10
51,55^,58,59 LD3.3V_[0..15] O4
5
RP26 RP14 5 LD3.3V_5
PLAYERSW4 8 1 PLAYERSW4_R 17 O5
4.7K I4
PLAYERSW5 7 2 PLAYERSW5_R 15 7 LD3.3V_6
U70 PLAYERSW6 6 3 PLAYERSW6_R 13 I5 O6
18 LD3.3V_0 PLAYERSW7 5 4 PLAYERSW7_R 11 I6 9 LD3.3V_7
O0 I7 O7 VCC3.3
1
9
RP11 16 LD3.3V_1 330
8 1 2 O1 PLAYERSW/DOORS_OE# 1 20
7 2 4 I0 14 LD3.3V_2 OE1 Vcc
I1 O2 ADDR 0X108
6 3 6 19 10
5 4 DOOR_BAT_LOW#_R 8 I2 12 LD3.3V_3 OE2 GND C349
48,55^ DOOR_BAT_LOW# I3 O3 VCC3.3 100nF
330 3 LD3.3V_4 74LCX244
O4
C RP10 5 LD3.3V_5 C
8 1 BATT_LOW1#_R 17 O5
52,55^ BATT_LOW1# I4
7 2 BATT_LOW0#_R 15 7 LD3.3V_6
10
52,55^ BATT_LOW0# I5 O6
5
23,35,55^ OTEMP#
6 3 OTEMP#_R 13
5 4 COIN_DIV_FLAG_R 11 I6 9 LD3.3V_7 RP27
48,55^ COIN_DIV_FLAG I7 O7 VCC3.3 4.7K
330
0X100_OE# 1 20 U69
OE1 Vcc 18 LD3.3V_8
ADDR 0X100 O0
19 10
9
OE2 GND C884 RP9 16 LD3.3V_9
100nF PLAYERSW8 8 1 PLAYERSW8_R 2 O1
74LCX244 I1 O2
PLAYERSW10 6 3 PLAYERSW10_R 6
I3 O3
330 3 LD3.3V_12
O4
RP8 5 LD3.3V_13
PLAYERSW12 8 1 PLAYERSW12_R 17 O5
PLAYERSW14 6 3 PLAYERSW14_R 13 I5 O6
I7 O7 VCC3.3
330
VCC3.3 55^,59 PLAYERSW/DOORS_OE# PLAYERSW/DOORS_OE# 1 20
OE1 Vcc
ADDR 0X108
19 10
OE2 GND C885
VCC3.3 100nF
10
74LCX244
5
RP29
4.7K
10
U68
5
B 18 LD3.3V_8 RP28 B
O0
4.7K
1
RP5 16 LD3.3V_9
8 1 METER_SENSE_R 2 O1 U72
48,55^ METER_SENSE I0
7 2 4 14 LD3.3V_10 18
I1 O2 O0 BUF_COIN_CHUTE0 55^,59
26,55^ CD_DET1#
6 3 CD_DET1#_R 6
9
5 4 CD_DET2#_R 8 I2 12 LD3.3V_11 RP7 16
26,55^ CD_DET2# I3 O3 O1 BUF_COIN_CHUTE1 55^,59
48,55^ COIN_CHUTE0
8 1 COIN_CHUTE0_R 2
330 3 LD3.3V_12 7 2 COIN_CHUTE1_R 4 I0 14
O4 48,55^ COIN_CHUTE1 I1 O2
48,55^ KEY_SW[0..3] 6 3 6
RP4 5 LD3.3V_13 5 4 8 I2 12
KEY_SW0 8 1 KEY_SW0_R 17 O5 I3 O3
KEY_SW1 7 2 KEY_SW1_R 15 I4 7 LD3.3V_14 330 3 LD3.3V_28
KEY_SW2 6 3 KEY_SW2_R 13 I5 O6 O4
KEY_SW3 5 4 KEY_SW3_R 11 I6 9 LD3.3V_15 RP6 5 LD3.3V_29
I7 O7 VCC3.3 8 1 17 O5
48,55^ ASPARE[0..2] I4
330 ASPARE0 7 2 ASPARE0_R 15 7 LD3.3V_30
0X100_OE# 1 20 ASPARE1 6 3 ASPARE1_R 13 I5 O6
55^,59 0X100_OE# OE1 Vcc I6
ADDR 0X100 ASPARE2 5 4 ASPARE2_R 11 9 LD3.3V_31
19 10 I7 O7 VCC3.3
OE2 GND C887 330
100nF 1 20
OE1 Vcc
74LCX244
55^,59 0X110_OE# ADDR 0X110 19 10
OE2 GND C886
100nF
74LCX244
54,55^,59 LD3.3V_[28..31]
VCC5 VCC3.3
12,19,27,34,43,45,46,48,50,53,55^,56,58 VCC5
TECHNOLOGIES
8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,48,51,52,53,54,55^,56,58,59,60,61,62 VCC3.3
ENG. APP.
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,49,50,51,52,53,54,55^,56,58,59,60,61,62 DGND REPRODUCED, REVEALED TO OR APPROPRIATED Input Buffers
PROD. APP.
PCA212268-2-1 1/1 1/1 57 62
5 4 3 2 1
5 4 3 2 1
U66
VCC3.3
51,54,55^,57,59 LD3.3V_[0..23] BUF_PLYRLAMP[0..15] 48,55^
LD3.3V_0 3 2 BUF_COIN_DIV_EN 48,55^
U75 U86 LD3.3V_1 4 D1 Q1 5
D2 Q2 BUF_COIN_DIV_DIR 48,55^
CLAMP 9 LD3.3V_2 7 6
LD3.3V_0 3 2 D_LD3.3V_0 1 16 BUF_PLYRLAMP0 LD3.3V_3 8 D3 Q3 9 COIN_INHIBIT# C888
D LD3.3V_1 4 D1 Q1 5 D_LD3.3V_1 2 15 BUF_PLYRLAMP1 LD3.3V_4 13 D4 Q4 12 BVAL_MRST# 100nF D
D2 Q2 D5 Q5 BUF_BVAL_MRST# 48,55^
LD3.3V_2 7 6 D_LD3.3V_2 3 14 BUF_PLYRLAMP2 LD3.3V_5 14 15 U71A
LD3.3V_3 8 D3 Q3 9 D_LD3.3V_3 4 13 BUF_PLYRLAMP3 LD3.3V_6 17 D6 Q6 16 PRN_MRST# 14
D4 Q4 D7 Q7 R756
LD3.3V_4 13 12 D_LD3.3V_4 5 12 BUF_PLYRLAMP4 LD3.3V_7 18 19
LD3.3V_5 14 D5 Q5 15 D_LD3.3V_5 6 11 BUF_PLYRLAMP5 D8 Q8 VCC5 BVAL_MRST# 1 2 Q77
LD3.3V_6 17 D6 Q6 16 D_LD3.3V_6 7 10 BUF_PLYRLAMP6 BC817-40L
LD3.3V_7 18 D7 Q7 19 D_LD3.3V_7 8 0X104_OUT_CLK 11 20 7
D8 Q8 GND 55^,59 0X104_OUT_CLK CLK VCC 3.3K
VCC5
ULN2003A RESET# 1 10 74LVC04/SO
0X10C_OUT_CLK 11 20 CLR GND C882
55^,59 0X10C_OUT_CLK CLK VCC 100nF
RESET# 1 10 74ABT273A/SO
CLR GND C895
100nF
74AHCT273 VCC3.3
BUF_PRN_MRST# 48,55^
U71B
14
R754
U65
PRN_MRST# 3 4 Q75
U85 LD3.3V_8 3 2 BC817-40L
D1 Q1 BUF_HOP_ENABLE 48,55^
U74 CLAMP 9 LD3.3V_9 4 5 BUF_HOP_MODE 48,55^
7
1 16 BUF_PLYRLAMP7 LD3.3V_10 7 D2 Q2 6 3.3K
D3 Q3 BUF_HOP_PHASE 48,55^
LD3.3V_8 3 2 D_LD3.3V_8 2 15 BUF_PLYRLAMP8 LD3.3V_11 8 9 BUF_HOP_BRAKE 48,55^ 74LVC04/SO
LD3.3V_9 4 D1 Q1 5 D_LD3.3V_9 3 14 BUF_PLYRLAMP9 LD3.3V_12 13 D4 Q4 12
D2 Q2 D5 Q5 BUF_DOOR_MODE 48,55^
BUF_PLYRLAMP_CLAMP
LD3.3V_10 7 6 D_LD3.3V_10 4 13 BUF_PLYRLAMP10 LD3.3V_13 14 15
LD3.3V_13 14 D5 Q5 15 D_LD3.3V_13 7 10 BUF_PLYRLAMP13 D8 Q8 VCC5
LD3.3V_14 17 D6 Q6 16 D_LD3.3V_14 8
D7 Q7 GND
LD3.3V_15 18 19 D_LD3.3V_15 0X104_OUT_CLK 11 20
D8 Q8 VCC5 ULN2003A CLK VCC
RESET# 1 10
0X10C_OUT_CLK 11 20 CLR GND C883
CLK VCC BUF_COIN_INHIBIT 48,55^
100nF
RESET# 1 10 74ABT273A/SO
C CLR GND R752 C
C894
100nF COIN_INHIBIT# Q74
74AHCT273 BC817-40L
4.7K
U77
U84
USB_EN#[0..3] 43,55^
CLAMP 9 LD3.3V_16 3 2 USB_EN#0
U94 1 16 BUF_PLYRLAMP14 LD3.3V_17 4 D1 Q1 5 USB_EN#1
2 15 BUF_PLYRLAMP15 LD3.3V_18 7 D2 Q2 6 USB_EN#2
LD3.3V_16 3 2 D_LD3.3V_16 3 14 LD3.3V_19 8 D3 Q3 9 USB_EN#3
D1 Q1 BUF_PRNLAMP 48,55^ D4 Q4 USB_EN#[4..7] 48,55^
LD3.3V_17 4 5 D_LD3.3V_17 4 13 BUF_BVAL_LAMP 48,55^ LD3.3V_20 13 12 USB_EN#4
LD3.3V_18 7 D2 Q2 6 BUF_HANDLE_SOL 5 12 LD3.3V_21 14 D5 Q5 15 USB_EN#5
LD3.3V_19 8 D3 Q3 9 6 11 LD3.3V_22 17 D6 Q6 16 VCC3.3
LD3.3V_20 13 D4 Q4 12 TWRLAMP0 7 10 LD3.3V_23 18 D7 Q7 19 BUF_PERIPHERAL_RESET# 48,55^
K
LD3.3V_21 14 D5 Q5 15 TWRLAMP1 8 D8 Q8 VCC5 U71C
D6 Q6 GND
LD3.3V_22 17 16 TWRLAMP2 D68 14
D7 Q7 R755
LD3.3V_23 18 19 TWRLAMP3 ULN2003A 24V 0X104_OUT_CLK 11 20
D8 Q8 VCC5 CLK VCC 5 6 Q76
55^,59 PERIPH_RESET#
RESET# 1 10 BC817-40L
A
0X10C_OUT_CLK 11 20 CLR GND C897 7

CLK VCC 100nF 3.3K
RESET# 1 10 74AHCT273 74LVC04/SO
CLR GND C355
100nF
74AHCT273
55^,59 METER[0..7] BUF_METER[0..7] 48,55^ VCC3.3

U83
B METER0 2 18 BUF_METER0 U71D B

METER1 4 A1 Y1 16 BUF_METER1 14
METER2 6 A2 Y2 14 BUF_METER2
METER3 8 A3 Y3 12 BUF_METER3 R480 0 9 8
METER5 13 A5 Y5 7 BUF_METER5 7
METER6 15 A6 Y6 5 BUF_METER6 74LVC04/SO
A8 Y8 VCC5
1 20 U78
1OE VCC U87 1 8 BUF_TWRLAMP2
19 10 1 8 BUF_TWRLAMP0 S1 D1_2
2OE GND C344 S1 D1_2 TWRLAMP2 2 7
100nF TWRLAMP0 2 7 G1 D1_1
74ABT244A G1 D1_1 3 6 BUF_TWRLAMP3
3 6 BUF_TWRLAMP1 S2 D2_2
S2 D2_2 TWRLAMP3 4 5 BUF_HANDLE_SOL
G2 D2_1 BUF_HANDLE_SOL 48,55^
TWRLAMP1 4 5
G2 D2_1
DUAL N CH MOSFET FDS6930B
DUAL N CH MOSFET FDS6930B
BUF_TWRLAMP[0..3] 48,55^
VCC5
BUF_TWRLAMP0
BUF_TWRLAMP1
R484
BUF_TWRLAMP2
COIN_DIV_LED 48,55^ BUF_TWRLAMP3
VCC3.3
150
VCC3.3
VCC3.3 VCC3.3 R766
4.7K - DNI
U71E U71F VCC5 VCC3.3
14 14 U98 C890
A 1 5 10nF ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE A
35,44,53,55^,59 PWR_OK
11 10 13 12
37,55^ BUF_PCI_RESET#
2
A
B
VCC
TECHNOLOGIES
7 7 12,19,27,34,43,45,46,48,50,53,55^,56,57 VCC5 TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
R767 0 Ohm 3 4 RESET# SAME IS PROECTEDTO THE EXTENT PERMITTED TITLE
74LVC04/SO 74LVC04/SO GND Y ENGR.
UNDER THE LAWS OF THE UNITED STATES AND
74LVC1G08 NEVADA. THIS INFORMATION IS DISCLOSED IN Alpha 2 iMPU, Marvell
8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,48,51,52,53,54,55^,56,57,59,60,61,62 VCC3.3 ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Output Buffers
PROD. APP.
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,49,50,51,52,53,54,55^,56,57,59,60,61,62 DGND IS LOANED ONLY AND RECIPIENT COVENANTS DWG. SIZE DWG. NO. REV.
PCA212268-2-1 1/1 1/1 58 62
5 4 3 2 1
5 4 3 2 1
VCC3.3
Bank 0 3.3 V Bank 1 1.8 V Bank 2 3.3 V Bank 3 3.3 V

VCC3.3 VCC1.8 VCC3.3 C857
U60D 100nF
G8
U60A GNDQ F6
E6 C844 C837 U60C C856 VMV3_0 R8
GNDQ
GNDQ
G15
F17
100nF U60B
V18
100nF GNDQ
T8
T15
100nF
VMV3_1
VCCI_B3_0
B2
C1
VCC3.3 Power/JTAG 2^,17,37,61,62 PCI_AD[0..31]
PCI_AD0
VMV0_0 H8 GNDQ H15 GNDQ R15 VCCI_B3_1 J8 PCI_AD1
VMV0_1 A3 VMV1_0 U15 VMV2_0 U6 VCCI_B3_2 K8 PCI_AD2
VCCI_B0_0 VCC3.3 VMV1_1 VMV2_1 VCCI_B3_3 VCC1.5
A20 B21 R9 N8 PCI_AD3
D VCCI_B0_1 VCCI_B1_0 VCC1.8 VCCI_B2_0 VCC3.3 VCCI_B3_4 D
H9 C22 R10 P8 PCI_AD4
VCCI_B0_2 H10 VCCI_B1_1 J15 VCCI_B2_1 R13 VCCI_B3_5 Y1 U60E PCI_AD5
VCCI_B0_3 H13 VCCI_B1_2 K15 VCCI_B2_2 R14 VCCI_B3_6 AA2 A19 C8 PCI_AD6
VCCI_B0_4 H14 VCCI_B1_3 N15 VCCI_B2_3 AB3 VCCI_B3_7 V5 B3 NC_0 VCC_0 C9 PCI_AD7
VCCI_B0_5 VCCI_B1_4 VCCI_B2_4 GEA0/IO188NDB3 PCI_DEVSEL# 2^,17,61,62 NC_1 VCC_1
D5 SPI_CS_P1 P15 AB20 V4 B19 C14 PCI_AD8
GAA0/IO00RSB0 VCCI_B1_5 VCCI_B2_5 GEA1/IO188PDB3 PCI_IRDY# 2^,17,61,62 NC_2 VCC_2
D6 LD3.3V_1 Y22 W 17 BUF_SPI_MISO_P1 U5 B20 C15 PCI_AD9
GAA1/IO01RSB0 VCCI_B1_6 GDA2/IO114RSB2 GEB0/IO189NDB3 PCI_C/BE0# 2^,17,61,62 NC_3 VCC_3
D7 LD3.3V_3 AA21 V16 U4 C3 H3 PCI_AD10
GAB0/IO02RSB0 VCCI_B1_7 GDB2/IO115RSB2 BUF_AC_DETECT 2^,56 GEB1/IO189PDB3 PCI_C/BE1# 2^,17,61,62 NC_4 VCC_4
E7 PCI CORE - A1 F18 W 15 R7 IDE_A_A1 C4 H20 PCI_AD11
GAB1/IO03RSB0 IO78NDB1 NVRAM_CS1# 2^,52 GDC2/IO116RSB2 ACFAIL# 2^,53 GEC0/IO190NPB3 NC_5 VCC_5
F8 LD3.3V_4 E18 AA18 RXD_TTL_SP9 T6 IDE_A_A0 C13 J10 PCI_AD12
GAC0/IO04RSB0 GBA2/IO78PDB1 NVRAM_CRE# 2^,52 IO117RSB2 GEC1/IO190PPB3 NC_6 VCC_6
F9 LD3.3V_8 G18 AB18 WAIT# Y2 C16 J11 PCI_AD13
GAC1/IO05RSB0 IO79NDB1 LBE_2# 2^,52 IO118RSB2 IO191NDB3 PCI_TRDY# 2^,17,61,62 NC_7 VCC_7
B4 IDE_B_A0 G17 AA17 TXD_TTL_SP9 W2 C17 J12 PCI_AD14
IO06RSB0 GBB2/IO79PDB1 LBE_1# 2^,52 IO119RSB2 IO191PDB3 PCI_PAR 2^,17,61,62 NC_8 VCC_8
A4 IDE_B_A1 G16 W 16 TXD_TTL_SP10 T7 IDE_A_A2 C19 J13 PCI_AD15
IO07RSB0 IO80NDB1 LBE_0# 2^,52 IO120RSB2 IO192NPB3 NC_9 VCC_9 VCC1.5
B5 IDE_B_A2 H16 LA24 AB17 RXD_TTL_SP10 VCC3.3 VCC3.3 T5 IDE_A_IOWG# C20 K9 PCI_AD16
IO08RSB0 GBC2/IO80PDB1 IO121RSB2 IO192PPB3 IDE_A_IOWG# 2^,26 NC_10 VCC_10
A5 IDE_B_IOW# F19 AA16 R6 IDE_A_IOW# C21 K14 PCI_AD17
IO09RSB0 IDE_B_IOW# 2^,25 IO81NDB1 NVRAM_WE# 2^,52 IO122RSB2 PERIPH_RESET# 2^,58 IO193NPB3 IDE_A_IOW# 2^,24 NC_11 VCC_11
C6 LD3.3V_0 E19 AB16 RXD_TTL_SP8 P7 IDE_WR_ENABLE D3 L9 PCI_AD18
IO10RSB0 IO81PDB1 NVRAM_ADV# 2^,52 IO123RSB2 IO193PPB3 NC_12 VCC_12
F7 LA3.3V_0 G19 T14 RD_CYC U3 D20 L14 PCI_AD19
IO11RSB0 IO82NPB1 LBE_3# 2^,52 IO124RSB2 IO194NPB3 PCI_C/BE2# 2^,17,61,62 NC_13 VCC_13
B6 IDE_B_IOWG# F20 V15 TXD_TTL_SP8 R749 R748 T4 D21 M9 PCI_AD20
IO12RSB0 IDE_B_IOWG# 2^,26 IO82PPB1 NVRAM_WAIT# 2^,52 IO125RSB2 IO194PPB3 SOFT_PWR_OFF 2^,35,53 NC_14 VCC_14
A6 J16 LA21 AB15 BUF_SPI_MISO_P2 10K 10K U2 Place on top of board D22 M14 C849 C848 PCI_AD21
IO13RSB0 IO83NPB1 IO126RSB2 IO195NDB3 PCI_C/BE3# 2^,17,61,62 NC_15 VCC_15
C7 LD3.3V_2 H17 LA25 AB14 BUF_SPI_MISO_P3 U1 in accessable area not E2 N9 100nF 10uF PCI_AD22
IO14RSB0 IO83PPB1 IO127RSB2 IO195PDB3 PCI_FRAME# 2^,17,61,62 restricted by Power NC_16 VCC_16
B7 F22 FPGA_1.8V_SPARE0 U14 OPER_TEST# R5 SPI_CS_P3 R432 E21 N14 PCI_AD23
IO15RSB0 D8 LD3.3V_6 IO84NDB1 E22 FPGA_1.8V_SPARE1 IO128RSB2 T13 USB_FLAG#4 IO196NPB3 P6 SPI_CS_P2 0 Ohm Supply or ETX Module F1 NC_17 VCC_17 P10 PCI_AD24
IO16RSB0 E8 LD3.3V_5 IO84PDB1 G21 LD31 IO129RSB2 W 14 USB_FLAG#5 IO196PPB3 R4 CLK_OUT F21 NC_18 VCC_18 P11 PCI_AD25
IO17RSB0 A7 IO85NDB1 G20 IO130RSB2 V14 IO197NPB3 R2 G3 NC_19 VCC_19 P12 PCI_AD26
IO18RSB0 IO85PDB1 NVRAM_CS0# 2^,52 IO131RSB2 USB_4_5_OC# 2^,18 IO197PPB3 PCI_STOP# 2^,17,61,62 NC_20 VCC_20 VCC3.3
B8 J17 LA22 AB13 T2 G22 P13 PCI_AD27
IO19RSB0 IO86NPB1 IO132RSB2 IO198NDB3 PCI_PERR# 2^,17,61,62 NC_21 VCC_21
A8 H18 AA13 T1 H1 R3 PCI_AD28
IO20RSB0 IO86PPB1 NVRAM_OE# 2^,52 IO133RSB2 IO198PDB3 PCI_SERR# 2^,17,35,61,62 NC_22 VCC_22
E9 LD3.3V_9 J19 LD27 U13 USB_FLAG#3 P3 SPI_SCK_P2 H2 R20 PCI_AD29
IO21RSB0 D9 LD3.3V_10 IO87NDB1 H19 LD30 IO134RSB2 W 13 USB_FLAG#2 IO199NDB3 P2 H21 NC_23 VCC_23 Y8 PCI_AD30
IO22RSB0 IO87PDB1 IO135RSB2 IO199PDB3 PCI_IRQA# 2^,17 NC_24 VCC_24
G9 LD3.3V_7 K19 LD23 R12 M2 PCI_AD25 H22 Y9 PCI_AD31
IO23RSB0 IO88NDB1 IO136RSB2 USB_2_3_OC# 2^,18 IO200NDB3 NC_25 VCC_25
B9 K18 LA20 U12 L2 PCI_AD21 J3 Y14
IO24RSB0 F10 LD3.3V_12 IO88PDB1 J22 LD29 IO137RSB2 V13 BAR_SELECT1 IO200PDB3 N1 PCI_AD29 J20 NC_26 VCC_26 Y15 C864 C876
IO25RSB0 A9 IO89NDB1 J21 LD28 IO138RSB2 AA12 BAR_SELECT0 IO201NDB3 N2 PCI_AD28 K3 NC_27 VCC_27 M6 4.7uF
IO26RSB0 IO89PDB1 IO139RSB2 IO201PDB3 NC_28 VCCPLF 100nF
E10 LD3.3V_13 K17 LA19 Y12 RXD_TTL_SP0 P4 PCI_AD31 L1 L7
IO27RSB0 D10 LD3.3V_14 IO90NPB1 J18 LA23 IO140RSB2 T12 METER7 IO202NDB3 P5 PCI_AD30 M1 NC_29 VCOMPLF T17 VJTAG
IO28RSB0 G10 LD3.3V_11 IO90PPB1 L15 LA14 IO141RSB2 W 12 BAR_SELECT2 IO202PDB3 N6 METER5 M22 NC_30 VJTAG U18 TRST
IO29RSB0 C10 LD3.3V_15 GCC0/IO91NPB1 K16 LA18 IO142RSB2 V12 TXD_TTL_SP0 IO203NDB3 N7 N3 NC_31 TRST V19 R474 33 OHM TDO
IO30RSB0 GCC1/IO91PPB1 IO143RSB2 IO203PDB3 RTS_TTL_SP5# 2^,56 NC_32 TDO
B10 L19 LD19 AB12 N5 PCI_AD26 N20 U17 VPUMP
IO31RSB0 GCB0/IO92NPB1 IO144RSB2 SLA_SCL 2^,56 IO204NDB3 NC_33 VPUMP
A10 L16 LA15 AB11 N4 PCI_AD27 P1 AA1
IO32RSB0 GCB1/IO92PPB1 IO145RSB2 SLA_SDA 2^,56 GFC2/IO204PDB3 NC_34 GND
G11 LD3.3V_16 L17 LA16 AA11 USB_FLAG#0 M7 METER4 P20 U16 TCK
IO33RSB0 E11 LD3.3V_18 GCA0/IO93NPB1 M16 LA11 IO146RSB2 R11 IO205NDB3 M8 METER3 R1 NC_35 TCK V17 TDI
IO34RSB0 GCA1/IO93PPB1 IO147RSB2 USB_0_1_OC# 2^,18 GFB2/IO205PDB3 NC_36 TDI
D11 LD3.3V_19 K20 LD24 Y11 M3 PCI_AD24 T3 W 18 TMS
IO35RSB0 IO94NPB1 IO148RSB2 SLB_SCL 2^,51 IO206NDB3 NC_37 TMS 2^,51,54,57,58 LD3.3V_[0..31]
F11 LD3.3V_17 M19 LD16 V11 USB_FLAG#1 M4 PCI_AD23 T20 AA22
IO36RSB0 C11 LD3.3V_20 GCA2/IO94PPB1 N16 LA7 IO149RSB2 AB10 GFA2/IO206PDB3 L5 18.432MHz_CLK U20 NC_38 GND AB1 R472 R466 R476 R477 C867 C870 LD3.3V_0
IO37RSB0 IO95NPB1 IO150RSB2 PWR_OK 2^,35,44,52,53,58 GFA0/IO207NDB3 NC_39 GND
H11 TXD_TTL_SP1 M15 LA10 U11 M5 PCI_AD22 V1 AB2 49.9 49.9 49.9 1K 330nF 10nF LD3.3V_1
IO38RSB0 GCB2/IO95PPB1 IO151RSB2 SLB_SDA 2^,51 GFA1/IO207PDB3 NC_40 GND
B11 L18 LA17 AA10 L4 PCI_AD19 V2 AB21 LD3.3V_2
IO39RSB0 IO96NPB1 IO152RSB2 ID_TAG 2^,53 GFB0/IO208NPB3 NC_41 GND
A11 M17 LA12 W 11 TXD_TTL_SP3 L6 METER2 V21 AB22 LD3.3V_3
IO40RSB0 A12 GCC2/IO96PPB1 L21 LD21 IO153RSB2 Y10 GFB1/IO208PPB3 L8 METER1 W1 NC_42 GND A1 R475 LD3.3V_4
IO41RSB0 IO97NDB1 IO154RSB2 SLAD_SDA# 2^,56 GFC0/IO209NPB3 NC_43 GND
F12 LD3.3V_22 L20 LD20 T11 TEST# K7 W3 A2 1K LD3.3V_5
IO42RSB0 IO97PDB1 IO155RSB2 GFC1/IO209PPB3 PCI_CLK 2^,60 NC_44 GND
C12 LD3.3V_25 K21 LD25 AB9 TXD_TTL_SP7 L3 PCI_AD20 W 20 A21 C334 C331 C336 LD3.3V_6
IO43RSB0 E12 LD3.3V_23 IO98NDB1 K22 LD26 IO156RSB2 V10 RXD_TTL_SP7 IO210NPB3 K4 PCI_AD16 W 21 NC_45 GND A22 150pF 150pF 150pF LD3.3V_7
IO44RSB0 D12 LD3.3V_24 IO98PDB1 L22 LD22 IO157RSB2 W 10 RXD_TTL_SP2 IO210PPB3 K2 PCI_AD17 W 22 NC_46 GND B1 LD3.3V_8
IO45RSB0 G12 LD3.3V_21 IO99NPB1 M21 LD18 IO158RSB2 U10 RXD_TTL_SP3 IO211NDB3 K1 PCI_AD18 Y3 NC_47 GND B22 LD3.3V_9
IO46RSB0 H12 RXD_TTL_SP1 IO99PPB1 N17 LA8 IO159RSB2 AA9 METER0 IO211PDB3 J1 PCI_AD14 Y13 NC_48 GND C5 LD3.3V_10
IO47RSB0 B12 IO100NPB1 M18 LA13 IO160RSB2 T10 TXD_TTL_SP2 IO212NDB3 J2 PCI_AD13 Y16 NC_49 GND C18 LD3.3V_11
IO48RSB0 F13 LD3.3V_27 IO100PPB1 N21 LD14 IO161RSB2 AB8 METER6 IO212PDB3 K5 PCI_AD15 Y17 NC_50 GND D4 LD3.3V_12
IO49RSB0 D13 LD3.3V_29 IO101NPB1 M20 LD17 IO162RSB2 V9 TXD_TTL_SP11 IO213NDB3 K6 Y19 NC_51 GND D19 LD3.3V_13
IO50RSB0 IO101PPB1 IO163RSB2 IO213PDB3 BUF_RXD_TTL_SP5 2^,56 NC_52 GND
E13 LD3.3V_28 N18 LA9 W9 G1 PCI_AD8 Y20 E3 LD3.3V_14
IO51RSB0 IO102NDB1 IO164RSB2 SLAD_SCL# 2^,56 IO214NDB3 NC_53 GND
G13 LD3.3V_26 N19 LD13 U9 RXD_TTL_SP11 G2 PCI_AD7 Y21 E20 LD3.3V_15
IO52RSB0 A13 IO102PDB1 P22 LD12 IO165RSB2 AA8 TXD_TTL_SP4 IO214PDB3 F3 PCI_AD4 AA3 NC_54 GND P14 LD3.3V_16
IO53RSB0 B13 IO103NDB1 N22 LD15 IO166RSB2 AB7 RXD_TTL_SP4 IO215NDB3 F2 PCI_AD5 AA14 NC_55 GND P9 LD3.3V_17
IO54RSB0 SPI_BIOS_WP# 2^,22 IO103PDB1 IO167RSB2 IO215PDB3 NC_56 GND
C D14 R21 LD8 V8 WR_CYC J7 RXD_TTL_SP6 AA15 V3 LD3.3V_18 C
IO55RSB0 F14 LD3.3V_31 IO104NDB1 P21 LD11 IO168RSB2 AA7 CFIFO_IN7 IO216NDB3 J6 TXD_TTL_SP6 AA19 NC_57 GND V20 LD3.3V_19
IO56RSB0 E14 IO104PDB1 T22 LD6 IO169RSB2 W8 CFIFO_IN5 IO216PDB3 J4 PCI_AD12 AA20 NC_58 GND W4 LD3.3V_20
IO57RSB0 B14 LA3.3V_23 IO105NDB1 R22 LD9 IO170RSB2 U8 CFIFO_IN8 IO217NDB3 H4 PCI_AD10 AB19 NC_59 GND W 19 LD3.3V_21
IO58RSB0 IO105PDB1 IO171RSB2 BUF_COIN_CHUTE0 2^,57 IO217PDB3 NC_60 GND
A14 LA3.3V_22 P17 LA5 W7 CFIFO_IN12 J5 PCI_AD11 J9 Y5 LD3.3V_22
IO59RSB0 IO106NDB1 IO172RSB2 BUF_HOP_FULL 2^,57 IO218NDB3 GND GND
G14 LD3.3V_30 P18 LA6 AB6 CFIFO_IN2 H5 PCI_AD9 J14 Y18 LD3.3V_23
IO60RSB0 IO106PDB1 IO173RSB2 BUF_COIN_TILT 2^,57 IO218PDB3 GND GND
D15 R19 LD7 Y7 CFIFO_IN1 E1 K10 L12 LD3.3V_24
IO61RSB0 0X110_OE# 2^,57 IO107NDB1 IO174RSB2 BUF_COIN_CREDIT0 2^,57 IO219NDB3 PCI_IDSEL0 2^,37 GND GND
F16 P19 LD10 AA6 CFIFO_IN3 D1 PCI_AD1 K11 L13 LD3.3V_25
IO62RSB0 BOARD_REV_ID# 2^,51 IO107PDB1 IO175RSB2 BUF_COIN_CREDIT1 2^,57 IO219PDB3 GND GND
B15 LA3.3V_25 U21 LD2 AB5 CFIFO_IN9 D2 PCI_AD2 K12 M10 LD3.3V_26
IO63RSB0 IO108NDB1 IO176RSB2 BUF_COIN_CHUTE1 2^,57 IO220NDB3 GND GND
A15 LA3.3V_24 T21 LD5 Y6 CFIFO_IN14 C2 PCI_AD0 K13 M11 LD3.3V_27
IO64RSB0 IO108PDB1 IO177RSB2 BUF_HANDLE_OPTIC 2^,57 IO220PDB3 GND GND
A16 V22 LD0 AA5 CFIFO_IN6 H6 L10 M12 LD3.3V_28
IO65RSB0 iBUTTON2_IN 2^,56 IO109NDB1 IO178RSB2 IO221NDB3 TXD_TTL_SP5 2^,56 GND GND
B16 U22 LD3 U7 CFIFO_IN10 H7 SPI_MOSI_P0 L11 M13 LD3.3V_29
IO66RSB0 iBUTTON1_IN 2^,56 IO109PDB1 IO179RSB2 IO221PDB3 GND GND
A17 R16 LA2 AB4 CFIFO_IN4 G4 PCI_AD6 N11 N10 LD3.3V_30
IO67RSB0 iBUTTON2_OE 2^,56 IO110NDB1 IO180RSB2 IO222NDB3 GND GND
B17 T16 LA0 AA4 CFIFO_IN11 G5 SPI_MOSI_P3 N12 N13 LD3.3V_31
IO68RSB0 iBUTTON1_OE 2^,56 IO110PDB1 IO181RSB2 BUF_HOP_SENSOR_SPARE 2^,57 IO222PDB3 GND GND
A18 T18 LA1 Y4 CFIFO_IN13 G7 FPGA_SPARE_OUT
IO69RSB0 iBUTTON2_OUT 2^,56 GDC0/IO111NDB1 IO182RSB2 BUF_HOP_COIN_OUT 2^,57 IO223NDB3 FPGA_SPARE_OUT 2^,56
B18 R18 LA3 V6 SPI_SCK_P3 G6 SPI_SCK_P1 A3P1000 FG484
IO70RSB0 iBUTTON1_OUT 2^,56 GDC1/IO111PDB1 IO184RSB2 GAC2/IO223PDB3
E17 P16 LA4 W5 CFIFO_IN0 F4 PCI_AD3
IO71RSB0 GDB0/IO112NPB1 IO183RSB2 BUF_COIN_SENSE 2^,57 IO224NDB3
F15 R17 V7 SPI_MOSI_P1 E4
GBC0/IO72RSB0 0X100_OE# 2^,57 GDB1/IO112PPB1 NVRAM_CLK 2^,52 GEC2/IO185RSB2 GAB2/IO224PDB3 BUF_PCI_RESET# 2^,37
E15 U19 LD1 T9 SPI_SCK_P0 F5 BUF_FPGA_SPARE_IN
GBC1/IO73RSB0 PLAYERSW/DOORS_OE# 2^,54,57 GDA0/IO113NDB1 GEA2/IO187RSB2 IO225NDB3 BUF_FPGA_SPARE_IN 2^,56
E16 T19 LD4 W6 SPI_CS_P0 E5 SPI_MOSI_P2
GBB0/IO74RSB0 0X104_OUT_CLK 2^,58 GDA1/IO113PDB1 GEB2/IO186RSB2 GAA2/IO225PDB3
D16
GBB1/IO75RSB0 0X10C_OUT_CLK 2^,58
D17 A3P1000 FG484 A3P1000 FG484 A3P1000 FG484
GBA0/IO76RSB0 D18 BUF_SPI_MISO_P0
GBA1/IO77RSB0
A3P1000 FG484
2^,52 LA[2..24]
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
Decoupling Capacitors LA14
VCC3.3 LA15
LA16
VCC1.5 LA17
LA18
LA19
R431 LA20
4.7K C318 LA21
10nF LA22
U57 LA23
1 4 C858 C851 C852 C847 C826 C866 C845 C846 C854 C825 C841 LA24
FPGA Test Header - 1 EN VCC 10uF 10nF 10nF 10nF 10nF 10nF
FPGA Test Header - 2 100nF 100nF 100nF 100nF 100nF
J20
2 3 18.432MHz_CLK
GND OUT
LA1 2 1 LA0 J21 FPGA JTAG Interface CWX823-18.432M
Keep clock trace as short as possible
LA3 4 3 LA2
LA5 6 5 LA4 J23
LA7 8 7 LA6 BAR_SELECT1 2 1 BAR_SELECT0
B B
LA9 10 9 LA8 CLK_OUT 4 3 BAR_SELECT2
LA11 12 11 LA10 WR_CYC 6 5 RD_CYC TCK 1 2
LA13 14 13 LA12 TEST# 8 7 WAIT# TDO 3 4 VCC1.8
LA15 16 15 LA14 FPGA_SPARE_OUT 10 9 OPER_TEST# TMS 5 6 VJTAG
2^,52 LD[0..31]
LA17 18 17 LA16 BUF_FPGA_SPARE_IN 12 11 VPUMP 7 8 TRST
LA19 20 19 LA18 14 13 TDI 9 10 LD0
LA21 22 21 LA20 LD1
LA23 24 23 LA22 LD2
LA25 26 25 LA24 3.3V DEBUG V-D/R Vert., DR Header C824 C861 C871 C829 C863 LD3
FPGA_1.8V_SPARE0 28 27 FPGA_1.8V_SPARE1 FCI AMP 10uF 100nF 100nF 10nF 10nF LD4
30 29 98424-G52-14ALF 5103308-1 LD5
LD6
LD7
LD8
1.8V DEBUG V-D/R LD9
FCI LD10
98424-G52-30ALF LD11
LD12
VCC3.3 LD13
LD14
LD15
LD16
LD17
LD18
C875 C823 C840 C830 C874 C821 C838 C873 C822 C865 C872 C859 C843 LD19
10uF 10uF 10uF 100nF 100nF 100nF 100nF 100nF 10nF 10nF 10nF 10nF 10nF LD20
LD21
LD22
LD23
LD24
LD25
LD26
LD27
LD28
LD29
VCC3.3 VCC1.8 VCC1.5 LD30
LD31
2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,48,51,52,53,54,56,57,58,60,61,62 VCC3.3
2^,52,53 VCC1.8
2^,56 BUF_SPI_MISO_P[0..3] RXD_TTL_SP[0..4] 2^,50 TXD_TTL_SP[6..11] 2^,50 2^,58 METER[0..7] 2^,56 SPI_SCK_P[0..3] 2^,53 VCC1.5
BUF_SPI_MISO_P0 RXD_TTL_SP0 TXD_TTL_SP6 METER0 SPI_SCK_P0 2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,49,50,51,52,53,54,56,57,58,60,61,62 DGND
BUF_SPI_MISO_P1 RXD_TTL_SP1 TXD_TTL_SP7 METER1 SPI_SCK_P1
RXD_TTL_SP4 TXD_TTL_SP10 METER4
TXD_TTL_SP11 METER5
2^,56 SPI_MOSI_P[0..3] METER6
METER7
SPI_MOSI_P0
SPI_MOSI_P1 TXD_TTL_SP[0..4] 2^,50 RXD_TTL_SP[6..11] 2^,50 2^,56 SPI_CS_P[0..3]
SPI_MOSI_P2 2^,43 USB_FLAG#[0..3]
SPI_MOSI_P3 TXD_TTL_SP0 RXD_TTL_SP6 SPI_CS_P0
TXD_TTL_SP1 RXD_TTL_SP7 USB_FLAG#0 SPI_CS_P1
2^,24,26 IDE_A_A[0..2]
A TXD_TTL_SP4 RXD_TTL_SP10 USB_FLAG#3 A
IDE_A_A0 RXD_TTL_SP11
IDE_A_A1
IDE_A_A2 2^,48 USB_FLAG#[4..7]
USB_FLAG#4
2^,25,26 IDE_B_A[0..2] USB_FLAG#5
IDE_B_A0
IDE_B_A1
IDE_B_A2

SHEET IS THE EXCLUSIVE PROPERTY OF BALLY D. LEBLANC 4/14/2011 Bally
TECHNOLOGIES
CONFIDENCE AND IS NOT TO BE COPIED, ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Actel FPGA
BY OTHERS, IN PART OR IN WHOLE, WITHOUT PROD. APP.
MATL. APP.
IS LOANED ONLY AND RECIPIENT COVENANTS
DWG. SIZE DWG. NO. REV.
IT WILL NOT BE USED IN ANY MANNER
Q.A. APP. C PCA212268-2-1 A
DETRIMENTAL TO THE INTEREST OF BALLY, AND
PCA212268-2-1 1/1 1/1 59 62
5 4 3 2 1
5 4 3 2 1
D D
EXAR OCTAL UART

EXAR QUAD UART
PCI_AD[0..31]
2^,17,37!,59!,61!,62! PCI_AD[0..31] PCI_AD[0..31] TXD_TTL_EXAR_SP[0..4]
TXD_TTL_EXAR_SP[0..4] TXD_TTL_EXAR_SP[0..4] 2^,50!
PCI_AD[0..31]
PCI_C/BE0# PCI_AD[0..31]
2^,17,59!,61!,62! PCI_C/BE0# PCI_C/BE0#
PCI_C/BE0# TXD_TTL_EXAR_SP8
PCI_C/BE1# RXD_TTL_EXAR_SP[0..4] PCI_C/BE0# TXD_TTL_EXAR_SP8
2^,17,59!,61!,62! PCI_C/BE1# PCI_C/BE1# RXD_TTL_EXAR_SP[0..4] RXD_TTL_EXAR_SP[0..4] 2^,50!
PCI_C/BE1#
PCI_C/BE2# PCI_C/BE1#
2^,17,59!,61!,62! PCI_C/BE2# PCI_C/BE2# TXD_TTL_EXAR_SP9
PCI_C/BE2# TXD_TTL_EXAR_SP9
RXD_TTL_EXAR_SP5 RXD_TTL_EXAR_SP5 2^,56! PCI_C/BE2#
2^,17,59!,61!,62! PCI_C/BE3# PCI_C/BE3#
PCI_C/BE3#
PCI_C/BE3#
PCI_CLK1 PCI_C/BE3# TXD_TTL_EXAR_SP10
PCI_CLK1 TXD_TTL_EXAR_SP10
TXD_TTL_EXAR_SP5 TXD_TTL_EXAR_SP5 2^,56!
PCI_CLK2
PCI_FRAME# PCI_CLK2
2^,17,59!,61!,62! PCI_FRAME# PCI_FRAME#
C PCI_FRAME# TXD_TTL_EXAR_SP11 C
PCI_IRDY# PCI_FRAME# TXD_TTL_EXAR_SP11
2^,17,59!,61!,62! PCI_IRDY# PCI_IRDY# RTS_TTL_EXAR_SP5# RTS_TTL_EXAR_SP5# 2^,56!
PCI_IRDY#
BUF_PCI_RESET# PCI_IRDY#
2^,37! BUF_PCI_RESET# BUF_PCI_RESET# RXD_TTL_EXAR_SP8
TXD_TTL_EXAR_SP6 BUF_PCI_RESET# RXD_TTL_EXAR_SP8
PCI_PAR TXD_TTL_EXAR_SP6 BUF_PCI_RESET#
2^,17,59!,61!,62! PCI_PAR PCI_PAR
PCI_PAR
PCI_IDSEL1 PCI_PAR RXD_TTL_EXAR_SP9
2^,37! PCI_IDSEL1 PCI_IDSEL1 RXD_TTL_EXAR_SP9
TXD_TTL_EXAR_SP7
TXD_TTL_EXAR_SP7
2^,37! PCI_IDSEL2 PCI_IDSEL2
2^,17,59!,61!,62! PCI_STOP# PCI_STOP#
PCI_STOP#
PCI_STOP# RXD_TTL_EXAR_SP10
PCI_SERR# RXD_TTL_EXAR_SP6 PCI_STOP# RXD_TTL_EXAR_SP10
2^,17,35,59!,61!,62! PCI_SERR# PCI_SERR# RXD_TTL_EXAR_SP6
PCI_SERR#
PCI_DEVSEL# PCI_SERR#
2^,17,59!,61!,62! PCI_DEVSEL# PCI_DEVSEL# RXD_TTL_EXAR_SP11
RXD_TTL_EXAR_SP7 PCI_DEVSEL# RXD_TTL_EXAR_SP11
PCI_TRDY# RXD_TTL_EXAR_SP7 PCI_DEVSEL#
2^,17,59!,61!,62! PCI_TRDY# PCI_TRDY#
PCI_TRDY#
PCI_IRQB# PCI_TRDY#
2^,17 PCI_IRQB# PCI_IRQB# VCC3.3
VCC3.3 VCC3.3 VCC3.3 VCC3.3
2^,17 PCI_IRQC# PCI_IRQC#
2^,17,59!,61!,62! PCI_PERR# PCI_PERR#
PCI_PERR#
PCI_PERR#
DGND PCI_PERR# DGND
2^,8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39!,40!,41!,43!,44!,45,46!,47!,48!,51!,52!,53!,54!,56!,57!,58!,59!,61!,62! VCC3.3
61 Exar Octal UART 62 Exar Quad UART
B
2^,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39!,40!,41!,43!,44!,45,46!,47!,48!,49!,50!,51!,52!,53!,54!,56!,57!,58!,59!,61!,62! DGND B
U34
2^,16 PCI_CLK
1 8 BUF_PCI_CLK0 R362 33 OHM PCI_CLK0 2^,59 2^,50 RXD_TTL_EXAR_SP[6..11]
CLKIN CLKOUT
3 BUF_PCI_CLK1 R336 33 OHM RXD_TTL_EXAR_SP6
FB25 120 OHM @ 100MHz CLK1 RXD_TTL_EXAR_SP7
VCC3.3 VCC3.3_FB 6 2 BUF_PCI_CLK2 R337 33 OHM RXD_TTL_EXAR_SP8
VCC CLK2 RXD_TTL_EXAR_SP9
C776 C777 5 RXD_TTL_EXAR_SP10
100nF 10nF CLK3 RXD_TTL_EXAR_SP11
4 7
GND CLK4 PCI clocks are 55 Ohm
Single Ended. Keep clocks
2^,50 TXD_TTL_EXAR_SP[6..11]
away from other signals and
CY2305
reference to ground plane. TXD_TTL_EXAR_SP6
1.6nS +/- 0.1nS delay to TXD_TTL_EXAR_SP7
destination pin of PCI device. TXD_TTL_EXAR_SP8
TXD_TTL_EXAR_SP9
TXD_TTL_EXAR_SP10
TXD_TTL_EXAR_SP11

TECHNOLOGIES
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED PCI UART Hierarchy
PROD. APP.
PCA212268-2-1 1/1 1/1 60 62
5 4 3 2 1
5 4 3 2 1
D D
37,60^
BUF_PCI_RESET#
17,60^
PCI_IRQB#
60^
PCI_CLK1
VCC3.3
VCC3.3 VCC3.3
NI
NI NI R692
17,37,59,60^,62 PCI_AD[0..31] R701 C763 6.8K
NI 6.8K 100nF
C786
PCI_AD0 100nF
RXD_TTL_EXAR_SP0
RXD_TTL_EXAR_SP1
TXD_TTL_EXAR_SP0
TXD_TTL_EXAR_SP1
NI
1
PCI_AD1 NI NI
PCI_AD2 R712 C244 C243
6.8K
PCI_AD3 NI 22pF 22pF
PCI_AD4 R696
PCI_AD5 6.8K
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_AD6
PCI_AD7 NI
PCI_AD8 XTAL2
PCI_AD9 14.745MHz
PCI_AD10
PCI_AD11
2
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PCI_AD12
PCI_AD13
PCI_AD14
EEDO
VCC
GND
VCC
CLK
INTA
EECK
EECS
EEDI
RESET
TEST
AD25
AD26
AD27
AD28
AD29
AD30
AD31
RX0
CTS0
DSR0
CD0
RI0
RTS0
DTR0
TX0
RX1
CTS1
DSR1
CD1
RI1
RTS1
DTR1
TX1
XTAL1
XTAL2
PCI_AD15
PCI_AD16
PCI_AD17 PCI_AD24 1 108
PCI_AD18 2 AD24 MPIO0 107
17,59,60^,62 PCI_C/BE3# CBE3 MPIO1
PCI_AD19 37,60^ PCI_IDSEL1
3 106 TXD_TTL_EXAR_SP2
PCI_AD20 4 IDSEL TX2 105
VCC3.3 VIO DTR2 VCC3.3
PCI_AD21 5 104
PCI_AD22 NI PCI_AD23 6 GND RTS2 103 NI
PCI_AD23 C790 PCI_AD22 7 AD23 RI2 102 R678 6.8K
C PCI_AD24 100nF PCI_AD21 8 AD22 CD2 101 C
PCI_AD25 PCI_AD20 9 AD21 DSR2 100 NI
PCI_AD26 PCI_AD19 10 AD20 CTS2 99 RXD_TTL_EXAR_SP2 R680
PCI_AD27 PCI_AD18 11 AD19 RX2 98 TXD_TTL_EXAR_SP3 6.8K
PCI_AD28 PCI_AD17 12 AD18 TX3 97
PCI_AD29 PCI_AD16 13 AD17 NI DTR3 96
PCI_AD30 14 AD16 U36 RTS3 95
17,59,60^,62 PCI_C/BE2# CBE2 RI3
PCI_AD31 17,59,60^,62 PCI_FRAME#
15 94
16 FRAME XR17D158 CD3 93
17,59,60^,62 PCI_IRDY# IRDY DSR3 VCC3.3
17,59,60^,62 PCI_TRDY# 17 92
18 TRDY CTS3 91 RXD_TTL_EXAR_SP3
17,59,60^,62 PCI_DEVSEL# DEVSEL RX3
VCC3.3
19 90
20 VIO VCC 89
NI 21 GND GND 88 TXD_TTL_EXAR_SP4
17,59,60^,62 PCI_STOP# STOP TX4 NI
C789 17,59,60^,62 PCI_PERR#
22 87 C751
100nF 23 PERR DTR4 86 NI
17,35,59,60^,62 PCI_SERR# SERR RTS4 100nF
24 85 R679
17,59,60^,62 PCI_PAR PAR RI4 6.8K
17,59,60^,62 PCI_C/BE1#
25 84
PCI_AD15 26 CBE1 CD4 83
PCI_AD14 27 AD15 DSR4 82
PCI_AD13 28 AD14 CTS4 81 RXD_TTL_EXAR_SP4
PCI_AD12 29 AD13 RX4 80
AD12 TX5 TXD_TTL_EXAR_SP5 56,60^
PCI_AD11 30 79
PCI_AD10 31 AD11 DTR5 78
AD10 RTS5 RTS_TTL_EXAR_SP5# 56,60^
PCI_AD9 32 77
PCI_AD8 33 AD9 RI5 76
34 AD8 CD5 75
VCC3.3 VIO DSR5
35 74
NI 36 GND MPIO2 73
17,59,60^,62 PCI_C/BE0# CBE0 MPIO3
C788
100nF
TMRCK
MPIO7
MPIO6
MPIO5
MPIO4
DSR7
DSR6
DTR7
DTR6
CTS7
RTS7
CTS6
RTS6
CTS5
ENIR
GND
GND
50,60^ RXD_TTL_EXAR_SP[0..4]
VCC
CD7
CD6
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
RX7
RX6
RX5
TX7
TX6
VIO
RI7
RI6
RXD_TTL_EXAR_SP0
VCC3.3 RXD_TTL_EXAR_SP1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
RXD_TTL_EXAR_SP2
B RXD_TTL_EXAR_SP3 B
RXD_TTL_EXAR_SP4
NI
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
R681
NI 6.8K
50,60^ TXD_TTL_EXAR_SP[0..4]
R691
NI NI TXD_TTL_EXAR_SP0
3.3K
R711 R706 TXD_TTL_EXAR_SP1
6.8K 6.8K TXD_TTL_EXAR_SP2
VCC3.3 VCC3.3
TXD_TTL_EXAR_SP3
NI NI TXD_TTL_EXAR_SP4
C785 C768
TXD_TTL_EXAR_SP7
TXD_TTL_EXAR_SP6
RXD_TTL_EXAR_SP7
RXD_TTL_EXAR_SP6
RXD_TTL_EXAR_SP5
50,60^
50,60^
50,60^
50,60^
56,60^
100nF 100nF
VCC3.3 VCC3.3
VCC3.3

8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,48,51,52,53,54,56,57,58,59,60^,62 VCC3.3
TECHNOLOGIES
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,49,50,51,52,53,54,56,57,58,59,60^,62 DGND TECHNOLOGIES, INC., LAS VEGAS, NEVADA AND THE CHECKED
ENG. APP.
REPRODUCED, REVEALED TO OR APPROPRIATED Exar Octal UART
PROD. APP.
PCA212268-2-1 1/1 1/1 61 62
5 4 3 2 1
5 4 3 2 1
D D
TXD_TTL_EXAR_SP8
RXD_TTL_EXAR_SP8
50,60^
50,60^
37,60^
BUF_PCI_RESET#
VCC3.3
17,60^
PCI_IRQC#
60^
PCI_CLK2
VCC3.3 VCC3.3
R646
17,37,59,60^,61 PCI_AD[0..31] C676 6.8K
100nF
C734
PCI_AD0 100nF
1
PCI_AD1 R665 C192 C191
PCI_AD2 6.8K 22pF 22pF
PCI_AD3 R650
PCI_AD4 6.8K
PCI_AD5
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_AD6
PCI_AD7
PCI_AD8 XTAL1
PCI_AD9 14.745MHz
PCI_AD10
PCI_AD11
2
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PCI_AD12
PCI_AD13
PCI_AD14
VIO
EEDO
GND
VCC
CLK
INTA
EECK
EECS
EEDI
RESET
TEST
AD25
AD26
AD27
AD28
AD29
AD30
AD31
RX0
CTS0
DSR0
CD0
RI0
RTS0
DTR0
TX0
NC32
NC31
NC30
NC29
NC28
NC27
NC26
NC25
XTAL1
XTAL2
PCI_AD15
PCI_AD16
C PCI_AD17 PCI_AD24 1 108 C
PCI_AD18 2 AD24 MPIO0 107
17,59,60^,61 PCI_C/BE3# CBE3 MPIO1
PCI_AD19 37,60^ PCI_IDSEL2
3 106 TXD_TTL_EXAR_SP9 50,60^
PCI_AD20 4 IDSEL TX1 105
VCC3.3 VIO DTR1 VCC3.3
PCI_AD21 5 104
PCI_AD22 PCI_AD23 6 GND RTS1 103
PCI_AD23 C743 PCI_AD22 7 AD23 RI1 102 R642 6.8K
PCI_AD24 100nF PCI_AD21 8 AD22 CD1 101
PCI_AD25 PCI_AD20 9 AD21 DSR1 100
PCI_AD26 PCI_AD19 10 AD20 CTS1 99
AD19 RX1 RXD_TTL_EXAR_SP9 50,60^
PCI_AD27 PCI_AD18 11 98
PCI_AD28 PCI_AD17 12 AD18 NC24 97
PCI_AD29 PCI_AD16 13 AD17 NC23 96
PCI_AD30 14 AD16 U31 NC22 95
17,59,60^,61 PCI_C/BE2# CBE2 NC21
PCI_AD31 17,59,60^,61 PCI_FRAME#
15 94
16 FRAME XR17D154 NC20 93
17,59,60^,61 PCI_IRDY# IRDY NC19 VCC3.3
17,59,60^,61 PCI_TRDY#
17 92
18 TRDY NC18 91
17,59,60^,61 PCI_DEVSEL# DEVSEL NC17
VCC3.3
19 90
20 VIO VCC 89
21 GND GND 88
17,59,60^,61 PCI_STOP# STOP TX2 TXD_TTL_EXAR_SP10 50,60^
C742 17,59,60^,61 PCI_PERR#
22 87 C674
100nF17,35,59,60^,61 23 PERR DTR2 86 R640 100nF
PCI_SERR# SERR RTS2
17,59,60^,61 PCI_PAR 24 85 6.8K
25 PAR RI2 84
17,59,60^,61 PCI_C/BE1# CBE1 CD2
PCI_AD15 26 83
PCI_AD14 27 AD15 DSR2 82
PCI_AD13 28 AD14 CTS2 81
AD13 RX2 RXD_TTL_EXAR_SP10 50,60^
PCI_AD12 29 80
PCI_AD11 30 AD12 NC16 79
PCI_AD10 31 AD11 NC15 78
PCI_AD9 32 AD10 NC14 77
PCI_AD8 33 AD9 NC13 76
34 AD8 NC12 75
VCC3.3 VIO NC11
35 74
36 GND MPIO2 73
B
17,59,60^,61 PCI_C/BE0# CBE0 MPIO3 B
C741
100nF
TMRCK
MPIO7
MPIO6
MPIO5
MPIO4
DSR3
DTR3
CTS3
RTS3
NC10
ENIR
GND
GND
VCC
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
CD3
NC9
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
RX3
TX3
VIO
RI3
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
R649
3.3K
R660
6.8K
VCC3.3 VCC3.3
TXD_TTL_EXAR_SP11
RXD_TTL_EXAR_SP11
50,60^
50,60^
C732 C682
100nF 100nF
VCC3.3

VCC3.3 PERTAINING TO THE ARTICLE SHOWN ON THIS
TECHNOLOGIES
8,12,14,16,17,18,19,22,23,24,25,26,27,28,31,32,34,35,36,37,39,40,41,43,44,45,46,47,48,51,52,53,54,56,57,58,59,60^,61 VCC3.3
ENG. APP.
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,45,46,47,48,49,50,51,52,53,54,56,57,58,59,60^,61 DGND REPRODUCED, REVEALED TO OR APPROPRIATED Exar Quad UART
PROD. APP.
PCA212268-2-1 1/1 1/1 62 62
5 4 3 2 1

Alpha-II Integrated: Schematic Component Notation "NI", "DNI" Not Installed

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Alpha-II Integrated: Schematic Component Notation "NI", "DNI" Not Installed

Uploaded by

Copyright:

Available Formats

5 4 3 2 1

Table of Contents Notes

23) Fan Controller 56) Misc. Communications Buffers

A ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE A

VCC3.3SBY VCC3.3 LPC BIOS - TPM

VCC5 Audio Codec AC_SYNC

VGA_I2C_DAT GBE0_MDI+2 WAKE0# WAKE1# WAKE0#

GBE0_MDI+3 PEG_ENABLE# PCIE_RESET# PEG_ENABLE#

GBE0_MDI-0 GBE0_MDI+1 GBE0_LINK1000#

DGND TEST_SWITCH# PERIPH_RESET# IDE_A_A[0..2] LD3.3V_[0..7]

VEE12 PERIPH_RESET# RXD_232_SP8

DGND AC_DETECT VCC5 VCC5 RXD_232_SP11 VCC12

DOOR_BAT_LOW# DGND TXD_232_SP1

VCC5SBY VCC12 Backplane Connectors 50 Serial Tranceivers

Size Document Number Rev

Date: Thursday, April 14, 2011 Sheet 2 of 62

Channel A Channel B HW-Monitor

iTPM SPI SPI Flash

MAC LPC Bus (33MHz)

optional instead of GbEthernet

Analog VGA / CRT

COM express connector

LPC Bus (33MHz)

Power Management Chipset control & SYS Mgmt signals

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

Intel Penryn Intel GS45 Intel ICH9M

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

CLK_CPU_BCLK (166/200/266 MHz)

CLK_PCIE_ICH (100 MHz)

CLK_ICH_14M318 (14.318 MHz)

CLK_SUS_32K (32 kHz)

CLK_PCIE_CON (100 MHz)

CLK_PCI_33M_EXT (33 MHz) COMexpress

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

F28 VCC[043] VCC_121 Y24 AP20 VCC_197 VCCP_050 AK36

AB26 B20 K38 U11 cavity in 2 rows

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

small form factor

small form factor

Place PU and PD within 1 inch of CPU.

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

H_D#_35 H_ADSTB#_1 H_ADSTB#1 8 SA_DQ_20 SA_DQS_0 M_A_DQS0_P 20 SB_DQ_20

R223 H_REQ#_0 L13 AU11 SA_DQ_53 AU3 SB_DQ_53

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

DNI 27 LVDS_B_CLK_N PEG_RX_11_N 2,38,39

BF20 BJ19 C2U2S03V6 R161 AC55

R1%10K0S02 R1%10K0S02 R1%0R0S02 C105

J39 AG47 DMI_TX0_N AD54 PEG_TX_15_C_N C107

V3.3_S0 A7 F38 MCH_GFX_VID2 T50 SDVOC_CLK_P C475

DDPC_CTRLCLK R165 B54 G39 CRT_IREF D32 W55 PEG_TX_11_C_P C103

R185 NC_10 CL_RST# MCH_CL_RST0# 18 C100N02V16

DNI R1%2K21S02 BL4 NC_15 SDVO_CTRLCLK A37 SDVO_CTRLCLK 2,38,39 3 2

R210 HDA_SDO CRT_VSYNC 2,42,45 R511

VCC GFX NCTF

AA31 R18 AL32 AN38

AL21 VCC_AXG_51 VCC_SM_LF2 BB38 VCCSM_LF3

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

ALL DESIGN OPERATIVE AND PROCESS DATA DRAWN BY DATE

C618 C570 C138 C143

Place for CPU Driven BSEL