Professional Documents
Culture Documents
Lab #2
Due September 29th, 6pm. Submitted to Canvas.
Submission: Prepare a concise report (< 5 pages) with important results only. You don’t have to
include the entire set of your circuit schematics or layout plots. Place the report in Assignment at
myasu with the filename as: EEE425_Lab_2_your name or EEE591_Lab_2_your name.
The objective of this software lab is to design and implement standard cells.
(1) Please exactly the same cell names as in the table. Cell names must not be modified;
(2) All the sizes are actual NMOS and PMOS transistor sizes to be implemented in the layout;
(3) Please follow layout guidelines and check the given layout examples;
(4) Run your schematic first: create a schematic for the cells. Create an appropriate symbol for
each cell. In the “sample” library example symbols are shown. Characterize the 50% delay of
both high-to-low and low-to-high, the rise time and the fall time.
(5) Create the layout of the cells. Ensure the size on the layout view matches that size on the
schematic view. Run DRC and LVS to ensure that you layout complies with the design rules
and with your schematic.
(6) Please use “Gate 1” as a learning crutch to understand DRC/LVS rules and try to complete it
as soon as possible.