This article has been accepted for inclusion in a future issue of this journal.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
A Resistorless High-Precision Compensated
CMOS Bandgap Voltage Reference
Ze-Kun Zhou , Member, IEEE, Yue Shi, Yao Wang, Nie Li, Zhiping Xiao, Yunkun Wang,
Xiaolin Liu, Zhuo Wang, and Bo Zhang, Member, IEEE
Abstract— A resistorless high-precision compensated CMOS
bandgap voltage reference (BGR), which is compatible with a
standard CMOS process, is presented in this paper. A higher-
order curvature correction method called base-emitter voltage
linearization is adapted to directly compensate the thermal
nonlinearity of base–emitter voltage. With proper mathematical
operations of high-order temperature currents, most of the
nonlinear temperature terms in VBE can be greatly eliminated.
The proposed BGR, which is implemented in 0.35-µm CMOS
technology, is capable of working down to 2 V supply voltages
with 1.14055 V mean output voltage. A minimum temperature
coefficient of 1.01 ppm/°C with a temperature range from −40 °C
to 125 °C is realized, and a power-supply noise attenuation
of 61 dB is achieved without any filter capacitors. The line
regulation is better than 2 mV/V from 2 V to 5 V supply voltage
while dissipating a maximum supply current of 33 µA. The active
area of the presented BGR is 180 µm × 220 µm.
Index Terms— Bandgap voltage reference, resistorless, high-
order curvature compensation, temperature nonlinearity.
I. I NTRODUCTION
V OLTAGE references play an important role in many
applications ranging from purely analog, mixed-mode
to purely digital circuits, such as data converters and power
managements for their high precision and temperature inde-
pendence [1]–[7]. The reference voltage is required to be
stabilized over supply voltage and temperature variations, and
also to be implemented without modification of fabrication
process [4]–[5], [7].
Bandgap voltage reference (BGR) is widely used to define
precise voltage that has low temperature variation over com-
mercial or military temperature ranges. To reduce the excur-
sion of BGR in wide temperature range, many high-order
Manuscript received March 20, 2018; revised June 5, 2018 and
July 3, 2018; accepted July 17, 2018. This work was supported in part
by the National Science Foundation of China under Grant 61674025 and
Grant 61306035, in part by the Fundamental Research Funds for the Central
Universities under Grant ZYGX2016J056, and in part by the Open Projects of
Sichuan Key Laboratory of Meteorological Information and Signal Processing
under Grant QXXCSYS201504 and Grant QXXCSYS201603. This paper
was recommended by Associate Editor F. M. Neri. (Corresponding author:
Ze-Kun Zhou.)
Z.-K. Zhou, Y. Wang, Z. Xiao, Y. Wang, X. Liu, Z. Wang, and B. Zhang
are with the State Key Laboratory of Electronic Thin Films and Integrated
Devices, University of Electronic Science and Technology of China, Chengdu
610054, China (e-mail: zkzhou@uestc.edu.cn).
Y. Shi is with the College of Communication Engineering, Chengdu
University of Information Technology, Chengdu 610225, China (e-mail:
october@cuit.edu.cn).
N. Li is with the Tsinghua Energy Internet Research Institute, Chengdu
610213, China (e-mail: 360592501@qq.com).
Digital Object Identifier 10.1109/TCSI.2018.2857821
1549-8328 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
temperature compensation techniques have been developed,
such as subthreshold MOSFET compensation [8]–[10],
adjusted piecewise compensation [11], quadratic tempera-
ture compensation [12]–[15], exponential temperature com-
pensation [16], piecewise-linear curvature correction [17],
temperature-dependent resistor ratio compensation [18]–[20],
and so on. In addition, resistor compensation scheme is also
usually used in most compensation techniques for its flexibil-
ity. However, the resistor usage increases not only the chip
area and the cost but also the noise coupling from substrate.
Besides, in standard digital CMOS technologies, models for
the resistors may not be available or reliable. Therefore,
it should be avoided especially in low noise applications, such
as sensing circuits and small signal readout interfaces. Some
particular circuits fabricated in digital CMOS technology
have been introduced to solve this problem. For example,
a BGR without resistors using MOS transistors biased in
subthreshold region has been reported in [6] and [21], where
accurate subthreshold device models are not usually avail-
able. Resistorless BGRs with active-region transistors are
also presented in [22]–[24] with the mutual compensation
of thermal voltage and base-emitter voltage. However, most
of the reported circuits face a challenge that the output
reference voltage is not accurate enough since the high-order
temperature compensation is difficult to be realized without
resistors.
In addition to BGRs, some non-bandgap structures have
been proposed in recent years [25]–[31]. Voltage reference
in [25] is based on a weighted threshold-voltage subtraction
of NMOS and PMOS at the expense of usage of resistors.
Resistorless voltage references adopt temperature com-
pensation between thermal voltage and threshold volt-
age are reported in [26]–[31]. However, either resistors or
subthreshold-region transistors are needed, which leads to
the similar limitations in BGRs. Besides, the temperature
characteristics are limited without any high-order temperature
compensation. What’s more, the values of output reference
voltages in the above non-bandgap voltage references are
directly related to threshold voltage, which can introduce a
larger variation with process than those in BGRs.
In order to overcome those mentioned issues, a resistorless
high-precision compensated CMOS BGR based on a novel
high-order compensation technique is described in this paper.
Since the temperature nonlinearity of base-emitter voltage
directly depends on the temperature power of bias current,
high-order complex current is introduced to realize base-
emitter voltage linearization (BEVL) technique for linear
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

temperature characteristics of VBE . Then, a high-precision

BGR can be implemented with a weighted sum of the
thermal-linearized VBE and proportional to absolute temper-
ature (PTAT) voltage. This is achieved by an operational
amplifier with PTAT offset voltage in a resistorless way.
Besides, in order to realize required characteristic bias cur-
rent, two resistorless self-biased current sources (RLSBCS)
are presented in this paper to generate current proportional
to μVTH2 and μV 2 , respectively, where μ is the carrier mobility
T
of MOSFET, VTH is threshold voltage, VT is thermal volt-
age kT/q, k is Boltzmann’s constant, and q is the charge
of an electron. Therewith, a curvature-compensation current
is injected into base-emitter voltage with proper mathematic
operations of these two kinds of current with the help of
translinear loop. As a result, the nonlinearity of the base–
emitter voltage is directly compensated instead of adding
additional compensation terms in reference output voltage to
achieve low temperature coefficient (TC). What’s more, the
proposed RLSBCS with feedback is also used to provide
supply current for the whole BGR, which can further improve
the performance of proposed voltage reference, such as TC,
and power-supply noise attenuation (PSNA).
This paper is organized as follows. Section II describes the
principle of proposed BGR, and the circuit implementation is
illustrated in Section III. To prove superiority, validated results
as well as performance comparison with some reported BGRs
are presented in Section IV, and the conclusion is given in
Section V.

II. P RINCIPLE OF P ROPOSED VOLTAGE R EFERENCE

Almost all BGRs are designed based upon the thermal
voltage VT . The principle of designing a BGR either in CMOS
technology or in BiCMOS technology is the same, which is
based on VREF = VBE + αVT , where α is a well-defined and
temperature-independent (TI) constant. Parasitic BJTs formed
in n-well or p-well are commonly used to implement the
BGRs in CMOS process. The base-emitter voltage can be
expressed by
T little, the TC and temperature nonlinearity of VBE (T ) decrease
VBE (T ) = VG0 (T0 ) − [VG0 (T0 ) − VBE (T0 )]
T0
− (η − ζ )VT ln(T /T0 ) (1)
where ζ is the temperature power of collector current.
VG0 is the bandgap voltage of silicon extrapolated to 0°K.
η = 4 − m, m is the temperature power of carrier mobility in
semiconductor body, η is usually between 3 and 4 with the
most representative value 3.54 [32]. T0 is reference tempera-
ture. From (1), the VT ln(T /T0 ) term demonstrates the high-
order nonlinearity of VBE . It was proposed in [23] to use
a PTAT2 current to realize curvature correction of the base-
emitter voltage, and it was mentioned that the compensation of
VBE (T ) could be improved by adopting strongly temperature-
dependent bias currents [33], [34]. In this paper, a strongly
temperature-dependent bias current, which includes many
high-order temperature terms, is generated in a resistorless way
to compensate the temperature nonlinearity of VBE .
The temperature behavior of VBE (T ) with different ζ is
illustrated in Fig. 1. Although the value of VBE changes
Fig. 1. Temperature characteristic of VBE with different ζ . (a) VBE ,
(b) ∂VBE /∂T .
with ζ approaching η. The situations with ζ = 0 and 1
represent the bias current for BJT is TI and PTAT, respec-
tively. These two cases are widely used in most voltage
reference structures, especially in voltage reference with
resistor. As shown in Fig. 1, the TCs of VBE (T ) with
ζ = 0 and 1 are around −1.995mV/°C with 8.18% vari-
ation and −1.897mV/°C with 6.11% variation, respectively.
Larger positive temperature items and high-order temperature-
compensation items are inevitable to realize reference voltage
with better TC at the expense of higher power consumption.
However, ζ is usually smaller than 1 in most reported
resistorless voltage reference circuits. This means the influ-
ence of VBE (T )’s nonlinearity has a greater impact on the
performance of reference voltage. With regard to ζ = 0.5,
a typical value in resistorless voltage reference, the TC of
VBE (T ) is about 1.923mV/°C with 7.22% variation. Since
high-order temperature-compensation items and signal oper-
ations are quite difficult to be implemented without resistor,
the temperature stability of resistorless voltage reference is
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ZHOU et al.: RESISTORLESS HIGH-PRECISION COMPENSATED CMOS BVR 3

to compensate the high-order TCs of VBE (T ), are quite diffi-

cult to be realized without resistors. Therefore, an alternative
method, BEVL, is adopted in this paper. As shown in (1),
parameter ζ is selected as the compensation factor to directly
weaken the temperature nonlinearity of VBE by making ζ close
to η. A special high-order complex compensation current,
Icomp , is achieved by μVTH
2 and μV 2 currents shown in Fig. 3.
T
Fig. 2. BEVL curvature compensation and reference generation concept. The translinear loop technique [35], [36] is adopted to realize
the mathematic operation of currents. The μVTH 2 current with

strong negative TC and the μVT current with weak positive

2
usually limited. A high-order temperature compensation cur- TC are injected into the particular high-order compensation
rent is generated without resistor in this paper to fit ζ = 3.5, current generator circuit to produce the required compensation
which can greatly reduce the temperature nonlinearity of VBE . current with strong positive TC.
By this BEVL technique, the TC of proposed BGR can be With the help of negative feedback loop formed by oper-
substantially improved. ational amplifier, OP, transistors MP8 and Q5, the voltage at
In order to intuitively illustrate the principle of proposed nodes VP and VN is to be equal. Then,
BGR, Fig. 2 is adopted to show the proposed BEVL concept.
Two currents, I1 and I2 , which are provided by μVT2 and μVTH 2 VEBQ4 + VEBQ5 = VEBQ6 + VEBQ7 (2)
RLSBCS, respectively, are injected into high-order curvature-
compensation generator (HOCCG) block. Hence, a current, I3 , where VEBQi is the emitter-base voltage of Qi . Since VEB =
which is proportional to μVT4 /VTH 2 , can be realized. Then, I , VT ln(IC /IS ), where IC and IS are the collector current and
4
a combination of I1 and I3 with a suitable weight, provides the saturation current, respectively, the generated high-order com-
bias current for BJT. As noted in (1), the temperature behavior pensation current can be shown as,
of VBE (T ) could be absolutely linear with ζ = η. I12 A2 μ2 VT4 T 4−n
Therefore, the proposed BEVL technique is implemented to I3 = = =χ (3)
I2 BμVTH 2
(1 − λT )2
make a base-emitter voltage have linear negative-temperature
property. Then, a PTAT voltage with linear positive- where parameters A, B, and χ = A2 C/(BVTH0 2 ) are TI
temperature property is adopted to eliminate the temperature constants. If n is equal to 1.5, which is the most representative
drift of VBE (T ) with BEVL. Based on the mutual compensa- value and the actual situation in the proposed design, current I3
tion of the two linear temperature items, a temperature-stable can be rewritten as,
reference voltage, VREF , can be generated.
Normally, a voltage proportional to VT , PTAT voltage, is I3 ≈ χ T 2.5 (1 + 2λT + 3λ2 T 2 ) (4)
generated as the voltage difference of two forward-biased
As previously analyzed, a strong temperature-dependent
p-n junctions, which is easy to be magnified using resistors.
bias currents is derived, which includes the terms of
However, the basic idea here to achieve VPTAT in the circuit
T 2.5 , T 3.5 , and T 4.5 . Therefore, the non-linearity of VBE (T )
without resistors is to use a differential amplifier with PTAT
can be compensated by the generated high-order current.
offset voltage. In this way, the negative temperature gradient
In order to better illustrate the thermal behavior of proposed
of the voltage across the emitter–base junction is compensated
circuit, an accurate temperature-dependence description of
by the voltage follower with built-in PTAT offset voltage.
VBE (T ) is necessary. To compensate the linearization of
III. P ROPOSED BGR the emitter–base voltage of Q8, a low-order current is also
needed, which is shown in Fig. 3. The current of Q8, I4 , can
The proposed resistorless high-precision compensated
be given by,
CMOS BGR is shown in Fig. 3, which includes μVTH 2 cur-
 
rent generator, μVT current generator, high-order compensa-
2
ET 2
tion current (HOCC) generator and buffer with PTAT offset I 4 = D1 I 1 + D2 I 3 = F T 2−n
1+ (5)
F(1 − λT )2
voltage. The carrier mobility can be expressed as μ = C T −n ,
where C is a TI constant, and n is usually between 1.5 and 2 in where D1 , D2 are TI constants, which represent the
semiconductor surface. The threshold voltage can be given by gain of current mirrors. Parameters F = D1 Ck 2 /q 2 and
VTH = VTH0 (1 − λT ), where VTH0 is the threshold voltage E = χ D2 /D1 are TI constants. According to Taylor series
at 0°K, λ is temperature coefficient of threshold voltage with expansion ln(1 + x) ≈ x − x 2 /2, the voltage VEB(Q8) can be
positive value. Therefore, μVTH
2 current is in direct proportion expressed as,
to the product of μ and VTH ; Similarly, μVT2 current is directly
2
VEB(Q8) ≈ VG0 + VT ln FE − (η + n − 2) VT ln T
proportional to the product of μ and VT2 . All the transistors
+ X T 3 + Y T 4 + Z T 5 (6)
are biased in strong inversion or cut-off region.
 
where Z = k B 2D1 λ2 − B /(2q D 2 ), Y = 2k Bλ/(q D1 ),
A. High-Order Current Compensate Technique and X = k B/(q D1 ) are TI constants. As shown in (6),
Conventional compensation techniques, which introduce the temperature nonlinearity of VBE (T ) comes from VT lnT can
temperature nonlinearity in the correction voltage drop VPTAT be directly cancelled out by selecting the ratio of A, B, D, E.
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 3. The proposed bandgap reference circuit configuration.

Fig. 5. Simulated temperature dependence of I2 .

Fig. 4. 2 current generator circuit.

μVTH

The schematic of the μVTH 2 RLSBCS is shown in Fig. 4. All

MOSFETs are biased in strong inversion region except those in

startup circuit, and transistor MN8 is biased in triode region,
which acts as a controlled resistor. The principle of μVTH 2

current generator is similar to that in [25] and [37], except a

triode region MOSFET as a controlled resistor adopted here
and less current branch for lower power dissipation. Given
(W/L)MP4 = 4(W/L)MP5 = 4(W/L)MP6 , and the aspect ratios
of transistors MN5, MN6, MN7 and MN9 are the same,
the current through MP5, I2 , can be given by,

2I2
VGSN5 = 2 + VTH (7)
μCOX SMN5
 Fig. 6. μVT2 current generator circuit.
2I2
VGSN6 = VGSN9 = + VTH (8)
μCOX SMN5

IMN8 = 4I2 = μCOX SMN8 (VGSMN8 − VTH ) The simulated temperature dependence of I2 is shown in
 Fig. 5. Due to μ = C T −n with the most representative value
1 n = 1.5, the current I2 is proportional to T −1.5 (1 − λT )2 ,
− VDSMN8 VDSMN8 (9)
2 and the TC of I2 is proportional to −[1.5T −2.5 (1 − λT )2 +
where Si is the aspect ratio of transistor i. With the help 2λT −1.5 (1 − λT )] in the proposed design,. Hence, it is consis-
of (7), (8), and (9), the current I2 can be expressed as, tent with the simulation results illustrated in Fig. 5. The value
of I2 and the absolute value of TC decreases with temperature
I2 = K 2 μVTH
2
(10) rising.
  2 Fig. 6 shows the μVT2 current generator circuit, whose
C OX SMN8 SMN8 SMN8
where K 2 = 8 SMN5 + SMN5 + 1 is a TI constant. principle is similar to that in [24]. Transistor MN4 is biased in
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ZHOU et al.: RESISTORLESS HIGH-PRECISION COMPENSATED CMOS BVR
Fig. 7. Simulated temperature dependence of I1 .
Fig. 8. Simulated temperature dependence of I3 .
triode region, which acts as a controlled resistor. The emitter
area of Q1 is N times larger than that of Q2 and Q3, where
N = 8 is selected for layout considerations in this paper. Given
SMP1 = SMP2 = SMP3 , and SMN1 = SMN2 = SMN3 = SMN4 ,
the voltage VDSMN2 is VT lnN. With the help of voltage-current
characteristics of MOSFETs, the current through MP2, I1 , can
be expressed as,
I1 = K 1 μVT2 (11)
  2
where K 1 = COX 2SMN4 (ln N)2 SMN4
SMN1 +
SMN4
SMN1 + 1 is a TI
constant.
The simulated temperature dependence of I1 is illustrated
in Fig. 7. As shown in (11), current I1 is proportional to μVT2 .
The current I1 is proportional to T 0.5 , and the TC is propor-
tional to 1/T 0.5 with a positive value in the proposed design.
Hence, it is consistent with the simulation results shown
in Fig. 7. The value of I1 increases and the TC decreases
with temperature rising.
Fig. 8 and Fig. 9 show the simulated temperature depen-
dence of I3 and I4 , respectively. As shown in (4) and (5),
currents I3 and I4 have strong positive temperature depen-
dency, and the TCs increase with temperature rising.
As shown in Fig. 4 and Fig. 6, additional branches, which
are formed by MN7, MN10, MP6, and MN3, MP3, Q3,
respectively, is adopted. These branches are used as negative
feedback control and voltage clamper to improve the perfor-
mance of SBCS [37]. Taken the schematic shown in Fig. 4 as
5
Fig. 9. Simulated temperature dependence of I4 .
an example, the voltage at node B and C can be set at the same
value with proper transistor sizes. In this way, the channel
length modulation effect can be greatly suppressed without the
necessity of long channel transistors. Besides, two feedback
loops are formed with the help of additional branch. One
is negative feedback loop with signal path ‘node B - node
A - node C - node B’, the other one is positive feedback loop
with signal path ‘node B - node A - node B’. Since the loop
gain of negative feedback loop is larger than that of positive
feedback loop, the performance, such as TC and PSNA,
of whole RLSBCS can be greatly improved with negative feed-
back control. Capacitors C1 and C2 are used as compensation
capacitors for loop stability. The characteristics of the feedback
loop can be expressed as,
2
TLOOP_GAIN ≈ gm RON_MN8 (roMP5 ||2roMN6 ) (12)
Pdominant = 1/[C2 (roMP5 ||2roMN6 )] (13)
where gm is the transconductance of transistors, which have the
same aspect ratio and current with MN6, roi is the output resis-
tance of transistor i, RON_MN8 is the equivalent resistance of
MN8. Through this method, the PSNA of proposed RLSBCS
can be greatly improved without any filter capacitor.
B. Voltage Reference Generator
The middle part in Fig. 3 is the voltage reference generator.
As previously analyzed, the temperature nonlinearity in VEB
has been greatly compensated by the strong temperature-
dependent bias current. Therefore, a PTAT voltage summer
is needed to generate the output reference voltage. As stated
in Section II, the principle of PTAT voltage summer is realized
by a unit-gain structure. The operational amplifier shown in
Fig. 3 has an input offset voltage, Vos. Therefore, the voltage
at VREF can be generated as,
VVREF = VEB(Q8) + VOS (14)
Suppose VOS is a PTAT voltage, the remaining tempera-
ture behavior of VEB(Q8) can be compensated to achieve a
temperature-stable reference voltage. By this method, PTAT
voltage generator and weighted voltage summer can be simul-
taneously implemented in one structure.
In order to realize such a voltage follower and improve the
performance of proposed BGR, a differential amplifier with
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Fig. 10. Simulated temperature dependence of the proposed BGR.
offset voltage is adopted, whose principle is shown in Fig.3.
Since the tail-current source, IMN12 , is mirrored from μVT2
SBCS, the current of MN13 and MN14 is direct proportional
to μVT2 . Given IMN12 = LI 1 , MSMP15 = SMP16 , where
L and M are TI constants, then IMN13 = [L/(1 + M)]I1 .
Since SMP18 = SMP19 , SMP14 = SMP17 , VSGMP18 = VSGMP19
is realized. With the help of volt-ampere characteristics of
transistors biased in active region and Kirchhoff’s voltage
law, the input voltage difference of the proposed differential
amplifier is equal to the overdrive voltage difference between
MN13 and MN14. Therefore, the input offset voltage, VOS ,
can be expressed as,
VOS = K 3 T
where
for the realization of low TC voltage reference. As a result
of proposed temperature compensation method, the output
voltage VVREF of proposed resistorless BGR has a peak-
to-peak variation of 0.04mV with temperature ranging from
−40 °C to 85 °C. Compared with other resistorless voltage
references in the state of art, the temperature drift has been
greatly suppressed by proposed BEVL technique in this paper.
C. Startup Circuit
There are two startup circuits in the proposed BGR, the prin-
ciples are the same. Taken the startup circuit of μVTH
2 current
generator circuit as an example, it comprises of MNS2,
MPS3 and MPS4. Since the voltage at node A is high, and the
voltage at node B is low at the beginning of startup process,
MPS4 turns on. Then, the voltage at node B will be pulled up,
and there will be a current flowing into MP6. As a result, there
will be current through the core of SBCS to keep away from
degenerate points. Then, the voltage at node A will reduce
until MPS4 can be turned off. Thus the startup circuit will not
affect the normal operation of the proposed BGR.
D. Requirement of Supply Voltage
The minimum supply voltage of the high-order current
compensation circuit is defined by two emitter-base voltage
and a overdrive voltage, which is presented by,
VDD ≥ 2VEB + VOV (16)
where VOV is the overdrive voltage of MOSFET. The supply
(15) voltage of buffer with offset voltage is limited by the output
voltage, a source-gate voltage, and a overdrive voltage, which
is expresses as,

K3 = L/(1 + M) SMN4 /SMN13 M SMN13 /SMN14 − 1 VDD ≥ VVREF + |VTH(M P19)| + 2VOV (17)



× SMN4 /SMN1 + SMN4 /SMN1 + 1 (k/q) ln N
is a TI constant and is dependent on the ratio of transistors’
aspect ratio. Therefore, it is quite stable without the influence
of process, temperature, and supply voltage. That means the
variation of process and supply voltage has little impact on
the performance of generated reference voltage VVREF . With
regard to (6), temperature-linearized base-emitter voltage with
negative TC can be well compensated by the offset voltage
with linear positive TC.
Fig. 10 shows a simulation plot of temperature compen-
sated voltages versus temperature. The first one is the out-
put reference voltage of proposed structure, VVREF , which
exhibits high-order temperature-compensated behaviors with
0.35 ppm/°C. The second one is the temperature dependence
of VEB(Q8)(T ), and the corresponding TC is shown in the
third waveform. With the help of proposed BEVL technique,
the average TC of VEB(Q8) is around −1.63mV/°C and the
nonlinear variation is reduced to 1.22%. What’s more, the TC
of VEB(Q8) shows the second order effect. This means the
compensated base-emitter voltage in proposed resistorless
voltage reference has similar characteristics with the ζ = η
one in Fig. 1. By this method, it can provide a strong support
where VTH(M P19) represents the threshold voltage of MP19.
Other constraints on supply voltage come from the RLSBCS
circuits. The minimum supply voltage of μVTH 2 current gen-
erator circuit is,
VDD ≥ VTH(M N10) + VTH(M N7) + 3VOV (18)
where VTH(M N10) and VTH(M N7) represent the threshold volt-
age of MN10 and MN7, respectively. The limitation in μVT2
current generator circuit is,
VDD ≥ VEB + VTH(M N3) + 2VOV (19)
where VTH(M N3) represents the threshold voltage of MN3.
The minimum required power supply voltage of the pro-
posed reference is the maximum of these four constrains
in (16)-(19). In the prototype, the overdrive voltage of
MOSFETs is set around 150mV, and output reference voltage
is about 1.15V. The VTH is around 0.78V at 0 °C, and VEB
is about 0.7V at room temperature in the selected process.
Therefore, the minimum supply voltage is approximately 2V.
A 1-V supply operation can be achieved with low-threshold-
voltage devices and dynamic threshold MOS transistors [38].
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ZHOU et al.: RESISTORLESS HIGH-PRECISION COMPENSATED CMOS BVR
Fig. 11. Chip micrograph of the proposed BGR.
TABLE I
N OMINAL T RANSISTOR S IZES
2
2
IV. E XPERIMENTAL R ESULTS AND D ISCUSSION
A prototype of the proposed bandgap voltage reference is
fabricated in 0.35-μm CMOS technology, where VTH is around
0.78V and VBE is about 0.7V at room temperature. The chip
micrograph of the proposed BGR is shown in Fig. 11, and the
active area is 180μm × 220μm. Table I shows the nominal
values of main parameters used in the proposed BGR.
Since the inevitable drifts of transistor characteristics and
mismatches in reality have impacts on the performance of
voltage reference, corresponding methods are required to
reduce the influence. As above analyzed, the mismatch effect
can be greatly reduced with proper layout techniques for
device size ratios used in the proposed BGR. Besides, trim-
ming is a common method in voltage reference to weaken
the disturbance of process variations [26], [39]. With regard
to (4), (10), (11), (14) and (15), two-step trimming method
is adopted in this paper. One is used to trim the high-order
temperature linearization compensation current by changing
the current gain of MP8 and MP13; and the other one is for
PTAT offset voltage trimming by adjusting the current gain of
MN11 and MN12. A digital controlled binary-weighted aspect
ratio adjustment method is adopted [27], which places pro-
grammable devices in parallel with MP13 and MN12, respec-
tively. In the proposed design, BEVL is firstly optimized by
a three-temperature-point measurement to minimize the VBE
temperature nonlinearity. Then, the PTAT voltage is trimmed
7
Fig. 12. Measured temperature dependence of proposed BGR.
to counteract the temperature drift of VBE with BEVL. This
procedure is repeated until the minimum TC is achieved [40].
In the proposed design, the BEVL trimming is achieved by
a 4-bit trimming of MP13, whose equivalent channel width
ranges from 9.6μm to 57.6μm with a 32μm nominal value.
A 4-bit trimming of MN12 is adopted to calibrate the linear
temperature term in output reference voltage, whose equivalent
channel width can vary from 9μm to 54μm with a 30μm
nominal value.
Fig. 12 shows a plot of the measured output voltage versus
temperature for the trimmed reference. The output voltage
of the proposed BGR has a deviation smaller than 0.47mV
with temperature ranging from −40 °C to 125 °C. The
minimum temperature coefficient is 1.16 ppm/°C and the
maximum temperature coefficient is 2.66 ppm/°C with power
supply ranging from 2V to 5V. With the help of proposed
BEVL technique, there is only a limited temperature variation
on the reference voltage as a result of two linear temperature
items. As previously analyzed in (6), (14), and (15), the TC
of proposed BGR should be as small as that shown in the
simulated results. The nonideal aspects are mainly formed
by the following ones. The first one is error induced by
current mirror, which can be weakened by using relatively
long channel devices in necessary parts. The second one is
the body effect in the core of proposed RLSBCS. Although
this can introduce a little drift to the generated current for
VTH , the influence can be decreased by minimizing the
overdrive voltages. What’s more, the line regulation is 2mV/V
at room temperature. This benefits from the proposed feedback
techniques and reference structure.
Fig. 13 shows a similar plot with 2V supply voltage in
which ten references are trimmed, respectively, to minimize
the temperature dependence of proposed BGR. In order to
study the influence of die-to-die (DTD) and within-die (WID)
variations, the samples include VRs from different dies and
different wafers. The difference between the maximum voltage
and the minimum voltage exhibited by any of these references
between −40 °C and 125 °C is within 0.73mV peak-to-peak.
The optimized TC of VREF is in the range of 1.01 ppm/°C to
3.88 ppm/°C. Fig. 14 shows the performance distribution of
proposed BGR for the thirty samples after trimming. As shown
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

TABLE II
P ERFORMANCE S UMMARY AND C OMPARISON WITH O THER CMOS V OLTAGE R EFERENCES

Fig. 13. Measured temperature dependence of ten trimmed samples.

Fig. 15. Measured PSNA versus frequency.

achieves a 61 dB PSNA for frequencies below 1 kHz, and

Fig. 14. Characteristic distribution of proposed BGR. (a) Distribution
of VREF for 30 samples at room temperature. (b) Distribution of TC for
30 samples.
in Fig. 14 (a), the measured mean output reference voltage
at room temperature is 1.14055V with a standard deviation
of 11.15 mV. Fig. 14 (b) shows the measured TC distribution,
whose mean value is 4.03 ppm/°C with a standard deviation
of 2.31 ppm/°C.
Fig. 15 shows a measurement plot of PSNA versus fre-
quency with a 3V supply voltage and at room tempera-
ture without any output filter capacitor. The proposed BGR
greater than 57 dB PSNA for frequencies below 10 kHz.
The high noise rejection of proposed BGR profits from the
presented voltage reference structure and feedback technique.
The performance can be further improved when cascode
current mirror or long-channel transistors are used. However,
the required supply voltage will increase, which is not suitable
for low-voltage-reference design.
Table II summarizes the performance of the proposed BGR
and compares it with some voltage references previously
reported in literature, which were fabricated with a CMOS
process. Except [31], other voltage references are realized
without resistors. Besides, transistors biased in subthreshold
region are adopted in all the listed voltage reference except
the proposed BGR. Since subthreshold-region transistors have
instinct advantages in low power applications, the power
dissipation is attractive at the expense of accuracy for greater
influence from leakage current and imperfect device mod-
els. Although the power consumption of proposed design is
higher than those references, where transistors are biased in
subthreshold region, it can be greatly decreased with more
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
ZHOU et al.: RESISTORLESS HIGH-PRECISION COMPENSATED CMOS BVR
advanced technology and dynamic threshold MOS transistor
(DTMOS) [41]. With the help of presented techniques, the TC
of proposed voltage reference is much smaller than that of
all compared references listed in Table II. Moreover, the
performance stability of proposed voltage reference keeps the
superiority of BGR structures and is competitive to other pub-
lished resistorless references shown in the comparison Table II.
V. C ONCLUSION
A resistorless high-precision compensated CMOS BGR has
been proposed and implemented by standard 0.35-μm CMOS
technology. A higher-order curvature correction method,
BEVL technique, is presented to directly compensate the
thermal nonlinearity of base–emitter voltage. With regard
to feedback effects, a weighted sum of PTAT voltage is
realized by a unity gain amplifier with PTAT offset voltage.
Combined with RLSBCS, the PSNA performance has been
enhanced without increasing power supply. In this way, two
linear temperature-dependent items are obtained to achieve a
voltage reference with low TC, whose minimum operating
supply voltage can be down to 2V. Besides, the process
variations have less impact on the performance of proposed
BGR. The proposed BGR is well suited for many mixed signal
systems for its high precision and high performance, which
are especially important to integrated circuits implemented in
process without large or precise resistors. Future work is trying
to reduce the supply voltage further. That will greatly expand
the application range of proposed BGR.
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10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

[35] C. Popa and O. Mitrea, “Optimal curvature-compensated BiCMOS Zhiping Xiao was born in 1996. He is currently pur-
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junct. 23rd Int. Conf. Inf. Technol. Interfaces, Jun. 2001, pp. 507–510. system integration with the University of Electronic
[36] J. Chen, X. Ni, B. Mo, and Z. Wang, “A high precision curvature Science and Technology of China, Chengdu, China.
compensated bandgap reference without resistors,” in Proc. 8th Int. Conf. His current research interests include power convert-
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pp. 1–4. in 1995. He received the B.S. degree in microelec-
[40] P. Luong, C. Christoffersen, C. Rossi-Aicardi, and C. Dualibe, tronics from the University of Electronic Science
“Nanopower, Sub-1 V, CMOS voltage references with digitally- and Technology of China, Chengdu, China, in 2017,
trimmable temperature coefficients,” IEEE Trans. Circuits Syst. I, Reg. where he is currently pursuing the M.Sc. degree with
Papers, vol. 64, no. 4, pp. 787–798, Apr. 2017. the School of Electronic Science and Engineering.
[41] F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, His current research interests include voltage refer-
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operation,” in Proc. IEEE Int. Electron Devices Meeting, Dec. 1994,
pp. 809–812.

Ze-Kun Zhou was born in 1984. He received

the B.S., M.Sc., and Ph.D. degrees from the Uni-
versity of Electronic Science and Technology of
China (UESTC), Chengdu, China, in 2005, 2008, Xiaolin Liu was born in Tongjiang, China, in 1995.
and 2012, respectively, all in microelectronics. He He received the B.S degree from the College of
is currently an Associate Professor with the State Microelectronic and Solid State Electronic, Univer-
Key Laboratory of Electronic Thin Films and Inte- sity of Electronic Science and Technology of China,
grated Devices, UESTC. His current research inter- Chengdu, China, in 2017, where he is currently
ests include power management integrated circuits, pursuing the master’s degree. His research interests
power electronics, Class D amplifiers, LDO, refer- include power converters.
ence, and LED drivers.

Yue Shi was born in 1981. She received the B.S. and
M.Sc. degrees in microelectronics from the Univer-
sity of Electronic Science and Technology of China,
Chengdu, China, in 2004 and 2008, respectively.
She is currently with the College of Communi- Zhuo Wang received the M.Sc. and Ph.D. degrees
cation Engineering, Chengdu University of Infor- in microelectronics from the University of Elec-
mation Technology, Chengdu. Her current research tronic Science and Technology of China (UESTC),
interests include power semiconductor devices, Chengdu, China, in 2001 and 2015, respectively. He
power management integrated circuits, and power is currently as an Associate Professor with UESTC.
electronics. His current research interests are power management
integrated circuits and power device.

Yao Wang was born in Jingjiang, Jiangsu, China,

in 1993. He received the B.S. degree in electronic
engineering from Xi’an University of Posts and
Telecommunications, Xi’an, China, in 2011. He is
currently pursuing the M.S. degree with the Uni-
versity of Electronic Science and Technology of
China, Chengdu, China. His current research inter- Bo Zhang was born on in 1964. He received the
ests include switching mode power supply, refer- B.Tech. degree in electronic engineering from the
ence, energy harvesting, and maximum power point Beijing Institute of Technology, China, in 1985, and
tracking. the M.Tech. degree from the University of Electronic
Science and Technology of China (UESTC) in 1988.
From 1988 to 1996, he was with UESTC, where
he was involved in power semiconductor devices
research and development. From 1996 to 1999, he
Nie Li was born in 1988. He received the B.S. and
was a Visiting Professor with the Virginia Poly-
M.Sc. degrees in microelectronics from the Univer-
technic Institute and State University, Blacksburg,
sity of Electronics Science and Technology of China,
USA, where his research activities include device
Chengdu, China, in 2011 and 2014, respectively.
simulations, power semiconductor cryogenics, SiC power devices, and other
He is currently with the Tsinghua Energy Internet
Si-based power semiconductor devices. Since 1999, he has been involved in
Research Institute. His research interests focuses on
power devices and smart power integrated circuits. He is currently a Professor.
power management integrated circuits, include dc-dc
He is also the Vice-Dean with the School of Microelectronics and Solid-State
converters, E-Fuse, and LDO.
Electronics, UESTC, and the Director of the Power Integrated Technology
Laboratory, UESTC. He has authored or co-authored over 100 papers in
international conferences and journals.