UR ONIE Yi PRT OT sture 22: Integrated fabrication Contents Introduction Tbeyeriog Patterning Doping 4.1. Thermal dif I Heat treatment MOSFET fabrication 1 Introduction The starting material f tal silicon wafer, The en ready for packaging a al test veing customer. The inte i fer fabrication (in cluding sort), Wafer fabr used to create semicondu Some common wafer terminol chip. These re specific functionality. T vst com and interchangeably refer andalone wafer surface. Thu ‘wafer can be said to be divided into m 8, as shown in figut 1Woetyonte anatortald Avie jan Fabel ation NMQOIT o 1: Schematic of wafer showing the division into individual dies, One dual die with electrioal contacts is also shown, Some of these dies for testing. Dies at the edge dies are incomplete, Adapted from ship fabrication - Peter van Zant.a — Figure 2: Schematic of various componen line (3) Test die (4) Edge chips ( Adapted from Microchap fabricat nn the dies is called a sc jual dies when the fabrication is The area betw arating the in can be blank but most often they consist of test stru tlectrical testing (e-test) during fabrication. This hel process issues during fabrication, without having to wait to be made. Along with the regular ICs, test di These dies are used for electrical testing at the end, for process or quality control. There are also some partial or edge dies at the corners of the wafers, These arise because the wafers are circular while the dies are usually rectan- gular. Comer dies cau be used for making smaller testing circuits for process control The various clements described above are marked in figure 2, Larger the wafer, more the munber of chips that can be manufactured (inchiding edge chips). Consider the Intel 17 core processor (codename Ivybridge) with a die rr enginvering dies are also fabricated.and fa orials, device Bieetronic mat MM 0 dies vo a total of 440 dies ee tal number of dic 100 mm wafers, afr, ee total number ¢ om ode re cnculatin). To exclude oe e201 (re af wafer by ae of de EWAN oy 30 zal to jes yore eeonon wwe can take the die to be a squar me ee a ool costs associa ated facture on larget wafers, butt (0 fab There are a number of different steps in 1 her, ; Samecnen Ge steps in the pr 2 Layering The layering step is use todd thin layers to the fa different material ora different he sumne material (polycrystalline Si or ¢ 3 shown jon of a simple MOSI " thin layers, Bf the device. The diferent layers hep ng the var of the MOSFET aa in obt nal device e.g ayer helps in contacts to Layering ean be of many diferent type rent types, though they id deposited, aining a funct ‘rically isolating the metal ¢ categories: grown secs erations are shown in figure 4 re ean ts undying wafer material (fy i tial (typically $)) ig Tis is formed by oxidation ot Si into ie example is the ture in figure 3. ly done in tw ways og Dry ox: $1 (s) + 0, (9) 120 (9) + Sidg (4 > $40, (5) + 2H (9) a)mnie materials, devices, and fabrication MMSO17: Bleet Souree i Gate Oxide Oxide) \ pst ( i Figure 3: Cross section of « MOSFET showing the different layers. Poly Si is ured as gate with SiN, used as the interlayer dielectric. Layering is the process by which all of these different Adapted from Fundamentals of semicondu control - May and Spar Layering operations iscown Deposited Oxidation evo Nitridation Evaporation Sputtering Electroplating All layering steps are classified Figure 4: Different kinds of layering steps. into two major types. Grown layers use the unde form new layers. Deposited layers do not consume to the surface. Adapted from Microchip fabrication erlying silicon substrate to the silicon but are added Peter van Zantxd fabrication ie manorial, GOVE an uatsor7: Electron! Furnace os To vent A Welanier Ne Hs Nel yoorent + He soit a Rar 8 CVD proces fr ath ed on he wes The ree rae er a rn in ee Scan be dope and i sel ws eae s control - May Fund = J semrconductor manufacturing and proces: ‘ Si layer. For further oxidation, the oxidizing species (O2 or H2O) ided on top. An example of this is the growth of epitaxial layers nical vapor deposition (CVD) process. ‘The epitaxial layer grown al as the substrate (homoepitary) or can be a dif- ary). Si can be grown epitaxially on Si wafers by Sila (9) + 2He(g) > Si (s) + 4HO1 (9) (2) T ox show: ain figure 5. The chemical reaction in CVD takes places mp ne. It wy lr pow ih op ches weve CVD provides conformal taaingy” Fgees oe of CVD growth of CrB, on de *P trenches: i vb. a w epitaxy (MBE) is another pont oer itil ayer ate evaporate fons soo Shen combine on the substrate to ton ct ratio structures ave where the cou- rate sources (‘molec the epitaxial layer ca be gown by MEN be grown hy MBE ye pe this P-type, Be can 2 a with Gn an As under phytic! rp Be capcanet also be evaporated i¢ 2 eee of layering opera. siepostion techniques when’? nto the wafer This can i ie «l for 6materials, devices, and fabrication deep trenches. The Figure 6: Chromium boride coatings grown by CVD conformal to the trench dimensions. This can coatings are highly shied by other deposition techniques since the opening wil be Bilt NP the trench. Source http://abelson.rnatse.illinois. ct before depositing in and other types of layers. Electroplating is another fd for depositing copper, which is used metals, oxides Jayering operation. ‘This is mainly as interconnects in the IC 3 Patterning is one of the most important steps in wafer fab: Patterning or lithograph; rication. Patterning refe portions of the surface for dep “The drive to pack more devices in « y to pattern smaller regions in the s is related to 5 to a series of stops to selectively mask or expose It sets the critical di. ition /doping/etching, p (smaller mensions of the device devices) is directly related to the water. The challenges in reduction patterning, The process is highly defect sensitive, espelte'Y Be shown in figure 7. Presence of defect particles in the patle™™ © affect the later steps like deposition doping/etch! of other layers. To make a pattern, reticle has to be first pre py of the design that is then transferred on abil of device size in recent I at smaller sizes, » and can also affect pattering red. Reticle refers to the hard pal to the chip. This hard copysumpoit 6 / % Defects on patterning proces +s, Pie 7. of ert pain a Fea Not al detects are killer defects nto killer defects. Ada 3 control - ba i vemconductor mansfocturing ond Pr May and Spano: ter ser beam or electron beam, is generated by ‘writing’ the pattern, using a laser be nrome coated glass. The design is then copied on to the chip using a suitable photoresist and UV exposure. The pattern transfer bve 1: Lor the sive can be reduced by a suitable lens system. Either the pattern or its negative can be transferred by suitable choice of photoresist i rized in figure 8. Use of photoresists for patterning is an example of a soft mask since the mask cau be easily removed without damaging the underlying substrate. Sowetines oxide or nitride layers are also used as anasks for pattern transfer Those are called hard masks, since these masks can withstand high temper le resints cannot anc they also need aggressive chemical procedures Thus, itis dificult to combine lithography with de D (where hard mask would be needed) but it can sporition pro- be used with therinal evaporation, sputtering, and e-beam deposition, jing m to the process where specific amounts are incorporated through ope aus _of lectrcally active alate typically porn type impusities and they race, The na impurities and they are m Me is rans, condos, ad etre ee fo levices 8MMS017) Bleetronie materials, devices, and fabrication f Figure 8: Overvies ative photoresists. P to wafer, while from Fundamentals of semiconductor manufacturing and proce May and Spanos. 3 directly transfer the pattern from reticle the patterning process, showing both positive sitive re tive resists transfer the inverse of the pat control hifabrication os, and ed from ‘Microchip piewe 9: porn ype dope penn Mate ae ¢ region where dopit tna to control the re fabrication - Peter wan Zant. ities, for Si, vical p type impurities, : thst combine to frm the IC, Typied PW formation of @ deed ae sept che wafer is shown in figure 9. ‘There are two my ion in a section of the wafer is st teciniques for doping 1. Thermal diffusion 2. Ton implantation Both processes produce different dopant concentration profiles at and below the surface, as shown in figure 10. 4.1 Thermal diffusion ‘As the name implies, in thermal diffusion, doping is carried out by movement ‘the dopant material from the surface tothe bull, by a thermally activated giffusion can be initiated from dopants in a vapor, liquid, or a ywafer has to be heated to high temperature, around 1000 diffusion process. Thus, thermal diffusion cannot be hy masks and a hard mask like oxide or nitride is ing in Si, some typical dopant materials are Sba0, (3), . POCL (04 (6), and PH (g). For p type Seoksy Puts, BxOs (6) and BCs (g). ‘Thermal diffusion % {though difusion rates might be different in differotand fabricat MM5017: Elect Gor of ‘dopant High velocity dopant ») stration profiles in (a) diffusion, the highest the highest concen: ic of the doping process aud conc ion, In therm plantation amentals of 8 Figure 10: Schemati thermal diffusion and (b) ion implantat concentration is at the surface while for ion imp tration is below the surface. Adapted from manufacturing and process control ~ May and Spanos. u° 2 (OSFET fabricationM017) fi ihe Wwetronie materialy, devices, aut falyrieatinn, (| il Figure 11: An overview showing tho various steps in MOSFET fabrication (a) Sturing wafer is (b) oxidized and then (c) patterned to grow the field oxide. (d) Poly Si ix then deposited and (e) patterned to form the top of the oxide, (f) A further patterning « source and drain and (g) finally metallization is done to define th \dapted from Microchip fabrication ~ Peter van Zant. ‘eeOrin sk Feld ride Stating Weer Mesh end Grow Gate Oxide 1 doping is done to define the backs,MMB017. Bloctanie matorials, deviees, and fabriemtion the lant atop in a pattorning stop the panel t sot wn ie Hyst Thin 13-step process illustrates thy va opm to make » MOSFET fe Si. Similarly, therw are ntoyw for making, oth joo componente, AML of thene are i pw final | Hit. Along. with ing thore are itn 1 At vation stagon and el 4, at tho om This in to make mire that dovier rpeciflentions are correc f This includes the physical dinennions of the vastou 1 an height) and the oloctrieal prope V chatactorint