IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.
1, JANUARY 2006
Overview of the Architecture, Circuit Design, and
Physical Implementation of a First-Generation
Cell Processor
Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox,
Paul Harvey, Paul M. Harvey, Member, IEEE, H. Peter Hofstee, Member, IEEE, Charles Johns, Jim Kahle,
Atsushi Kameyama, Member, IEEE, John Keaty, Member, IEEE, Yoshio Masubuchi, Member, IEEE,
Mydung Pham, Jürgen Pille, Stephen Posluszny, Mack Riley, Daniel L. Stasiak, Masakazu Suzuoki,
Osamu Takahashi, Member, IEEE, James Warnock, Member, IEEE, Stephen Weitzel, Member, IEEE, Dieter Wendel,
and Kazuaki Yazawa, Member, IEEE
Abstract—This paper reviews the design challenges that current
and future processors must face, with stringent power limits,
high-frequency targets, and the continuing system integration
trends. This paper then describes the architecture, circuit design,
and physical implementation of a first-generation Cell processor
and the design techniques used to overcome the above challenges.
A Cell processor consists of a 64-bit Power Architecture processor
coupled with multiple synergistic processors, a flexible IO inter-
face, and a memory interface controller that supports multiple
operating systems including Linux. This multi-core SoC, imple-
mented in 90-nm SOI technology, achieved a high clock rate by
maximizing custom circuit design while maintaining reasonable
complexity through design modularity and reuse.
Index Terms—Bus interface controller (BIC), cell processor,
element interconnect bus (EIB), flexible IO, hardware content
protection, local store, media-centric computing, memory inter-
face controller (MIC), modularity, multi-core, natural human
interaction, Power Architecture, power processor element (PPE),
real-time system, simultaneous multi-threading, SoC, synergistic
processor, virtualization, 90-nm SOI.
I. INTRODUCTION
T HE architectural vision of “bringing supercomputer
power to everyday life” is the driving force behind the
Cell processor design, setting a new performance standard
by exploiting parallelism while achieving high frequency [1].
Cell is designed for natural human interactions: photorealistic,
predictable real-time response, and virtualized resource for
Manuscript received May 15, 2005; revised August 15, 2005.
D. C. Pham, D. Boerstler, M. Bolliger, R. Chaudhry, P. Harvey, P. M. Harvey,
H. P. Hofstee, C. Johns, J. Kahle, J. Keaty, M. Pham, J. Pille, S. Posluszny,
M. Riley, D. L. Stasiak, O. Takahashi, and S. Weitzel are with the
IBM Systems and Technology Group, Austin, TX 78717 USA (e-mail:
dacpham@us.ibm.com).
T. Aipperspach and D. Cox are with the IBM Systems and Technology Group,
Rochester, MN 55901 USA.
A. Kameyama and Y. Masubuchi are with Toshiba America Electronic Com-
ponents, Austin, TX 78717 USA.
M. Pham is with the IBM Systems and Technology Group, 11501 Burnet
Road, Austin, TX 78758 USA.
M. Suzuoki and K. Yazawa are with Sony Computer Entertainment, Tokyo,
Japan.
J. Warnock is with the IBM Systems and Technology Group, Yorktown
Heights, NY 10598 USA.
D. Wendel is with IBM Entwicklung GmbH, Boeblingen 71032, Germany.
Digital Object Identifier 10.1109/JSSC.2005.859896
0018-9200/$20.00 © 2006 IEEE
179
concurrent activities. Cell supports multiple operating sys-
tems including Linux, and is designed for flexibility with a
wide variety of application domains. Other attributes include
hardware content protection and extensive single-precision
floating-point capability. By extending the Power Architecture
with synergistic processor elements (SPE) having coherent
direct memory access (DMA) to system storage and with
multi-operating system resource management, Cell supports
concurrent media-centric and conventional computing. With a
dual-threaded power processor element (PPE) and eight SPEs
this implementation is capable of ten simultaneous threads and
over 128 outstanding memory requests.
II. ARCHITECTURE OVERVIEW
The first-generation Cell processor consists of eight SPEs
[2], each with its own local store (LS) [3], the PPE and its
L2 cache, a high bandwidth internal element interconnect bus
(EIB), a memory interface controller (MIC), a bus interface con-
troller (BIC) providing two configurable noncoherent IO inter-
faces, a pervasive unit that supports extensive test, monitoring,
and debug functions, a power management unit (PMU), and a
thermal management unit (TMU). The high-level chip diagram
is shown in Fig. 1, along with a die photograph in Fig. 2. Each
of these major components is described in turn in the following
discussion.
The SPEs share system memory with the PPE via coherent
translated and protected DMA, but store data and instructions
in a private real address space supported by a 256 K local
store, with one array dedicated to each SPE. The SPEs provide
much of the computational performance of the Cell processor.
Each of the eight processors contains a 128-bit wide dual-issue
SIMD dataflow that is fully pipelined for all operations except
double-precision floating-point. Operands are provided by
a unified 128-entry by 128-bit-wide register file. The single
ported LS supports full-bandwidth concurrent read and write
DMA to the EIB, as well as 16-byte SPE loads and stores
and instruction (pre)fetch. The SPEs access main storage by
issuing DMA commands with an effective address (EA) to the
associated memory flow control (MFC). The MFC applies the
standard Power Architecture address translation to the EA and
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Fig. 1. Processor high-level diagram.
Fig. 2. Processor die photograph.
then asynchronously transfers data between the local storage
and main storage. This allows overlapping communication
and computation, facilitating real-time operation. SPE access
to shared memory via DMA, a large register file, and stan-
dard in-order execution semantics provide a general-purpose
streaming programming environment. Each SPE can be dynam-
ically configured to operate in a mode in which its resources can
only be accessed by validated programs. The SPE is organized
in a modular fashion, so that a single integrated SPE physical
entity is placed 8 times on the chip.
The PPE is a 64-bit processor compliant to the family of
Power Architecture processors [4], [5]. It is implemented as a
dual-threaded core with the integer, floating point, VMX, and
MMU units of the Power Architecture. The processor contains
32-kB instruction and data caches, a 512-kB L2 cache, and
on-chip bus interface logic. The PPE core is a completely new
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006
implementation, built from the ground up with an extended
pipeline to achieve a low FO4 cycle time to match the SPE. The
core is an enhanced in-order design with a moderate pipeline
length to provide state-of-the-art performance capability. The
PPE has been extended with resource management tables for
the cache and translation tables to support real-time operations.
Through memory mapped IO (MMIO) control registers, the
PPE can also initiate DMA requests on behalf of an SPE
and can support communication with SPE mailboxes. It also
implements the Power Architecture hypervisor extension to
allow multiple concurrent operating systems to be run on it at
the same time through thread management support.
The EIB is central to the Cell processor. This coherent bus
transfers up to 96 bytes per processor cycle. The bus is orga-
nized as four 16-byte-wide (half-rate) rings that each support
up to three simultaneous data transfers. A separate address and
PHAM et al.: ARCHITECTURE, CIRCUIT DESIGN, AND PHYSICAL IMPLEMENTATION OF A FIRST-GENERATION Cell PROCESSOR
Fig. 3. Element interconnect bus (EIB).
command network manages bus requests and the coherence pro-
tocol. Each of the 12 on-ramps to the bus and 12 off-ramps are
16 bytes wide and operate at half the base clock rate. Fig. 2
shows the location of the EIB relative to the other units within
the processor die. Fig. 3 shows the physical interleaving of the
bus, designed to minimize noise coupling issues.
The MIC supports two Rambus XDR memory banks. Each
bank is 36 bits wide with an independent control bus. The two
banks are interleaved in the processor’s address space, but for
increased system flexibility, the MIC can be configured to sup-
port just a single bank of XDR memory. For added reliability, the
MIC supports ECC and a periodic ECC scrub of memory. The
XDR interface operates asynchronously to the processor and
IO interfaces; hence, the MIC contains speed-matching SRAM
buffers and logic, and requires two clock domains. One clock
domain operates at half the global processor clock rate, while
the other domain operates at half the rate of the XDR inter-
face. When the processor frequency is lower than that of the
XDR, the MIC is configured to pace memory requests in order
to avoid overrunning the SRAM buffers. The asynchronous in-
terface not only provides for greater flexibility, but the separa-
tion of clocks also allows the processor to be stopped and its
system state scanned out without affecting the training of the
transceiver. This training is required as a result of the high speed
of the XDR interface, with the training sequence performed by
either the PPE or an SPE.
The BIC provides two flexible interfaces with varying pro-
tocols and bandwidth capabilities to address differing system
requirements. The interfaces can be configured as either two IO
interfaces (IOIF 0/1) or as an IO and a coherent SMP interface
(IOIF and BIF). With seven transmit and five receive bytes of
Rambus RRAC IOs, this design provides substantial bandwidth
support. For increased flexibility, the RRAC transmitters and re-
ceivers operate asynchronously to the processors and memory,
and the available bandwidth is configurable between the two in-
terfaces. In addition, the RRACs for one of the interfaces can be
run at half rate. The design thus supports multiple configurations
without the need to redesign or repackage the chip. The BIC
provides an asynchronous interface between the EIB and the
two IO interfaces, and hence contains speed-matching SRAM
buffers and logic with three clock domains. The processor side
operates at half the global rate, while the IO side operates at one
third the rate of the RRACs, with a small distribution network
operating at half the rate of the RRACs. For BIC and RRAC cal-
ibration, required to support the high speed of the transmitters
and receivers, an elastic buffer is used to eliminate the skew be-
tween the bytes comprising the interface.
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The pervasive unit contains all of the global logic needed for
basic functional operation of the chip, lab debug, and manufac-
turing test. For each of these areas, described in detail below,
debug mechanisms have been incorporated into the design to as-
sist with bring-up and characterization of the logic and circuits.
The pervasive unit provides several features needed to sup-
port basic functional operation of the chip. The unit contains a
serial peripheral interface (SPI) that is used by an external con-
troller to communicate with the chip during normal operation,
and to receive status information from the pervasive unit. The
SPI interface is also used by the external controller to train the
high-speed IO. In addition, the pervasive unit provides the con-
trol for the clock generation and distribution. This logic enables
the correct phase-locked loop (PLL) functions on the chip, de-
termines which clocks are active on each of the different clock
grids, enabling/disabling asynchronous clocks as required, and
maintains the phase relationships between full-speed and half-
speed clocks across the chip. Power-on reset (POR) is another
base function that is provided here. The POR engine for the Cell
processor is a 32-instruction state machine that systematically
initializes all the units of the processor. The POR engine has
four hard-coded initialization sequences that can be selected by
configuration pins on the chip. The POR engine also has a debug
mode that allows its instructions to be single-stepped, skipped,
or performed out of order.
For lab debug and bring-up, the pervasive unit contains chip
level error checking and reporting mechanisms. Global fault iso-
lation registers are provided to allow the operating system to
quickly determine which unit generated an error condition. To
assist with performance analysis, a performance monitor (PFM)
is provided, which consists of a centralized unit connected to all
functional units on the chip via a the trace/debug bus. To assist
with debug, an on-board trace logic analyzer (TLA) captures
stores internal signals while the chip is running at full speed.
The TLA is programmable and allows complex trace/capture
sequences to be created. An on-chip control processor, with
an IEEE 1149.1 interface, is also available to help with debug.
The pervasive logic interfaces with this processor to control and
monitor the chip internal logic.
For manufacturing test, the pervasive unit supports 11 dif-
ferent test modes, which include debug mechanisms to assist
with test pattern development and bring-up. Array built-in self-
test (ABIST) is one such mode controlled by the pervasive unit.
The ABIST engines are programmable to provide debug ca-
pability and the ability to add customized test patterns during
manufacturing test. All ABIST engines are operated in parallel
to reduce test time. Logic BIST (LBIST) is also provided, by
means of a centralized controller housed in the pervasive unit
and 15 LBIST satellites elsewhere in the design. Both ABIST
and LBIST are capable of scanning and capturing data at full
functional speed to improve AC test speed, and all internal scan
chains are timed at the full functional speed to support this re-
quirement. Finally, the pervasive unit provides the logic used
for programming and testing electronic fuses (eFuses), which
are used for array repair and chip customization during manu-
facturing test.
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Fig. 4. Digital thermal sensor schematic.
Power dissipation and thermal design are two key is-
sues which were considered early in the development of the
first-generation Cell processor. For power reduction, a power
management unit (PMU) provides a mechanism to allow soft-
ware controls to reduce the chip power when the full processing
capabilities are not needed. The PMU allows the operating
system to throttle, pause, or stop single or multiple units, or
the entire chip, in order to manage chip power. For thermal
monitoring and control, the processor employs two types of
thermal sensors and a hardware controlled thermal manage-
ment unit (TMU). A linear diode connected to two module
pins allows an external device to monitor the temperature of
the processor. This sensor is located in a relatively constant
temperature location, giving a reading of the global temperature
of the processor. This sensor is designed to be used for control-
ling external cooling mechanisms. Ten digital thermal sensors
(DTS) are distributed on the chip to monitor temperatures in
critical local regions. One DTS is located in each element and
one is adjacent to the linear sensor. The TMU continuously
monitors each digital thermal sensor and can be programmed
to dynamically control the temperature of each processing
element and interrupt the PPE when a temperature specified for
each sensor is observed. The temperature of each element is
controlled by adjust the instruction issue rate (i.e. throttling) a
processing element based on the temperature of the associated
DTS. Software controls the TMU by setting four temperature
values and the amount of throttling for each sensor in the TMU.
In increasing temperature, the first temperature specifies when
the throttling of an element stops, the second when throttling
starts, the third when the element is completely stopped, and
the fourth when the chips clocks are shut down. The first two
temperature levels provide some level of hysteresis to avoid
frequent transitions between throttling and normal operation.
The third level stops the processing element when throttling
alone is not enough to control the temperature. As long as the
temperature is maintained below the third level, the processing
element is guaranteed to achieve a certain performance level to
meet the real-time needs of an application. When the temper-
ature exceeds the safe operating range, specified by the fourth
level, the TMU automatically shuts down the chip clocks to
avoid permanent damage to the chip.
The DTS employed in the first-generation Cell processor is a
diode-based design with a programmable temperature set point.
Fig. 4 shows a schematic of the DTS. The diode reference
voltage (Vref_diode) linearly decreases with increasing tem-
perature while the reference voltage (Vref) linearly increases
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006
with an increase in temperature. By comparing Vref_diode to
Vref, the temperature can be determined to be below or above
the temperature associated with the reference voltage. The DTS
provides many reference voltages and an analog multiplexer for
the selection of which Vref to compare. The TMU constantly
changes the selection to find the reference voltages where the
comparison (Tx Detect) changes. Once determined, the tem-
perature is within the range associated with reference voltages.
The voltage difference between each reference corresponds to
a 2 C temperature difference. While the relative difference
is constant, the absolute temperature varies with process. To
eliminate the process variance, each DTS is calibrated during
manufacture of the chip.
III. CMOS TECHNOLOGY SOI AND PACKAGING
TECHNOLOGY OVERVIEW
The Cell processor was designed in a 90-nm PD-SOI
process. The choice of the technology characteristics was
crucial in being able to meet the design goals of the chip. Previ-
ously, designers of high-speed systems were mainly concerned
with performance and area, but current and future designs must
meet the triple constraints of power, performance, and area. In
addition to system-level controls such as clock gating, and cir-
cuit level control such as low-power latch designs, technology
choices of device thresholds, voltages, oxide thicknesses, and
channel lengths are keys to controlling the power. Table I shows
the technology parameters.
The 90-nm device targets included a 10.5-A gate oxide thick-
ness, 46-nm channel length, and a nominal voltage of 1 V. This
device had the requisite performance to achieve the frequency
goal at the 11FO4 design point. The optimum point for the
device definition was a balance between the various character-
istics. A thinner gate oxide would result in potentially higher
performance but with significantly higher gate tunneling cur-
rent and reliability concerns especially at the slower end of the
process window. A shorter channel length or lower threshold
voltage would result in potentially improved performance at the
expense of significantly increased leakage current especially at
the faster end of the process window. A higher voltage would
result in more performance but higher AC and DC power across
the process window. A detailed study of these gradients was
conducted to determine the optimum design point. Since not all
devices are used in circuits with critical delay paths, an addi-
tional higher threshold voltage (HVT) was used to help reduce
the power of the chip. The HVT device was used throughout the
design in logic blocks, array cells, and analog designs.
PHAM et al.: ARCHITECTURE, CIRCUIT DESIGN, AND PHYSICAL IMPLEMENTATION OF A FIRST-GENERATION Cell PROCESSOR
TABLE I
TECHNOLOGY PARAMETERS
Analog designs required additional devices with significantly
longer channel lengths and a thicker gate oxide. The thicker
oxide device relied on a 22.5-A gate oxide, and channel lengths
up to 20 times the minimum value were used. In addition, in
PD-SOI designs, body-contacted devices are used for better
control and tracking of threshold voltages. Chip decoupling
capacitors had the added option of using an intermediate oxide
thickness of 15 A.
The metal stack used in wiring and powering the chip was
another major design consideration. It was important to match
the performance of the device with a low- high-performance
metal approach. The optimization of the wiring scheme was
carried out in a fashion similar to that of the device definition,
subject to the triple constraints described above. Too few levels
of wiring would have increased chip area, and too many levels
would have added cost without reducing the chip size. An eight
layer of metal stack was used with five layers of 1 wiring, one
layer of 2 wiring, and two layers of 6 wiring, in addition to
a local interconnect.
The electronic package design was driven by the high off-chip
signal bandwidth and low-noise power delivery requirements
of the Cell processor. A systematic and comprehensive study
of various packaging options resulted in an optimized flip-chip
plastic ball grid array (FC PBGA) package comprised of a thin
core, multi-layer build-up substrate with decoupling capacitors
mounted on the opposite side of the package substrate directly
underneath the chip, and a thick lid in thermal contact with the
backside of the die via a thermal interface material, as illustrated
in Fig. 5.
Careful planning and coordinated co-design of the chip,
package, and prospective system afforded optimal performance
at minimum cost. In this design, high-speed differential nets
are routed off two sides of the chip into corresponding sides of
the package. The high-speed nets are routed in the top build-up
layers and then transitioned to the BGA balls through optimized
signal via structures. Isolated analog supplies that service the
183
Fig. 5. Cross section of Cell processor package.
IO partitions on the chip are routed in the bottom build-up
layers from interior BGA locations in the same region of the
package. Other sides of the chip and package are principally
dedicated to core power distribution as well as to PLL, test,
and various other miscellaneous signals. The Cell processor is
designed for power-limited applications, and employs gating
algorithms and other methods to intelligently reduce overall
power usage. While these techniques contribute to the overall
power reduction, they can also spawn unique noise events
which must be taken into account in package design and anal-
ysis by ensuring a robust mid-frequency AC noise response.
The package substrate facilitates fine-pitch mechanical drilling
which minimizes the effective inductance loop between the
chip and the module decoupling capacitors and enhances the
mid-frequency response to on-chip current fluctuations. Con-
tinual advances in fine-pitch substrate drilling have enabled
high-performance laminates at reasonable cost.
Statistically derived design rules which account for all man-
ufacturing tolerances were used to route all high-speed differ-
ential nets. Thermomechanical reliability tradeoffs were also
considered in the optimization of the via structures used in the
package. Signal and power distribution integrity in the package
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Fig. 6. PLL block diagram.
was verified by quasi-static 2-D and 3-D and full-wave 3-D elec-
tromagnetic extraction and simulation and validated by passive
characterization of specifically designed test vehicles. Final ver-
ification was done by passive and active characterization of the
initial prototype hardware.
IV. CIRCUIT DESIGN OVERVIEW
A. PLL
Fig. 6 shows a block diagram of the PLL [6] containing a
differential receiver, a phase-frequency detector (PFD), charge-
pump (CP), current reference (IREF), filter capacitor/low-pass
filter (LPF), voltage-controlled oscillator (VCO), and frequency
dividers in the forward (VCODIV) and feedback (FBDIV) paths
for frequency-scaling capabilities. The PLL power is supplied
by a separate analog supply (AVDD), while the logic circuits
and PLL-to-logic level shifters are powered by the regular chip
supply (VDD). The typical supply voltages for both AVDD and
VDD range from 0.8 to 1.2 V.
Self-resetting CMOS PFD architectures have previously
been described [7] which effectively eliminate any dead zone
using a combination of simple static and dynamic circuits.
This PFD design used similar concepts but with enhanced
resetting techniques for extending the performance to higher
frequencies. Fig. 7 shows the PFD topology consisting of
symmetric paths containing enabling latches, dynamic triggers,
and pulse stretchers for the reference clock (REF) and feedback
clock (FB) paths, and a common reset generator path. When
the REF signal arrives before FB, the dynamic trigger for REF
responds to the rising edge of REF, causing Q to rise and
issuing a fast localized disable of the trigger. The UP output
is then asserted after a delay created by the two inverters.
A subsequent rising transition of FB similarly causes the FB
trigger to respond and issue its own local disable. After delay
of the three inverters, the UP output is stretched by an amount
. The reset generator signal R1 now forces a reset to
both enabling latches in preparation for the reset of the triggers.
After some delay, the reset generator signal R pre-charges
both dynamic triggers, which in turn force R and R high,
completing the reset process. Finally, when REF and FB falling
transitions occur, the triggers are enabled in preparation for the
next cycle.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006
Fig. 7. Phase-frequency detector.
Fig. 8. Interleaved VCO with five delay elements.
To reduce the large transient turn-on currents that can occur
in the CP, a conventional CP circuit topology has complemen-
tary current paths added to it which prevents internal switching
nodes from drifting toward the supply rails during the high-
impedance OFF state [6]. Matched replica devices are also added
to the CP and are connected to opposite polarities of the control
signals from the PFD to counteract the error introduced by para-
sitic gate-source and gate-drain capacitances during switching.
Direct feed-forwarding of the PFD signals into the VCO was
used to avoid the problems normally associated with integrated
PLL resistors, such as high capacitance and lack of adjustability.
The VCO [8] consists of a ring of five delay elements with in-
terleaved control/feed-forward connections as shown in Fig. 8,
where each delay element consists of a main ring inverter, a
control section, and a feed-forward section (Fig. 9). The VCO
uses mostly two levels of device stacking, contributing to large
signal swings, high operating frequency, and low-voltage oper-
ation. Simulated VCO gain for the interleaved VCO design is
9.4 GHz/V.
Body-contacted devices were used in areas of the PLL where
the history effect [9] caused by SOI may be a concern, although
this usually resulted in a larger area and increased parasitic.
Body contacts were also used in the analog circuits to improve
threshold voltage ( ) matching, and to reduce current variation
with drain-source voltage .
Fig. 10 shows the lock range as a function of AVDD for
the PLL, where and represent the maximum and
minimum lock frequencies, respectively. The measured
PHAM et al.: ARCHITECTURE, CIRCUIT DESIGN, AND PHYSICAL IMPLEMENTATION OF A FIRST-GENERATION Cell PROCESSOR
Fig. 9. VCO delay element.
Fig. 10. PLL lock range versus analog supply voltage Avdd.
increases roughly linearly with frequency from 6.6 GHz at
0.804 V to 16.4 GHz at 1.337 V and maintains an average
ratio of 2.6 over this range. Above 1.3 V, the slope
of decreases significantly, and a maximum lock frequency
of 17.5 GHz was measured at 1.819 V for this part. 10.0 GHz
operation was achieved at a supply voltage of less than 0.960 V.
The maximum PLL lock frequency measured was 21.424 GHz.
Cycle-to-cycle (C-C) jitter measurements were taken using a
proprietary time-interval analysis tool. Fig. 11 shows the C-C
jitter histogram taken at 1.2 V for the PLL output divided by 32
with jitter of 12.7 ps peak-to-peak, 1.57 ps rms. The minimum
C-C PLL jitter measured was 9.48 ps peak-to-peak, 1.09 ps rms.
B. Clock Distribution
The chip contains three distinct clock distribution systems,
each sourced by an independent PLL, to support processor, bus
interface, and memory interface requirements. A main high-
frequency clock grid [10] covers over 85% of the chip, deliv-
ering the clock signal to processors and miscellaneous circuits.
Second and third clock grids, each operating at fractions of the
main clock signal frequency and covering areas of 8 mm and
15 mm , respectively, are interleaved with the main clock grid
structure, creating multiple clock frequency islands within the
chip. In these interleaved regions, logic circuits are permitted to
operate from either the main clock frequency or the auxiliary
clock frequency, or from both.
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Fig. 11. PLL jitter histogram at 16 GHz cycle-to-cycle jitter = 12.7 ps
peak-to-peak, 1.57 ps rms.
The clock distribution is an extension of a previous Power
clock distribution design [11], enhanced for significantly higher
performance over the predecessor designs, and for lower power
dissipation at a given clock frequency. All clock grids were con-
structed on the lowest impedance final two layers of metal, and
supported by a matrix of over 850 individually tuned buffers.
This enabled control of the clock signal arrival times and tran-
sition rates, especially for the main clock grid, which covers
most of the area of the chip and encompasses regions of widely
varying clock load densities. Collectively, the three clock grids
required over 1100 clock buffers and 19.4 m of metal. Higher
clock speeds were attained by reducing wire lengths between the
grid and grid buffer, as well as by reducing distances between
grid buffers.
One of the clock distribution design goals was to signifi-
cantly reduce power dissipation over previous designs [10],
[11]. Early studies showed that much of the clock distribution
power dissipation was determined by three main categories of
capacitances—clock load, lower level twig and mesh wires,
and grid clock buffers (see Fig. 12). Clock load, consisting of
mostly macro gate capacitance and minor local clock wires,
was monitored for excessive capacitance. Clock twig wires,
connecting clock loads to the clock grid, had widths tuned
within reserved physical regions, thereby decreasing both their
area and perimeter wire capacitance components. For the chip,
wire width tuning decreased clock twig wire capacitance by as
much as 42% without sacrificing local clock skew. Less clock
load, and smaller clock twig wire capacitance, and lower level
grid wire capacitance allowed reduction in grid buffer drive
strengths. Further reduction in grid buffer drive strength was
achieved through matching one of seven buffer drive strengths
to the local grid and clock load capacitances. Together, these
techniques lowered clock distribution power dissipation by
more than 20% over previous designs [10].
High-frequency clock signal distribution optimization and
verification required wire simulation models that included
frequency sensitive inductance and resistance elements as well
as extracted capacitances. A rapid simulation engine completed
the chip grid analysis within four hours. Fig. 13 shows the
simulated chip clock skew to be less than 12 ps.
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Fig. 12. Total effective clock distribution capacitance composition.
Fig. 13. Main clock distribution normalized arrival time.
C. Local Clock Buffers, Latches, and Flip-Flops
In any microprocessor, as the frequency is increased by
decreasing the depth of logic in each pipeline stage, the number
and density of latches and flip-flops will increase correspond-
ingly. Therefore, these clocked elements will account for a
larger and larger fraction of the overall chip power as the cycle
time is pushed downwards. Also, as logic depth is reduced, the
fraction of the overall cycle time devoted to the latch or flip-flop
will increase, given a fixed overhead for these elements. In
light of the conflicting requirements driven by these trends
(lower power, but smaller latency), it was essential to develop a
strategy aimed at minimizing the power consumption of these
clocked elements for the design as a whole, while still allowing
special high-speed constructs for speed-critical paths in order
to meet the aggressive cycle time targets. A rich set of latches
and flip-flops were developed to span this range of application
requirements. A general scan design (GSD) approach was
chosen, with a single global clock and local clock splitters at
the register level. Fine grained clock gating was practiced to
minimize AC power. The most effective clock gating strategy
was to keep the data in the slave latch, gating the slave clock
off, with master clock fixed high.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006
The key clock components of a local clock splitter are shown
in Fig. 14, where the base block provides a foundation for all
locally generated clocks on the chip. To minimize the hold time
of the local clock control signals, including test hold, functional
activate and force scan, the base block behaves functionally as
if it included a latch. Starting from the cycle boundary (falling
global clock), if the “gate” signal is initially high, the “clk” node
will not be pulled high, and the clock signal will not propagate.
The delayed clock path into the OAI gate will hold “gate” high
after the initial sampling period, thereby allowing the various
control inputs to change without affecting the local clock. On
the other hand, if “gate” is initially low, “clk” is pulled high,
propagating a clock edge, and also causing “fb” to pull low.
Once “fb” is low, “gate” can then be reset back high again by the
clock delay path, without any impact on the local clock signal.
The base block accepts a local clock activate signal, which
can be overridden by the scan control signal for scan testing, and
also a global priority input “testhold_b” for controlling the clock
during test operations. Since there is only a small window near
the cycle boundary where the control inputs are sampled, all
input setup and hold times are specified against only the falling
global clock edge.
For a typical master–slave flip-flop (Fig. 15), clocks are de-
rived off the base blocks as shown in Fig. 14. Overall clock
latency and absolute clock uncertainty are minimized by this
scheme since there are only three gate delays between the global
clock input and the data launch clock (lclk). Also, the common
point for both launch clock and capture clock is at the output
of the base block, minimizing the relative uncertainty between
launch and capture clocks. As sketched out above, when clocks
are in the gated state, launch clock (lclk) is held inactive, and the
capture clock (dclk) is held high. The system state is therefore
stored in the slave latch.
For timing critical paths, a high-performance latch (HPL) was
designed which combined a wide multiplexer (up to 10-way),
relying on a dynamic NOR gate, with a set-reset latch (Fig. 16)
[12], [13]. This circuit accepts static inputs and provides static
outputs, but leverages the performance advantage of an em-
bedded dynamic NOR. The dynamic NOR starts evaluating with
PHAM et al.: ARCHITECTURE, CIRCUIT DESIGN, AND PHYSICAL IMPLEMENTATION OF A FIRST-GENERATION Cell PROCESSOR
Fig. 14. Basic local clock components.
Fig. 15. Standard master–slave flip-flop.
rising lclk, sampling the data inputs at the start of the cycle.
After a fixed amount of delay (giving the dynamic NOR enough
time to discharge), all sel_b inputs are forced high, after which
time d_b and sel inputs may change without affecting the value
stored in the set-reset latch. For scan testing, one multiplexer
input (and one select line) was devoted to scan data. The scan
select signal is given priority over the functional selects.
For power reduction, the standard flip-flop (Fig. 15) can be
run in pulsed mode, with a clock configuration shown in Fig. 17.
In this case the slave clock is pulsed in normal operation, and
master clock is held high. There is also a “chicken switch” which
allows running in normal master–slave clocked mode if race
problems are seen in the hardware. A nonscannable pulsed latch
(consisting of only the slave latch portion of the flip-flop in
Fig. 15) was also supported, minimizing area, power, and la-
tency in situations where a longer hold time could be tolerated.
D. SRAM Arrays
The two different processing elements, as described in the
chip overview, drive different memory requirements. Starting
with the PPE, the cache system includes separated L1 caches
for instruction and data, and a 512-kB unified L2.
187
Fig. 16. High-performance latch and clock details.
Fig. 17. Clocking for pulsed-mode operation of the flip-flop.
The 32-kB L1 macro was organized as a two-way associative
memory, with interleaving of the two ways to improve parity
check performance. As shown in Fig. 18, the overall latency
is three cycles, with the first cycle being occupied by the sum
address decoder (SAD). The array access is performed in the
second cycle, and finally parity checking, data formatting, and
way select in the third cycle concludes the L1 access. The macro
is organized internally with 512 word-lines, each accessing 32
bytes of 9-bit data for each way. Writing occurs one way at a
time and can be 64 bytes (two consecutive word-lines) or 32
bytes with byte write capability. Up to 16 bytes of data can be
read, with parity checking on each byte. In formatted mode,
eight consecutive bytes are provided, starting with any of the
32 bytes in the word. The SRAM core is built up from local
bit-lines with 16 cells per bit-line and a dot of 8 onto a global
bit-line in a ripple domino read approach.
The L2 Cache was constructed as an eight-way associative,
512-kB cache, composed of four individual 1024 8 140
macros. Shown in Fig. 18, the L2 cache resides in a timing
domain which is clocked at half the core rate. To conserve
power, the way select is decoded prior to the array access,
activating only 1/8 of the macro. Single-word 140-bit writes or
double-word 280-bit reads are supported. The array is pipelined
such that a write takes two cycles to complete. For reads, it
188
Fig. 18. PPE L1/L2 complex.
takes three cycles for the first 140-bit word to be read, with
the second word in the fourth cycle. Thus, write/reads can be
interleaved with data continuously being fetched. Bit-line re-
dundancy is implemented using a bit-shifting approach. There
is one repair action possible for each sub-array leading to a
total of 16 repairs per macro.
The SPE main memory is the LS. The LS unit in the SPE
is a local memory comprised of several macros performing
load/stores, transactions for DMA, and instruction fetches
into an instruction line buffer (ILB). Because the LS occupies
one-third of the SPE floorplan, area, power, and yield are as
important as performance.
As shown in Figs. 19 and 20, the LS consists of a sum
addressed decoder (memdec), four 64-kB memory arrays
(mem64k), write accumulation buffers (wacc and wtb), and
read accumulation buffers (rdb1, rdb2, and rdb41), distributed
throughout the SPE. It takes four cycles to complete a write
and six cycles to perform a read. The numbered latch points
in the pipeline diagram also appear in the physical image to
indicate the location of the latches. A memory access starts
by setting address operand registers in the memdec macro.
The memdec effectively adds the operands while pre-decoding
bit groups of the sum, with the results latched at the macro
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006
output at the end of the first cycle. In the second cycle, the
pre-decoded indices are distributed to the four copies of the
64-kB mem64k memory block. The decoding of the address is
completed within mem64k in the third cycle, which ends with
the word-line selection latched at the word-line (WL) driver.
The sub-array access (fourth cycle), starts with WL activation,
and a write operation completes during this cycle. For a read,
the sense amplifier (SA) senses the bit-line differential signal
and holds the value until it is captured by the read latch (RL)
at the beginning of the fifth cycle. The remainder of the fifth
cycle transfers the data read from the arrays either to the read
buffers or to a four-ported latch (rdb41). The fetched data are
forwarded to the execution units in the sixth cycle. Macro
placement, number of inversions, pin locations, wire length bal-
ance, bus interleaving, hostile/quiet neighbor wire assignment,
choice of metal layer, metal width and spacing were engineered
to achieve the six-cycle 11FO4 path.
Two basic read schemes were used for the arrays on this chip.
The base domino read implementation used for both the L1 and
L2 caches is shown in Fig. 21. The local bit-line has 16 cells
connected. The global bit-line can have 4, 8, or 16 local evalua-
tion circuits connected. The continuous bit-line has 64, 128, or
256 cells connected, respectively. The local/global bit-lines are
PHAM et al.: ARCHITECTURE, CIRCUIT DESIGN, AND PHYSICAL IMPLEMENTATION OF A FIRST-GENERATION Cell PROCESSOR
Fig. 19. SPE local store.
Fig. 20. Die photo of the PPE caches and SPE local store.
used to read the cell, the continuous bit-line and write data_b are
used to write. The local evaluation shown is a minimum device
solution to reduce the local overhead. The local/global bit-lines
are used to read the cell in dynamic fashion when the cell is
activated. The continuous bit-line and write data_b are used to
write the cell. The continuous bit-line provides compliment data
directly to the cell while data_b provides true data to the local
eval to drive onto the local bit-lines to the cell. When the cell is
activated the true and compliment data update the cell contents.
The local evaluation shown is a minimum device solution to re-
duce the local overhead.
189
The sense amplifier used in the LS design is also shown.
The sense amplifier is a traditional gate only input design with
added cross coupled PFETs to enhance its signal sensing ability,
while retaining the ability to pre-charge at a different time than
the storage cells. One sense amplifier can service four sets of
64-cell/bit-line groups.
Special attention was directed to cell stability. mis-
matches, due to random dopant fluctuations, increase as
transistors get smaller. In addition factors like ACLV, corner
rounding, printability issues, poly roughness and SOI history
effects add variability to the devices, representing a tremen-
190 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006

Fig. 21. SRAM arrays read schemes.

dous challenge for the cell design in 90-nm technology and

beyond. Cell stability depends on the ratio of the pull-down
device to the access devices and on the switching point of the
pull-up/pull-down device pair. During the read operation the
down level at the internal cell node (voltage divider between
pull-down and access device) must be lower than the switch
point of the cell’s inverter to allow a stable read operation
(Fig. 22). The most important parameter for writability of the
cell is the strength ratio of the access device to the pull-up
device. A dynamic statistical analysis (DSA) approach is used
to determine the probability of a cell fail due to stability or
writability.
Fig. 22. Bit cell stability.

V. PHYSICAL IMPLEMENTATION OVERVIEW

A. Chip Integration
Fig. 2 shows the die photograph with approximately 241 M
transistors from 17 major physical partitions and 8912 discrete
chip-level floorplan floorplanned blocks (e.g., PLL, IO, thermal
sensors, engineered bus transport). The chip total across all
levels of hierarchy included 177 K floor-planned blocks, 580 K
repeaters and 1.55 M unit, partition, and global signal nets. At
the center of the chip is the EIB composed of four 128-bit data
rings plus a 64-bit tag operated at half the processor clock rate.
The wires were arranged in groups of four, interleaved with
GND and VDD shields twisted at the center to reduce coupling
noise on the two unshielded wires. To ensure signal integrity,
many other nets were custom-tailored, and over 50% of the
57 K chip-level nets were engineered with 32 K repeaters.
The Cell SoC uses 3349 C4s in a 90-column by 61-row varied
pitch matrix with five regions of different row–column pitches
attached to the low-cost organic package described earlier.
This structure supports 20 separate power domains on-chip,
many of which overlap physically on the die. The entire chip
PHAM et al.: ARCHITECTURE, CIRCUIT DESIGN, AND PHYSICAL IMPLEMENTATION OF A FIRST-GENERATION Cell PROCESSOR
Fig. 23. Hierarchical noise analysis.
hierarchy, from processor elements to power and clock distri-
butions, global routing, and the chip assembly techniques, are
engineered to support a modular design in a building-block-like
construction.
B. Noise Analysis
Given the aggressive frequency targets and the circuit design
techniques described in the previous section, it was apparent that
a detailed chip noise analysis strategy would be required to en-
sure stable operation of the chip. With the chip device counts de-
scribed above, it is impractical to analyze the whole chip using
a flat transistor-level simulator. Thus, in keeping with the hier-
archical/modular design philosophy, a hierarchical noise anal-
ysis approach was applied, which relied on a macro-level static
noise analysis [14], followed by a unit/chip-level noise analysis,
as shown in Fig. 23.
Macro-level static noise analysis was carried out on all de-
signs, including static/dynamic circuits, arrays, and synthesized
random logic macros (RLMs), creating a noise abstract at the
same time. The analysis was performed by a transistor-level
simulator, running on a net list with parasitic extracted from
the layout. This noise tool carried out a static noise analysis on
each channel connected component, looking for noise failures
throughout the design. A macro-level noise abstract was gener-
ated during the analysis, which included input noise tolerance
level, input capacitance, and output resistance.
Unit/chip-level noise analysis was then performed using the
macro noise abstracts and information from timing analysis.
Macros were represented by their abstracts, which specified the
input capacitance and output resistance. Extracted parasitic pa-
rameters are obtained from the global layout. Unit or/chip-level
noise was then analyzed with an equivalent circuit composed of
resistors, capacitors, and voltage sources which were driven ac-
cording to the timing information. A noise failure is reported if
the noise level on a net exceeds the receiver pin’s input toler-
ance level, which was determined during the macro-level noise
analysis.
191
C. Power Analysis
To calculate the total power, input switching factors (SF) and
clock activity (CA) for each macro are monitored in an RTL-
level simulation of a given workload. For every macro instance,
the input SF is calculated by observing the percent of inputs that
have changed state from the previous cycle. The CA is measured
by observing the number of local clock buffers that are turned
on in a given cycle. The ability to have a cycle-by-cycle power
for each macro for a realistic workload made this methodology
very useful for package analysis. Since power is dependent on
both SF and CA, these factors need to be calculated for every
cycle of the simulation and cannot be simply averaged over the
entire simulation. In a given cycle the total power is calculated
as
1
2
where is the amount of global net capacitance switched
in the cycle.
To estimate the power consumption of the first-generation
Cell processor and for refining and verifying the power manage-
ment logic of the chip, each core or functional unit on the chip
was required to run at least three different types of workloads:
idle, typical, and high power. The idle workload was expected to
be the lowest power state, since it shuts off as many local clock
buffers as possible. The high power test case was used as a stim-
ulus for power grid integrity analysis, thermal analysis, and as
an input for the IR drop analysis.
Fig. 24 shows the power analysis flow. Fig. 25 shows the
macro and net powers of the typical power workload, and also
the power traces of the three workloads. Fig. 26 shows the
number of local clock buffers active for the three different
workloads. The runtime for 4000 clock cycles on a core with
20.9 M transistors was approximately 30 minutes.
192
Fig. 24. Power analysis flow.
Fig. 25. (a) Macro and net power for a typical work load. (b) Total power.
D. Thermal Analysis
Due to local heating caused by independent operation of
individual processing units, sophisticated local thermal sensing
strategies and thermal control mechanisms were required to
allow aggressively low-cost and quiet thermal solutions. This
SoC presented new challenges in chip thermal design. Under
high heat flux conditions, the silicon substrate behaves like a
relatively low thermal conductance body. Given the definition
of (effective Biot number) as defined by (1) it can be
determined under which conditions small hot spots would
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006
Fig. 26. Percent of local clock buffers active for idle, typical, and high-power
workload.
create local heat spikes on top of the die global temperature
distribution.
(1)
where is substrate area, is the source area, is the ef-
fective heat transfer coefficient at the opposite side of silicon
substrate, is the substrate thickness, and is the thermal con-
ductivity of silicon.
Then, peak temperature excesses can be estimated by analytic
modeling techniques based on classical steady-state thermal dif-
fusion theory [15], as well as on transient analysis [16]. These
models approximate a rectangular source, with the general for-
mula described as
1 1
(2)
where is the energy generation rate, is the radius, is the
time, is the height of the cylinder, is the thermal diffusion
of silicon, and is the temperature.
PHAM et al.: ARCHITECTURE, CIRCUIT DESIGN, AND PHYSICAL IMPLEMENTATION OF A FIRST-GENERATION Cell PROCESSOR 193

ACKNOWLEDGMENT
The authors gratefully acknowledge the collaborations
and contributions from the entire Sony-Toshiba-IBM team
who worked tirelessly side-by-side on the design of this pro-
cessor. They also gratefully acknowledge the executive and
the management teams of the three companies who provided
management oversight and created the right business conditions
for this project. Special thanks go to M. Beattie, E. Behnen,
C. Carter, S. Dhong, T. Himeno, B. Krauter, S. Lee, J. Petrovick,
G. Plumb, P. Restle, D. Shippy, J. Silberman, K. Miki, J. Qi,
E. Hailu, M. Yoshida, and D. Widiger for their contributions to
this project.

Fig. 27. Die thermal map. REFERENCES

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194
Dac C. Pham received the B.S.E.E. degree from
University of Rhode Island, Kingston, in 1986,
the M.S.E.E. degree from Rensselaer Polytechnic
Institute, Troy, NY, in 1987, and the Ph.D. degree
in materials science from the University of Vermont,
Burlington.
He joined IBM in 1987, where he worked on
IBM’s 386 SX, 386SLP, and Blue Lightning family
of processors that were used in IBM PS/2 Systems.
In 1992, he joined the Apple-IBM-Motorola Som-
erset Design Center, where he worked on IBM’s
PowerPC 603 and follow-on processors which lead to PowerPC G3. He also
worked on IBM’s PowerPC 602 and a Graphics Co-Processor that were used in
Gaming Systems, Consumer Electronics, and PDA devices. In 1997, he joined
the IBM Giga-Processor team where he worked on IBM’s Power 4 processor
which was used in IBM servers and Apple’s G5. Between 1999 and 2003, he
was with Intel’s Texas Design Center and managed the Chip Implementation
team of a next-generation Pentium processor. He re-joined IBM in 2003, where
he worked on the high-speed, multi-core, first-generation Cell processor.
Dr. Pham is currently the Sony-Toshiba-IBM Design Center Chief Engineer
and Global Convergence Functional Manager.
Tony Aipperspach received the B.S. degree in elec-
trical engineering from Montana State University,
Bozeman, in 1979.
He joined IBM’s Rochester Development Labora-
tory, Rochester, MN, in July 1979. He was involved
in the design of an on-chip DRAM in 3 m NMOS.
From 1981 to 1993, he was involved with various
ASIC library designs, as well as integrated SRAM
design. From 1994 to 1996, he was involved in
BICMOS circuit design and a variety of memory
configurations including SRAM, CAM, and register
arrays. From 1996 to 2000, he was the team lead for the array design group and
supported all memory elements of the Star series of processors for the AS400.
Between 2000 and 2005, he was Array Lead for various processor designs
in support of the gaming industry, including the Cell processor. His current
position is Array and Circuit Lead/Consultant on various projects.
David Boerstler received the B.S. degree in elec-
trical engineering from the University of Cincinnati,
Cincinnati, OH, in 1978, the M.S. degree in electrical
engineering from Syracuse University, Syracuse,
NY, in 1981, and the M.S. degree in computer
engineering from Syracuse University in 1985.
Since joining IBM Corporation in 1978, he has
worked in various research and product development
organizations with an emphasis on high-frequency
and mixed-signal circuit design. In the last ten years
at IBM, he has been involved primarily with the
design of multi-GHz PLLs, clock distribution, and serial IO in advanced bulk
and SOI CMOS technologies. He is currently an IBM Senior Technical Staff
Member in the IBM Systems and Technology Group in Austin, TX, and leads
the analog and mixed-signal design team for the STI Design Center.
Mark Bolliger received the B.S. degree in computer
science from the University of Utah, Salt Lake City,
in 1988 and the M.S. degree in computer science from
Rensselaer Polytechnic Institute, Troy, NY, in 1994.
He joined IBM in 1988 where he worked on IBM’s
386SX, 386SLP and Blue Lightning processor
family. In 1992, he joined the Apple-IBM-Motorola
Somerset Design Center, where he worked on the
IBM’s PowerPC processor family. From 1996 to
2001, he was Director of Information Systems for
a group of privately held companies. He re-joined
IBM in 2001, where he worked on Apple’s G5 processor. In 2002, he joined
the Sony/Toshiba/IBM Design Center where he worked on the first-generation
Cell processor in Chip Integration on the Global Convergence Team.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006
Rajat Chaudry received the B.S. and M.S. degrees
in electrical engineering from the University of Texas
at Austin in 1996 and 1998, respectively.
He currently works for the Tools and Method-
ology group at the STI Design Center in Austin,
TX. He works on power estimation and power grid
verification tools.
Dennis Cox received the B.S. degree in electrical
engineering from the University of Wisconsin at
Madison in 1970 and the M.S. degree in electrical
engineering from Syracuse University, Syracuse,
NY, in 1975.
He is a Distinguished Engineer in Engineering and
Technology Services (E&TS) and a member of the
IBM Academy of Technology working in the area
of technology delivery and circuit design. He joined
IBM, Kingston, NY, in 1970 as a Circuit Design
Engineer where he designed SRAMs, dynamic logic
processors, and PLA. He transferred to Circuit Technology in Rochester, MN,
in 1976 and worked in the development of ASIC design systems. Subsequently,
as a part of Server Group, he worked on a number of different Power PC
microprocessors. With the advent of E&TS, he has been working with a
number of companies in different design and consulting contracts as well as
leading various IBM Academy studies.
Paul Harvey received the B.S.E.E. degree from
Texas A&M University, College Station, in 1981.
He is currently the Sony-Toshiba-IBM Design
Center Timing Technical Lead. He joined Motorola’s
MC68000 microprocessor design team in 1981 as a
logic designer in the floating point group. He joined
IBM in 1986 and micro-coded the transcendental
functions for the FPA floating point accelerator card.
In 1987, he worked on the Power1, Power2, and
Power3 microprocessor designs as the FPU and FXU
Technical Team Lead, and on Power4 and Power5 as
the Timing Technical Lead. In 2002, he joined the Cell processor design team
in his current role.
Paul M. Harvey (M’88) received the B.S. degree in
chemical engineering from Brigham Young Univer-
sity, Provo, UT, and the M.S.E.E. degree from Syra-
cuse University, Syracuse, NY.
He is a Senior Technical Staff Member at IBM,
Austin, TX, and is the Technical Team Leader of
the STI Packaging Design Team, responsible for
the package design and analysis for the Cell mi-
croprocessor and derivative products. He has more
than 20 years experience in all aspects of electronic
packaging design, analysis and characterization. He
has six issued patents with nine pending and has authored over 40 publications
on various aspects of electronic packaging.
PHAM et al.: ARCHITECTURE, CIRCUIT DESIGN, AND PHYSICAL IMPLEMENTATION OF A FIRST-GENERATION Cell PROCESSOR
H. Peter Hofstee (M’96) received the “Doctorandus”
degree in theoretical physics from Groningen Univer-
sity, The Netherlands, in 1989, and the Ph.D. degree
in computer science from the California Institute of
Technology (Caltech), Pasadena, in 1995.
He is a Senior Technical Staff Member in the Sony-
Toshiba-IBM (STI) Design Center, IBM, Austin, TX.
He is the chief scientist for Cell and the chief architect
of the Cell Synergistic Processor Element. He joined
the Caltech faculty in 1995 and 1996 to teach com-
puter science and VLSI. In 1996, he joined the IBM
Austin Research Laboratory where he helped to create the first GHz CMOS
processor. Between 1997 and 2000, he worked on a number of other high-fre-
quency server processor designs. In 2000, he helped create the concept for Cell
and became one of the founding members of the STI Design Center in 2001. His
current interest focuses on application of the Cell processor beyond the gaming
space and on future Cell processor designs. He is a member of the ACM and a
member of the IBM Academy of Technology.
Charles Johns received the B.S. degree in electrical engineering from the Uni-
versity of Texas at Austin in 1984.
He is a Senior Technical Staff Member in the Sony-Toshiba-IBM Design
Center, Austin, TX. After joining IBM Austin in 1984, he worked on various
disk, memory, voice communication, and graphics adapters for the IBM Per-
sonal Computer. From 1988 until he transferred to the STI project in 2000, he
was part of the Graphics Organization and was responsible for the architecture
and development of entry and midrange 3-D graphics adapters and rater engines.
He is now responsible for the Cell Broadband Engine Architecture (BPA) and
participates in the development of the first-generation Cell processor.
Jim Kahle received the B.S. degree from Rice Uni-
versity, Houston, TX, in 1983.
He is an IBM Fellow with over 20 years of
research and development experience in chip design.
He is a renowned expert in the microprocessor
industry for delivering break through designs. His
current role is Chief Architect and Director of
Technology for the Austin’s Design Center for the
Cell Technology which is a partnership between
IBM, Sony, and Toshiba. He has been working for
IBM since the early 1980s on RISC-based micropro-
cessors. His work started in Physical Design tools and now has concentrated
on RISC Architecture. He was a key designer for the RIOS I processor that
launched IBM into the RS/6000 line of workstations and servers. He was also
one of the founding members of the Somerset Design center were he was the
project manager for the PowerPC 603 and follow-on processors which lead to
PowerPC G3. These chips and cores have been used in many applications from
embedded cores to Apple systems and Nintendo’s new Game Cube. He was key
to the definition of the Power Architecture and of the superscalar techniques
used in IBM. He has been on the forefront of Dual Core designs, Asymmetric
Multiprocessors, Superscalar design, and SMT micro-architectures. He was the
Chief Architect for the Power4 core and continually assists in Power processor
roadmap planning.
Atsushi Kameyama (M’91) received the B.S., M.S.,
and Ph.D. degrees in physical electronics from the
Tokyo Institute of Technology, Tokyo, Japan, in
1982, 1984, and 1999, respectively.
In 1984, he joined Toshiba VLSI Research Center,
where he was engaged in the circuit design and de-
velopment of GaAs digital ICs. From 1992 to 1994,
he was a visiting scholar at Stanford University, Stan-
ford, CA, doing research in the field of pnp-type Al-
GaAs/GaAs HBT. Since 1994, he has been involved
in the development of GaAs MMIC and low-power
circuit design using SOI. He is currently a Design Engineering Manager with
Toshiba America Electronic Components, Inc., Austin, TX
195
John Keaty (M’86) received the B.S. Degree in
mathematics from the State University of New
York, Plattsburgh, in 1974, and the M.A. degree
in mathematics in 1977 and the M.S. degree in
computer science, both from the University of
Wisconsin-Madison, in 1980.
He is a Senior Technical Staff Member and Global
Integration Leader in the STI Design Center, Austin,
TX. He joined the IBM Microelectronics Division in
Burlington, VT, in 1981 to work on automated di-
agnostic systems for semiconductor logic products.
Since then, he has worked in ASIC product development on several CMOS
logic families, and also on industry standard microprocessor development in the
IBM Microelectronics Division before transferring to the IBM Server Group in
Austin, TX, in 1996. He was responsible for timing of the Power4 processor in
the R/S 6000 Regatta system. He is currently responsible for the global integra-
tion and physical design of the Cell processor family.
Yoshio Masubuchi (M’89) received B.S. and M.S.
in Electronics Engineering from University of Tokyo
in 1981 and 1983 respectively.
He is an Assistant to the General Manager, Broad-
band System LSI Development Center, Toshiba
Corporation Semiconductor Company, Austin, TX.
Since joining Toshiba in 1983, he has been engaged
in research and development of microprocessors
and computer systems. From 1988 to 1990, he was
a visiting Fellow at the University of California,
Berkeley. He served as Toshiba Project Leader for
the Cell project at the STI Design Center, Austin, TX, from 2002 to 2005. He
is a member of the ACM, the Information Processing Society of Japan, and the
Institute of Electronics, Information and Communication Engineers.
Mydung Pham received the B.S. degree in electrical
and computer engineering from the University of Ver-
mont, Burlington, in 1992.
Since joining Apple-IBM-Motorola’s Somerset
Design Center in 1992, she has worked on various
microprocessor designs of the PowerPC 603 and
follow-on processors which lead to PowerPC G3.
In 2000, she worked on the PowerPC G5 as Chip
Timing Lead. In 2001, she joined the Cell processor
design team as Memory Management Technical
Lead. She is currently a Manager of the circuit
design, timing, and physical integration team for the PowerPC Processor
Element (PPE).
Jürgen Pille received the M.S. degree in microelec-
tronics from the University of Hanover, Germany, in
1990.
He joined IBM at the IBM Development Labora-
tory, Boeblingen, Germany, in 1990 to work on Ad-
vanced VLSI Designs. He was involved in several
areas of the S/390 and PowerPC microprocessor de-
velopment including assignments at the IBM Devel-
opment Laboratories, Poughkeepsie, NY, and Austin,
TX. He has worked in several areas including circuit
design, array design, and custom logic design. As a
Senior Technical Staff Member, he is currently responsible for array designs in
the STI Design Center, Austin, TX.
196
Stephen Posluszny received the B.S. and M.S. de-
grees in computer engineering from Rensselaer Poly-
technic Institute, Troy, NY, in 1982.
He joined IBM in 1982, working in Fishkill, NY,
with IBM’s corporate design automation organiza-
tion in the area of silicon compaction. In 1988, he
moved to Austin, TX, to work on logic synthesis
development for the RS/6000 line of processors.
Between 1995 and 2000, he worked in IBM’s
Austin Research Laboratory on the first 1-Gigahertz
Processor. In 2001, he joined the Sony-Toshiba-IBM
Design Center as IBM’s Senior Technical Staff Member and Tools and Method-
ology Technical Lead. He has contributed to the Center’s high-frequency design
methodology definition and leads the tools team supporting the design effort.
Mack Riley received the B.S.E.E. degree from the
Tuskegee Institute, Tuskegee, AL, in 1979, and the
M.S.E.E. degree in electrical engineering from Stan-
ford University, Stanford, CA, in 1981.
He joined IBM in 1981 at the Austin, TX, site. Ini-
tially, he worked on design and field support for the
IBM 5520 Administrative system and several 55xx
peripheral products. He was a member of the original
design teams for the RT PC and the RS6000 system
design teams. In 1989, he joined the Graphics Devel-
opment team for the RS/6000 systems. In this role,
he was manager of entry and mid-range 2-D and 3-D graphics adapters and 3-D
graphics controller design. In 2001, he joined the STI project as Manager and
Technical Lead for the Pervasive and Design for Test teams. In this role, he is
responsible for all the chip level control, performance monitors, debug, RAS,
test logic functions and delivery of manufacturing test patterns.
Daniel L. Stasiak received the B.S.E.E. degree from University of Missouri-
Rolla in 1987, and the M.S.E.E. degree from University of Minnesota, Min-
neapolis, in 1991.
Since joining IBM in 1987, he has worked on various microprocessor design
and development: AS400 processor design, IBM’s PowerPC, and most recently,
a first-generation Cell processor design. He is currently the Sony-Toshiba-IBM
Design Center Power Technical Lead.
Masakazu Suzuoki, photograph and biography not available at the time of
publication.
Osamu Takahashi (M’97) received the B.S. degree
in engineering physics and the M.S. degree in elec-
trical engineering from the University of California,
Berkeley, in 1993 and 1995, respectively, and the
Ph.D. degree in computer and mathematical sciences
from Tohoku University, Sendai, Japan, in 2001.
He joined IBM Austin Research Laboratory,
Austin, TX, in 1995 as a member of the high-per-
formance VLSI design research team. He has been
involved in the development of the first 1-GHz
processor as well as the development of fully syn-
chronous and pipelined 1-GHz clock 1-MB embedded DRAM macro. He is
an IBM Senior Technical Staff Member and the Manager of the circuit design,
timing, and physical integration team for the Synergistic Processor Element
(SPE) developed by Sony, Toshiba, and IBM.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006
James Warnock (M’89) received the Ph.D. degree
in physics from the Massachusetts Institute of Tech-
nology, Cambridge, in 1985.
Since then, he has been at IBM, Yorktown Heights,
NY, working on advanced bipolar and CMOS silicon
technologies, and more recently in the area of circuit
design for high-performance digital microprocessors.
This included work on the S/390 G4 processor and
also on the Power4 chip, where he was the circuit de-
sign team leader. Currently, he is the circuit lead for
the Entertainment and Embedded Processor Devel-
opment Organization in IBM’s Systems and Technology group. He is involved
with work on the Cell processor and also with several other microprocessor de-
velopment programs. He has experience in process technology and device de-
sign as well as in SOI digital circuit design, and has authored or co-authored
over 160 conference or journal papers.
Stephen Weitzel (M’75) received the the B.S.
in electrical engineering from Pennsylvania State
University, University Park.
He joined IBM as a Test Equipment Engineer in
1974 and held various positions in test engineering
and circuit design in the East Fishkill development
center, Noyce design center, and Somerset design
center. He is currently a Senior Technical Staff
Member working on high-frequency clock distribu-
tions for IBM in the STI Design Center, Austin, TX.
He has 11 patents and has co-authored seven papers.
Dieter Wendel received the B.S. degree in electrical
engineering from the University of Wuerzburg, Ger-
many, in 1981.
He is an IBM Distinguished Engineer. He joined
IBM in 1981 to work on the very large scale integra-
tion fellowship team in Boeblingen, Germany. After
a two-year assignment from 1984 to 1986 at the IBM
Research Laboratory in Yorktown Heights, NY, he
joined the S/390 microprocessor development organ-
ization at the IBM Boeblingen Laboratory to work in
several areas including test, array design, and custom
logic design. He joined the STI Design Center in Austin, TX, when it was
founded in 2001 as circuit lead. His current interests focus on concepts in high-
frequency circuit design and the exploitation of new technologies.
Kazuaki Yazawa (M’99) received the B.S. degree
in mechanical engineering from Chiba University,
Japan, in 1980, and is currently pursuing the Ph.D.
degree in mechanical engineering from Toyama
Prefectural University, Japan.
He has 25 years of mechanical and thermal engi-
neering experience for various consumer products
of Sony Corporation after he joined the company.
He has published four journal papers and 11 con-
ference papers, and holds 34 patents, some pending.
He is currently serving as Thermal Architect for
Sony Computer Entertainment Inc., Tokyo, Japan, as well as Distinguished
Engineer for the Micro Systems Network Company of Sony Corporation.