19BEI0046 YANSHU

ADC LAB EXPERIMENT :7&8

SUDHAKAR .N. SLOT:L33+L34
YANSHU YADA 19BEI004
V

6

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Experiment :07
AIM:
To design Half adder and Full adder using basic logic gates .

APPARATUS REQ:
P SPICE capture CISlite,digCLC(source),(7408/7400),(7586/7400),(7432/7400)

CIRCUIT DIAGRAMS:

HALF ADDER:





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FULL ADDER:
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PROCEDURE:

1.CREATE A NEW BLANK PROJECT.

2.ADD THE ELEMENTS FROM THE LIBRARY TO SCHEAMATIC AS PER

THE CIRCUIT DIAGRAM.CLICK ON P SPICE AND SELECT NEW
SIMUKATION PROFILE AND CREATE IT.

3. FOR HALF ADDER SET THE SIMULATION ANALYSIS TYPE AS “TIME

DOMAIN” (TRANSIENT ),RUN TO TIME :4ms .FOR FULL ADDER SET
THE SIMULATION ANALYSIS TYPE AS “TIME DOMAIN”
(TRANSIENT),RTT:8ms.CLICK OK.

4.NOW PLACE THE VOLTAGE PROBES AT INPUT AND OUTPUT ENDS

OF THE REQUIRED PLACE.

5.CLICK RUN BUTTON AND GET THE REQUIRED OUTPUT FOR

DIFFERENT PULSES.

RESULT:

THE CIRCUIT AND OUTPUT WERE NOTE D AND VERIFIED .OUPUT

MATCHES WITH TABLE.
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EXPERIMENT:08
CODE CONVERTERS - BINARY-GRAY & GRAY-BINARY

AIM:

TO design code converters (binary-gray and gray-binary)

APPARATUS REQUIRED:
P spice ,digiclock(source),-3,2XOR gates (7486/7400).

CIRCUIT DIAGRAM:

BINARY TO GRAY CONVERTER:



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OBSERVATION:3BIT BINARY TO GRAY

GRAY TO BINARY CONVERTER:

OBSERVATION 3BIT GRAY TO BINARY:

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PROCEDURE:

1.CREATE A NEW BLANK PROJECT.

2.ADD THE ELEMENTS FROM THE LIBRARY TO SCHEAMATIC AS PER

THE CIRCUIT DIAGRAM.CLICK ON P SPICE AND SELECT NEW
SIMUKATION PROFILE AND CREATE IT.

3. FOR BOTH CONVERSIONS SET THE SIMULATION ANALYSIS TYPE

AS “TIME DOMAIN” (TRANSIENT ),RTT 8ms.CLICK OK.

4.NOW PLACE THE VOLTAGE PROBES AT INPUT AND OUTPUT ENDS

OF THE REQUIRED PLACE.

5.CLICK RUN BUTTON AND GET THE REQUIRED OUTPUT FOR

DIFFERENT PULSES.