Chapter2 Computer System CPU

Addis Ababa science & Technology University
College of Electrical & Mechanical Engineering
Course Name :Computer Architecture & Organization
Instructor Name : Tayachew Fikire
Mail Address : tayachew.fikire@aastu.edu.et
Major References : William Stallings: Computer Organization and Architecture

Chapter2 :The Central processing unit (CPU)
Lesson Objective:
• The objective of this lesson is to introduce students the structure &
function of of CPU
Topics to be covered
• Top-Level View of Computer Function and Interconnection
• Computer arithmetic, Instruction sets, Instruction format and addressing
modes, CPU Structure, RISC and CISC, Pipelining, The Control Unit.
Prepared by: Tayachew Fikire Computer architecture & organization 2

Chapter2 :The Central processing unit (CPU)
Learning outcomes:
At the end of this chapter students will be able to:
• Top-level structure of computer components
• The components and functions of the CPU

Part 1
Top-level structure of computer components

Structure-Top level
Start
Model categories

Structure-CPU
Start
Model categories

Structure-Control Unit
Start
Model categories

Computer Components
 Contemporary computer designs are based on concepts developed by John

von Neumann at the Institute for Advanced Studies, Princeton
 Referred to as the von Neumann architecture and is based on three key

concepts:
 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location, without regard to the type of
data contained there
 Execution occurs in a sequential fashion (unless explicitly modified) from one
instruction to the next
 Hardwired program
 The result of the process of connecting the various components in the desired
configuration

Computer Components
Programming in
hardware
Hardware and • rewiring the
Software Approaches hardware for each
new program
Programming in
software
• Instead of rewiring
the hardware for
each new program,
the programmer
merely needs to
supply a new set of
control signals.

Computer Components
Software Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction and generates
control signals
• Provide a new sequence of codes for each new program
instead of rewiring the hardware
Major components: I/O
• CPU Components
• Instruction interpreter
• Module of general-purpose arithmetic and logic functions
• I/O Components
• Input module
• Contains basic components for accepting data and
instructions and converting them into an internal form of
signals usable by the system
• Output module
• Means of reporting results
Memory Memory buffer
address register (MBR) MEMORY
register (MAR) • Contains the data
• Specifies the to be written into
address in memory memory or
for the next read or receives the data
write read from memory
MAR
I/O address I/O buffer

register (I/OAR) register (I/OBR)
• Specifies a • Used for the
particular I/O exchange of data
device between an I/O
module and the
CPU
MBR

Computer Components Top-level view

Basic instruction cycle

Fetch Cycle
 At the beginning of each instruction cycle the processor fetches an instruction

from memory
 The program counter (PC) holds the address of the instruction to be fetched
next
 The processor increments the PC after each instruction fetch so that it will fetch
the next instruction in sequence
 The fetched instruction is loaded into the instruction register (IR)
 The processor interprets the instruction and performs the required action

Action Categories
• Data transferred from processor to • Data transferred to or
memory or from memory to processor from a peripheral
device by
transferring between
the processor and an
I/O module
Processor- Processor-
memory I/O
Data
Control
processing
• An instruction may • The processor may

specify that the perform some
sequence of arithmetic or logic
execution be altered operation on data

I/O Function
 I/O module can exchange data directly with the processor
 Processor can read data from or write data to an I/O module

 Processor identifies a specific device that is controlled by a particular I/O module
 I/O instructions rather than memory referencing instructions
 In some cases it is desirable to allow I/O exchanges to occur directly with

memory
 The processor grants to an I/O module the authority to read from or write to memory
so that the I/O memory transfer can occur without tying up the processor
 The I/O module issues read or write commands to memory relieving the processor of
responsibility for the exchange
 This operation is known as direct memory access (DMA)

The interconnection structure must support the following
types of transfers:
Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory
An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access

A communication pathway Signals transmitted by any I
connecting two or more one device are available for
devices reception by all other
• Key characteristic is that it is a devices attached to the bus n
shared transmission medium • If two devices transmit during the
same time period their signals will t
overlap and become garbled
e
r
Typically consists of multiple
Computer systems contain a c
communication lines
number of different buses
• Each line is capable of that provide pathways B o
transmitting signals representing
binary 1 and binary 0 between components at
various levels of the u n
computer system hierarchy
s n
e
System bus c
• A bus that connects major The most common computer
computer components (processor,
interconnection structures t
memory, I/O)
are based on the use of one
or more system buses i
o
n
Data Bus
 Data lines that provide a path for moving data among system modules
 May consist of 32, 64, 128, or more separate lines
 The number of lines is referred to as the width of the data bus
 The number of lines determines how many bits can be transferred at a time
 The width of the data bus

is a key factor in
determining overall
system performance

Address Bus Control Bus
 Used to designate the source or

 Used to control the access and the
destination of the data on the data use of the data and address lines
bus
 If the processor wishes to read a  Because the data and address lines
word of data from memory it puts are shared by all components there
the address of the desired word must be a means of controlling their
on the address lines use
 Width determines the maximum  Control signals transmit both

command and timing information
possible memory capacity of the among system modules
system
 Timing signals indicate the validity
 Also used to address I/O ports of data and address information
 The higher order bits are used to
select a particular module on the  Command signals specify operations
bus and the lower order bits to be performed
select a memory location or I/O
port within the module

Part 2
The central processing Unit (CPU)

Processor Structure and Function

Processor Organization
Processor Requirements:
 Fetch instruction
 The processor reads an instruction from memory (register, cache, main memory)
 Interpret instruction
 The instruction is decoded to determine what action is required
 Fetch data
 The execution of an instruction may require reading data from memory or an I/O module
 Process data
 The execution of an instruction may require performing some arithmetic or logical operation on data
 Write data
 The results of an execution may require writing data to memory or an I/O module
 In order to do these things the processor needs to store some data temporarily and therefore
needs a small internal memory

CPU with System Bus

Internal Structure of CPU

Register Organization
 Within the processor there is a set of registers that function as a

level of memory above main memory and cache in the
hierarchy
 The registers in the processor perform two roles:
User-Visible Registers Control and Status Registers
 Enable the machine or  Used by the control unit to control the

assembly language operation of the processor and by
programmer to minimize main privileged operating system programs
memory references by to control the execution of programs
optimizing use of registers

User-visible Register
Categories:
Referenced by means of •General purpose
the machine language •Can be assigned to a variety of functions by
the programmer
that the processor •Data
executes •May be used only to hold data and cannot be
employed in the calculation of an operand
address
•Address
•May be somewhat general purpose or may be
devoted to a particular addressing mode
•Examples: segment pointers, index registers,
stack pointer
•Condition codes
•Also referred to as flags
•Bits set by the processor hardware as the
result of operations

Control and Status Registers
Four registers are essential to instruction execution:
 Program counter (PC)

 Contains the address of an instruction to be fetched
 Instruction register (IR)

 Contains the instruction most recently fetched
 Memory address register (MAR)

 Contains the address of a location in memory
 Memory buffer register (MBR)

 Contains a word of data to be written to memory or the word most
recently read

Program Status Word (PSW)
Register or set of registers that

contain status information
Common fields or flags include:

• Sign
• Zero
• Carry
• Equal
• Overflow
• Interrupt Enable/Disable
• Supervisor

Microprocessor register organization

Instruction cycle
Includes the following

stages:
Fetch Execute Interrupt
If interrupts are
Read the next enabled and an
Interpret the opcode
instruction from interrupt has occurred,
and perform the
memory into the save the current
indicated operation
processor process state and
service the interrupt

Instruction cycle

Instruction cycle state diagram

Data flow –fetch cycle

Data flow –interrupt cycle

Pipelining Strategy
To apply this concept

to instruction
execution we must
Similar to the use of recognize that an
an assembly line in a instruction has a
manufacturing plant number of stages
New inputs are

accepted at one end
before previously
accepted inputs
appear as outputs at
the other end

Additional Stages
 Fetch instruction (FI)
 Read the next expected  Fetch operands (FO)
instruction into a buffer  Fetch each operand from
memory
 Decode instruction (DI)
 Operands in registers need
 Determine the opcode and the not be fetched
operand specifiers
 Execute instruction (EI)
 Calculate operands (CO)
 Perform the indicated
 Calculate the effective address operation and store the
of each source operand result, if any, in the specified
 This may involve displacement, destination operand location
register indirect, indirect, or
other forms of address  Write operand (WO)
calculation  Store the result in memory

Timing- diagram for instruction pipeline
operation

The effect of conditional branch on instruction
pipeline operation

Pipeline Hazards .
• A pipeline hazard occurs when
the pipeline, or some portion of the
pipeline, must stall because
conditions do not permit continued
execution.
There are
Occur when the
three types • Such a pipeline stall is also
pipeline, or some
portion of the pipeline, of hazards: referred to as a pipeline bubble.
must stall because • Resource There are three types of hazards:
conditions do not
permit continued • Data resource, data, and control.
execution • Control
Also referred to
as a pipeline
bubble

Resource Hazards
• A resource hazard occurs when two (or more)

instructions that are already in the pipeline need the
same resource.
• The result is that the instructions must be executed in
serial rather than parallel for a portion of the pipeline.
A resource hazard is sometime referred to as a
structural hazard.
• Let us consider a simple example of a resource hazard.
Assume a simplified five-stage pipeline, in which each
stage takes one clock cycle.
• Figure a shows the ideal case, in which a new
instruction enters the pipeline each clock cycle. Now
assume that main memory has a single port and that
all instruction fetches and data reads and writes must
be performed one at a time.

Resource Hazards • Further, ignore the cache. In this case, an operand read
to or write from memory cannot be performed in
parallel with an instruction fetch.
• This is illustrated in Figure b, which assumes that the
source operand for instruction I1 is in memory, rather
than a register.
• Therefore, the fetch instruction stage of the pipeline
must idle for one cycle before beginning the
instruction fetch for instruction I3.
• The figure assumes that all other operands are in
registers.
• Another example of a resource conflict is a situation
in which multiple instructions are ready to enter the
execute instruction phase and there is a single ALU.
• One solutions to such resource hazards is to increase
available resources, such as having multiple ports into
main memory and multiple ALU units.

Data Hazards • A data hazard occurs when there is a conflict in the
access of an operand location.
• In general terms, we can state the hazard in this form:
Two instructions in a program are to be executed in
sequence and both access a particular memory or
register operand.
• If the two instructions are executed in strict sequence,
no problem occurs.
• However, if the instructions are executed in a pipeline,
then it is possible for the operand value to be updated
in such a way as to produce a different result than
would occur with strict sequential execution. In other
words, the program produces an incorrect result
because of the use of pipelining.

Data Hazards As an example, consider the following x86 machine
instruction sequence:
ADD EAX, EBX /* EAX = EAX + EBX
SUB ECX, EAX /* ECX = ECX – EAX
The first instruction adds the contents of the 32-bit

registers EAX and EBX
and stores the result in EAX. The second instruction
subtracts the contents of EAX
from ECX and stores the result in ECX. Figure 14.16
shows the pipeline behavior.

Types of Data Hazard
 Read after write (RAW), or true dependency

 An instruction modifies a register or memory location
 Succeeding instruction reads data in memory or register location
 Hazard occurs if the read takes place before write operation is complete
 Write after read (WAR), or antidependency

 An instruction reads a register or memory location
 Succeeding instruction writes to the location
 Hazard occurs if the write operation completes before the read operation takes
place
 Write after write (WAW), or output dependency

 Two instructions both write to the same location
 Hazard occurs if the write operations take place in the reverse order of the
intended sequence

Control Hazard
 Also known as a branch hazard
 Occurs when the pipeline makes the wrong decision on a branch

prediction
 Brings instructions into the pipeline that must subsequently be discarded
 Dealing with Branches:

 Multiple streams
 Prefetch branch target
 Loop buffer
 Branch prediction
 Delayed branch

Interrupt Processing
Interrupts and Exceptions

 Interrupts
 Generated by a signal from hardware and it may occur at random times during the
execution of a program
 Maskable
 Nonmaskable
 Exceptions
 Generated from software and is provoked by the execution of an instruction
 Processor detected
 Programmed
 Interrupt vector table

 Every type of interrupt is assigned a number
 Number is used to index into the interrupt vector table

Vector Number Description
0 Divide error; division overflow or division by zero
1 Debug exception; includes various faults and traps related to debugging
2 NMI pin interrupt; signal on NMI pin
3 Breakpoint; caused by INT 3 instruction, which is a 1-byte instruction useful for debugging
4 INTO-detected overflow; occurs when the processor executes INTO with the OF flag set
5 BOUND range exceeded; the BOUND instruction compares a register with boundaries stored in
memory and generates an interrupt if the contents of the register is out of bounds.
x86 6 Undefined opcode

7 Device not available; attempt to use ESC or WAIT instruction fails due to lack of external device
Exception 8 Double fault; two interrupts occur during the same instruction and cannot be handled serially
and 9 Reserved
Interrupt 10 Invalid task state segment; segment describing a requested task is not initialized or not valid
11 Segment not present; required segment not present
Vector 12 Stack fault; limit of stack segment exceeded or stack segment not present
Table 13 General protection; protection violation that does not cause another exception (e.g., writing to a
read-only segment)
14 Page fault
15 Reserved
16 Floating-point error; generated by a floating-point arithmetic instruction
17 Alignment check; access to a word stored at an odd byte address or a doubleword stored at an
address not a multiple of 4
18 Machine check; model specific
19-31 Reserved
32-255 User interrupt vectors; provided when INTR signal is activated

The ARM Processor
ARM is primarily a RISC system with the following attributes:
 Moderate array of uniform registers
 A load/store model of data processing in which operations only perform on operands in

registers and not directly in memory
 A uniform fixed-length instruction of 32 bits for the standard set and 16 bits for the Thumb
instruction set
 Separate arithmetic logic unit (ALU) and shifter units
 A small number of addressing modes with all load/store addresses determined from
registers and instruction fields
 Auto-increment and auto-decrement addressing modes are used to improve the operation
of program loops
 Conditional execution of instructions minimizes the need for conditional branch

instructions, thereby improving pipeline efficiency, because pipeline flushing is reduced

ARM-organization

Processor -Models
Most application
programs execute in
ARM user mode
architecture • While the processor is in
supports seven user mode the program
being executed is unable
execution to access protected
modes system resources or to
change mode, other than
by causing an exception
to occur
Remaining six Advantages to defining

so many different
execution modes privileged modes
are referred to as •The OS can tailor the use of
privileged modes system software to a variety
of circumstances
• These modes are •Certain registers are
used to run system dedicated for use for each of
the privileged modes, allows
software swifter changes in context

Part 3
Control unit operation

Constituent elements of program execution

Sequence of events –Fetch cycle

Execution cycle flow chart

Data buses & Control Signals

Micro-Operations & Control Signals

CPU with Internal Bus

CPU with Internal Bus

Part 4

Instruction Sets: Characteristics and Functions

Machine Instruction Characteristics
 The operation of the processor is determined by the instructions it
executes, referred to as machine instructions or computer instructions
 The collection of different instructions that the processor can execute is

referred to as the processor’s instruction set
 Each instruction must contain the information required by the processor

for execution

Elements of a Machine Instruction
Operation code Source operand

(opcode) reference
• Specifies the operation • The operation may
to be performed. The involve one or more
operation is specified source operands, that
by a binary code, is, operands that are
known as the operation inputs for the operation
code, or opcode
Result operand Next instruction

reference reference
• The operation may • This tells the processor
produce a result where to fetch the next
instruction after the
execution of this
instruction is complete

Instruction cycle state diagram

Source & result operations can be in one
of four areas
3) Processor register
 A processor contains one or
1) Main or virtual memory more registers that may be
 As with next instruction referenced by machine
references, the main or virtual instructions.
memory address must be
supplied  If more than one register
exists each register is
assigned a unique name or
number and the instruction
2) I/O device must contain the number of
 The instruction must specify the desired register
the I/O module and device for 4) Immediate
the operation. If memory-
mapped I/O is used, this is  The value of the operand is
just another main or virtual contained in a field in the
memory address instruction being executed

Instruction Representation
 Within the computer each instruction is represented by a sequence of
bits
 The instruction is divided into fields, corresponding to the constituent

elements of the instruction

Instruction Representation
 Opcodes are represented by abbreviations
called mnemonics
 Examples include:
 ADD Add
 SUB Subtract
 MUL Multiply
 DIV Divide
 LOAD Load data from memory
 STOR Store data to memory
 Operands are also represented symbolically
 Each symbolic opcode has a fixed binary representation

 The programmer specifies the location of each symbolic operand

Instruction Types
• Arithmetic instructions provide • Movement of data into or
computational capabilities for out of register and or
processing numeric data memory locations
• Logic (Boolean) instructions operate
on the bits of a word as bits rather
than as numbers, thus they provide
capabilities for processing any
other type of data the user may wish
to employ
Data Data
processing storage
Data
Control
movement
• Test instructions are used to test the • I/O instructions are needed
value of a data word or the status of a to transfer programs and
computation data into memory and the
• Branch instructions are used to branch results of computations
to a different set of instructions back out to the user
depending on the decision made

Instruction Set Design
Very complex because it affects so many aspects of the computer system
Defines many of the functions performed by the processor
Programmer’s means of controlling the processor
Fundamental design issues:
Operation repertoire Data types Instruction format Registers Addressing

• How many and which • The various types of data • Instruction length in bits, • Number of processor • The mode or modes by
operations to provide and upon which operations are number of addresses, size registers that can be which the address of an
how complex operations performed of various fields, etc. referenced by instructions operand is specified
should be and their use

Types of Operands

Types of Operands –numbers
 All machine languages include numeric data types
 Numbers stored in a computer are limited:

 Limit to the magnitude of numbers representable on a machine
 In the case of floating-point numbers, a limit to their precision
 Three types of numerical data are common in computers:

 Binary integer or binary fixed point
 Binary floating point
 Decimal
 Packed decimal
 Each decimal digit is represented by a 4-bit code with two digits
stored per byte
 To form numbers 4-bit codes are strung together, usually in multiples
of 8 bits

Types of Operands –Characters
 A common form of data is text or character strings
 Textual data in character form cannot be easily stored or transmitted by data

processing and communications systems because they are designed for binary
data
 Most commonly used character code is the International Reference Alphabet

(IRA)
 Referred to in the United States as the American Standard Code for Information
Interchange (ASCII)
 Another code used to encode characters is the Extended Binary Coded Decimal
Interchange Code (EBCDIC)
 EBCDIC is used on IBM mainframes

Types of Operands –Logical data
 An n-bit unit consisting of n 1-bit items of data, each item having the value 0 or 1
 Two advantages to bit-oriented view:

 Memory can be used most efficiently for storing an array of Boolean or binary data items
in which each item can take on only the values 1 (true) and 0 (false)
 To manipulate the bits of a data item
 If floating-point operations are implemented in software, we need to be able to shift
significant bits in some operations
 To convert from IRA to packed decimal, we need to extract the rightmost 4 bits of each
byte

Data Transfer
Must specify:
• Location of the source and
destination operands
Most fundamental type of • The length of data to be
machine instruction transferred must be indicated
• The mode of addressing for each
operand must be specified

 Most machines provide the basic arithmetic operations of
add, subtract, multiply, and divide
 These are provided for signed integer (fixed-point) numbers
 Often they are also provided for floating-point and packed
decimal numbers
 Other possible operations include a variety of single-
operand instructions:
 Absolute
 Take the absolute value of the operand
 Negate Arithmetic
 Negate the operand
 Increment
 Add 1 to the operand
Decrement
 Subtract 1 from the operand

Shift & Rotate Operations

Examples of Shift and Rotate Operations
Input Operation Result

10100110 Logical right shift (3 bits) 00010100
10100110 Logical left shift (3 bits) 00110000
10100110 Arithmetic right shift (3 bits) 11110100
10100110 Arithmetic left shift (3 bits) 10110000
10100110 Right rotate (3 bits) 11010100
10100110 Left rotate (3 bits) 00110101

Instructions that
change the Conversion
format or
operate on the
format of data
An example of a
more complex
editing
instruction is the
An example EAS/390
is converting Translate (TR)
from instruction
decimal to
binary

Input/Output
 Variety of approaches taken:
 Isolated programmed I/O
 Memory-mapped programmed I/O
 DMA
 Use of an I/O processor
 Many implementations provide only a few I/O instructions, with the

specific actions specified by parameters, codes, or command words

System Control
Instructions that can be executed only while the processor is in a

certain privileged state or is executing a program in a special
privileged area of memory
Typically these instructions are reserved for the use of the

operating system
Examples of system control operations:
A system control instruction An instruction to read or Access to process control

may read or alter a control modify a storage protection blocks in a
register key multiprogramming system

Transfer Control
 Reasons why transfer-of-control operations are required:

 It is essential to be able to execute each instruction more than once
 Virtually all programs involve some decision making
 It helps if there are mechanisms for breaking the task up into smaller pieces that
can be worked on one at a time
 Most common transfer-of-control operations found in instruction sets:

 Branch
 Skip
 Procedure call

Transfer Control- branch instructions

Skip Instructions
Typically implies that one

instruction be skipped,
Includes an implied thus the implied address
address equals the address of the
next instruction plus one
instruction length
Because the skip

instruction does not Example is the
require a destination increment-and-skip-if-
address field it is free to zero (ISZ) instruction
do other things

Procedure Call Instructions
 Self-contained computer program that is incorporated into a larger program

 At any point in the program the procedure may be invoked, or called
 Processor is instructed to go and execute the entire procedure and then return to the
point from which the call took place
 Two principal reasons for use of procedures:

 Economy
 A procedure allows the same piece of code to be used many times
 Modularity
 Involves two basic instructions:

 A call instruction that branches from the present location to the procedure
 Return instruction that returns from the procedure to the place from which it was called

Procedure Call Instructions
 Self-contained computer program that is incorporated into a larger program

 At any point in the program the procedure may be invoked, or called
 Processor is instructed to go and execute the entire procedure and then return to the
point from which the call took place
 Two principal reasons for use of procedures:

 Economy
 A procedure allows the same piece of code to be used many times
 Modularity
 Involves two basic instructions:

 A call instruction that branches from the present location to the procedure
 Return instruction that returns from the procedure to the place from which it was called

Part 5
Instruction Sets: Addressing Modes

Major issues
1. How is the address of an operand specified?
2. How are the bits of an instruction organized to define the
operand addresses and operation of that instruction?

Addressing Modes
Immediate
Direct
Indirect
Register
Register indirect
Displacement
Stack

Addressing Modes

Basic Addressing Modes
Mode Algorithm Principal Advantage Principal Disadvantage

Immediate Operand = A No memory reference Limited operand magnitude
Direct EA = A Simple Limited address space
Indirect EA = (A) Large address space Multiple memory references
Register EA = R No memory reference Limited address space
Register indirect EA = (R) Large address space Extra memory reference
Displacement EA = A + (R) Flexibility Complexity
Stack EA = top of stack No memory reference Limited applicability

Immediate Addressing
 Simplest form of addressing
 Operand = A
 This mode can be used to define and use constants or set initial values of
variables
 Typically the number will be stored in twos complement form
 The leftmost bit of the operand field is used as a sign bit
 Advantage:
 No memory reference other than the instruction fetch is required to obtain the
operand, thus saving one memory or cache cycle in the instruction cycle
 Disadvantage:
 The size of the number is restricted to the size of the address field, which, in most
instruction sets, is small compared with the word length

Direct Addressing
Address field
contains the
effective address of
the operand
Effective address
(EA) = address field
(A)
Was common in
earlier generations
of computers
Requires only one

memory reference
and no special
calculation
Limitation is that it
provides only a
limited address
space

Indirect Addressing
 Reference to the address of a word in memory which contains a full-length

address of the operand
 EA = (A)
 Parentheses are to be interpreted as meaning contents of
 Advantage:
 For a word length of N an address space of 2N is now available
 Disadvantage:
 Instruction execution requires two memory references to fetch the operand
 One to get its address and a second to get its value
 A rarely used variant of indirect addressing is multilevel or cascaded indirect

addressing
 EA = ( . . . (A) . . . )
 Disadvantage is that three or more memory references could be required to fetch an operand

Register Addressing
Address field
refers to a
register rather EA = R
than a main
memory address
Advantages: Disadvantage:
• Only a small • The address space
address field is is very limited
needed in the
instruction
• No time-consuming
memory references
are required

Register Indirect Addressing
 Analogous to indirect addressing

 The only difference is whether the address field refers to a memory location or a
register
 EA = (R)
 Address space limitation of the address field is overcome by having that field
refer to a word-length location containing an address
 Uses one less memory reference than indirect addressing

Displacement Addressing
 Combines the capabilities of direct addressing and register indirect addressing
 EA = A + (R)
 Requires that the instruction have two address fields, at least one of which is
explicit
 The value contained in one address field (value = A) is used directly
 The other address field refers to a register whose contents are added to A to produce
the effective address
 Most common uses:

 Relative addressing
 Base-register addressing
 Indexing

Relative Addressing
The implicitly referenced register is the program counter (PC)

• The next instruction address is added to the address field to produce the EA
• Typically the address field is treated as a twos complement number for this
operation
• Thus the effective address is a displacement relative to the address of the
instruction
Exploits the concept of locality
Saves address bits in the instruction if most memory references

are relatively near to the instruction being executed

Base-Register Addressing
 The referenced register contains a main memory address and the address field
contains a displacement from that address
 The register reference may be explicit or implicit
 Exploits the locality of memory references
 Convenient means of implementing segmentation
 In some implementations a single segment base register is employed and is used

implicitly
 In others the programmer may choose a register to hold the base address of a
segment and the instruction must reference it explicitly

Indexing
 The address field references a main memory address and the referenced register
contains a positive displacement from that address
 The method of calculating the EA is the same as for base-register addressing
 An important use is to provide an efficient mechanism for performing iterative

operations
 Autoindexing
 Automatically increment or decrement the index register after each reference to it
 EA = A + (R)
 (R)  (R) + 1
 Postindexing
 Indexing is performed after the indirection
 EA = (A) + (R)
 Preindexing
 Indexing is performed before the indirection
 EA = (A + (R))

Stack Addressing
 A stack is a linear array of locations

 Sometimes referred to as a pushdown list or last-in-first-out queue
 A stack is a reserved block of locations

 Items are appended to the top of the stack so that the block is partially
filled
 Associated with the stack is a pointer whose value is the address of the top of
the stack
 The stack pointer is maintained in a register
 Thus references to stack locations in memory are in fact register indirect
addresses
 Is a form of implied addressing
 The machine instructions need not include a memory reference but
implicitly operate on the top of the stack

x86 Addressing mode calculation

x86 Addressing mode
Mode Algorithm
Immediate Operand = A
Register Operand LA = R
Displacement LA = (SR) + A
Base LA = (SR) + (B)
Base with Displacement LA = (SR) + (B) + A
Scaled Index with Displacement LA = (SR) + (I) ´ S + A
Base with Index and Displacement LA = (SR) + (B) + (I) + A
Base with Scaled Index and Displacement LA = (SR) + (I) ´ S + (B) + A
Relative LA = (PC) + A
LA = linear address
(X) = contents of X
SR = segment register
PC = program counter
A = contents of an address field in the instruction
R = register
B = base register
I = index register
S = scaling factor

Instruction Formats
Must include
Define the
an opcode For most
layout of the
and, implicitly instruction
bits of an
or explicitly, sets more than
instruction, in
indicate the one
terms of its
addressing instruction
constituent
mode for each format is used
fields
operand

Instruction Length
 Most basic design issue
 Affects, and is affected by:

 Memory size
 Memory organization
 Bus structure
 Processor complexity
 Processor speed
 Should be equal to the memory-transfer length or one should be a multiple of

the other
 Should be a multiple of the character length, which is usually 8 bits, and of the
length of fixed-point numbers

Allocation of Bits
Number of addressing modes: Sometimes an addressing mode
Number of
Number of can be indicated implicitly. For example, certain opcodes might
addressing
operands always call for indexing. In other cases, the addressing modes
modes must be explicit, and one or more mode bits will be needed.
Register Number of operands: We have seen that fewer addresses can

Number of
versus make for longer, more awkward programs Typical instruction
register sets
memory formats on today’s machines include two operands. Each
operand address in the instruction might require its own mode
indicator, or the use of a mode indicator could be limited to just
Address Address one of the address fields.
range granularity

Allocation of Bits
Number of Register versus memory: A machine must have registers so that
Number of
addressing data can be brought into the processor for processing. With a
operands
modes single user-visible register (usually called the accumulator), one
operand address is implicit and consumes no instruction bits.
Register However, single-register programming is awkward and requires
Number of
versus many instructions. Even with multiple registers, only a few bits
register sets
memory are needed to specify the register. The more that registers can be
used for operand references, the fewer bits are needed. A number
of studies indicate that a total of 8 to 32 user-visible registers is
Address Address Most contemporary architectures have at least 32 registers.
range granularity

Allocation of Bits
Address range: For addresses that reference memory, the range
Number of
Number of of addresses that can be referenced is related to the number of
addressing
operands address bits. Because this imposes a severe limitation, direct
modes addressing is rarely used. With displacement addressing, the
range is opened up to the length of the address register. Even so,
Register it is still convenient to allow rather large displacements from the
Number of
versus register address, which requires a relatively large number of
register sets
memory address bits in the instruction.
Address granularity: For addresses that reference memory
rather than registers, another factor is the granularity of
Address Address addressing. In a system with 16- or 32-bit words, an address can
range granularity reference a word or a byte at the designer’s choice. Byte
addressing is convenient for character manipulation but
requires, for a fixed-size memory, more address bits.

Instruction formats –Examples

Instruction formats –Examples
X89 instruction formats

Part 6
Reduced instruction set Computer(RISC)

Characteristics of Some CISCs, RISCs, and
Superscalar Processors
Complex Instruction Set Reduced Instruction

(CISC)Computer Set (RISC) Computer
Characteristic IBM VAX Intel SPARC MIPS
370/168 11/780 80486 R4000
Year developed 1973 1978 1989 1987 1991
Number of 208 303 235 69 94
instructions
Instruction size (bytes) 2–6 2–57 1–11 4 4
Addressing modes 4 22 11 1 1
Number of general- 16 16 8 40 - 520 32
purpose registers
Control memory size 420 480 246 — —
(kbits)
Cache size (kB) 64 64 8 32 128

Characteristics of Some CISCs, RISCs, and
Superscalar Processors
Superscalar
Characteristic PowerPC Ultra MIPS
SPARC R10000
Year developed 1993 1996 1996
Number of 225
instructions
Instruction size (bytes) 4 4 4
Addressing modes 2 1 1
Number of general- 32 40 - 520 32
purpose registers
Control memory size — — —
(kbits)
Cache size (kB) 16-32 32 64

Instruction High-level languages (HLLs)
• Allow the programmer to express algorithms more
Execution concisely
• Allow the compiler to take care of details that are
not important in the programmer’s expression of
Characteristics algorithms
• Often support naturally the use of structured
programming and/or object-oriented design
Execution sequencing
Semantic gap
• Determines the control and
pipeline organization • The difference between the
operations provided in HLLs
and those provided in computer
architecture
Operands used
• The types of operands and the Operations performed
frequency of their use
• Determine the functions to be
determine the memory
performed by the processor
organization for storing them
and its interaction with memory
and the addressing modes for
accessing them
Implications
 HLLs can best be supported by optimizing performance of the most time-

consuming features of typical HLL programs
 Three elements characterize RISC architectures:

 Use a large number of registers or use a compiler to optimize register usage
 Careful attention needs to be paid to the design of instruction pipelines
 Instructions should have predictable costs and be consistent with a high-performance

implementation

The Use of a Large Register File
Software Solution
Hardware Solution
 Requires compiler to allocate  More registers

registers
 Thus more variables will be in
 Allocates based on most used registers
variables in a given time
 Requires sophisticated
program analysis

Global Variables
 Variables declared as global in an HLL can be assigned memory locations by the
compiler and all machine instructions that reference these variables will use
memory reference operands
 However, for frequently accessed global variables this scheme is inefficient
 Alternative is to incorporate a set of global registers in the processor

 These registers would be fixed in number and available to all procedures
 A unified numbering scheme can be used to simplify the instruction format
 There is an increased hardware burden to accommodate the split in register

addressing
 In addition, the linker must decide which global variables should be assigned to
registers

Why CISC ?
(Complex Instruction Set Computer)
 There is a trend to richer instruction sets which include a larger and more
complex number of instructions
 Two principal reasons for this trend:

 A desire to simplify compilers
 A desire to improve performance
 There are two advantages to smaller programs:

 The program takes up less memory
 Should improve performance
 Fewer instructions means fewer instruction bytes to be fetched
 In a paging environment smaller programs occupy fewer pages, reducing page
faults
 More instructions fit in cache(s)

Characteristics of Reduced Instruction
Set Architectures(RISC)
One machine
• Machine cycle --- the time it takes to fetch two operands from registers,
instruction per perform an ALU operation, and store the result in a register
machine cycle
Register-to-register • Only simple LOAD and STORE operations accessing memory

operations • This simplifies the instruction set and therefore the control unit
Simple addressing • Simplifies the instruction set and the control unit
modes
• Generally only one or a few formats are used

Simple instruction • Instruction length is fixed and aligned on word boundaries
formats • Opcode decoding and register operand accessing can occur
simultaneously

RISC versus CISC Controversy
 Quantitative
 Compare program sizes and execution speeds of programs on RISC and CISC machines
that use comparable technology
 Qualitative
 Examine issues of high level language support and use of VLSI real estate
 Problems with comparisons:

 No pair of RISC and CISC machines that are comparable in life-cycle cost, level of
technology, gate complexity, sophistication of compiler, operating system support, etc.
 No definitive set of test programs exists
 Difficult to separate hardware effects from complier effects
 Most comparisons done on “toy” rather than commercial products
 Most commercial devices advertised as RISC possess a mixture of RISC and CISC
characteristics

Chapter2 Computer System CPU

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Chapter2 Computer System CPU

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Addis Ababa science & Technology University

College of Electrical & Mechanical Engineering

Course Name :Computer Architecture & Organization

Instructor Name : Tayachew Fikire

Mail Address : tayachew.fikire@aastu.edu.et

Major References : William Stallings: Computer Organization and Architecture

• The objective of this lesson is to introduce students the structure &

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At the end of this chapter students will be able to:

• Top-level structure of computer components

• The components and functions of the CPU

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Top-level structure of computer components

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 Contemporary computer designs are based on concepts developed by John

 Referred to as the von Neumann architecture and is based on three key

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I/O address I/O buffer

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 At the beginning of each instruction cycle the processor fetches an instruction

 The fetched instruction is loaded into the instruction register (IR)

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• An instruction may • The processor may

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 Processor can read data from or write data to an I/O module

 In some cases it is desirable to allow I/O exchanges to occur directly with

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Memory Processor I/O to or

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 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The width of the data bus

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 Used to designate the source or

 Width determines the maximum  Control signals transmit both

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The central processing Unit (CPU)

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 Within the processor there is a set of registers that function as a

 The registers in the processor perform two roles:

User-Visible Registers Control and Status Registers

 Enable the machine or  Used by the control unit to control the

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 Program counter (PC)

 Instruction register (IR)

 Memory address register (MAR)

 Memory buffer register (MBR)

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Register or set of registers that

Common fields or flags include:

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Includes the following