Instruction set of 8085 microprocessor

6 Instruction Set of 8085
and Programming
Statistical Analysis of Chapter 6

Year 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20
IES(obj) 6 2 3 3 3 2 4 1 5 1 9 5 1 1 4 2 1
IES(Con) 14 6 38 25 38 10 10 20 10 20
E&T 1 2 2 2 6 4 2 4 2 2 2 1 1 2 2
GATE 2 - - - - - - - - - - - - - - 1
3 - - - - - - - - - - - - - - 1 1
IES(obj) 1 2 3 8 4 5 4 6 7 10 7 4 4 8 7 4 3 2
IES(Con) 44 15 24 12 15 18 20 14 19 32 32 20
EE 1 2 2 2 1 4 4 3 2 2 2 1 2
GATE
2 - - - - - - - - - - - - - - 2
IAS (mains) 20 20 20 20 58 24 40 45 30 35 20 5 20 10
IN GATE 4 1 2 2 2 5 3 2 2 3
* Number in box is no. of Questions for IES (obj) and marks for all other exams
Conclusion
This is core chapter of 8085. It is most important for all the examinations
6.1 Classification of Instructions

1. Single Byte Instructions
These instructions require one byte of the memory while storing the program in the memory. Such
instruction needs only one byte of memory for storing of Opcode only. Examples : CMA, RLC, RAL,
MOV R, M etc
2. Two Byte Instructions
These instructions require two memory locations while storing a program in the memory. These
instructions have 8 bit data as operand in instruction along with mnemonics. One byte of memory is
required to store Opcode and one byte for 8 bit data.
Examples : MVI R, 8 bit data; ADI 8 bit data etc.
3. Three Byte Instructions
These instructions require three bytes of memory while storing a program in the memory. These
instructions have 16 bit data as operand in instruction along with mnemonics. One byte of memory is
required to store Opcode and two bytes for 16 bit data.
Examples : LDA 16 bit address; LXI Rp, 16 bit data.
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Instruction Set of 8085 and Programming [2]
6.2 Addressing Modes of 8085
Every instruction of a microprocessor system has some data on which it performs its operation. There are
many techniques of specifying this data. These techniques of specifying the data of instruction are called
addressing modes. 8085 microprocessor has five different types of modes which are briefly described as
under,
1. Register Addressing Mode
When the data transfer is between two registers the addressing mode is called register addressing mode.
e.g. MOV A,B, PCHL, SPHL , ADD B , SUB B etc.
2. Direct Addressing Mode
When the data transfer is with the memory or I/O device and address of memory or I/O device is
included in the instruction itself, the addressing mode is called direct addressing mode. e.g. LDA 16
bit address, STA 16 bit address , IN 8bit address, OUT 8bit address etc.
3. Indirect Addressing Mode
When the data transfer is with the memory or I/O device and address of memory or I/O device is not
included in the instruction rather it is indicated through a memory pointer, the addressing mode is
called indirect addressing mode.
e.g. MOV M, R ; LDAX D etc.
4. Implicit or Implied Addressing Mode
When the instruction modifies the contents of accumulator without using any operand the mode of
addressing is called implicit or implied. In implied addressing mode, the location of the operand is
contained within the opcode e.g. CMA, RLC, etc.
5. Immediate Addressing Mode
When 8 bit or 16 bit data is given in the instruction as operand the addressing mode is called immediate
addressing mode. e.g. ADI 8 bit data; SUI 8bit data; MVI R, 8 bitdata; LXI Rp, 16 bit data.
Note: i. When ever there is letter ‘I’ at the end in a Mnemonics that indicates immediate addressing mode.
ii. When one of the operand is letter ‘M’ that indicates the indirect addressing mode.
6.3 Writing, Storing and Execution of Assembly Language Program
6.3.1 Opcode, Operand and Mnemonic
An instruction is divided into two parts: Opcode and Operand. Opcodes are the abbreviated symbols
specified by the manufacturer to indicate the type of operation or function that will be performed by the
machine code.
The operand part of an instruction specifies the item to be processed; it can be 8-or 16-bit data, a register,
or a memory address.
An instruction, called a mnemonic or mnemonic instruction, is formed by combining an opcode and an
operand.
6.3.2 Assembly Language Program
Tasks 8085 Mnemonics
1. Load register C with 8A H MVI C, 8AH
2. ADD content of C to A. ADD C
3. Send the number to the output-port 03 H. OUT 03H
4. End of the program. HLT
6.3.3 Translation from Assembly Language to Machine Language
Now, to translate the assembly language program into machine language, look up the hexadecimal machine codes for
each instruction in the 8085 instruction set and write each machine codes in the sequence, as follows:
8085 Mnemonics Hex Machine Code
1. MVI C, 8AH 0E
8A
2. ADD C 81
3. OUT 03 D3
03
4. HLT 76
This program has six machine codes and will require six bytes of memory to enter the program into your
system. If microcomputer has R/W memory starting at the address 5000H, this program can be entered in
the memory locations 5000H to 5005H.
If the system has R/W memory with the starting address at 5000H and the output port address 03H, the
program will be stored as follows:
Memory Hex
Address Memory Contents Code
5000 00001110 0E
5001 10001010 8A
5002 10000001 81
5003 11010011 D3
5004 00000011 03
5005 01110110 76
The format generally used to write an assembly language program is described in the next section.
6.3.4 Program Format
Memory Machine Opcode Instruction Comments
Address Code Operand
(Hex) (Hex)
5000 0E MVI C,8AH ; Loads register C with data 8AH
5001 8A
5002 81 ADD C ; Adds (C) to (A)
5003 D3 OUT 03 ; Displays accumulator contents
5004 03 ; at port 03 H
5005 76 HLT ; Ends of the program
This program has five columns: Memory Address, Machine Code, Opcode, Operand, and comments.
Comments are separated by semicolon(;) from the mnemonics.
Machine Codes are the hexadecimal numbers (instruction codes) that are entered (or stored) in the respective
memory addresses through the hexadecimal keyboard of the microcomputer. The monitor program, which
is stored in Read-Only memory (ROM) of the microcomputer, translates the Hex numbers into binary digits
and stores the binary digits in the R/W memory. The Key Monitor program is a set of instructions that
continuously checks whether a key is pressed and stores the binary equivalent of a pressed key in a memory
location. When the power is turned on, the monitor program stored either in EPROM or ROM comes alive.
The RESET key clears the program counter, and the program counter holds the memory address 0000H.
As soon as the RESET key is pushed, the program counter places the memory address 0000H on the address
bus, the instruction at that location is fetched, and the execution of the Key Monitor program begins.
Therefore, the Key Monitor program is stored on page 00H.
6.3.5 Entering and Execution of a Program
To enter the program:
1. Push the RESET key.
2. Enter the 16-bit memory address of the first machine code of your program.
3. Enter and store all the machine codes sequentially, using the hexadecimal keyboard on your system.
4. Reset the system.
5. Enter the memory address where the program begin and push the Execute key.
6.4 Instruction Set

Instructions of the 8085 are classified in five categories on the basis of function performed.
1. Data Transfer Instructions
This group of instructions copy data from a location called a source to another location called a destination,
without modifying the contents of the source. In technical manuals, the term data transfer is used for this
copying function. However, the term transfer is misleading; it creates the impression that the contents of the
source are destroyed when, in fact, the contents are retained without any modification.
2. Arithmetic Instructions
These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement.
In addition /subtraction operation any 8-bit number, or the contents of a register or the contents of a memory
location can be added/subtracted to/from the contents of the accumulator and the result is stored in the
accumulator. The 8-bit contents of a register or a memory location can be incremented or decrement by 1.
Similarly, the 16-bit contents of a register pair (such as BC) can be incremented or decrement by 1. These
increment and decrement operations differ from addition and subtraction in an important way; i.e., they can
be performed in any one of the registers or in a memory location.
3. Logical Instructions
These instructions perform various logical operations such as AND,OR, ExOR, NOT, Rotate, Compare and
compliment operations with the contents of the accumulator. The logical operation of AND, OR, ExOR of
any 8-bit number, or the contents of a register or the contents of a memory location is performed with the
contents of the accumulator and the result is stored in the accumulator.
4. Machine Control Operations
These instructions control machine functions such as Halt, Interrupt, or do nothing.
5. Branching Operations
This group of instructions alters the sequence of program execution either conditionally or unconditionally.
Branch instructions of 8085 microprocessor are Jump, Call, Return and Restart. Conditional jumps
instructions use the status of flags for altering the sequence of execution of the program. Call instructions
are used to call subroutine conditionally or unconditional and return instructions are used to return to
main program from subroutine conditionally or unconditionally. Restart instructions are software interrupts
which are nothing but calling of subroutine stored at specific memory addresses.
6.4.1 Data Transfer Instructions
1. MOV Rd, Rs i. Copy the data of source register Rs to the
Rs → A, B, C, D, E, H&L destination register Rd
Rd → A, B, C, D, E, H & L ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4T
v. No flag is affected
Note: No flag is affected by data transfer instructions
Note: OP : Op Code Fetch, MW : Memory write , MR : Memory read, IOR : I/O read, IOW: I/O write.
2. MOV M, R i. Copy the data of register R to the memory
R → A, B, C, D, E, H & L location whose address is stored in HL pair
M → Memory address ii. 1-byte instruction
stored in HL pair iii. Register indirect addressing mode
iv. Two machine cycles (OP+MW) & 7T-states.
3. MOV R, M i. Copy the data of memory location whose
R→ A, B, C, D, E, H & L address is stored in HL pair to the register R
stored in HL pair iii. Register indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
4. MVI R, 8 bit data i. Copy the 8 bit data immediately to the register R
R → A, B, C, D, E, H & L ii. 2-byte instruction
iii. Immediate addressing mode
5. MVI M, 8 bit data i. Copy the 8 bit data immediately to the memory
M → Memory address location whose address is stored in HL pair
stored in HL pair ii. 2-byte instruction.
iii. Immediate-indirect addressing mode.
iv. Three machine cycles (OP+MR+MW)&10 T-states.
v. No flag is affected.
6. LXI RP, 16 bit data i. Load the 16 bit data immediately in register
Rp→BC, DE, HL & SP pair,Rp
ii. 3-byte instruction
iv. Three machine cycles (OP+MR+MR)& 10 T-states
v. No flag is affected .
Note : While storing instruction in memory, the lower byte of 16 bit is stored at lower address and higher order
byte is stored at higher address and at the time of execution the lower order byte stored at lower address is
first read into lower order register of register pair Rp and higher order byte stored at higher address is read
into higher order register.
Ex 6.1 : Consider the instruction : 2000 LXI B, 3000 H
The given instruction is stored in memory as under,
2000 XX ; Let XX→Opcode
2001 00
2002 30
At the time of execution the lower order byte(i.e. 00H) stored at 2001 is moved to lower order register C
and higher order byte (i.e. 30H) is moved to higher order register, B.
7. LDA 16 bit address i. Load accumulator directly with the contents of

given 16 bit address.
iii. Direct addressing mode
iv. Four machine cycles (OP+MR+MR+MR) &
13 T-states
8. STA 16 bit address i. Store the contents of ‘A’ at given 16 bit address
iv. Four machine cycles (OP+MR+MR+MW) &
13 T-states
9. LDAX RP i. Load accumulator with contents of memory

RP→BC & DE location whose address is stored in register RP
iii. Indirect addressing mode
iv. Two machine cycles (OP+MR) & 7 T-states.
10. STAX RP i. Store the contents of accumulator at memory

RP→BC & DE location whose address is stored in register pair RP
ii. 1 byte instruction
iv. Two machine cycles (OP+MW) & 7 T-states.
11. LHLD 16 bit address i. Load HL pair with the contents of given address
and next address. The contents of given address
are moved to L and contents of next address
are moved to H.
iv. Five machine cycles (OP+MR+MR+MR+MR)
& 16 T-states
Ex.6.2 LHLD 3000 H , loads register L with contents of 3000 H and register H with contents of 3001 H.
12. SHLD 16 bit address i. Store HL pair at given 16 bit address and next
address. The contents of L are moved to given
and contents of H are moved to next address.
iv. Five machine cycles (OP+MR+MR+MW+MW)
& 16 T-states
Ex.6.3 SHLD 3000 H , stores the contents of L at 3000H and contents of register H at 3001H.
Ex 6.4 Consider the execution of the following instructions by a 8085 microprocessor :

LXI H, 01FFH
SHLD 2050H
What are the contents of memory locations 2050H and 2051H and the registers H and L after execution of
above instructions.
IES(EE,02)
Solution:
LXI H, 01FFH [ Load H = 01H, L = FFH]
SHLD, 2050H
After the execution of SHLD instruction, the contents of L are stored in 2050 and the contents of H are
stored in next memory location i.e. 2051. The content of H and L are not altered
2050H = FF
2051H = 01
H = 01
L = FF
Note: The contents of lower order register are always stored at lower address and higher order register at higher
address.
13. SPHL i. The contents of HL pair are copied in stack

pointer
iv. One machine cycle (OP) & 6 T-states
14. PCHL i. The contents of HL Pair are copied in program

counter.
15. XCHG i. Exchange the contents HL pair with DE pair.
16. IN 8 bit port address i. Copy the contents of I/O mapped I/O device
connected at given 8 bit port address directly to
accumulator .
iv. Three machine cycles (OP+MR+IOR) & 10 T-states
17. OUT 8 bit port address i. Copy the contents of accumulator directly to I/
O mapped I/O device connected at given 8 bit
port address
iv. Three machine cycles (OP+MR+IOW) & 10 T-states
6.4.2 Arithmetic Instructions
1. ADD R i. Add the contents of R to A and store the result
R→A, B, C, D, E, H & L in A
v. All flags are affected
2. ADD M i. Add the contents of memory location, whose

M → Memory address address is stored in HL pair to A & store result
stored in HL pair in A
iii. Register indirect addressing mode
3. ADI 8bit data i. Add the 8 bit data immediately to A and store
the result in A
4. ADC R i. Add the contents of R along with carry flag to

R→A, B, C, D, E, H & L contents of A and store the result in A
5. ADC M i. Add the contents of M along with carry flag to
M → Memory address contents of A and store the result in A
stored in HL pair ii. 1-byte instruction
6. ACI 8 bit data i. Add the 8 bit data along with carry flag to
contents of A & store result in A
7. DAD RP i. Add the contents of register pair Rp to contents

RP→ BC, DE, SP & HL of HL pair and store the result in HL pair.
iv. Three machine cycles & 10 T-states
v. Only CY flag is set if result is more than 16 bits.
No other flag is affected.
Ex.6.5 An 8085 executes the following instructions.
2710 LXI H, 30A0H
2713 DAD H
2714 PCHL
All addresses and constants are in Hex. What are contents of PC and HL just after executing PCHL?
GATE(EC,08)
Solution:
2710 LXI H, 30A0H ;
Loads HL pair with 30A0 H. So, H = 30 H and L = A0 H
2713 DAD H ;
Adds the contents of HL pair(i.e. 30A0H) to HL pair
(i.e. 30A0H) and store result in HL pair.
HL : 0011 0000 1010 0000
+HL : 0011 0000 1010 0000
HL : 0110 0001 0100 0000
6 1 4 0
After addition, HL = 6140 H
2714 PCHL ; Moves the contents of HL (i.e 6140H) pair to
Program Counter. So, PC = 6140 H.
So, after execution of PCHL , HL = 6140 H and PC = 6140 H.
8. DAA i. Decimal Adjust Accumulator. Binary contents

of accumulator are changed to its two digit BCD
equivalent
iii. Implicit or Implied addressing mode
Note: DAA instruction changes the binary values of contents of accumulator to its two digit equivalent BCD
number. This instruction makes use of status of CY and AC flags. It performs the operation as follows,
I. If value of lower order four bits (D3-D0) in the accumulator is greater than 9 or if AC flag is set , the
instruction adds 0110 to low order four bits.
II. If value of higher order four bits (D7-D4) in the accumulator is greater than 9 or if CY flag is set , the
instruction adds 0110 to higher order four bits.
Note: DAA is used for BCD addition only not for BCD subtraction.
Ex6.6 The following instructions have been executed by an 8085 microprocessor,

ADDRESS (HEX) INSTRUCTION
6010 LXI H, 8A79 H
6013 MOV A, L
6014 ADD H
6015 DAA
6016 MOV H, A
6017 PCHL
What will be address of the next instruction be fetched?
GATE(EC,97)
Solution :
6010 LXI H, 8A79 H ; Loads HL pair with 8A79H . With H = 8AH and
L = 79H
6013 MOV A, L ; Moves the contents of L (i.e. 79H ) to A. So, A = 79H
6014 ADD H ; Adds the content of H(i.e. 8AH ) to contents of A
and store the result in A.
79H = 0111 1001
8AH =1000 1010
1111
1 0000 0011
CY 0 3H
6015 DAA
; As both AC and CY flags are set during execution of
ADDH, So, DAA, adds 0110H to lower order bits
and 0110H to higher order bits to A to adjust binary
result to Binary coded decimal.
03H = 0000 0011
0110 0110
0110 1001=69H
So, A = 69H
6016 MOV H, A ; Moves the contents of A ( i.e. 69H ) to H.So, H = 69H
6017 PCHL ; Copies the contents of HL pair ( i.e. H = 69H and
L = 79H) to program counter. So, PC = 6979H
After the execution of PCHL the program counter has 6979H . So, the address of next instruction to be
fetched will be 6979H.
9. SUB R i. Subtract contents of R from contents of A and

R→A, B, C, D, E, H & L store result in A
10. SUB M i. Subtract contents of M from A and store result

M → Memory address in A
11. SUI 8bit data i. Subtract the 8 bit data immediately from
contents of A and store the result in A
12. SBB R i. Subtract the contents of R along with carry flag

R→A, B, C, D, E, H & L from contents of A and store the result in A
13. SBB M i. Subtract the contents of M along with carry

M → Memory address flag from A and store the result in A
14. SBI 8 bit data i. Subtract the 8 bit data along with carry flag
from contents of A & store result in A
15. INR R i. Increment contents of R by 1

R→A, B, C, D, E, H & L ii. 1-byte instruction
v. All flags are affected except CY flag
16. INR M i. Increment contents of M by 1

stored in HL pair iii. Indirect addressing mode
iv. Three machine cycles (OP+MR+MW) & 10 T-states
17. DCR R i. Decrement contents of R by 1

R→A, B, C, D, E, H & L ii. 1-byte instruction
18. DCR M i. Decrement contents of M by 1

stored in HL pair iii. Indirect addressing mode
iv. Three machine cycles (OP+MR+MW) & 10 T-states
19. INX RP i. Increment contents of register pair RP by 1
Rp→BC, DE, HL & SP ii. 1-byte instruction
20. DCX RP i. Decrement contents of register pair RP by 1

Rp→BC, DE, HL & SP ii. 1-byte instruction
Ex6.7 In an 8085 system containing 8 KB of ROM and 8 KB of RAM, the ROM is selected when A15 is 1. A13 and
A14 are unused. The CPU executes the following program
Prog 1
MVI A, 00H
STA 8080 H
DCR A
STA C080H
RET
What are the content of memory location 8080 H after the execution of the RETURN instruction?
GATE(IN,03)
Solution:
MVI A, 00 H ; Moves 00H to register A. So, A = 00H
STA 8080H ; Stores the contents of register A at memory location
8080H. So the contents of 8080H becomes 00H .
DCR A ; Decrements the contents of A by one. So the contents
of A after decrement becomes FFH.
STA C080H ; Stores the contents of register A at memory location
C080H. So the contents of C080H becomes FFH .
RET ; Returns to the main program.
The content of memory location 8080H after the execution of the RETURN instruction is 00H.
Ex6.8 MVI B, 00H

MVI A, 1CH
DCR B
DAA
STA TEMP
HLT
What is the content of TEMP location after the execution of the above program ?
IAS(2008)
Solution:
MVI B, 00H ; Moves 00H to register B.
So, B = 00H
MVI A, 1CH ; Moves 1C H to register A.
So, A = 1CH
DCR B ; Decrements the contents of B (i.e. 00H) by one. So,
B = FFH
DAA ; DAA instruction changes the binary values of
contents of accumulator to BCD. This instruction
makes use of status of CY and AC flags. It performs
the operation as follows,
I. If value of lower order four bits (D3-D0) in the
accumulator is greater than 9 or if AC flag is set , the
instruction adds 0110H to low order four bits.
II. If value of higher order four bits (D7-D4) in the
accumulator is greater than 9 or if CY flag is set, the
instruction adds 0110H to higher order four bits.
Here , lower order nibble of A is more than 9 but AC
flag is set by DCR B and upper nibble is less than 9,
therefore, DAA, adds 0110H to lower order nibble of
A to adjust binary result to Binary coded decimal.
A : 1C H = 0001 1100
+0110
0010 0010
So, A = 22H
STA TEMP ; Stores the contents of Accumulator at memory
location TEMP.
HLT ; Halts the execution of program.

Thus contents of TEMP are 22H.
6.4.3 Logical Instructions

1. ANA R i. Contents of R are ANDed with contents of A
R→A, B, C, D, E, H & L and result is stored in A
v. All flags are affected. CY flag is reset and AC
flag is set.
Note: ANA A does not affect the contents of accumulator but resets the carry flag and sets auxiliary carry flag.
2. ANA M i. Contents of M are ANDed with contents of A
M → Memory address and result is stored in A
v. All flags are affected. CY flag is reset and AC
flag is set.
3. ANI 8bit data i. 8 bit data is ANDed with contents of A and result is
stored in A
v. All flags are affected. CY flag is reset and AC flag is
set.
4. ORA R i. Contents of R are ORed with contents of A
v. All flags are affected. Both CY and AC flag are reset.
Note: ORA A does not affect the contents of accumulator but resets the carry and auxillary carry flags.
5. ORA M i. Contents of M are ORed with contents of A
M → Memory address and result is stored in A
6. ORI 8bit data i. 8 bit data is ORed with contents of A and result
is stored in A
7. XRA R i. Contents of R are Ex-ORed with contents of A

Note: XRA A clears the contents of accumulator but resets the carry and auxiliary carry flags.
8. XRA M i. Contents of M are Ex-ORed with contents of A
and result is stored in A
9. XRI 8bit data i. 8 bit data is Ex-ORed with contents of A and
result is stored in A
10. CMA i. Compliment the contents of Accumulator

Note: CMA performs the logical NOT operation.
11. CMC i. Compliment the Carry flag
iii. No addressing mode
v. CY flag is complemented. No other flag is affected.
12. STC i. Set the Carry flag

v. CY flag is set. No other flag is affected.
13. RLC i. Rotate the contents of Accumulator to left without

Carry(CY) flag. The contents of bit D7 are shifted to
CY flag as well as D0 bit.
CY D7 D6 D5 D4 D3 D2 D1 D0

v. Only CY flag is affected.
14. RAL i. Rotate the contents of Accumulator to left through

Carry flag. The contents of bit D7 are shifted to
CY flag and CY flag shifted to D0.
CY D7 D6 D5 D4 D3 D2 D1 D0

15. RRC i. Rotate the contents of Accumulator to right without

Carry flag. The contents of bit D0 are shifted to
CY flag as well as D7 bit.
CY D7 D6 D5 D4 D3 D2 D1 D0

16. RAR i. Rotate the contents of Accumulator to right through

Carry flag. The contents of bit D0 are shifted to CY
flag and CY flag shifted to D7.
CY D7 D6 D5 D4 D3 D2 D1 D0

17. CMP R i. Compare the contents of R with contents of A.
v. All flags are affected.
Note: Comparison is made by subtracting the contents of register R from contents of Accumulator. The contents of
A and R remain unaltered after comparison. The result of operation is reflected by status of flags as under,
If A – R > 0 then S = 0 ; Z = 0 ; CY = 0.
If A – R = 0 then S = 0 ; Z = 1 ; CY = 0.
If A – R < 0 then S = 1 ; Z = 0 ; CY = 1.
18. CMP M i. Compare the contents of M with contents of A.
Note: Comparison is made by subtracting the contents of memory location M from contents of Accumulator. The
contents of A and M remain unaltered after comparison. The result of operation is reflected by status of flags
as under,
If A – M > 0 then S = 0 ; Z = 0 ; CY = 0.
If A – M = 0 then S = 0 ; Z = 1 ; CY = 0.
If A – M < 0 then S = 1 ; Z = 0 ; CY = 1.
19. CPI 8-bit data i. Compare the 8-bit data with contents of A.
Note: Comparison is made by subtracting the 8-bit data from contents of Accumulator. The contents of A remain
unaltered after comparison. The result of operation is reflected by status of flags as under,
If A – (8-bit data) > 0 then S = 0 ; Z = 0 ; CY = 0.
If A – (8-bit data) = 0 then S = 0 ; Z = 1 ; CY = 0.
If A – (8-bit data) < 0 then S = 1 ; Z = 0 ; CY = 1.
Ex.6.9 An 8085 assembly language program is given below.

Line 1 : MVI A, B5H
2 : MVI B, 0EH
3 : XRI 69H
4 : ADD B
5 : NI 9BH
6 : CPI 9FH
7 : STA 3010H
8 : HLT
What is the status of the CY and Z flags after execution of line 7 of the program?
GATE(EC,07)
Solution:
Line 1 : MVI A, B5H ; Moves B5 H to accumulator, A. So , A = B5H
2 : MVI B, 0EH ; Moves 0E H to B. So, B = 0EH
3 : XRI 69H ; Contents of A are ExORed with 69H and result is
stored in A.
A : 1011 0101 (B5H)
69H : 0110 1001
1101 1100 = DCH
So, A = DCH
4: ADD B ; Adds contents of B to contents of A and result is

stored in A.
A : 1101 1100
B : 0000 1110
1110 1010 = EAH
So, A = EAH
5: ANI 9BH ; Contents of A are ANDed with 9BH and result is
stored in A.
A : 1110 1010
9BH : 1001 1011
1000 1010 = 8AH
So, A = 8AH
6: CPI 9FH ; Compares 9FH with contents of A. The contents of
A remains unaffected but status of result is reflected
by flags.
A :1000 1010
9F H :1001 1111
1111 1011
So, CY = 1 & Z = 0
7: STA 3010H ; Stores the contents of A at memory location 3010H.
8: HLT ; Halts the execution of program.
Thus, after execution of line 7 of the program, the CY flag is’1’ and Z flag is ‘0’.
Ex 6.10 Consider the following set of instruction:
STC
CMC
MOV A, B
RAL
MOV B, A
Find the function performed by this set of instructions.
IES(EE,97)
Solution :
Let the contents of register B are 92H. 92 H = 10010010
STC ; Set carry is CY = 1.
CMC ; Complements of carry i.e. CY = 0
MOV A, B ; Copies the contents of B (i.e. 92H) into accumulator.
So, A = 92 H
RAL ; Rotates the contents of accumulator to left through
carry Before rotation -
CY = 0
A =
1 0 0 1 0 0 1 0
A = 92H
After rotation :
CY = 1
A =
0 0 1 0 0 1 0 0
A = 24H
MOV B,A ; Copies contents of accumulater A in register B.
Doubling the contents of register B before execution of RAL instruction,
10010010 : 92 H
10010010 : 92 H
100100100 : 124 H
Thus result after execution of RAL is double of contents of register B before execution of RAL . Hence this
program doubles the contents of register B.
Ex.6.11 Read the following Assembly Language Program Segment of 8085 Microprocessor :
LXI H, 2501H
MOV A, L
ORI F0H
MOV L, A
MOV A,H
ANI F0H
MOV H, A
HLT
What are the contents of A, H and L registers after executing the above set of instructions in sequence?
IES(EE,07)
Solution :
LXI H, 2501H ; Loads HL pair with 2501H. With H =25H and L =
01H
MOV A, L ; Moves the contents of L (i.e. 01H ) to A.
So, A = 01H
ORI F0H ; Contents of A are ORed with F0H and result is stored
in A.
A : 0000 0001
F0H : 1111 0000
1111 0001 = F1 H
So, A = F1 H
MOV L, A ; Moves the contents of A (i.e. F1H ) to L.
So, L = F1H
MOV A,H ; Moves the contents of H (i.e. 25H ) to A.
So, A = 25H
ANI F0 H ; Contents of A are ANDed with F0H and result is
stored in A.
A : 0010 0101
F0H : 1111 0000
0010 0000 = 20 H
So, A = 20 H
MOV H, A ; Moves the contents of A (i.e. 20H ) to H.
So, H = 20H
So, after executing the above set of instructions in sequence the contents of A, H and L registers are 20H,
20H and F1H respectively.
Ex. 6.12 The following program is written for an 8085 microprocessor to add two bytes located at
memory addresses 1FFEH and 1FFFH
LXI H, 1FFEH
MOV B, M
INR L
MOV A,M
ADD B
INR L
MOV M, A
XRA A
What is memory location at which the result of addition is found on completion of the execution of the
above program.
GATE(EE,03)
Solutions:
LXI H, 1FFEH ; Loads HL pair with 1FFEH. So, H= 1FH and L = FEH
MOV B, M ; Moves the contents of memory location whose
address is stored in HL pair (i.e 1FFEH ) to register, B.
INR L ; Increases the contents of register L by one. So,
L = FFH.
MOV A,M ; Moves the contents of memory location whose address
is stored in HL pair (i.e 1FFFH ) to register, A.
ADD B ; Adds the contents of register B to register A and stores
the result in A. So the contents of memory location
1FFEH that are in register B are added to contents
of memory location 1FFFH that are in register A and
sum is stored in A only.
INR L ; Increases the contents of register L by one. So,L = 00H.
MOV M, A ; Moves the contents of accumulator A to memory
location whose address is stored in HL pair (i.e 1F00H).
XRA A ; The contents of A are Ex-ORed either with contents
of A itself and result is stored in A only. This
instruction will clear the accumulator and set the zero
flag and reset the carry flag.
So, the sum of two bytes stored at 1FFEH and 1FFFH will be stored at memory location 1F00H.
Ex.6.13 The following 8085 instructions are executed sequentially
XRA A
MOV L, A
MOV H, L
INX H
DAD H
What the contents of HL pair after execution of above program?
GATE(IN,04)
Solution:
XRA A ; Performs ExOR operation on the contents of A
and stores the result in A. The operation clears the
accumulator.
MOV L, A ; Copy the contents of A (i.e.00H) into L. So,L =00H
MOV H, L ; Copies the contents of L (i.e.00H) into H. So. H = 00H
INX H ; Increment the contents of HL pair by one. So,
HL = 0001H.
DAD H ; Adds the contents of HL pair (i.e. 0001H) to contents
of HL pair(i.e.0001H) and stores the result in HL
pair.
HL: 0000 0000 0000 0001
HL :0000 0000 0000 0001

0000 0000 0000 0010
0 0 0 2
So, now contents of HL pair after the execution of program becomes 0002H.
Ex.6.14 The following program starts at location 0100H.
LXI SP, 000FH
LXI H, 0701H
MVI M, 00H
MVI A, 20H
SUB M
If in addition following code exists from 0109H onwards,
ORI 40H
ADD M
What will be the result in the accumulator after the last instruction is executed?
GATE(EC,05)
Solution:
0100H LXI SP, 000FH
; Initializes the stack pointer with 000F H address
0103H LXI H, 0701H
: Loads HL pair with 0701H. So, H = 07H and L = 01H
0106H MVI M, 00H ; Moves 8 bit data 00H to memory location whose
address is stored in HL pair. So, 00H is moved to
memory location 0701H.
0108H MVI A, 20H ; Moves 8-bit data 20H to accumulator. So, A= 20H
So, the contents of A is 20H when program counter
reaches 0109H
010AH ORI 40H ; The contents of A(i.e.20H) are ORed with 8-bit data
40H.
20H : 00100000
40H : 01000000
01100000
⇒ A =
60H
010CH ADD M
Adds the contents of memory location, whose address ;
is stored in HL pair (i.e. 0701H) to the contents of
A(i.e. 60H) and stores the result in A.
60 H : 01100000
00 H : 00000000
01100000
⇒ A =
60H
The content of accumulator after the last instruction is executed is 60H
6.4.4 Machine Control Instructions
1. HLT i. Halt the execution of program
iv. Two or more machine cycles & 5 or more T-states
Note: When HLT statement is given , the microprocessor completes the execution of current instruction and halts
further execution. The microprocessor enters into Halt acknowledgment machine cycle and Wait states are
inserted in every clock cycle. All the address and data buses are tri-stated (High impedance state) and
contents of registers are unaffected during execution of HLT instruction. The processor can be brought out
of the wait state either by pressing RESET key or by giving an interrupt.
2. NOP i. No operation is performed.
Note: NOP instruction is used to introduce a delay of 4 T states between two successive instructions.
Ex.6.15. In 8085 with 2 MHz clock frequency, what is the time delay obtained after execution of 4 NOP instructions ?
IAS(2007)
Solution:
The instruction NOP require only Opcode fetch machine cycle.
No. of T-states in opcode fetch machinecycle = 4
No. of T-states required in 4 NOP instructions = 16
One T state is precisely equal to one time period of clock signal.
1
So, Time of one T-state, T = µ s
2
1
Time of 16 T-states = 16T = 16 × =8 µ s
2
So, execution of 4 NOP instructions introduces a time delay of 8 µs.
6.4.5 Jump Instructions
I. Unconditional jump instruction:
1. JMP 16 bit address i. Jump execution of program immediately at the
given 16-bit address
iv. Three machine cycles (OP+MR+MR) &10 T-states
II. Conditional jump instruction.
1. JC 16 bit address - Jump if CY = 1
2. JNC 16 bit address - Jump if CY = 0
3. JZ 16 bit address - Jump if Z = 1
4. JNZ 16 bit address - Jump if Z = 0
5. JP 16 bit address - Jump if plus i.e. S = 0
6. JM 16 bit address - Jump if minus i.e S = 1
7. JPE 16 bit address - Jump if P = 1
8. JPO 16 bit address - Jump if P = 0
i. Jump execution of program immediately at the
given 16-bit address if condition is true
iv. a. Three machine cycles (OP+MR+MR) & 10
T-states if condition is true
b. Two machine cycles & 7 T-states if condition
is false
Note : When jump instruction is executed by microprocessor it takes total three machine cycles.
During first machine cycle it fetches the Opcode of instruction. During second and third machine cycles
it reads the address which is operand of the instruction and stores it in temporary register pair WZ. Then
microprocessor places the address of from WZ pair on address lines to transfer the execution to new
address. The program counter is then loaded with WZ +1 i.e address of next byte to be fetched and
thereafter normal execution is resumed through program counter. In conditional return microprocessor
checks the conditon during first two machine cycles and does not go for third machine cycle if the condition
fails.
Ex.6.16 Consider the program given below, which transfers a block of data from one place in memory to another :
MVI C, 0BH
LXI H, 2400H
LXI D, 3400H
L1 : MOV A, M
STAX D
INR L
INR E
DCR C
JNZ LI
What is the total number of memory accesses (including instruction fetches) carried out ?
IES(EE,05)
Solution:
Mnemonic Operand No. of machine cycles/memory accesses
MVI C, 0BH 2
LXI H,2400H 3
LXI D, 3400H 3
L1 : MOV A, M 2
STAX D 2
INR L 1
INR E 1
DCR C 1
JNZ LI 3 or 2
Instructions before L1 needs 8 memory accesses and L1 to JNZ L1 requires 10 memory accesses during
each iteration upto last iteration but 9 machine cycles in last iteration when Z = 0. The loop is executed 11
times till the contents of C becomes zero. So, the total number of memory accesses are 8 + 10*10 + 9 = 117.
JNZ requires 2 machine cycles when condition is false. So total machine cycles will be 117.
Ex.6.17 Consider the following program intended to transfer a block of 5 bytes from A000H to 9000H:
START: LXI B, 9000H
LXI H, A000H
MVI C, 05H
LOOP: MOV A, M
STAX B
INX B
INX H
DCR C
JNZ LOOP
HLT
The above program will not work properly. Find out the reason.
IES(E&T,04)
Solution:
START: LXI B, 9000H
LXI H, A000H
MVI C, 05H
LOOP: MOV A, M
STAX B
INX B
INX H
DCR C
JNZ LOOP
HLT
The above program is intended to transfer a block of 5 bytes from A000H to 9000H, will not work because
the instruction INX B in the loop increases the BC pair by ‘1’ , the instruction DCR C again restore same
contents in BC pair as before execution of INX B. So, the contents of register ‘C’ will never become Zero
and instruction DCR C will not set the zero flag and program will enter into infinite loop. The program will
work properly if another register such as D is used as counter instead of register C.
The correct program will as under,
START: LXI B, 9000H
LXI H, A000H
MVI D, 05H
LOOP: MOV A, M
STAX B
INX B
INX H
DCR D
JNZ LOOP
HLT
Ex.6.18 Consider the following assembly language program,
MVI B,87H
MOV A, B
START: JMP NEXT
MVI B, 00H
XRA B
OUT PORT 1
HLT
NEXT: XRA B
JP START
OUT PORT 2
HLT
What is result after execution of the above program in an 8085 microprocessor.
GATE(EC,02)
Solution:
The Sequence of execution of above program will be as under,
MVI B,87H ; Moves 87 H to B
MOV A, B ; Moves the contents of B (i.e. 87 H) to A. So, A = 87 H
START: JMP NEXT ; Jumps to NEXT unconditionally
NEXT: XRA B ; Contents of B (i.e. 87H) are ExORed with contents of
A(i.e. 87H) and result is stored in A.
A ⊕ B : 10000111
10000111
00000000
⇒ A = 00H
JP START ; Jumps to START if sign flag is reset. As XRA B in
previous step resets the sign flag so the program
jumps back to START.
START: JMP NEXT ; Jumps to NEXT unconditionally
NEXT: XRA B ; Contents of B (i.e. 87H) are ExORed with contents of
A(i.e. 00H) and result is stored in A.
A ⊕ B : 00000000
10000111
10000111
⇒ A = 87H
As D7 bit of A is high so sign(S) flag is set.
JP START ; Jumps to START if sign flag is reset.
As XRA B in previous step sets the sign flag so the
program comes out of loop.
OUT PORT 2 ; Sends contents of A(i.e. 87H) to I/O device of PORT2
Thus, program displays 87 H at port 2.
Ex.6.19 An Intel 8085 processor is executing the program given below.

MVI A, 10H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
What is the number of times that the instruction NOP will be executed?
IAS(2006)
Solution:
MVI A, 10H
Moves data 10H to A. ;
MVI B, 10H
Moves data 10H to register B. ;
BACK : NOP
No operation ;
ADD B ;
Adds contents of register B(i.e. 10H) to A(i.e. 10H)
and store result in A.
10H : 00010000
+ 10H : 00010000
00100000
⇒ A = 20 H and CY = 0
RLC ; Rotates contents of accumulator to left without carry
flag.
Before rotation:
CY = 0

0 0 1 0 0 0 0 0
After rotation:
CY = 0

0 1 0 0 0 0 0 0
⇒ A = 40 H and CY = 0
JNC BACK ; Jumps to BACK if CY = 0
HLT ; Halts the execution
After execution of RLC instruction 3 times CY flag will be set. So, the instruction NOP will be executed
three times in the given program.
Ex.6.20 How many time will the following loop be executed?

LXI B, 0010 H
LOOP: DCX B
MOV A,B
ORA C
JNZ LOOP
IES(EE,06)
Solution :
LXI B, 0010 H ; Loads BC pair with 0010H. So, B = 00H and
C = 10H.
LOOP: DCX B ; Decreases the contents of BC pair by 1.
MOV A,B ; Moves the contents B (i.e. 00H) to A.
ORA C ; Contents of C are ORed with contents of A and
results are stored in A.
A OR C : 00000000
00001111
00001111
⇒ A = 0 FH
JNZ LOOP ; Jumps to LOOP until Z = 1
During the first execution of loop C=0FH and during last execution of loop C =00H . As C is decremented
by 1 every time so , the loop will be executed 16 times before the execution comes out of loop.
Ex.6.21 A software delay subroutine is written as given below :
DELAY: MVI H, 255 D ; 255 D is in decimal
MVI L, 255 D ; 255 D is in decimal
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR L instruction will be executed ?
GATE(EE,06)
Solution :
DELAY: MVI H, 255 D ; Moves decimal number 255 in register H.
MVI L, 255 D ; Moves decimal number 255 in register L.
LOOP: DCR L ; Decrements L by ‘1’
JNZ LOOP ; First time DCR L runs for 255 times and second time
onward DCR L is executed 256 times as because
second time onward contents of L also changes from
00H to FFH .
DCR H ; Decrements H by ‘1’
JNZ LOOP ; Jumps to LOOP until contents of H becomes zero. It
will run the loop 255 times.
During first run DCR L is executed 255 times. From second run onward DCR L is executed 256 times.
So, total number times DCR L will be executed will be 255 + 254*256 = 65279
Ex.6.22 8-bit signed integers in 2’s complement form are read into the accumulator of an 8085 microprocessor from
an I/O port using the following assembly language program segment with symbolic addresses
BEGIN : IN PORT
RAL
JNC BEGIN
RAR
END: HLT
What is final outcome of above program?
GATE(IN,07)
Solution :
BEGIN :IN PORT ; Reads the data into accumulator from IO device
connected at PORT.
RAL ; Rotates the contents of accumulator to left through
carry flag.
JNC BEGIN ; Jumps to BEGIN if CY is not set.
RAR ; Rotates the contents of accumulator to right through
carry flag.
END: HLT ; Halts the execution of program.
When number read from IO device is negative number , the bit D7 of accumulator is ‘1’. So the instruction
RAL will set the carry flag and program execution will not jump to BEGIN when it executes JNC BEGIN
instruction as CY=1. So, the execution will continue with RAR instruction and at end the program execution
will halt after execution of HLT instruction.
Ex.6.23 A part of a program written for an 8085 microprocessor is shown below.

SUB A
MOV C,A
LOOP 1: INR A
DAA
JC LOOP2
INR C
JNC LOOP 1
LOOP 2: NOP
When the program execution reaches LOOP2, what are contents of register C?
GATE(IN,08)
Solution:
SUB A ;
Subtracts the contents of A from A and store the result
in A. Instruction clears the accumulator , A. So,
A = 00 H.
MOV C,A ; Moves the contents of A to register C. So, C = 00H
LOOP 1: INR A ; Increments the contents of A by one.
DAA ; Converts the contents of A to BCD equivalent.
JC LOOP2 ; Jumps to LOOP2 if carry flag is set.
INR C ; Increments the contents of C by one.
JNC LOOP 1 ; Jumps to LOOP1 if carry flag is reset.
LOOP 2: NOP ; No operation.
The program will remain in LOOP1 till BCD equivalent in A is less than 100. When BCD equivalent in A
becomes 100 carry flag is generated and execution is transferred to LOOP2, The contents of C by that time
will be Hexadecimal equivalent of 99 which is 63 H.
6.4.6 Stack and Its Related Instructions
Stack is the group of memory locations used by the microprocessor or programmer to store the data
temporarily during the execution of a program. The stack can be used to store the contents of program
counter (PC) by the microprocessor automatically when a subroutine is called. The stack can also be used
by the programmer for storing the contents of register pairs of BC, DE, HL & PSW (Program Status
word). Program Status Word indicates the contents of Accumulator and Flag register. Here Accumulator
is considered as higher order and Flag register is considered as lower order register. Top of the stack
is pointed by a 16 bit register called stack pointer(SP). The stack pointer is the programmable register
which always stores the address of top most location of the stack. The stack pointer can be initiated by the
instruction, LXI SP, 16 bit data. The contents of a register pair can be stored on the top of the stack by
using PUSH instruction and contents from the top of the stack can be loaded in to a regster pair using POP
instruction. Stack pointer is always decremented by 2 after the execution of each PUSH instruction and it is
incremented by 2 after the execution of each POP instructions. It works on the principle of last-in first-out.
The information on stack is not destroyed until new information is stored in those locations.
Note: The data storage on the stack begins from the address next to the address with which stack pointer is
initiated. For example when SP is initiated with 2000H the data storage will begin from 1FFF H.
Note: Stack pointer must be initiated before using PUSH, POP or Call instructions.
The Instructions Related to Stack :
1. PUSH RP i. Store the contents of register pair Rp on two
Rp→BC, DE, HL & PSW top locations of stack.
iv. Three machine cycles (OP+MW+MW) & 12 T-states
Note: PSW (Program Status Word) represents the contents of the accumulator and the flag regiser; the accumulator
is high order register and the flag register is low order register.
Note: PUSH instruction first decrements the SP by one and then copies the contents of higher order register of
pair Rp on the location shown by stack pointer . Then stack pointer register is again decremented by one
and the content of lower order register of pair Rp are copied on the location shown by stack pointer. Thus
stack pointer is decremented by two after execution of PUSH instruction.
2. POP RP i. Retrieve the contents of two top locations of
Rp→BC, DE, HL & PSW stack to register pair Rp .
iv. Three machine cycles (OP+MR+MR) & 10 T-states
Note: POP instruction first copies the contents of memory location indicated by stack pointer (SP) to lower order
register of pair Rp and then increment stack pointer by one . It again copies the contents of memory location
indicated by SP to higher order register of pair Rp and then increment stack pointer by one. Thus stack
pointer is incremented by two after execution of each POP instruction.
3. XTHL i. Exchange the contents of two top locations of stack
with contents of HL pair.
iv. Five machine cycles (OP+MR+MR + MW + MW)
&16 T-states
Note: The contents of L are exchanged with location indicated by SP and contents of H are exchanged with
memory location (SP+1). However , the contents of SP remains unaltered.
Note: All instructions related to stack have indirect addressing mode.
Ex.6.24 Consider the following Assembly Language program :
MVI A, 30H
ADI 30H
XRA A
POP H
What are the contents of A at the end of program.
IES(EE,98)
Solutions:
MVIA, 30H ; Moves data 30H to A
ADI 30H ; Adds 30H to contents of A and store result in A.
A + A : 00110000
00110000
01100000
⇒ A = 60H
XRA A ; Performs ExOR operation the contents of A and
store result in A.
A⊕ A : 01100000
01100000
00000000
⇒ A = 00H
POP H ; Moves the contents of top of stack to HL pair.
Thus, the contents of A after the execution of program will be A = 00H
Ex.6.25 In a 8085 microprocessor the value of the stack pointer (SP) is 2010H and that of DE register pair is 1234H
before the following code is executed.
LXI H, 0000H
PUSH H
PUSH H
POP B
DAD SP
XCHG
What are contents of the DE register pair after the execution of above program?
GATE(IN,05)
Solution:
Given, Contents of DE =1234H
Contents of SP =2010H
LXI H, 0000H ; Loads HL pair with 0000H. So, H= 00H and L = 00H
PUSH H ; Stores the contents of HL pair on the top of the stack.
The stack pointer is first decremented by one from
2010H to 200FH and then contents of H(i.e.00H)
are stored at 200FH, the stack pointer is again
decremented by one from 200FH to 200EH and then
contents of L(i.e.00H) are stored at 200EH. So at end
of instruction, contents of SP are 200EH, contents of
200EH are 00H and contents of 200FH are 00H.
PUSH H ; Stores the contents of HL pair on the top of the stack
The stack pointer is first decremented by one from
200EH to 200DH and then contents of H(i.e.00H)
are stored at 200DH, the stack pointer is again
decremented by one from 200DH to 200CH and then
contents of L(i.e.00H) are stored at 200CH. So at end
of instruction, contents of SP are 200CH, contents of
200CH are 00H and contents of 200DH are 00H.
POP B ; Stores the contents of top of stack in BC pair. The
contents of 200CH(i.e.00H) are store in C and then
stack pointer is incremented by one from 200CH
to 200DH and then contents of 200DH(i.e.00H) are
stored in B, the stack pointer is again incremented by
one from 200DH to 200EH. So at end of instruction,
contents of SP are 200EH, contents of B are 00H and
contents of C are 00H.
DAD SP ; Adds the contents of stack pointer(i.e. SP=200EH) to
contents of HL pair(i.e.0000H) and store the result in
HL pair and contents of SP remains unaltered.
HL : 0000 0000 0000 0000
SP : 0010 0000 0000 1110

0010 0000 0000 1110
2 0 0 Ec
So, now contents of HL pair becomes 200EH

XCHG ; Exchanges the contents of HL pair(i.e. 200EH) with
contents of DE pair(i.e.1234H). At end of instruction
HL=1234H and DE = 200EH.
The value of the DE register pair after the execution of program is 200EH.
6.4.7 Call Instructions
Call instructions are used to call a subroutine during execution of a main program. A subroutine is a set of
instructions used to perform a task repeatedly.
I. Unconditional Call Instruction
1. CALL 16 bit address i. Call immediately the subroutine stored at the
given 16- bit address
iii. Immediate/Register Indirect addressing mode
iv. Five machine cycles (OP+MR+MR+MW+MW)
& 18 T-states
II. Conditional Call Instructions
1. CC 16 bit address - Call if CY = 1
2. CNC 16 bit address - Call if CY = 0
3. CZ 16 bit address - Call if Z = 1
4. CNZ 16 bit address - Call if Z = 0
5. CP 16 bit address - Call if plus i.e. S = 0
6. CM 16 bit address - Call if minus i.e S = 1
7. CPE 16 bit address - Call if P = 1
8. CPO 16 bit address - Call if P = 0
i. Call immediately the subroutine stored at the
given 16- bit address if condition is true.
iii. Immediate/Register Indirect addressing mode
iv. a. Five machine cycles (OP+MR+MR + MW
+ MW) &18 T-states if condition is true.
b. Two machine cycles & 9T-states if condition
is false.
Note : When CALL instruction is executed by microprocessor it takes total five machine cycles.
During first machine cycle it fetches the Opcode of instruction. During second and third machine cycles it
reads the address of subroutine and stores in temporary register pair WZ. In the 4th and 5th machine cycles
the microprocessor saves the contents of Program Counter(PC), which has address of next instruction is to
be executed, on the top of stack. So, stack pointer must be initiated in the main program before calling of
subroutine.After saving the contents of program counter on the top of stack the microprocessor places the
address of subroutine, from WZ pair, on address lines to transfer the execution to subroutine. The program
counter is then loaded with WZ +1 i.e address of next byte to be fetched.
Note : During execution of conditional call instructions if condition is true the number of machines cycles are
same as in case of unconditional call but if condition is false only two machines cycles are required.
Ex.6.26 The following sequence of instructions are executed by an 8085 microprocessor:
1000 LXI SP, 27FFH
1003 CALL 1006H
1006 POP H
What will be contents of the stack pointer (SP) and the HL, register pair on completion of execution of these
instructions?
GATE(EC,96)
Solution:
1000 LXI SP, 27FFH ; Initializes the stack pointer with 27FFH.
1003 CALL 1006H ; Saves the contents of program counter (i.e. address
of next instruction, 1006H) on top of stack and call
the subroutine stored at address 1006H . During the
saving the contents of program counter the stack
pointer is decremented by one and 10H is saved at
27FEH and stack pointer is again decremented by
one& 06H is saved at 27FDH.
1006 POP H ; Retrieves the contents of top of stack in HL pair.
During poping up of stack the contents of 27FDH
(i.e.06H ) are stored in L and stack pointer is
incremented by one to 27FEH. Then the contents of
next memory location 27FEH (i.e. 10H)are stored in
H and stack pointer is again incremented by one to
27FFH.
Therefore, the contents of the stack pointer (SP) and the HL register pair on completion of execution of
these instructions are SP = 27FFH and HL = 1006H.
Ex.6.27 The stack pointer of an 8085A microprocessor contains ABCDH.
PUSH PSW
XTHL
PUSH D
JMP EC75H
At the end of the execution of the above instructions, what would be the content of the stack pointer?
IES(EE,08)
Solution :
Given, SP = ABCDH
PSW stands for Program Status Word. It is a 16 bit combination of Accumulator and flag register.
Accumulator is higher order and flag register is lower order register.
PUSH PSW ; This instruction first decrements the SP by one from
ABCDH to ABCCH and then copies the contents of
accumulator on the location shown by stack pointer
register(i.e. ABCCH). Then stack pointer register is
decremented by one and the content of flag register
are copied on the next memory location(i.e.ABCBH).
The contents of SP becomes ABCBH
XTHL ; Exchanges the contents of HL pair with top of stack.
Contents of ABCBH are exchanged with L and
contents of ABCCH are exchanged with H. But
after execution of XTHL the stack pointer points at
ABCBH. So, the contents of SP remain ABCBH.
PUSH D ; Pushes the contents of DE pair on top of stack. First
stack pointer is decrement by one to ABCA H and
then contents of D are store at ABCAH . The stack
pointer is again decremented by one to ABC9H and
then contents of E are stored at ABC9H
JMP EC75H ; The program execution jumps to memory location
EC75H , unconditionally.
At the end of execution of above instruction the contents of Stack pointer are ABC9H.
6.4.8 Return Instructions
Return instructions are used at the end of the subroutine. When microprocessor encounters a return
instruction , the execution of the program is returned to the main program.
I. Unconditional Return Instruction
1. RET i. Return to main program unconditionally
iii. Register Indirect addressing mode
iv. Three machine cycles (OP+MR+MR) & 10 T-states
II. Conditional Return Instructions
1. RC - Return if CY = 1
2. RNC - Return if CY = 0
3. RZ - Return if Z = 1
4. RNZ - Return if Z = 0
5. RP - Return if plus i.e. S = 0
6. RM - Return if minus i.e S = 1
7. RPE - Return if P = 1
8. RPO - Return if P = 0
i. Return to main program if condition is true.
iii. Register Indirect addressing mode
iv. a. Three machine cycles (OP+MR+MR) &12
T-states if condition is true.
b. One machine cycles & 6 T-states if condition
is false.
Note 1: When RET instruction is executed by microprocessor it takes three machines cycles. During first machine
cycle miroprocessor fetches the Opcode and during second and third machines it reads the contents of top
of stack and stores in temporary register pair WZ. The contents of WZ pair are ,then, placed on address
lines and program counter is loaded with WZ +1 i.e. address of next byte to be fetched.
Note 2 : During execution of conditional return instructions if condition is true the number of machines cycles are
same as in case of unconditional return but if condition is false only one machines cycle is required.
Ex.6.28 In an 8085 based system the subroutine TEST given below is called by another program.
TEST: MVI A, 00H
CALL TEST1
TEST1: INR A
RET
What are the contents of the accumulator when the processor returns from the subroutine TEST?
GATE(IN,02)
Solution :
TEST: MVI A, 00H ; Moves 00H to register A. So, A = 00H
CALL TEST1 ; Calls the subroutine TEST1.
TEST1: INR A ; Increments the contents of A by one.
RET ; Returns to main program.
In the above program the instructions INR A is executed twice. Once by calling of TEST1 by Subroutine
TEST and once by subroutine TEST itself. So, the contents of accumulator are incremented twice.
Therefore, the contents of A after returning from subroutine TEST will be 02H.
Ex.6.29 Following is the segment of a 8085 assembly language program:
LXI SP, EFFF H
CALL 3000 H
:
:
3000 H : LXI H, 3CF4 H
PUSH PSW
SPHL
POP PSW
RET
What are the contents of SP on completion of RET execution?
GATE (EC,06)
Solution :
LXI SP, EFFF H ; Loads SP with EFFFH
CALL 3000 H ; Calls a subroutine stored at address 3000H. The
contents of program counter are stored on top of stack
at memory location EFFE and EFFD respectively.
:
:
:
3000 H : LXI H, 3CF4 H ; Loads HL pair with 3CF4 H
PUSH PSW ; This instruction first decrement the SP by one from
EFFD to EFFC and then copies the contents of
accumulator on the location shown by stack pointer
register (i.e. EFFC H). Then stack pointer register is
decremented by one and the content of flag register
are copied on the next memory location(i.e. EFFBH).
The contents of SP becomes EFFB H
SPHL ; Moves the copy of contents of HL pair(i.e. 3CF4 ) in
SP pointer. So, contents of SP becomes 3CF4.
POP PSW ; Stores the contents of location indicated by stack
pointer (i.e. 3CF4) in F and and and stack pointer is
then incremented by one to 3CF5 and then contents
of 3CF5 are stored in A register. So the contents of
3CF4 are stored in flag register and contents of 3CF5
in Accumulator and stack pointer is updated to 3CF6.
RET ; Reads the contents of top of stack in temporary
register pair WZ. The contents of 3CF6 goes to Z and
that of 3CF7 goes to W register and stack pointer is
updated to 3CF8 H.
Thus , contents of SP are 3CF8 H after execution of RET instruction.

OBJECTIVE TYPE PRACTICE QUESTIONS
GATE QUESTIONS
Q.1 The total number of memory accesses involved (inclusive of the op-code fetch) when an 8085 processor
executes the instruction LDA 2003 is
(a) 1 (b) 2
(c) 3 (d) 4
GATE(EC.96)
Q.2 In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator
is less than that of register B. As a result
(a) Carry flag will be set but Zero flag will be reset
(b) Carry flag will be reset but Zero flag will be set
(c) Both Carry flag and Zero flag will be reset
(d) Both Carry flag and Zero flag will be set
GATE(EC,03)
Q.3 The number of memory cycles required to execute the following 8085 instructions
(I) LDA 3000 H
(II) LXI D, F0F1 H
would be
(a) 2 for (I) and 2 for (II) (b) 4 for (I) and 3 for (II)
(c) 3 for (I) and 3 for (II) (d) 3 for (I) and 4 for (II)
GATE(EC,04)
Q.4 Consider the sequence of 8085 instructions given below.
LXI H, 9258
MOV A, M
CMA
MOV M, A
Which one of the following is performed by this sequence?
(a) Contents of location 9258 are moved to the accumulator
(b) Contents of location 9258 are compared with the contents of the accumulator
(c) Contents of location 8529 are complemented and stored in location 8529
(d) Contents of location 5892 are complemented and stored in location 5892
GATE(EC,04)
Q.5 If the HLT instruction of a 8085 microprocessor is executed,
(a) the microprocessor is disconnected from the system bus till the Reset is pressed
(b) the microprocessor enters into a Halt state and the buses are tri-stated
(c) the microprocessor halts execution of the program and returns to monitor
(d) the microprocessor reloads the program from the locations 0024 and 0025 H.
GATE(EE,92)
Q.6 The contents of the accumulator in an 8085 microprocessor is altered after the execution of the instruction.
(a) CMPC (b) CPI 3 A
(c) ANI 5 C (d) ORA A
GATE(EE,94)
Q.7 In an 8085 microprocessor, after the execution of XRA A instruction
(a) the carry flag is set
(b) the accumulator contains FFH
(c) the zero flag is set
(d) the accumulator contents are shifted left by one bit
GATE(EE,95)
Q.8 The 8085 assembly language instruction that stores the contents of H and L registers into the memory
locations 2051 H and 2050H, respectively, is
(a) SPHL 2050H (b) SPHL 2051H
(c) SHLD 2050H (d) STAX 2050H
GATE(EE,05)
Q.9 In 8085 microprocessor, CY flag may be set by the instruction
(a) SUB (b) INX
(c) CMA (d) ANA
GATE(IN,01)
Q.10 For an 8085 microprocessor, the Stack Pointer (SP) and Program Counter (PC) registers contain the number
2400H and F000H in Hex respectively. The contents of the register after execution of the instruction CALL
E000H would be
(a) PC : F003H SP : 2400H (b) PC : E000H SP : 2400H
(c) PC : E000H SP : 2401H (d) PC : E000H SP : 23FEH
GATE(IN,00)
Q.11 Find the correct match among the following pair in the context of an 8085 microprocessor.
a. DAA e. Program control instruction
b. LXI f. Data movement instruction
c. RST g. Interrupt instruction
d. JMP h. Arithmetic instruction
(a) a-e, b-f, c-g, d-h (b) a-h, b-f, c-g, d-e
(c) a-h, b-g, c-f, d-e (d) a-f, b-h, c-g, d-e
GATE(IN,00)
Q.12 A memory mapped I / O device has an address of 00F0H. Which of the following 8085 instructions outputs
the content of the accumulator to the I/O device?
(a) LXI H, 00F0H (b) LXI H, OOFOH
MOV M, A OUT M
(c) LXI H, 00F0H (d) LXI H, 00F0H
OUT F0H MOV A, M
GATE(IN,06)
Q.13 In an 8085 A microprocessor based system, it is desired to increment the contents of memory location
whose address is available in (D,E) register pair and store the result in same location. The sequence of
instructions is
(a) XCHG (b) XCHG
INR M INX H
(c) INX D (d) INR M
XCHG XCHG
GATE(EE,06)
Q.14 An 8085 assembly language program is given below.
Line 1 : MVI A, B5H
2 : MVI B, 0EH
3 : XRI 69H
4 : ADD B
5 : ANI 9BH
6 : CPI 9FH
7 : STA 3010H
8 : HLT
The contents of the accumulator just after execution of the ADD instruction in line 4 will be
(a) C3H (b) EAH
(c) DCH (d) 69H
GATE(EC,07)
Q.15 In an 8085 microprocessor, the contents of the Accumulator, after the following instructions are executed
will become
XRA A
MVI B, F0H
SUB B
(a) 01 H (b) 0F H
(c) F0 H (d) 10 H
GATE(EE,09)
Q.16 The following is an assembly language program for 8085 microprocessors
Address Instruction Code Mnemonic
1000H 3E 06 MVI A,06H
1002H C6 70 ADI 70 H
1004H 32 07 10 STA 1007H
1007H AF XRA A
1008H 76 HLT
When this program halts, the accumulator contains
(a) 00H (b) 06H
(c) 70H (d) 76H
GATE(IN,09)
Q.17 For the 8085 assembly language program given below, the content of the accumulator after the execution
of the program is
3000 MVI A , 45 H
3002 MOV B, A
3003 STC
3004 CMC
3005 RAR
3006 XRA B
(a) 00H (b) 45H
(c) 67 H (d) E7H
GATE(EC,10)
Q.18 When a “CALL Addr” instruction is executed, the CPU carries out the following sequential operations
internally :
Note :–
(R) means content of register R
((R)) means content of memory location pointed to by R
PC means Program Counter
SP means Stack Pointer
(a) (SP) incremented (b) (PC) ← Addr
(PC) ← Addr ((SP)) ← (PC)
((SP)) ← (PC) (SP) incremented
(c) (PC) ← Addr (d) ((SP)) ← (PC)
(SP) incremented (SP) incremented
((SP)) ← (PC) (PC) ← Addr
GATE(EE,10)
Q.19
In an 8085 processor, the main program calls the subroutine SUB1 given below. When the program returns
to the main program after executing SUB1, the value in the accumulator is
Address Opcode Mnemonic
2000 3E 00 SUB1 : MVI A,00H
2002 CD 05 20 CALL SUB2
2005 3C SUB2 : INR A
2006 C9 RET
(a) 00 H (b) 01 H
(c) 02 H (d) 03 H
GATE(IN,10)
Q.20 The subroutine SBX given below is executed by an 8085 processor. The value in the accumulator immediately
after the execution of the subroutine will be.
SBX : MVI A, 99 H
ADI 11H
MOV C,A
RET
(a) 00 H (b) 11 H
(c) 99 H (d) AA H
GATE(IN,10)
Q.21 An 8085 assembly language program is given below. Assume that the carry flag is initially unset. The
contents of the accumulator after the execution of the program is
MVI A,07H
RLC
MOV B,A
RLC
RLC
ADD B
RRC
(a) 8CH (b) 64 H
(c) 23H (d) 15H
GATE(EC,11)
Q.22 A portion of the main program to call a subroutine SUB in an 8085 environment is given below.
:
:
LXI D, DISP
LP: CALL SUB
:
:
It is desired that control be returned to LP + DISP + 3 when the RET instruction is executed in the subroutine.
The set of instruction that precede the RET instruction in the subroutine are
(a) POP D (b) POP H
DAD H DAD D
PUSH D INX H
INX H
INX H
PUSH H
(c) POP H (d) XTHL
DAD D INX D
PUSH H INX D
INX D
XTHL
GATE(EE,11)
Q.23 The contents (in Hexadecimal) of some of the memory locations in an 8085A based system are given
below:
Address Contents
•• ••
26FF 00
26FF 01
2700 02
2701 23
2702 04
•• ••
The contents of stack pointer (SP), program counter (PC) and (HL) are 2700H, 2100H and 0000H
respectively. When the following sequence of instructions are executed.
2100 H: DAD SP
2101 H: PCHL
The contents of (SP) and (PC) at the end of execution will be
(a) (PC) = 2102H, (SP) = 2700H. (b) (PC) = 2700H, (SP) = 2700H.
(c) (PC) = 2800H, (SP) = 26FEH. (d) (PC) = 2A02H, (SP) = 2702H.
GATE(EE,08)
Q.24 An input device is interfaced with Intel 8085A microprocessor as memory mapped I/O. The address of the
device is 2500H. In order to input data from the device to accumulator, the sequence of instructions will be
(a) LXI H, 2500H (b) LXI H,2500H
MOV A, M MOV M, A
(c) LHLD 2500H (d) LHLD 2500H
MOV A, M MOV M, A
GATE(EE,08)
Q.25 For 8085 microprocessor, the following program is executed.
MVI A, 05H;
MVI B, 05H;
PTR: ADD B;
DCR B;
JNZ PTR;
ADI 03H;
HLT;
At the end of program, accumulator contains
(a) 17 H (b) 20 H
(c) 23 H (d) 05 H
GATE (EC, 13)
Q.26 In 8085 A microprocessor, the operation performed by the instruction LHLD 2100H is
(a) (H) ← 21H, (L) ← 00H (b) (H) ← M(2100H), (L) ← M(2100H)
(c) (H) ← M(2101H), (L) ← M(2100H) (d) (H) ← 00H, (L) ← 21H
GATE (2014/EE-III/1 M)
Q.27 In an 8085 microprocessor, the following program is executed
2000 H XRA A
2001 H MVI B,04H
2003 H MVI A, 03H
2005 H RAR
2006 H DCR B
2007 H JNZ 2005
200 AH HLT
At the end of program, register A contains
(a) 60 H (b) 30 H
(c) 06 H (d) 03 H
GATE (2014/EE-II/2 M)
Q.28 In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are,
respectively
(a) B and F (b) A and F
(c) H and F (d) A and C
GATE (2015/EC-I/1 M)
Q.29 Which one of the following 8085 microprocessor programs correctly calculates the product of two 8-bit
numbers stored in registers B and C?
(a) MVI A, 00H (b) MVI A, 00H
JNZ LOOP CMP C
CMP C LOOP DCR B
LOOP DCR B JNZ LOOP
HLT HLT

(c) MVI A, 00H (d) MVI A, 00H
LOOP ADD C ADD C
DCR B JNZ LOOP
JNZ LOOP LOOP INR B
HLT HLT
GATE (2015/EC-III/1 M)
Q.30 In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?
(a) MOV B, M (b) PCHL
(c) RNZ (d) SBI BEH
GATE (2015/EC-II/1 M)
Q.31 In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the
following options is the correct reason for this?
(a) For POP, the data transceivers remain in the same direction as for instruction fetch (memory to
processor), whereas for PUSH their direction has to be reversed.
(b) Memory write operations are slower than memory read operations in an 8085 based system.
(c) The stack pointer needs to be pre-decremented before writing registers in a PUSH, whereas a POP
operation uses the address already in the stack pointer.
(d) Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
GATE (2016/EC-I/2 M)
Q.32 In an 8085 microprocessor, the contents of the accumulator and the carry flag are A7 (in hex) and 0,
respectively. If the instruction RLC is executed, then the contents of the accumulator (in hex) and the carry
flag, respectively, will be
(a) 4E and 0 (b) 4E and 1
(c) 4F and 0 (d) 4F and 1
GATE (2016/EC-III/1 M)
Q.33 The following FIVE instructions were executed on an 8085 microprocessor.
MVI A, 33H
MVI B, 78H
ADD B
CMA
ANI 32H
The Accumulator value immediately after the execution of the fifth instruction is
(a) 00H (b) 10H

(c) 11H (d) 32H
GATE (EC-I/2017/ 2 M)
Q.34
An 8085 microprocessor accesses two memory locations (2001 H) and (2002H), that contain 8-bit numbers
98H and B1H respectively. The following program is executed:
LXI H, 2001 H
MVIA, 21H
INX H
ADD M
INX H
MOV M, A
HLT
At the end of this program, the memory location 2003H contains the number in decimal (base 10) form
________.
GATE (EE/2020/ 2 M)
IES QUESTIONS
Q.35 Which one of the following addressing technique is not used in 8085 microprocessor ?
(a) Register (b) Immediate
(c) Register indirect (d) Relative
IES (EE,09)
Q.36 When the operand required for an instruction is stored inside the processor, then what this addressing mode
is called ?
(a) Direct (b) Register
(c) Implicit (d) Immediate
IES (EE,09)
Q.37 Which one of the following instructions is a 3 - byte instruction ?
(a) MVI A (b) LDAX B
(c) JMP 2050 (d) MOV A, M
IES(EE,06)
Q.38 Match List-I (Type of instruction) with List-II (instruction) and select the correct answer using the codes
given below the Lists :
List-I List-II
A. One byte instruction 1. MVI A, data
B. Two bytes instruction 2. MOV A,B
C. Three bytes instruction 3. MOV A,M
D. Register indirect addressing 4. JMP addr.
Code :
A B C D
(a) 1 2 4 3
(b) 2 1 4 3
(c) 2 1 3 4
(d) 1 2 3 4
IES(EE,97)
Q.39 In 8085 microprocessor system, the direct addressing instruction is
(a) MOV A, B (b) MVI B, 0AH
(c) MOV C, M (d) STA addr
IES(EE,98)
Q.40 Match List-I (Instructions) with List-II (Type of Addressing) with reference to a 8085 microprocessor and
select the correct answer using the codes given below the Lists:
List-I List-II
A. MOV A, M 1. Direct addressing
B. LXI H, E400H 2. Register addressing
C. LDA F1CDH 3. Implicit addressing
D. CMC 4. Register indirect addressing
5. Immediate addressing
Code:
A B C D
(a) 5 4 1 3
(b) 4 5 3 1
(c) 5 4 2 3
(d) 4 5 1 3
IES(EE,03)
Q.41 For Intel 8085, Match List-I (Addressing Mode) with List-II (Instruction) and select the correct answer
using the codes given below the lists:
List-I List-II
A. Implicit addressing 1. JMP 3FA0H
B. Register-indirect 2. MOV A, M
C. Immediate 3. LDA 03FCH
D. Direct addressing 4. RAL
Code:
A B C D
(a) 4 1 2 3
(b) 4 2 1 3
(c) 3 2 1 4
(d) 3 1 2 4
IES(EE,04)
Q.42 For the purpose of data processing an efficient assembly language programmer makes use of the general
purpose register rather than memory. The reason is :
(a) The set of instructions for data processing with memory is limited
(b) Data processing becomes easier when registers are used
(c) More memory related instructions are required in the program for data processing
(d) Data processing with registers takes fewer cycles than that with memory
IES(EE,11)
Q.43 Match List - I(Character used in Programming) with List - II(Assembly Language Assembly language) and
select the correct answer using the code given below the lists :
List-I List-II
A. Blank 1. Beginning of comment field
B. Colon 2. End of label field
C. Semicolon 3. Separator for operand
D. Comma 4. Separator for op field and operand
Code:
A B C D
(a) 1 3 4 2
(b) 4 2 1 3
(c) 1 2 4 3
(d) 4 3 1 2
IES(E&T,06)
Q.44 A sequence of instruction is executed as follows:

begin
decode the instruction fetched;
if operand in memory then fetch operand;
execute instructions;
end
This sequence of instructions has performed
(a) fetch cycle (b) both fetch and execute cycles
(c) execute and decode cycles (d) execute cycle
IES(EE,00)
Q.45 Match List-I (Instruction) with List-II (Operation) for Intel 8085 and select the correct answer using the
codes given below the lists:
List-I List-II
A. PCHL 1. Exchange the top of the stack with the contents of HL pair
B. SPHL 2. Exchange the contents of HL with those of DE pair
C. XTHL 3. Transfer the contents of HL to the stack pointer
D. XCHG 4. Transfer the contents of HL to the program counter
Code:
A B C D
(a) 3 4 1 2
(b) 3 4 2 1
(c) 4 3 2 1
(d) 4 3 1 2
IES(EE,04)
Q.46 An example of 8085-instruction that uses direct addressing is
(a) RLC (b) STA
(c) RRC (d) CMA
IES(EE,10)
Q.47 Match List-I (Instructions) with List-II (Application) and select the correct answer using the codes given
below the lists:
List-I List-II
A. SIM 1. 16-bit addition
B. DAD 2. Initializing the stack pointer
C. DAA 3. Serial output data
D. SPHL 4. Checking the current interrupt mask settings
5. BCD addition
Code:
A B C D
(a) 5 4 2 1
(b) 3 1 5 2
(c) 5 1 2 4
(d) 3 4 5 1
IES(EE,04)
Q.48 Consider the following set of instruction:
STC
CMC
MOV A, B
RAL
MOV B, A
This set of instructions
(a) doubles the number in register by B (b) divides the number in register by 2
(c) multiplies B by A (d) adds A and B
IES(EE,97)
Q.49 An RRC instruction in 8085 microprocessor instruction will affect
(a) CY, S, flag (b) CY flag
(c) S flag (d) Z flag
IES(EE,98)
Q.50 In a 8085 microprocessor, the following sequence of instructions is executed :
STC
CMC
MOV A,B
RAL
MOV B,A
After the last instruction, the output will
(a) rotate the contents of the accumulator and store it in B
(b) get the contents of B register into accumulator and rotate it to left by one bit
(c) double contents of B register
(d) manipulate carry in A and B
IES(EE,98)
Q.51 Consider the following Assembly Language program :
MVI A, 30 H
ADI 30 H
XRA A
POP H
After the execution of the above program the contents of the Accumulator will be
(a) 30 H (b) 60 H
(c) 00 H (d) contents of Stack
IES(EE,98)
Q.52 In 8085 microprocessor whenever the POP H instruction is executed
(a) data bytes in the HL pair are stored in the stack
(b) two data bytes at the top of the stack are transferred to the HL pair
(c) two data bytes at the top of the stack are transferred to the PC
(d) two data bytes from the HL registers that were previously stored on the stack are transferred back to the
HL pair
IES(EE,99)
Q.53 Which one of the following is a correct statement in connection with commands of CMP and CPI?
(a) CMP takes less number of m/c cycles compared to CPI
(b) CMP takes more number of m/c cycles compared to CPI
(c) Both CMP and CPI take the same number of m/c cycles
(d) CMP takes either less or the same number of m/c cycles as compared to CPI
IES(EE,99)
Q.54 When RET instruction is executed by any subroutine then
(a) the top of the stack will be popped out and assigned to the PC
(b) without any operation, the calling program would resume from instruction immediately following the
call instruction
(c) the PC will be incremented after the execution of the instruction
(d) without any operation, the calling program would resume from instruction immediately following the
call instruction, and also the PC will be incremented after the execution of the instruction
IES(EE,93)
Q.55 Consider the following set of 8085 instructions used to read a byte of data from the output of an ADC. The
byte represents digital equivalent of analog input voltage Vin applied to ADC when is asserted.
ADC : EQU 30H
GETADC : IN ADC
RET
When RET is executed.
1. Op-code of IN is fetched 2. Port address 30 H is decoded
3. Op-code of IN is decoded 4. I/O read operation is performed
The correct sequence of these operations is
(a) 3, 1, 4, 2 (b) 1, 3, 2, 4
(c) 1, 3, 4, 2 (d) 3, 1, 2, 4
IES(EE,01)
Q.56 Which logical operation is performed by ALU of 8085 to complement a number ?
(a) AND (b) NOT
(c) OR (d) EXCLUSIVE OR
IES(EE,02)
Q.57 Which one of the following functions is performed by the 8085 instruction MOV H, C?
(a) Moves the contents of H register to C register
(b) Moves the contents of C register to H register
(c) Moves the contents of C register to HL pair
(d) Moves the contents of HL pair to C register
IES(EE,02)
Q.58 After an arithmetic operation, the flag register of a 8085 microprocessor has the following look:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 X 1 X 0 X 1
The arithmetic operation has resulted in
(a) A carry and an odd parity number having 1 as the MSB
(b) Zero and the auxiliary carry flag being set
(c) A number with even parity and 1 as the MSB
(d) A number with odd parity and 0 as the MSB
IES(EE,03)
Q.59 Examine the following instruction to be executed by a 8085 microprocessor. The input port has an address
of 01H and has a data 05H to input:
IN 01
ANI 80
After execution of the two instructions the following flag portions may occur:
1. Zero flag is set 2. Zero flag is reset
3. Carry flag is cleared 4. Auxiliary carry flag is set
Select the correct answer using the codes given below:
(a) 1 and 3 (b) 2,3 and 4
(c) 3 and 4 (d) 1,3 and 4
IES(EE,03)
Q.60 How many and which types of machine cycles are needed to execute PUSH PSW by an Intel 8085 A
microprocessor?
(a) 2, Fetch and Memory write
(b) 3, Fetch and 2 Memory write
(c) 3, Fetch and 2 Memory read
(d) 3, Fetch, Memory read and Memory write
IES(EE,03)
Q.61 If the accumulator of an Intel 8085 A microprocessor contains 37 H and the previous operation has set the
carry flag, the instruction ACI 56 H will result in
(a) 8EH (b) 94H
(c) 7EH (d) 84H
IES(EE,03)
Q.62 Which one of the following 8085 assembly language instructions does not affect the contents of the
accumulator?
(a) CMA (b) CMP B
(c) DAA (d) ADD B
IES(EE,04)
Q.63 The contents of memory locations 2000 H, 2001 H and 2002 H are AAH, BBH and CCH respectively. What
are the contents of H and L registers after executing the following instructions in sequence?
LXI H, 2001 H
LHLD 2001 H
Select the correct answer using the codes given below :
(a) Contents of H and L registers are 20 H and 01H, respectively.
(b) Contents of H and L registers are AAH and BBH, respectively.
(c) Contents of H and L registers are ACH and DBH, respectively
(d) Contents of H and L registers are CCH and BBH, respectively.
IES(EE,06)
Q.64 In 8085, the DAA instructions is used for
(a) Direct Address Accumulator (b) Double Add Accumulator
(c) Decimal Adjust Accumulator (d) Direct Access Accumulator
IES(EE,06)
Q.65 Consider the following statements about register indirect addressing :
1. It helps in writing code that executes faster.
2. It helps in writing compact code .
3. It allows reuse of memory CPU data transfer instruction.
4. It is essential for stack operations.
Which of the statements given above are correct ?
(a) 1,3 and 4 (b) 1,2 and 4
(c) 2,3 and 4 (d) 1,2 and 3
IES(EE,05)
Q.66 Consider the following 8085 instructions :
ANA A, ORAA, XRAA, SUBA, CMPA.
Now, consider the following statements :
1. All are arithmetic and logic instructions.
2. All cause the accumulator to be cleared irrespective of its original contents.
3. All reset the carry flag.
4. All of them are 1-byte instructions.
Which of the statements given above is/are correct ?
(a) 1,2,3 and 4 (b) 2 only
(c) 1,2 and 4 (d) 1,3 and 4
IES(EE,05)
Q.67 INR instruction of 8085 does not affect carry flag. Which of the following is correct about INR instruction ?
(a) Overflow can not be detected
(b) Overflow can be detected
(c) If a program requires overflow to be detected, ADD instruction should be used instead of INR
(d) It can be used to increases the contents of the BC register pair
IES(EE,05)
Q.68 What are the number of machine cycles n, and the types of machine cycles carried out for PUSH B ?
(a) n = 2, fetch and memory write (b) n = 3, fetch and 2 memory write
(c) n = 3, fetch, memory write and read (d) n = 3, fetch and 2 memory read
IES(E&T,05)
Q.69 Consider the following instructions of 8085 µP:
1. MOV M, A 2. ADC
3. MVI A, FF 4. CMP M
Which of these cause change in the status of flag(s)?
(a) 1 and 2 (b) 1,2 and 3
(c) 3 and 4 (d) 2 and 4
IES(E&T,02)
Q.70 Assertion (A): A subroutine is a program written separately from the main program to perform a function
that occurs repeatedly in the main program.
Reason (R) : A subroutine can be call by a CALL instruction.
(a) Both (A) and (R) are individually true and (R) is the correct explanation of (A).
(b) Both (A) and (R) are individually true but (R) is not the correct explanation of (A).
(c) (A) is true but (R) is false
(d) (A) is false but (R) is true.
IES(EE,07)
Q.71 On execution of the following segment of instructions in sequence
MVI A, 91H
XRI 91H
Which one of the following is correct ?
(a) Content of accumulator is 00H. Carry, Auxiliary Carry and Zero flag set to 0, 1 and 0, respectively
(b) Content of accumulator is 91HCarry, Auxiliary Carry and Zero flag set to 0, 0 and 1, respectively
(c) Content of accumulator is 00 H, Carry , Auxiliary Carry and Zero flag set to 0, 0 and 1, respectively
(d) Content of accumulator is 91H. Carry, Auxiliary Carry, Auxiliary Carry and Zero flag set to 0, 1 and 0,
respectively
IES(EE,07)
Q.72 If the HLT instruction of an Intel 8085A microprocessor is executed
(a) The microprocessor is disconnected from the system bus till the RESET is pressed
(b) The microprocessor halts the execution of the program and returns to the monitor
(c) The microprocessor enters into a HALT state and the buses are tri-stated
(d) The microprocessor reloads the program counter from the locations 0024 H and 0025 H
IES(EE,08)
Q.73 Match List-I(Feature of instruction) with List-II(Instruction) and select the correct answer using the code
given below the Lists:
List-I List-II
A. Maskable interrupt 1. RST 5.5
B. Signal 2. XTHL
C. Instruction 3. SID
D. Memory location 002C H 4. RST 6.5
Code :
A B C D
(a) 4 1 2 3
(b) 2 3 4 1
(c) 4 3 2 1
(d) 2 1 4 3
IES(EE,08)
Q.74 What is the number of machine cycles in the instruction LDA 2000 H that consists of thirteen T-states?
(a) 2 (b) 3
(c) 4 (d) 5
IES(EE,08)
Q.75 The addressing mode used in the instruction JMP F347 H in case of an Intel 8085 A microprocessor is which
one of the following ?
(a) Direct (b) Register-indirect
IES(EE,08)
Q.76 Which one is the indirect addressing mode in the following instructions ?
(a) LXI H 2050 H (b) MOV A, B
(c) LDAX B (d) LDA 2050 H
IES(EE,08)
Q.77 Carry flag is not affected after the execution of
(a) ADD B (b) SBB B
(c) INR B (d) ORA B
IES(EE,08)
Q.78 Match List- I with List-II and select the correct answer using the code given below the lists :
List -I List-II
A. Immediate addressing 1. LDA 30 FF
B. Implied addressing 2. MOV A,B
C. Register addressing 3. LXI H,2050
D. Direct addressing 4. RRC
Code :
A B C D
(a) 3 4 2 1
(b) 2 1 3 4
(c) 3 1 2 4
(d) 2 4 3 1
IES (E&T,08)
Q.79 If 8085 adds 87 H and 79 H ,then
(a) both CARRY and ZERO flags will be set to 0
(b) CARRY flag will be set to 0, ZERO flag to 1
(c) CARRY flag will be set to 1, ZERO flag to 0
(d) both CARRY and ZERO flags will be set to 1
IES (E&T,08)
Q.80 On the 8085, which of the following machine cycles are not used in the CALL instruction ?
1. Instruction Fetch 2. I/O
3. Memory Read 4. Memory Write
Select the correct answer using the code given below:
(a) 2 only (b) 1 and 4
(c) 2,3 and 4 (d) None of the above
IES (E&T,08)
Q.81 The contents of accumulator in an 8085 microprocessor are altered after the execution of the instruction ?
(a) CMP C (b) CPI 3A
(c) ANI 5C (d) ORAA
IES(E&T,02)
Q.82 In an 8085 microprocessor after execution of XRA A instruction
(a) the carry flag is set
(b) the accumulator contains FFH

(c) the content of accumulator is shifted by one
(d) the zero flag is set
IES(E&T,02)
Q.83 Consider of the following instructions of 8085 µP
1. MOV M, A 2 . ADD C
3 . MVI A, FF 4 . CMP M
Which of these cause change in the status of flag(s) ?
(a) 1 and 2 (b) 1,2 and 3
(c) 3 and 4 (d) 2 and 4
IES(E&T,02)
Q.84 Which one of the following addressing technique is not used in 8085 microprocessor ?
(a) Register (b) Immediate
(c) Register indirect (d) Relative
IES (EE,09)
Q.85 When the operand required for an instruction is stored inside the processor, then what this addressing mode
is called ?
IES (EE,09)
Q.86 What is the correct 8085 assembly language instruction that stores the contents of L and H registers into the
memory locations 1080 H and 1081 H respectively?
(a) SPHL 1080H (b) SHLD 1080 H
(c) STAX 1080 H (d) SPHL 1081 H
IES (EE,09)
Q.87 An 8085 microprocessor is executing the programme as follows :
MVI A, 20 H
MVI B, 10 H
BACK : NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed ?
(a) 4 (b) 3
(c) 2 (d) 1
IES (EE,09)
Q.88 The stack pointer of an 8085 microprocessor is ABCD H. At the end of execution of the sequence of
instructions, what will be the content of the stack
pointer ?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
(a) ABCB H (c) ABC9 H
(b) ABCAH (d) ABC8 H
IES (EE,09)
Q.89 For which one of the following the instruction XRA A in 8085 microprocessor can be used?
(a) Set the carry flag
(b) Set the zero flag
(c) Reset the carry flag and clear the accumulator
(d) Transfer FFH to the accumulator
IES (EE,09)
Q.90 An output device is interfaced with an 8085 microprocessor as memory-mapped I/O. The address of the
devices is 1000 H. In order to output data from the accumulator to the device, what will be the sequence of
instructions ?
(a) LXI H, 1000H (b) LXI H, 1000H
MOV A, M MOV M, A
(c) LHLD 1000H (d) LHLD 1000H
MOV A, M MOV M, A
IES (EE,09)
Q.91 Which stack is used in 8085 microprocessors ?
(a) FIFO (b) FILO
(c) LIFO (d) LILO
IES (EE,09)
Q.92 In an instruction of 8085 microprocessor, how many bytes are present ?
(a) One or two (b) One, two or three
(c) One only (d) Two or three
IES (EE,09)
Q.93 Match List-I (Instruction code) with List-II (Addressing mode) and select the correct answer using the code
given below the Lists :
List-I List-II
A. JMP 2021 H 1. Direct addressing
B. LDAX B 2. Immediate addressing
C. IN 10H 3. Register Indirect addressing
D. RLC 4. Implicit addressing
Code :
A B C D
(a) 4 3 1 2
(b) 2 3 1 4
(c) 4 1 3 2
(d) 2 1 3 4
IES (EE,09)
Q.94 Which one of the following addressing modes is used in the instruction PUSH B ?
(c) Register indirect (d) Immediate
IES (E&T,09)
Q.95 Consider the following instruction of 8085 microprocessor :
1. MOV B, C
2. STA address
3. ORI byte
The correct sequence in the decreasing order of their respective memory space requirement is :
(a) 3, 2 and 1 (b) 1, 3 and 2
(c) 1, 2 and 3 (d) 2, 3 and 1
IES(E&T,10)
Q.96 If the CALL instruction of 8085 in the main program is conditional then RETURN instruction in the
subroutine can be :
(a) Conditional (b) Conditional or unconditional
(c) Can be determined by LDA instruction (d) Unconditional
IES(E&T,10)
Q.97 In the following 8085 program how many times (decimal) is the DCR C executed ?
MVI C, 78 H
LOOP: DCR C
JNZ LOOP
HLT
(a) 119 (b) 120
(c) 78 (d) 77
IES(E&T,10)
Q.98 A single instruction to clear the lower four bits of the accumulator in 8085 assembly language is :
(a) XRI 0FH (b) ANI F0H
(c) XRI F0H (d) ANI 0FH
IES(E&T,10)
Q.99 Which of the following instructions copies a byte of data into the accumulator from the memory address
given in the instruction ?
(a) LDA address (b) LDAX B
(c) LHLD address (d) STA address
IES(E&T,10)
Q.100 LXI SP, 7FFFH
MVI A, 25H
XRI 02H
PUSH PSW
POP H
MOV A, L
ORI 10H
HLT
What are the contents of A, H, L, SP? and PSW registers after executing the above set fo instructions?
Assume undefined flags always remain cleared.
(a) 10H, 25H, 00H, 7FFFH, 00H respectively
(b) 14H, 27H, 04H, 7FFFH, 04H respectively
(c) 14H, 25H, 00H, 7FFFH, 04H respectively
(d) 10H, 27H, 04H, 7FFFH, 00H respectively
IES (EE, 10)
Q.101 MVI A, AAH
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the above set of instructions in sequence ?
(a) AAH and 00H (b) FFH and 66H
(c) 00H and 54H (d) 00H and 00H
IES (EE, 10)
Q.102 The field, which is never present in an assembly language statement, is
(a) Opcode (b) Operand
(c) Continue (d) Comment
IES (EE, 10)
Q.103 The opcode for the instruction “Add Immediately to Accumulator with carry” in 8085 microprocessor is
(a) ADI (b) ACI
(c) ADC (d) ADD
IES (EE,10)
Q.104 In 8085 microprocessor, how many interrupts are maskable
(a) Two (b) Three
(c) Four (d) Five
IES(2004/EE/1A(c)/2)
Q.105 The __________ instruction allows control to transfer to a subroutine, which when complete, issue the
___________ instruction to return control to the main program
(a) CALL, JMP (b) CALL, RET
(c) CALL, RST1 (d) EI, DI
IES(2006/EE/1A(g)/2)
Q.106 A single instruction to clear the lower four bits of the accumulator in 8085 microprocessor is
(a) XRI 0FH (b) ANI F0H
(c) XRI F0H (d) ANI 0FH
IES(2009/EE/1f/2)
Q.107 The addressing mode used in the instruction STAX B is
(a) direct (b) immediate
(c) implicit (d) indirect
IES(2008/EE/1A(e)/2)
Q.108 Which one of the following statements is NOT correct ?
(a) CMP A is a single byte instruction and CMA is not an instruction
(b) The instruction SUB A sets the zero flag
(c) Bus is a group of wires
(d) Instruction INR C does not affect carry flag
IES(EE,11)
Q.109 To execute the following instructions
(i) LDA 2100 H (ii) LXI H, 2100 H
by an Intel 8085 microprocessor the numbers of memory cycles required are :
(a) 2 for (i) and 2 for (ii) (b) 4 for (i) and 2 for (ii)
(c) 3 for (i) and 3 for (ii) (d) 4 for (i) and 3 for (ii)
IES(EE,11)
Q.110 In 8085 microprocessor, during PUSH PSW operation, stack pointer is :
(a) Decremented by one (b) Decremented by two
(c) Incremented by one (d) Incremented by two
IES(EE,11)
Q.111 Assertion (A) : STACK is used temporarily to store the data in RAM locations specified by the programmer
in main program.
Reason (R) : PUSH and POP instructions are used to send or retrieve the data from the STACK.
(a) Both A and R are individually true and R is the correct explanation of A
(b) Both A and R are individually true but R is NOT the correct explanation of A
(c) A is true but R is false
(d) A is false but R is true
IES(EE,11)
Q.112 If 8085 microprocessor adds 87 H and 79 H, the flags will be :
(a) S = 1, Z = 0, AC = 0 and Cy = 1
(b) S = 0, Z = 0, AC = 1 and Cy = 0
(c) S = 1, Z = 1, AC = 1 and Cy = 1
(d) S = 0, Z = 1, AC = 1 and Cy = 1
IES(E&T,11)
Q.113 The following instruction copies a byte of data from the accumulator into the memory address given in the
instruction:
(a) STA address (b) LDAX B
(c) LHLD address (d) LDA address
IES(EE,12)
Q.114 The instruction that exchanges top of stack with HL pair is
(a) XTHL (b) SPHL
(c) PUSH H (d) POP H
IES(EE, 12)
Q.115 Statement (I) : 2’s complement arithmetic is preferred in digital computers.
Statement (II): The hardware required to obtain the 2’s complement of a number, is simple.
(a) Both statement (I) and Statement (II) are individually true and statement (II) is the correct explanation
of statement (I)
(b) Both statement (I) and Statement (II) are individually true and statement (II) is not the correct
explanation of statement (I)
(c) Statement (I) is true but Statement (II) is false
(d) Statement (I) is false but Statement (II) is true.
IES(EE, 12)
Q.116 The instruction PCHL in 8085 is used to
(a) Load PC with contents of HL
(b) Load HL with contents of memory location pointed by PC
(c) Load HL with contents of PC
(d) Load PC with the contents of memory location pointed by HL pair
IES(EE, 12)
Q.117 A small code of 8085 as given below, is executed
MVI A, 7 FH
ORA A
CPI A2H
The contents of the accumulator and flags after execution are
(a) A = DD, S = 1, Z = 0, CY = 0
(b) A = 7F, S = 1, Z = 0, CY = 1
(c) A = DD, S = 0, Z = 1, CY = 0
(d) A = 7F, S = 0, Z = 1, CY = 1
IES(E&T,12)
Q.118 Following program finds absolute value of N:
MVI A, N
ORA A
JM ONE
OUT 01H
HLT
ONE : P
Q
OUT 01H
HLT
The instructions of P and Q must be
(a) CMA and ADI 0H
(b) CMC and ADI 0H
(c) INR A and CMC
(d) INR A and CMA
IES(E&T,12)
Q.119 An Intel 8085 processor is executing the program given below :
MVI A, 10H
MVI B, 10H
BACK : NOP
ADD B
RLC
JNC BACK
HLT
Time number of times that the operation NOP will be executed is
(a) 1 (b) 2
(c) 3 (d) 4
IES(E&T,12)
Q.120 Match List I with List II and select the correct answer using the code given below the lists:
List-I List-II
A. Immediate addressing 1. LDA 30FF
B. Implicit addressing 2. MOV A, B
C. Register addressing 3. LXI H, 2050
Code :
A B C D
(a) 3 4 2 1
(b) 1 4 2 3
(c) 3 2 4 1
(d) 1 2 4 3
IES(E&T,12)
Q.121 While executing a program, 8085 microprocessor completes fetching of instruction JMP 2050 H stored at
address 2057 H. The contents of the program counter after fetching the instruction would be
(a) 2050 H (b) 2057 H
(c) 205A H (d) 2051 H
IES(E&T,12)
Q.122 For the 8085 assembly language program given below, the content of the accumulator after the execution
of the program is
3000 MVI A, 45H
3002 MOV B, A
3003 STC
3004 CMC
3005 RAR
3006 XRA B
3007 HLT
(a) 00 H (b) 45 H
(c) 67 H (d) E7 H
IES(E&T,12)
Q.123 The 8085 microprocessor instructions with required number of T states are given below. Which pair is
correctly matched?
(a) STAX : 8T-states (b) SPHL : 6 T-states
(c) SIM : 7 T-states (d) STA : 12 T-states
IES(E&T,12)
Q.124 The crystal frequency of 8085 microprocessor is 6 MHz. The time required to execute instruction XTHL
over this microprocessor is
(a) 5.33 µsec (b) 10.67 µsec
(c) 4.33 µsec (d) 8.67 µsec
IES(E&T,12)
Q.125 In 8085 microprocessor, after the execution of RST 5 instruction, the program control shifts to
(a) 0030 H (b) 0005 H
(c) 0028 H (d) 0024 H
IES(E&T,12)
Q.126 With reference to 8085 microprocessor, which of the following statements are correct ?
1. The DAD instruction adds the contents of the specified register pair to the contents of the DE register
pair.
2. The program counter is an instruction pointer.
3. Whenever an instruction uses the HL pointer, the addressing is called indirect addressing.
4. HL register pair is also called data pointer.
(a) 1 and 2 only (b) 1, 2 and 3
(c) 2, 3 and 4 (d) 2 and 4 only
IES(E&T,13)
Q.127 On the 8085, which of the following machine cycles are not used in the CALL instruction ?
1. Instruction fetch 2. I/O
3. Memory Read 4. Memory Write
(a) 2 only (b) 1 and 4 only
(c) 2, 3 and 4 (d) 1, 2, 3 and 4
IES(E&T,13)
Q.128 The stack pointer will be affected by instructions :
1. PUSH PSW
2. CALL ADDR
3. XTHL
4. RST n
(a) 1, 2, 3 and 4 (b) 1 and 3 only
(c) 1, 2 and 4 only (d) 2, 3 and 4 only
IES(E&T,13)
Q.129 Which one of the following instructions uses implied addressing mode ?
(a) CMA (b) JMP
(c) ADC (d) SBB
IES(E&T,13)
Q.130 The 8085 programming manual says that it takes seven T states to fetch and execute the MOV instruction.
If the system clock has a frequency of 2.5 MHz, how long is an instruction cycle ?
(a) 2.8 s (b) 2.5 ns
(c) 2.8 ns (d) 2.8 µs
IES(EE,13)
Q.131 What is the content of accumulator 8085 µP after the execution of XRI F0H instruction ?
(a) Only the upper nibble of accumulator is complemented
(b) Only the lower nibble is complemented
(c) Only the upper nibble is reset to zero
(d) Only the lower nibble is reset to zero
IES(EE,13)
Q.132 A software delay subroutine is written as given below :
DELAY : MVI H, 255 D
MVI L, 255 D
LOOP : DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR L instruction will be executed ?
(a) 255 (b) 510
(c) 65025 (d) 65279
IES(EE,13)
Q.133 The content of Accumulator are 70 H. Initially all flags are zero. What will be values of Cy and S after
executing instruction RLC ?
(a) Cy = 0 and S = 0 (b) Cy = 1 and S = 1
(c) Cy = 1 and S = 0 (d) Cy = 0 and S = 1
IES(EE,13)
Q.134 The difference between 8085 instructions RST n and PCHL is :
(a) RST n is equivalent to a sub-routing call while PCHL is equivalent to unconditional branch.
(b) RST n uses direct addressing while PCHL uses register indirect addressing
(c) RST n is a software interrupt while PCHL simulates a hardware interrupt
(d) RST n resets the processor while PCHL restarts the processor
IES(EE,13)
Q.135 The following program starts at location 0100 H
LXI, SP, 00FF
LXI H, 0701
MVI A, 20 H
SUB M
The content of accumulator when the program the program counter reaches 0107 H is:
(a) 20 H (b) 02 H
(c) 00 H (d) FF H
IES(EE,13)
Q.136 Find the content of the accumulator after the execution of the following program :
MVI A, F0 H
ORI FF H
XRI F0 H
(a) 00 H (b) F0H
(c) 0FH (d) FFH
IES(EE,13)
Q.137 It is desired to multiply the numbers 0A H by 0B H and store the result in the accumulator. The numbers are
available in registers B and C respectively. A part of the 8085 program for this purpose is given below :
MVI A, 00H
Loop: .........................
.........................
.........................
HLT END
The sequence of instruction to complete the program would be :
(a) JNZ LOOP ; ADD B ; DCR C (b) ADD B; JNZ LOOP; DCR C
(c) DCR C ; JNZ LOOP ; ADD B (d) ADD B; DCR C; JNZ LOOP
IES(E&T,13)
Q.138 Assume that the Accumulator and the register C of 8085 microprocessor contain respectively F0 H and 0F
H initially. What will be the content of Accumulator after execution of instruction ADD C?
(a) 00 H (b) FF H
(c) EF H (d) FE H
IES(EE,13)
Q.139 The following sequence of instructions is executed by an 8085 microprocessor:
1000 LXI SP 27FF
1003 CALL 1006
1006 POP H
The contents of the stack pointer (SP) and the HL register pair on completion of execution of these
instructions are
(a) SP = 27 FF, HL = 1003 (b) SP = 27 FD, HL = 1003
(c) SP = 27 FF, HL = 1006 (d) SP = 27 FD, HL = 1006
IES(E&T,14)
Q.140 Statement I: Branch instructions in a micro-processor are used to change the sequence of program.
Statement II: All logical instructions are branch instructions.
(a) Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation
of Statement (I)
(b) Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation
of Statement (I)
(c) Statement (I) is true but Statement (II) is false
(d) Statement (I) is false but Statement (II) is true
IES(EE,14)
Q.141 With reference to 8085 micro-processor, which of the following statements are correct?
1. IN is 1-byte instruction
2. OUT is 2-byte instruction
3. STA is 3-byte instruction
(a) 1 and 2 only (b) 2 and 3 only
(c) 1 and 3 only (d) 1, 2 and 3
IES(EE,14)
Q.142 In 8085 micro-processor, which mode of addressing does the instruction CMP M use?
(a) Direct addressing (b) Register addressing
(c) Indirect addressing (d) Immediate addressing
IES(EE,14)
Q.143 Which of the following 8085 instruction will require maximum T-states for execution?
(a) XRI byte (b) STA address
(c) CALL address (d) JMP address
IES(EE,14)
Q.144 How many machine cycles are required by STA instruction?
(a) 2 (b) 3
(c) 4 (d) 5
IES(EE,14)
Q.145 Which of the following instructions is closest match to the instruction POP PC?
(a) RET (b) PCHL
(c) POP PSW (d) DAD SP
IES(EE,14)
Q.146 Which of the following data transfers is not possible in micro-processor?
(a) Memory to accumulator (b) Accumulator to memory
(c) Memory to memory (d) I/O device to accumulator
IES(EE,14)
Q.147 A ‘DAD H’ instruction is the same as shifting each bit by one position to the
(a) Left
(b) Right
(c) Left with a zero inserted in LSB position
(d) Right with a zero inserted in LSB position
IES(EE,15)
Q.148 Among the given instructions, the one which affects maximum number of flags is
(a) RAL (b) POP PSW
(c) XRA A (d) DCR A
IES(EE,15)
Q.149 Each instruction in an assembly language program has the following fields.
1. Label field 2. Mnemonic field
3. Operand field 4. Comment field
What is the correct sequence of these fields?
(a) 1, 2, 3 and 4 (b) 2, 1, 4 and 3
(c) 1, 3, 2 and 4 (d) 2, 4, 1 and 3
IES(EE,15)
Q.150 What will be the contents of DE and HL register pairs respectively after the execution of the following
instructions?
LXI H, 2500H
LXI D, 0200H
DAD D
XCHG
(a) 0200H, 2500H (b) 0200H, 2700H
(c) 2500H, 0200H (d) 2700H, 0200H
IES(EE,15)
Q.151 XCHG instruction of 8085 exchanges the content of
(a) Top of stack with contents of register pair (b) BC and DE register pairs
(c) HL and DE register pairs (d) None of the above
IES(EE,15)
Q.152 The instruction JNC 16-bit refers to jump to 16-bit address if
(a) Sign flag is set (b) CY flag is reset
(c) Zero flag is set (d) Parity flag is reset
IES(EE,16)
Q.153 Which one of the following statements is correct regarding the instruction CMP A?
(a) Compare accumulator with register A (b) Compare accumulator with memory
(c) Compare accumulator with register H (d) This instruction does not exist
IES(EE,16)
Q.154 The instruction RET executes with the following series of machine cycle
(a) Fetch, read, write (b) Fetch, write, write
(c) Fetch, read, read (d) Fetch, read
IES(EE,16)
Q.155 Statement I :
Stack works on the principle of LIFO
Statement II :
Stack pointer contains address of the top of the stack.
(a) Both statements I and statement II are individually true and statement II is the correct explanation of
statement I
(b) Both statement I and statement II are individually true but statement II is not the correct explanation of
statement I
(c) Statements I is true but statement II is false
(d) Statement I is false but statement II is true
IES(E&T,2018)
Q.156 Statement I :
I/O devices can be accessed using IN and OUT instructions.
Statement II :
Arithmetic and logic operations can be directly performed with I/O data.
statement I
statement I
IES(E&T,2018)
Q.157 Statement I :
On executing the HLT instruction, the microprocessor enters into a half state and all the buses are tri-stated.
Statement II :
On executing the HLT instruction, the microprocessor is disconnected from the system bus till the reset is
pressed.
statement I
statement I
IES(E&T,2018)
Q.158 Statement I :
Stack is organized as 8-bit storage in the microprocessor.
Statement II :
Stack is a set of memory locations in R/W memory reserved for storing information temporarily during the
execution of a program.
statement I
statement I
IES(E&T,2018)
Q.159 In the following 8085 assembly language program, assume that the carry flag is initially reset. What is the
content of the accumulator after the execution of the program?
MVI A, 04H
RRC
MOV B, A
RLC
RLC
ADD B
RCC
(a) 02H (b) 05H
(c) 15H (d) 25H
IES(E&T,2018)
Q.160 A 2-byte instruction which accepts the data from the input port- specified in the second byte and loads into
the accumulator is
(a) OUT <8-bit port address> (b) IN <8-bit port address>
(c) OUT R <8-bit port address> (d) IN R <8-bit port address
IES (E&T, 2019)
Q.161 Which one of the following types of ‘ instructions will be used to copy from the source to the destination
location?
(a) Arithmetic instructions (b) Data transfer instructions
(c) Logical instructions (d) Machine control instructions
IES (E&T, 2019)
Q.162 Which of the following instructions of 8085 are the examples of implied addressing ?
1. CMA 2. IN byte
3. RET
(a) 1, 2 and 3 (b) 1 and 2 only
(c) 2 and 3 only (d) 1 and 3 only
IES (EE, 2019)
Q.163 The contents of the accumulator and register C are 2EH and 6CH respectively. The instruction ADD C is
used. The values of AC and P flags are
(a) 0 and 0 (b) 1 and 1
(c) 0 and 1 (d) 1 and 0
IES (EE, 2019)
Q.164 PUSH and POP operations are performed by
(a) Program counter register (b) General purpose register
(c) Stack pointer register (d) Link register
MISCELLANEOUS QUESTIONS
Q.165 The advantages of immediate addressing is

(a) to decode the operand easily
(b) to execute the instruction immediately
(c) not to fetch operand from memory
(d) to allow both positive and negative operands
IAS(2001)
Q.166 The addressing mode in which the machine language instruction itself includes the data is called
(a) Immediate (b) Indexed
(c) Indirect (d) Direct
IAS(2002)
Q.167 Match List I with List II and select the correct answer using the codes given below the lists:
List-I List-II
A. Immediate addressing 1. LDA 3000 H
B. Implied addressing 2. MOV A, B
C. Register addressing 3. LXI H, 2050H
Code:
A B C D
(a) 3 2 1 4
(b) 3 4 2 1
(c) 3 2 4 1
(d) 2 3 1 4
IAS(1994)
Q.168 Match List - I (Character) with List - II (Interpretation) and select the correct answer using the code given
below the lists:
List-I List-II
A. Colon (:) 1. Separates operation and operand fields
B. Blank ( ) 2. Separates operands
C. Comma (,) 3. Beginning of comment field
D. Semicolon (;) 4. End of label field
Code:
A B C D
(a) 2 3 4 1
(b) 4 1 2 3
(c) 2 1 4 3
(d) 4 3 2 1
IAS(2006)
Q.169 The number of flags affected when a data-transfer instruction is executed by 8085 is
(a) 0 (b) 1
(c) 3 (d) 5
IAS(2004)
Q.170 In an 8085 microprocessor, the accumulator contents get altered by the instruction
(a) ANI 5CH (b) CMP C
(c) CPI 3AH (d) ORA A
IAS(2000)
Q.171 DAA is an instruction in the instruction set of many microprocessors. This instruction is used in a
microprocessor to perform
(a) Binary addition (b) BCD addition
(c) ASCII addition (d) Binary subtraction
IAS(2003)
Q.172 Which 8085 instruction uses the stack ?
(a) JMP (b) MOV
(c) RET (d) DCR A
UPPCS(2004)
Q.173 Which 8085 instruction does not affect the flags?
(a) INR A (b) INX B
(c) ORA C (d) DCR A
UPPCS(2004)
Q.174 Following instruction does not use the stack :
(a) CALL (b) JMP
(c) RET (d) None of these
UPPCS(2004)
Q.175 What is the effect of a DAD H instruction?
(a) To shift each bit one position to the right with a zero inserted in MSB position
(b) To shift each bit one position to the left with a zero inserted in LSB position
(c) To shift each bit one position to the right
(d) To shift each bit one position to the left.
IAS(2006)
Q.176 In order to complement the lower order nibble of the accumulator, one can use which one of the following ?
(a) ANI 0F H (b) XRI 0F H
(c) ORI 0F H (d) CMA
IAS(2008)
Q.177 Which one of the following statements is correct?
With a clock frequency of 3MHz, the execution time for the instruction “STA addr” of 8085 will be
(a) 4333 ns (b) 3975 ns
(c) 3115 ns (d) 3960 ns
IAS (2009)
Q.178 Consider the following :
The 16 bit register/register-pair which cannot be stored in stack using PUSH instruction is
1. HL 2. SP
3. PSW 4. PC
Select the correct answer using the code given below :
(a) 1 and 2 (b) 1 and 3
(c) 2 and 3 (d) 2 and 4
IAS (2009)
Q.179 Consider the following 8085 microprocessor program segment.
MVI A, 92H
ORA A
JP PORT1
XRA A
PORT1 : OUT F2H
HLT
After executing this program, the output at port F2H will be
(a) 00H (b) 50H
(c) 7FH (d) 92H
DRDO(EE,08)
Q.180 What is the addressing mode used in the instruction PUSH B ?
(c) Register indirect (d) Immediate
IAS (2009)
Q.181 Consider the following program for 8085
XRA A
LXI B, 0007H
LOOP : DCX B
JNZ LOOP
The loop will be executed
(a) 8 times (b) once
(c) 7 times (d) infinite times
ISRO (2009)
Q.182 The content of the memory location 2070 H after the execution of the following 8085 program is
LXI B, 2070H
MVI A, 8FH
MVI C, 68H
SUB C
ANI 0FH
STAX B
HLT
(a) 04 H (b) 07 H
(c) 09 H (d) 0F H
BSNL-JTO(TC,09)
Q.183 A 8085 microprocessor program uses all available Jump instructions, each only once. For this program, the
total memory (in Bytes) occupied by the Jump instructions is
(a) 30 (b) 27
(c) 24 (d) 18
BSNL-JTO(TC,09)
Q.184 In the register indirect addressing mode of 8085 microprocessor, data is stored
(a) at the address contained in the register pair
(b) in the register pair
(c) in the accumulator
(d) in a fixed location of the memory
DRDO(E&C,08)
Q.185 An arithmetic operation in the 8085 microprocessor sets the sign and parity flags. The contents of the
accumulator after the execution of the operation can be
(a) 1011 0100 (b) 0010 1101
(c) 1010 1101 (d) 0110 0111
BSNL-JTO(EE,09)
Q.186 An instruction of the 8085 microprocessor that requires both memory read and memory write machine
cycles is
(a) MVI M, 8F (b) LHLD 8088
(c) RST 1 (d) ADD M
BSNL-JTO(EE,09)
Q.187 After the execution of the following program in the 8085 microprocessor, the contents of the accumulator
are
Address Code Mnemonics
203A 3E 20 MVI A, 20H
203C 2A 3A 20 LHLD 203AH
203F 86 ADD M
2040 76 HLT
(a) 20H (b) 40H
(c) 5EH (d) 7CH
BSNL-JTO(EE,09)
Q.188 Before executing the following program, A, B, C and Flag registers of 8085 processor store the numbers a,
b, c and f, respectively
PUSH B
PUSH PSW
POP B
XRA A
MOV B,A
PUSH B
POP PSW
After execution of this program, A, B, C, and Flag registers will contain,
(a) 0,0, f, f (b) a, b, c, f
(c) a, b, a, b (d) 0, b, c, f
DRDO(E&T,05)
Q.189 In an 8085 microprocessor, the accumulator contents are AA H. After executing the instruction ‘CPI 99 H’
in the microprocessor,
(a) carry flag will be set but zero flag will be reset
(b) both carry and zero flags will be reset
(c) carry flag will be reset but zero flag will be set
(d) both carry and zero flags will be set
DRDO(EE,09)
ANSWERS AND EXPLANATIONS
Q.1 Ans (d)

LDA 2003 requires 13 T states and 4 machines cycles, out of which one is opcode fetch and two memory
read cycles for reading lower byte and higher byte of 16 bit operand and one memory read for reading 2003
memory location.
Q.2 Ans (a)
The instruction CMP B, compares the contents of B with contents of accumulator. The comparison is made
by subtracting the contents of B from the contents of A. Depending upon results of comparison various flags
are affected as under,
I. A < B CY = set and Z = reset
II. A = B CY = reset and Z = set
III. A > B CY = reset and Z = reset
Given, A < B, so Carry flag will be set and Zero flag will be reset.
Q.3 Ans (b)
(I) LDA 3000 H ; This instruction load the accumulator with contents of memory location
3000H. It needs 4 memory cycles out of which one is opcode fetch and 3
memory read cycles.
(II) LXI D, F0F1 H ; This instruction load the DE pair with 16 bit F0F1H. It needs 3 memory cycles
out of which one is opcode fetch and 2 memory read cycles.
Q.4 Ans (a)
LXI H, 9258H ; Loads HL pair with 16 bit data 9258H . So, H = 92H and L = 58H.
MOV A, M ; Moves contents of memory location, whose address is stored in HL pair, to
accumulator. So the contents of 9258H are moved to A.
CMA ; Complements the contents of A.
MOV M, A ; Moves the contents of A to memory location , whose address is stored in HL
pair. So, the contents of A are moved to 9258H.
The above program moves the contents of memory location 9258H. to accumulator and compliments it and
stores the result back to 9258H..
Q.5 Ans (b)
If the HLT instruction of an Intel 8085A microprocessor is executed the microprocessor enters into a HALT
state and the buses are tri-stated
Q.6 Ans (c)
ANI 5C : 8 bit data 5C is ANDed with contents of A and result is stored in A , so, contents
of accumulator get modified.
CMP C : This instruction compares the contents of register C with the contents of
accumulator but contents of A and C remains unchanged.
CPI 3A : This instruction compares the 8 bit data 3A with the contents of accumulator
but contents of A and C remains unchanged.
ORA A : Contents of A are ORed with contents of A itself and result is stored in A,
but result of operation is same as contents before execution of ORA A. So,
contents of accumulator remains unchanged.
Q.7 Ans (c)
Let contents of A are 60 H
XRA A : Performs XOR operation the contents of A and store result in A.
A ⊕ A : 01100000
01100000
00000000

⇒ A = 00H
Since the contents of A are 00H after execution of XRA A instruction so zero flag is set.
Note : XRA A instruction can be used to reset CY & AC flags and set Z flag.
Q.8 Ans (c)
I. SPHL : Copies the contents of HL pair to stack pointer. No operand is required
ininstruction. So the given instruction is incorrect.
II. SHLD 2050H : Store s the contents of HL pair directly on memory locations 2050H and
2051H . The contents of lower order register (i.e. L )are moved to lower
address (i.e. 2050 H ) and contents of higher order register(i.e. H) are moved
to higher address (i.e. 2051H)
III.STAX 2050H : Stores the contents of A directly at memory locations 2050H directly.
Q.9 Ans (a)
SUB may set or reset the CY flag and INX , CMA does not affect the any flag including CY flag. The
instruction ANA always reset the CY flag.
Q.10 Ans (d)
Given, Contents of PC = F000H
Contents of SP =2400H
CALL instruction requires five machine cycles. During the execution of CALL E000H, microprocessor
stores the address E000H in 16 bit temporary register WZ pair during second and third machine cycles of
CALL instruction. During fourth and fifth machine cycles processor saves contents of program counter (i.e.
address of next instruction, F003H) on top of stack. During the saving the contents of program counter the
stack pointer is decremented by one from 2400H to 23FFH and then higher order byte of PC i.e. E0H is
saved at 23FFH and stack pointer is again decremented by one to 23FEH & then lower byte of PC i.e. 03H
is saved at 23FEH . So, after execution of CALL E000H , the program counter contains F003H and stack
pointer contains 23FEH. And address E000H is placed by WZ pair on address line at the end of CALL
instruction. The program counter is then updated with contents WZ pair plus one. From the given options
option (d) is nearest answer but not correct.
Q.11 Ans (b)
I. DAA is an arithmetic instruction
II. LXI is a data movement instruction
III. RST is an interrupt instruction
IV. JMP is a program control instruction
Q.12 Ans.(a)
Facts about memory mapped I/O:
1. I/O devices are identified with 16-bit addresses just like a memory location.
2. I/O devices are accessed using same instructions which are used to access memory locations. IN and
OUT instructions are used to access I/O mapped I/O devices.
3. There can be maximum of 216 or 64 K memory mapped I/O devices which can be identified with 8085
microprocessor.
4. Arithmetic and logic operations can be directly performed with the I/O data in memory mapped I/O
devices. But in case of I/O mapped I/O devices data is first store in accumulator and only then arithmetic
or logical operation can be performed.
For transferring the contents of accumulator to a memory mapped device, connected at address 00F0 H,
following instructions can be used,
LXI H, 00F0H : Load the HL pair with 00F0H .
MOV M, A : Moves the contents of accumulator to the I/O device whose address is stored
in HL pair.
Q.13 Ans.(a)
The sequence of instructions to increment the contents of memory location whose address is available in
(D,E) register pair and store the result in same location is as under,
XCHG : Exchanges the contents of HL-pair with contents of DE-pair.
INR M : Increments the contents of memory location whose address is stored in HL
pair and store the result at same memory location.
Q.14 Ans.(b)
Line 1 : MVI A, B5H ; Moves B5 H to accumulator, A. So, A = B5 H
2 : MVI B, 0EH ; Moves 0E H to B. So, B = 05 H
3 : XRI 69H ; Contents of A are ExORed with 69H and result is stored in A.
A : 1011 0101
69H : 0110 1001
1101 1100 = DC H
So, A = DC H
4 : ADD B ; Adds contents of B to contents of A and result is stored in A.
A : 1101 1100
B : 0000 1110
1110 1010 = EA H
So, A = EA H
5 : ANI 9BH ; Contents of A are ANDed with 9BH and result is stored in A.
A : 1110 1010
9BH : 1001 1011
1000 1010 = 8A H
So, A = 8A H
6 : CPI 9FH ; Compares 9FH with contents of A. The contents of A remains unaffected
but status of result is reflected by flags.
A : 1000 1010
9F H : 1001 1111
1 1110 1011
7. STA 3010H ; Stores the contents of A at memory location 3010H.
8. HLT ; Halts the execution of program.
Thus, contents of A after execution of line 4 are EAH.
Q.15 Ans. (d)
XRA A ; The instruction XRA A performs ExOR operation on contents of A with
contents of A only and store the result in A. The instruction clears the contents
of A. So, after execution of XRA A the zero flag is set by the instruction, sign
flag is reset , parity flag is set, CY and AC flags are reset.
MVI B, F0 H ; Moves data F0 H to register B.
So, contents of B = F0 H
SUB B ; Subtracts the contents of B(i.e. F0H) from contents of A (i.e.00H)and store
the result in A.
A : 00000000
+ B : 11110000
1 00010000
⇒ A = 10H and CY = 1
Q.16 Ans. (d)
Addr. Instruction Mnemonic Comments
Code
1000H 3E 06 MVI A,06H ;
Moves data 06 H to register A. So, contents of A = 06H
1002H C6 70
Adds 70 H to contents of A.ADI 70H ;
A: 00000110
+ B : 01110000
0 01110110
So, A = 76H and CY = 0

1004H 32 07 10 STA 1007H ; Stores the contents of A(i.e. 76H) directly to memory location
1007H. So, the contents of 1007H becomes 76H. So, program
code AF H stored at 1007H is changed to 76 H which is code
of HLT statement.
1007H AF XRA A ; Since new contents of 1007H are 76 H which is code of HLT
statement so, the program execution comes to an Halt without
executing XRA A and contents of A remains 76 H.
1008H 76 HLT ; This instruction will not be executed as program execution has
already come to an Halt.
So, the contents of accumulator at the end of execution of above program are 76 H.
Q.17 Ans (c)
3000 MVI A, 45 H ; Moves 45 H to accumulator A. So, contents of A = 45 H
3002 MOV B, A ; Moves contents of A, ie. 45 H to B.
So contents of B = 45 H
3003 STC ; Set carry flag , CY =1
3004 CMC ; Compliment CY flag . So, CY=0
3005 RAR ; Rotates content of A to right through carry flag.
Before rotation:
Cy Before rotation
0 0 1 0 0 0 1 0 1

After rotation:
Cy After rotation

1 0 0 1 0 0 0 1 0
So, content of A = 22 H
3006 XRA B ; Performs XOR operation between contents of A & B and store the result in
accumulator.
A:0 01 0 0 01 0
B:0 1 0 0 0 1 0 1

A ⊕ B : 01 1 0 0 111
6 7
So, contents of A after execution of program are 67 H.
Q.18 Ans (d)
When a “CALL Addr” instruction is executed, the CPU carries out the following sequential operations
internally,
Step-I : C
ontents of Program counter are moved to on top of stack pointed by stack pointer.
Step-II : The stack pointer is incremented.
Step-III : The address Addr is moved to program counter.
Note : In 8085 the contents of SP are decremented automatically by two when contents are moved on top of stack
because the stack pointer in 8085 is initiated with high address and data storage begins from address lower
than the address stored in SP. But in the given question there is no such option.
Q.19 Ans. (c)
SUB1 : MVI A,00H ; M o v e s d a t a 0 0 H t o a c c u m u l a t o r , A . S o , c o n t e n t s o f
A = 00H
CALL SUB2 ; Calls the subroutine SUB2
SUB2 : INR A ; Increases the contents of A by one.
RET ; Returns to calling subroutine.
In the above program the instructions INR A is executed twice. Once by calling of SUB2 by Subroutine
SUB1 and once by subroutine SUB1 itself. So, the contents of accumulator are incremented twice.
Therefore, the contents of A after returning from subroutine SUB1 will be 02H.
Q.20 Ans. (d)
SBX : MVI A, 99 H ; Moves data 99H to accumulator A.
ADI 11H ; Adds 11 H to contents of A(i.e. 99H).
A : 10011001
+ 11H : 00010001
10101010
⇒ A = AA H and CY = 0
MOV C,A ; Moves contents of A to register C.
RET ; Returns to main program.
So, at the end of the program the contents of A are AA H.
Q.21 Ans(c)
Given contents of CY flag, CY = 0
MVI A,07H ; Moves data 07H to accumulator , A. So, A = 07H.
RLC ; Rotates contents of accumulator to left without carry flag.
Before rotation:
CY = 0

0 0 0 0 0 1 1 1
After rotation:
CY = 0

0 0 0 0 1 1 1 0
⇒ A = 0E Hand Cy = 0
MOV B,A ; Moves the contents of A(i.e. 0EH) to B . So B = 0EH.
Before rotation:
CY = 0

0 0 0 0 1 1 1 0
After rotation:
CY = 0

0 0 0 1 1 1 0 0
⇒ A = 1CHand Cy = 0
Before rotation:
CY = 0

0 0 0 1 1 1 0 0
After rotation:
CY = 0

0 0 1 1 1 0 0 0
⇒ A = 38Hand CY = 0
ADD B ; Adds the contents of B(i.e. 0EH) to the contents of A(i.e. 38H).
0EH : 00001110
+ 38H : 00111000
01000110
⇒ A = 46H and CY = 0
RRC ; Rotates contents of accumulator to right without carry flag.
Before rotation:
CY = 0

0 1 0 0 0 1 1 0
After rotation:
CY = 0

0 0 1 0 0 0 1 1
⇒ A = 23 Hand CY = 0
Q.22 Ans (c)
Let,
Disp = 1000 H
Lp = 2000 H
SUB = 5000 H
Main program :
:
:
LXI D, DISP
LP : CALL SUB
:
:
Subroutine:
POP H
DAD D
PUSH H
RET
Program Description :
The segment of main program given above first stores the 16 bit data (i.e. 1000 H) in DE pair and than call
the subroutine stored at add beginning with SUB (i.e. 5000 H).
In last two machine cycles of CALL instruction the processor saves the contents of PC on top of stack.
So, before transferring the control of execution to subroutine the processor saves the contents of program
counter (i.e. LP + 3) on top of stack.
In sub routine during last three instruction preceding the RET instruction, the processor first
copies the contents of top of stack (i.e. 4 + 3) in HL pair, then adds contents of DE pair
(i.e. DISP) to contents of HL pair. After execution of DAD D instruction the contents of HL pair becomes
LP + DISP + 3. Then processor saves the contents of HL pair on top of stack. Now when RET instruction is
executed the processor first copies the contents of top of stack (i.e. LP + DISP + 3) in the program counter
and then returns to main program. So, program execution is transferred to LP + DISP + 3 after execution
of RET instruction.
Main Program
.
.
LXI D, DISP ; Loads DE pair with 16-bit data ‘DISP’ . So, the contents of DE pair are ‘DISP’
LP: CALL SUB ; Calls the subroutine stored at address ‘SUB’. During last two machine cycles
of CALL, the microprocessor saves address of next instruction (i.e. LP + 3) on
top of stack.
Subroutine SUB :
POP H ; Moves the contents of top of stack (i.e. LP + 3) in HL pair. So contents of HL
pair become LP + 3.
DAD D ; Adds contents of DE pair (i.e. DISP) to contents of HL pair (i.e. LP + 3 ) and
saves the result in HL pair. So, contents of HL pair become LP + DISP + 3.
PUSH H ; Moves the contents of HL pair (i.e. LP + DISP + 3) on top of stack.
RET ; Returns the execution to address stored on top of stack (i.e. LP + DISP + 3).
When return instruction is executed the microprocessor moves contents of
top of stack to program counter. So the execution is transferred to the address
LP + DISP + 3.
Q.23 Ans.(b)
Given, SP =2700 H PC =2100 H and HL = 0000H
2100 H: DAD SP ; Adds the contents of SP pair(i.e. 2700H) to HL pair (i.e. 0000H) and store
result in HL pair.
HL :0000 0000 0000 0000
+ SP :0010 0111 0000 0000
HL :0010 0111 0000 0000
2 7 0 0
After addition, HL = 2700 H
2101 H: PCHL ; Moves the contents of HL (i.e 2700H) pair to Program Counter. So, PC =
2700 H.
The contents of (SP) and (PC) at the end of execution will be , PC = 2700H and SP = 2700H.
Q.24 Ans.(a)
Memory mapped I/O devices are identified with 16-bit addresses just like a memory location. Memory
mapped I/O devices are accessed using same instructions which are used to access memory locations. So,
for reading the data into accumulator from I/O device connected at 2500 H, following instructions can be
used,
LXI H, 2500H ; Load HL pair with 2500 H. So, H = 25 H and L = 00 H
MOV A, M ; Moves the contents of memory location, whose address is stored in HL pair,
to accumulator.
Q.25 Ans (a)
MVI A, 05 H ; Moves 05 H to Accumulator. So, A = 05 H
MVI B, 05 H ; Moves 05 H to Register ‘B’ . So, B = 05 H
PTR : ADDB ; Adds the contents of B to A and stores result in ‘A’.
DCR B ; Decrements contents of B by one.
JNZ PTR ; Jumps to PTR until content of ‘B’ becomes zero.
ADI 03 H ; Adds 03 H to contents of ‘A’.
HLT ; Halts the program execution.
Above program adds contents of ‘B’ five times to ‘A’ and contents of ‘B’ are decremented everytime and at
last 03H is added to A.
The result shall be as under,
A = 05 + 05H + 04H + 03H + 02H + 01H + 03H = 17H
Q.26 Ans (c)
The instruction LHLD 2100H , loads register L with contents of 2100H and register H with contents of
2101H.
Q.27 Ans. (a)
2000 H XRA A ; Performs ExOR operation the contents of A and store
result in A. Result in A after operation becomes 00H.
Resets the carry flag, i.e. CY = 0
2001 H MVI B,04H ; Moves 04 H in register B. So B = 04 H
2003 H MVI A, 03H ; Moves 03 H in accumulator A. So, A = 03 H
2005 H RAR ; Rotates the contents of A to right through carry flag.
Before rotation:
CY = 0

0 0 0 0 0 0 1 1
After rotation:
CY = 1

0 0 0 0 0 0 0 1
⇒ A = 01 H and CY = 1
2006 H DCR B ; Decreases the content of register B by one and all
flags are affected except carry flag. The contents of B
after decrement, B = 03 H. As contents of B are non-
zero so zero flag is reset. i.e. Z = 0.
2007 H JNZ 2005 ; Jump the execution to address 2005 if zero flag is not
set. So, the execution jumps to 2005 H till zero flag is
set.
200AH HLT ; Halt the execution of program.
Here, the execution jumps back to address 2005 H thrice till the contents of B become zero. Thus instruction
RAR is executed four times and the contents of A are rotated to four times through carry flag in total. In
first run contents are A = 01H, CY = 1 and B = 03H as shown above. In second run the contents become
A = 80H, CY= 1 and B = 02H. During third run A = C0H, CY= 0 and B = 01H. and in last and fourth run,
A = 60H, CY= 0 and B = 00H and Z = 1. Thus execution goes to HLT when zero flag is set.
Q.28 Ans. (b)
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are
accumulator (A) and flag (F), respectively.
Q.29 Ans. (c)
Program used for multiplication of two 8-bit numbers stored in registers B and C is,
MVI A, 00H ; Moves 00H to accumulator. So, A = 00H.
LOOP ADD C ; Adds the contents of register C to A.
DCR B ; Decrements the contents of B by one.
JNZ LOOP ; Jumps back to LOOP till the zero flag is set.
HLT ; Halts the execution.
In the above program first accumulator is loaded with 00H. The execution enters into loop till the contents
of B become zero. Thus the contents of C are added to A for a number of times equal to number stored in
B. Thus the results stored in A at the end of the program are equal to the product of contents of B and C.
Q.30 Ans. (d)
MOV B, M ; Moves the contents of memory location M whose address is stored in HL pair
to register B.
PCHL ; Moves the contents of HL pair to the program counter
RNZ ; Return the execution to the calling subroutine if zero flag is not set.
SBI BEH ; Subtracts 8-bit data BEH from contents of accumulator along with borrow.
Thus, the instruction which changes the content of the accumulator is SBI BEH.
Q.31 Ans. (c)
In an 8085 system, a PUSH operation requires more clock cycles than a POP operation because the the stack
pointer needs to be pre-decremented before writing registers in a PUSH, whereas a POP operation uses the
address already in the stack pointer.
Q.32 Ans. (d)
Given contents of accumulator and carry flag, A = A7 = 10100111; CY = 0
Before rotation:
CY = 0

1 0 1 0 0 1 1 1
After rotation:
CY = 1

0 1 0 0 1 1 1 1
⇒ A = 4FH and CY = 1
Q.33 Ans.(b)
MVI A, 33H ; Moves 33 H to A
MVI B, 78H ; Moves 78 H to B
ADD B ; Adds the contents of B to A and stores result in A.
The contents of A after addition,
A : 00110011 or 33 H
+B : 01111000 or 78 H
________________
` A : 10101011 or AB H
CMA ; Complitments the contents of A. Contents of A after complimenting becomes,
A : 01010100 or 54 H
ANI 32H ; Performs AND operation of 32 H with contents of A and stores result in A.
A : 01010100 or 54 H
AND: 00110010 or 32 H
________________
A : 00010000 or 10 H
Thus the contents of A after execution of the fifth instruction is 10 H.
Q.34 Ans (210 to 210)
The function performed by the given program is as under,
LXI H, 2001 H ; Loads the HL pair with 16-bit data 2001 H with 20 H in H and 01 H in L
register.
MVIA, 21H ; Moves 8 bit data 21 H to accumulator. So, contents of A become 21H.
INX H ; Increments the contents of HL pair by 1. So, the contents of HL pair become
2002 H with 21 H in H and 02 H in L.
ADD M ; Adds the contents of memory location whose address is stored in HL pair to
the contents of accumulator and stores the result in accumulator.
As contents of HL pair is 2002 H. So, the data of memory location 2002
H is added in the contents of accumulator. After addition the contents of A
become (21 H + B1 H) = D2 H
INX H ; Increments the contents of HL pair by 1. So, the contents of HL pair now
become 2003H with 21 H in H and 03 H in L.
MOV M, A ; Moves the content of A to memory location indicated by HL pair. The contents
of HL pair are now 2003 H. So, the content of A are moved to memory location
2003 H. The content of A is D2 H so data D2 H is moved to memory location
2003 H. The decimal equivalent of D2 H is 210.
Thus the memory location 2003H contains 210 at the end of this program.
Q.35 Ans. (d)
Addressing modes used in 8085 are,
i. Register
ii. Immediate
iii. Direct
iv. Register indirect
v. Implicit or Implied
Q.36 Ans. (b)
When the operand required for an instruction is stored in registers inside the processor, then the addressing
mode is called register addressing mode. For example instruction MOV A,B has register addressing mode
because operand required in the instruction is stored in registers inside the processor.
Q.37 Ans.(c)
I. MVI A is a one byte instruction.
II. LDAX B is a one byte instruction.
III. JMP 2050 is a three byte instruction.
IV. MOV A, M is a one byte instruction.
Q.38 Ans (b)
A . One byte instruction is MOV A,B
B. Two bytes instruction is MVI A, data
C. Three bytes instruction is JMP address
D. Register Indirect addressing is MOV A,M
Q.39 Ans (d)
I. MOV A,B is a Register Addressing
II. MVI B, 0A H is an Immediate Addressing
III. MOV C,M is Register Indirect Addressing
IV. STA addr is a Direct Addressing
Q.40 Ans (d)
A. MOV A, M is a Register Indirect Addressing
B. LXI H, E400H is a Immediate Addressing
C. LDA FICDH is a Direct Addressing
D. CMC is has no addressing mode.
Q.41 Ans (b)
A. Implicit addressing is used in RAL.
B. Register Indirect addressing is used in MOV A, M.
C. Immediate addressing is used in JMP 3FA0H
D. Direct Addressing is used in LDA 03FCH
Q.42 Ans (d)
For the purpose of data processing an efficient assembly language programmer makes use of the general
purpose register rather than memory because data processing with registers takes fewer cycles than that
with memory.
Q.43 Ans.(b)
Characters used in assembly language and their meaning are as under,
A. Blank is used as separator for op field and operand
B. Colon is used as end of label field
C. Semicolon is used as beginning of comment field
D. Comma is used as a separator for operand
Q.44 Ans (b)
The sequence of instructions is as follows:
1. The instruction (opcode) is fetched and decoded
2. The operand is fetched and instruction is executed. Example MOV A,M
The execution of this instruction is as follows:
1. The processor fetches the opcode from memory and then decode.
2. In the next step microprocessor fetch the operand from memory and execute the instruction.
Hence both fetch and execution cycles are included.
Q.45 Ans (d)
A. PCHL : Transfers the contents of HL pair to program counter
B. SPHL : Transfers the contents of HL pair to stack pointer
C. XTHL : Exchange the top of the stack with the contents of HL pair
D. XCHG : Exchange the contents of HL pair with DE pair
Q.46 Ans. (b)
i. RLC uses implicit addressing mode.
ii. STA uses direct addressing mode.
iii. RRC uses implicit addressing mode.
iv. CMA uses implicit addressing mode.
Q.47 Ans (b)
A. SIM is used for Serial output data
B. DAD is used for 16 bit addition
C. DAA is used for BCD addition
D. SPHL is used for initializing the stack pointer
Q.48 Ans (a)
Let the contents of register B are 92 H.
92 H = 10010010
STC ; Sets the carry flag. So, CY = 1.
CMC ; Complements of carry i.e. CY = 0
MOV A, B ; Copies the contents of B (i.e. 92H) into accumulator. So, A = 92 H
RAL ; Rotates the contents of accumulator to left through carry
Before rotation -
CY = 0
A=
1 0 0 1 0 0 1 0
A = 92H
After rotation :
CY = 1
A=
0 0 1 0 0 1 0 0
⇒ A = 24 H
Doubling the contents of register B before execution of RAL instruction,
10010010 : 92 H
10010010 : 92 H
100100100 : 124 H
Q.49 Ans (b)
An RRC instruction shifted each bit to the right without carry flag. The carry flag is modified according to
bit Do. No other flag is affected by RRC instruction.
Q.50 Ans (c)
Let the contents of register B are 92 H.
92 H = 10010010
STC ; Sets the carry flag . So, CY = 1.
CMC ; Complement of carry i.e. CY = 0
MOV A, B ; Copies the contents of B into accumulator i.e. A = 92 H
RAL ; Rotates the contents of accumulator to left through carry
Before rotation -
CY = 0
A=
1 0 0 1 0 0 1 0
A = 92H
After rotation :
CY = 1
A=
0 0 1 0 0 1 0 0
⇒ A = 24 H
Doubling the contents of register B before execution of RAL instruction ,
10010010 : 92 H
10010010 : 92 H
100100100 : 124 H
Q.51 Ans (c)
MVI zA, 30H ; Moves data 30H to A
ADI 30H ; Adds 30H to contents of A and store result in A.
A + A : 00110000
00110000
01100000
⇒ A = 60H
XRA A ; Performs ExOR operation the contents of A and store result in A.
A ⊕ A : 01100000
01100000
00000000
⇒ A = 00 H
Q.52 Ans (b)
When POP H instruction is executed, two data bytes at the top of the stack are transferred to the H-L pair.
The contents of the memory location indicated by the stack pointer register are copied in to low-order
register (e.g. register L) and then the stack pointer register is incremented by 1 and then contents of next
memory location are copied into high order register (e.g. register H) and stack pointer register is again
incremented by 1.
Q.53 Ans (d)
CMP is a 1-byte instruction but may have 1 or 2 two machine cycles and CPI is a 2-byte instruction having
2 machine cycles. Therefore, CMP takes either less or the same number of m/c cycles as compared to CPI.
Note : CMP R has 1 machine cycle , CMP M has two machine cycles and CPI has two machine cycles.
Q.54 Ans (a)
When the RET (return) instruction is executed at the end of the subroutine the memory address stored on
the stack is retrieved and the sequence of execution (assigned to PC) is resumed in the main program.
Q.55 Ans (b)
ADC : EQU 30H
GETADC : IN ADC
RET
When RET is executed the sequence is
Step-I : Opcode of IN is fetched
Step-II : Opcode of IN is decoded
Step-III: Port address 30H is decoded.
Step-IV: I/O read operation is performed.
Q.56 Ans (b)
NOT is performed by ALU of 8085 to complement a number stored in accumulator. Instruction CMA is
used to perform NOT operation in 8085.
Q.57 Ans (b)
MOV H, C; The contents of register C are moved to register H.
Q.58 Ans (a)
Location of flags in flag register are,
S Z AC P CY
D7 D6 D5 D4 D3 D2 D1 D0
1 0 X 1 X 0 X 1
From above flag register,

S = 1 ; MSB is 1. The result is a negative number.
CY = 1 ; Carry is generated in arithmetic operation.
Z = 0 ; The result of operation is non-zero
P = 0 ; The result has odd parity.
Q.59 Ans (d)
IN 01H ; Read the 05H from I/O device connected at port address 01H.
ANI 80H ; Microprocessor logically AND the data 80H with 05H
80 H = 10010000
05H = 00000101
00000000
ANI instructions reset the carry flag, sets the axillary carry flag and affects all other flags according to the
result of operation. As result is 00 H , so, zero flag will be set.
Q.60 Ans (b)
PSW stands for Program Status Word. It is a 16 bit combination of Accumulator and flag register.
Accumulator is higher order and flag register is lower order register.
PUSH PSW: This instruction first decrements of stack pointer by one and then copies the contents of
accumulator on the location shown by stack pointer. Then stack pointer register is again decremented by
one and the content of flag register are copied on the next memory location.
The instruction requires 3 machine cycles, one for opcode fetch, one for writing the contents of accumulator
on memory locations and one for writing the contents of flag register on next memory location.
Q.61 Ans (a)
Given, A = 37H and CY = 1
The instruction ACI 56H adds 56H with carry to the contents of accumulator (34H) and store the result in
accumulator.
37 H = 00110111
56 H = 01010110
⇒
CY +1
10001110 = 8E H
Thus result in accumulator is 8EH
Q.62 Ans (b)
CMA : Complement the content of accumulator hence the contents of accumulator
get modified.
DAA : This instruction adjust the contents of accumulator from binary to BCD;
hence contents of A get modified.
ADD B : This instruction adds the contents of register B to the contents of register A
and store the result in A, So, contents of A are changed.
CMP B : This instruction compares the contents of register B with the contents of
accumulator but contents of A and B remains unchanged.
Q.63 Ans.(d)
Given, Contents of 2000H = AAH
Contents of 2001H = BBH

Contents of 2002H = CCH
LXI H, 2001H : Loads the HL pair with 2001H . So , H =20 H and L = 01 H
LHLD 2001H : Loads the HL pair directly with the contents of memory location 2001H and
next memory location, 2002H . The contents of 2001 are loaded in L and
contents of 2002H are loaded in H. So, new contents of H & L will be, So,
L =BBH and H =CCH
Note : In LHLD instruction the contents of lower address goes to lower order register and contents of higher address
goes to higher address register. For example contents of 2001H goes L and contents of 2002H goes to H.
Q.64 Ans.(c)
In 8085, the DAA instructions is used for Decimal Adjust Accumulator.
Note : DAA instruction changes the binary values of contents of accumulator to BCD. This instruction makes use
of status of CY and AC flags. It performs the operation as follows,
II. If value of higher order four bits (D7-D4) in the accumulator is greater than 9 or if AC flag is set , the
Q.65 Ans.(c)
Facts about register indirect addressing :
1. It takes more time to transfer a data byte between microprocessor and memory as compared to direct
addressing mode so, it is slower than direct addressing.
2. It helps in writing compact code .
3. It allows reuse of memory-CPU data transfer instruction.
4. It is essential for stack operations.
Indirect addressing or register indirect addressing mode takes 4 bytes and direct addressing mode takes 3
bytes. If only one byte is to be transferred than direct addressing is more efficient.
But for a block of memory transfer, the instruction LDA will have to be repeated for each memory location.
On the other hand , a loop can be run with instruction with register indirect addressing mode and contents
of register pair can be incremented or decremented. Hence for transfer a block of data register indirect
addressing is more efficient.
Q.66 Ans.(d)
Given statement : ANA A, ORAA, XRAA, SUBA, CMPA
Facts about given statements,
1. All are arithmetic and logic instructions.
2. Only XRA A and SUB A clear contents of A irrespective of its original contents.
3. All reset the carry flag.
4. All of them are 1-byte instructions.
So, statements 1, 3 and 4 are correct.
Q.67 Ans.(a)
Since INR instruction of 8085 does not affect carry flag , therefore, overflow can not be detected with INR
instruction.
Q.68 Ans.(b)
PUSH B requires 3 machine cycles out of which one is opcode fetch and two cycles are memory write cycles.
Q.69 Ans.(d)
Data transfer instruction i.e. MOV and MVI do not affect the status of flags. ADC and CMP affects the flags
as per the result of operation.
Q.70 Ans.(b)
I. A subroutine is a program written separately from the main program to perform a function that occurs
repeatedly in the main program. The assertion is true.
II. A subroutine can be called by a CALL instruction. The reason is also true but it is not correct explanation
of assertion.
Q.71 Ans(c)
MVI A, 91H ; Move 91H to A. So , A = 91 H
XRI 91H ; Contents of A are ExORed with 91H and result is stored in A.
A : 1001 0001
91H : 1001 0001
0000 0000 = 00 H
So, A = 00 H
So, content of accumulator is 00 H, Carry , Auxiliary Carry and Zero flags are set to 0, 0 and 1 ,
respectively.
Q.72 Ans.(c)
If the HLT instruction of an Intel 8085A microprocessor is executed the microprocessor enters into a HALT
state and the buses are tri-stated.
Q.73 Ans.(c)
A. Maskable interrupt of 8085 microprocessor are RST 5.5, RST 6.5, RST 7.5 and INTR
B. SID signal is serial input data of 8085 µP.
C. XTHL is an instruction of 8085 µP.
D. Memory location 002C H is related to RST 5.5 interrupt of 8085 µP.
Q.74 Ans.(c)
LDA 2000 H is used load accumulator with the contents of memory location 2000 H. It requires 4 machines
cycles i.e. one opcode fetch, three memory read cycles.
Q.75 Ans.(d)
The addressing mode used in the instruction JMP F347 H in case of an Intel 8085 A microprocessor is
immediate.
Q.76 Ans.(c)
I. LXI H 2050 H has immediate addressing mode.
II. MOV A, B has register addressing mode
III. LDAX B has indirect addressing mode
IV. LDA 2050 H has direct addressing mode
Q.77 Ans.(c)
INR B instruction does not affect Carry flag.
Q.78 Ans(a)
A. LXI H, 2050 H uses immediate addressing.
B. RRC uses implied or implicit addressing.
C. MOV A,B uses register addressing.
D. LDA 30 FF uses direct addressing.
Q.79 Ans(d)
87H : 1000 0111
+79H : 0111 1001
1 0000 0000
The result of addition is zero and generates a carry. So, both CARRY and ZERO flags will be set to 1
Q.80 Ans(a)
CALL instruction requires five machine cycles which are one opcode fetch, two memory read and two
memory write.
Q.81 Ans.(c)
I. CMP C : Compares the contents of C with contents of A. The comparison is made by
subtracting the contents of C from contents of A without altering the contents
of A and C. The status of result is reflected by flags.
II. CPI 3A : Compares 3A H with contents of A. The comparison is made by subtracting
3A H from contents of A without altering the contents of A. The status of
result is reflected by flags.
III. ANI 5C : The 8bit data 5CH is ANDed with contents of A and result is stored in A. So
contents of A gets altered.
IV. ORA A : The contents of A are ORed with contents of A and result is stored in A only.
The operation results in no alteration in contents of A.
Q.82 Ans.(d)
The instruction XRA A performs ExOR operation on contents of A with contents of A and store the result is
stored in A. The instruction will clear the contents of A. So, the zero flag is set by the instruction.
Q.83 Ans.(d)
1. MOV M, A : Does not affect any flag because a data transfer instruction does not affect
flags.
2 . ADD C : Affects all the flags because it is arithmetic instruction.
3 . MVI A, FF : Does not affect any flag because a data transfer instruction does not affect
flags.
4 . CMP M : Affects all the flags because comparison operation is performed by subtracting
contents of memory location M from contents of A. The contents of A and M
remains unaltered but status of result is reflected by flags.
Q.84 Ans. (d)
Addressing modes used in 8085 are,
i. Register
ii. Immediate
iii. Direct
iv. Register indirect
v. Implicit or Implied
Q.85 Ans. (b)
When the operand required for an instruction is stored inside the processor in a register, then this addressing
mode is called register. For example instruction MOV A,B has register addressing mode because operand
required in the instruction is stored in registers inside the processor.
Q.86 Ans. (b)
I. SPHL 1080H ; The instruction is wrong. Correct instruction is SPHL. SPHL does not have
any operand. It copies the contents of HL pair to stack pointer register, SP.
II. SHLD 1080 H ; Directly stores the contents of HL pair at memory location
1080 H and 1081 H . The contents of L are stored at 1080 H and contents of
H are stored at 1081 H.
III. STAX 1080 H ; The instruction is wrong. Correct instruction is STAX B or STAX D. STAX
B/D instruction stores the contents of accumulator at memory location whose
address is stored in BC / DE pairs.
IV. SPHL 1081 H ; The instruction is wrong. Correct instruction is SPHL. SPHL does not have
any operand. It copies the contents of HL pair to stack pointer register, SP.
Q.87 Ans. (b)
MVI A, 20H ; Moves data 20H to accumulator , A.
MVI B, 10 H ; Moves data 10H to register, B.
BACK : NOP ; No operation
ADD B ; Adds contents of register B(i.e. 20H) to A(i.e. 10H) and store result in A.
20H : 00100000
+ 10H : 00010000
00110000
⇒ A = 30H and CY = 0
Before rotation:
CY = 0

0 0 1 1 0 0 0 0
After rotation:
CY = 0

0 1 1 0 0 0 0 0
⇒ A = 60Hand CY = 0
After execution of RLC instruction 3 times CY flag will be set. So, the instruction NOP will be executed
three times in the given program.
Q.88 Ans. (c)
PUSH PSW ; This instruction first decrements the contents of stack pointer by one to ABCCH
and then copies the contents of accumulator on the location shown by stack
pointer register (i.e. ABCDH). Then stack pointer register is decremented
again by one to ABCB H and then content of flag register are copied at
ABCBH. So, the contents of stack pointer becomes ABCBH after execution
of PUSH PSW.
XTHL ; Exchanges the contents of top of stack with HL pair. Contents of location
ABCBH are exchanged with L and ABCCH are exchanged with H. But
contents of SP remains ABCBH at the end of instruction.
PUSH D ; This instruction first decrements the contents of stack pointer by one to ABCA
H and then copies the contents of D on the location shown by stack pointer
register (i.e. ABCA H). Then stack pointer register is decremented again by
one to ABC9 H and the content of E are copied at ABC9 H. So, the contents
of stack pointer becomes ABC9 H after execution of PUSH D.
JMP FC70 H ; Jumps the execution of program to memory location FC70 H. This instruction
does not affect the contents of stack pointer.
So, at the end of execution of given program the contents of stack pointer are ABC9 H.
Q.89 Ans. (c)
Let contents of A are 60 H
XRA A : Performs XOR operation the contents of A and store result in A.
A ⊕ A : 01100000
01100000
00000000
⇒ A = 00H
Since the contents of A are 00H after execution of XRA A instruction so zero flag is set.
Note : XRA A instruction can be used to reset CY & AC flags and set Z flag.
Q.90 Ans. (b)
A memory-mapped I/O device is identified by 8085 microprocessor just like a memory location. The
instruction used with memory mapped I/O devices are also same as instructions used for operations with
contents of memory location. So, contents of accumulator can be transferred to the device connected at
1000 H by using the same instruction as in case of memory location 1000H. The instructions used will be
as below,
LXI H, 1000H ; Loads HL pair with 16 bit data 1000 H. So contents of HL pair becomes 1000 H.
MOV M, A ; Moves the contents of accumulator in memory mapped device connected at
location whose address is stored in HL pair(i.e. 1000H).
Q.91 Ans. (c)
Stack used in 8085 microprocessor is Last-In First -Out(LIFO).
Q.92 Ans. (b)
Instructions of 8085 microprocessor can have one byte, two bytes or three bytes.
Q.93 Ans. (b)
A. JMP 2021 H has immediate addressing mode.
B. LDAX B has indirect register addressing.
C. IN 10H has direct addressing mode.
D. RLC has implicit addressing mode.
Q.94 Ans. (c)
The instruction PUSH B has register indirect addressing.
Q.95 Ans. (d)
1. MOV B, C is a one byte instruction. So it requires one byte of memory.
2. STA address is a three byte instruction. So it requires three bytes of memory.
3. ORI byte is a two byte instruction. So it requires two bytes of memory.
Q.96 Ans.(b)
If the CALL instruction of 8085 in the main program is conditional then RETURN instruction in the
subroutine can be conditional or unconditional.
Q.97 Ans(b)
LOOP : MVI C,78 H ; Moves 78 H to register C.
So, C = 78 H.
DCR C ; Decreases the contents of C by 1.
JNZ LOOP ; Jumps at LOOP if zero flag is not set.
The execution of program remains in LOOP till the zero flag is set. The zero flag is set when contents of C
becomes zero. During each iteration of loop the contents of C are reduced by one. The initial contents of C
are 78 H. The decimal equivalent of 78H is 120. So, the loop is executed 120 times.
Q.98 Ans(b)
Let the contents of A are 25H
ANI F0 H ; Contents of A are ANDed with F0H and result is stored in A.
A : 0010 0101
F0H : 1111 0000
0010 0000 = 20 H
So, A = 20 H
The contents of lower four bits of accumulator are cleared.
Q.99 Ans(a)
i. LDA address ; Loads a byte of data into the accumulator from the memory address given in
the instruction.
ii. LDAX B ; Loads a byte of data into the accumulator from the memory location whose
address is stored in BC pair.
iii. LHLD address ; Load the HL pair directly with the contents of given memory location and next
memory location. The contents address given in instruction are loaded in L
and contents of next are loaded in H.
iv. STA address ; Stores a byte of data from the accumulator to the memory address given in
the instruction.
Q.100 Ans. (b)
Mnemonics Comments
LXI SP, 7FFF H ; Loads stack pointer SP with 7FFF H. So, contents of SP becomes 7FFF H.
MVI A, 25H ; Moves 25 H to accumulator A. So, contents of A = 25 H
XRI 02H ; Performs Ex-OR operation between contents of A and 02 H and store the result
in A.
A(25H ) : 0 0 1 0 0101
02H : 0 0 00 0010

A XOR B : 00 1 0 0111
2 7
So, A = 27 H,
XRI instruction resets CY and AC flags and other flags are affected as per
result. So, Z = 0, P = 1 , S = 0. Location of flags in flag register are,
S Z x AC x P x CY
x - unused bits of register. So, the contents of flag register after the
execution of above program will be,
0 0 x 0 x 1 x 0

If contents of undefined flags always remain cleared then contents of flag
register are 04 H.
PUSH PSW ; This instruction first decrements the contents of stack pointer by one to 7FFE
H and then copies the contents of accumulator(i.e. 27 H) on the location
shown by stack pointer register (i.e. 7FFE H). Then stack pointer register is
decremented again by one to 7FFD H and the content of flag register
(i.e. 04H) are copied at 7FFD H. So, the contents of stack pointer becomes
7FFD H after execution of PUSH PSW.
POP H ; When POP H instruction is executed, two data bytes at the top of the stack
are transferred to the HL pair. The contents (i.e. 04 H) of the memory
location(i.e.7FFD) indicated by the stack pointer are copied in to low-
order register (e.g. register L ) and then the stack pointer register is incremented
by 1 to 7FFE and then contents(i.e. 27 H) of memory location 7FFE are
copied into high order register (e.g. register H) and stack pointer register is
again incremented by 1 to7FFF H. So, After the execution of POP H, H = 27
H and L = 04 H.
MOV A, L ; Moves the contents of L(i.e. 04 H) to A. So, A= 04 H.
ORI 10H ; Performs OR operation between contents of A and 10 H.
A(04H) : 000 0100
10H : 0001 0000

A OR10H : 0001 0100
1 4
HLT ; Halts the execution of the program.

Thus the contents of A, H, L, SP and PSW registers after executing the above set fo instructions? Assume
undefined flags always remain cleared.
Contents of A = 14H,
Contents of H = 27H,
Contents of L = 04H,
Contents of SP = 7FFFH,
Contents of PSW(Flag register) = 04H
Q.101 Ans. (c)
Mnemonics Comments
MVI A, AA H ; Moves AA H to accumulator A. So, contents of A = AA H
ORI FF H ; Performs OR operation between contents of A & 8 bit data FF H and store the
result in accumulator.
A(AA H) :1 0 1 0 1 010
FFH :11111111

A OR B : 1111 1111
F F
So, A = FF H and CY = 0 (OR instruction resets the CY flag)

RRC ; Rotates content of A to right without carry flag.
CY Before rotation
0 1 1 1 1 1 1 1 1

Cy After rotation

1 1 1 1 1 1 1 1 1
So, content of A = FF H
And CY flag = 1
RRC ; Rotates content of A to right without carry flag.
CY Before rotation
1 1 1 1 1 1 1 1 1
Cy After rotation

1 1 1 1 1 1 1 1 1
So, content of A = FF H
And CY flag = 1
CMC ; Compliments Carry Flag. So, Cy = 0.
INR A ; Increases contents of A by 1. The instruction INR A affects all flags except

Cy flag.
So, after execution of INR A instruction,
Contents of accumulator , A = 00 H
Carry Flag, , Cy = 0
Parity Flag, P = 1
Sign Flag, S = 0
Zero Flag, Z = 1
Location of flags in flag register are,
S Z x AC x P x CY
x - unused bits of register.
So, the contents of flag register after the execution of above program will be,
01x1x1x 0
If contents of undefined flags always remain cleared then contents flag register are 54 H.
Q.102
Ans. (c)
The field, which is never present in an assembly language statement, is ‘Continue’
Q.103
Ans. (b)
Detailed description of ADI, ACI, ADC and ADD instructions is given below
1. ADD R i. Add the contents of R to A and store the result
R→A, B, C, D, E, H & L in A
iv. One machine cycles (OP) & 4 T-states
2. ADI 8bit data i. Add the 8 bit data immediately to A and store the
result in A
3. ADC R i. Add the contents of R along with carry flag to contents
of A and store the result in A
iv. One machine cycles (OP) & 4 T-states
4. ACI 8 bit data i. Add the 8 bit data alongwith carry flag to contents of
A & store result in A
Q.104 Ans (c)
In 8085 microprocessor, four interrupts (i.e. INTR, RST5.5, RST6.5, RST 7.5) are maskable and one
interrupt (i.e. TRAP ) is non-maskable.
Q.105 Ans (b)
The CALL instruction allows control to transfer to a subroutine, which when complete, issue the RET
instruction to return control to the main program
Q.106 Ans (b)
A single instruction to clear the lower four bits of the accumulator in 8085 microprocessor is ANI F0H
Q.107 Ans (d)
The addressing mode used in the instruction STAX B is indirect.
Q.108 Ans (a)
i. CMP A is single byte instruction which compares the contents of A with A itself.
ii. CMA is also a single byte instruction which compliments the contents of accumulator.
iii. SUB A subtracts the contents of A from A only so the result is zero which sets the zero flag.
iv. Bus is a group of wires which connect external peripherals with microprocessor.
v. Instruction INR C increments the contents of register C but does not affect carry flag.
So, option (a) is incorrect.
Q.109 Ans (d)
i. LDA 2100 loads the accumulator directly with the contents of memory location 2100H. It requires one
opcode fetch and three memory read cycles. So, it requires total four machines cycles.
ii. LXI H, 2100 H loads the HL pair with 16 bit data 2100 H. It requires one opcode fetch and two
memory read cycles. So, it requires three machine cycles.
Q.110 Ans (b)
The instruction PUSH PSW of 8085 microprocessor stores the contents of accumulator and flag register on
the two most locations of stack. Whenever PUSH instructioon is executed the contents of stack pointer are
decremented by two.
Q.111 Ans (b)
i. STACK is used temporarily store the data in RAM locations specified by the programmer in main
program. The assertion is a true statement.
ii. PUSH and POP instructions are used to send or retrieve the data from the STACK. The reason is also
correct statement but it is not correct explanation of assertion.
Q.112 Ans (d)
87 H : 1 0 0 0 0 1 1 1 H
+ 79 H : 0 1 1 1 1 0 0 1 H
1 0 0 0 0 0 0 0 0 H : 00 H
The sign flag (S) is set if D7 bit of result is set, zero flag (Z) is set when result of addition is zero, AC flag is
set when a carry is passed from D3 bit to D4 bit during addition of two numbers, and Carry flag (Cy) is set
when addition results in generation of a carry.
After addition of 87 H and 79 H the sum is zero so zero flag is set, D7 bit is zero so sign flag is reset, carry
is generated so carry flag is set and carry is passed to D4 bit so AC flag is set.
Therefore, S =0, Z = 1, AC = 1 and Cy = 1.
Q.113 Ans (a)
Instruction Operation Performed
STA address ; Stores the contents of accumulation at 16 bit address given in instruction.
LDAX B ; Loads the accumulator with contents of memory location whose address is
stored in BC pair.
LHLD address ; Loads HL pair directly with contents of 16 bit memory address and next
address. The contents of given address are moved to L and contents of next
address are moved to H.
LDA address ; Loads the accumulator with the contents of 16 bit address given in instruction.
Q.114 Ans (a)
Instruction Operation Performed
XTHL ; Exchanges the contents of top of stack with HL pair.
SPHL ; Moves the contents of HL pair to SP.
PUSH H ; Stores the contents of HL pair on top of the stack.
POP H ; Loads the HL pair with the contents of the top of stack.
Q.115 Ans(a)
2’s complement arithmetic is preferred in digital computers because the hardware required to obtain the 2’s
complement of a number, is simple. So, both statements are true and statement (II) is correct explanation of
statement (I).
Q.116 Ans(a)
The instruction PCHL in 8085 is used to load PC with contents of HL.
Q.117 Ans(a)
MVI A, 7 FH ; Moves 7F H to A.
ORA A ; Performs the OR operation between contents of A itself. After execution of
this instruction the contents of A remains 7F H.
CPI A2 H ; Compares the contents of A (i.e. 7FH) with A2 H. The comparison operation
is performed by subtracting A2H from the contents of A.
7F H : 0 1 1 1 1 1 1 1
A2 H : 1 0 1 0 0 0 1 0
1 1 1 0 1 1 1 0 1 : DD H
So, after execution of given set of instructions the contents of A and flags become as under,
A = DD, S = 1, Z = 0, CY = 0
Q.118 Ans(a)
The absolute value of a positive number is number itself and absolute value of a negative number is 2’s
compliment of the number. The given set of instructions check the positiveness of the number. If number is
positive then the number itself is its absolute value and it is displayed on port 01. If the number is negative
then 2’s compliment operation is performed on the number. The 2’s compliment which is absolute value of
the negative number is then displayed on port 01. The 2’s compliment can be performed by complimenting
the number and then adding 01H to the number. So, the correct program required to find the absolute
number is as under,
MVI A, N ; Moves the number N to A.
ORA A ; The contents of A are ORed with itself.
JM ONE ; Jump to ONE if sign flag is set which means that the
number is negative.
OUT 01H ; If the number is positive then content of A is absolute
value of the number and it is displayed on the port
address 01H.
HLT ; Halts the execution.
ONE : P(CMA) ; Compliments the contents of A which happens only
when N is negative.
Q(ADI 0H) ; Adds 01 H for performing 2’s compliment operation .
OUT 01H ; Displays the contents of A to port address 01H which
is now the absolute value of negative number N.
The instructions of P and Q are CMA and ADI 0H.
Q.119 Ans(c)
MVI A, 10H
Moves data 10H to A ;
MVI B, 10H
Moves data 10H to register B. ;
BACK : NOP
No operation ;
ADD B ;
Adds contents of register B(i.e. 10H) to A(i.e. 10H)
and store result in A.
10H : 00010000
+ 10H : 00010000
00100000
⇒ A = 20H and CY = 0
RLC ; Rotates contents of accumulator to left without carry
flag.
Before rotation:
CY = 0

0 0 1 0 0 0 0 0 0
After rotation:
CY = 0

0 1 0 0 0 0 0 0 0
⇒ A = 40 H and CY = 0
After execution of RLC instruction 3 times CY flag will be set. So, the instruction NOP will be executed three
times in the given program.
Q.120 Ans(a)
A. LXI H, 2050 has the immediate addressing mode.
B. RRC has the implicit addressing mode.
C. MOV A, B has the register addressing mode.
D. LDA 30FF has the direct addressing.
Q.121 Ans(c)
The instruction JMP 2050 H is stored at address 2057 H at under,
2057 Opcode
2058 50 H
2059 20 H
205A Opcode of next instruction.
The instruction JMP 2050 H is a three byte instruction which takes three byte of memory for storage of instruction
in memory. So, this instruction is stored from the memroy locations 2057 H to 2059 H. When the instruction is
executed the program counter is incremented by one after fetching each byte of instruction from the memory.
After fetching all the bytes of JMP 2050 H the program counter is incremented to 205A H.
Q.122 Ans(c)
3000 MVI A, 45 H ; Moves 45 H to accumulator A. So, contents of A = 45 H
3002 MOV B, A ; Moves contents of A, ie. 45 H to B. So contents of B = 45 H
3003 STC ; Set carry flag , CY =1
3004 CMC ; Compliment CY flag . So, CY=0
3005 RAR ; Rotates content of A to right through carry flag.
Before rotation:
Cy Before rotation
0 0 1 0 0 0 1 0 1

After rotation:
Cy After rotation

1 0 0 1 0 0 0 1 0
So, content of A = 22 H
3006 XRA B ; Performs XOR operation between contents of A & B and store the result
in accumulator.
A:0 01 0 0 01 0
B:0 1 0 0 0 1 0 1

A ⊕ B : 01 1 0 0 111
6 7
So, contents of A after execution of program are 67 H.

Q.123
Ans(b)
Intruction No. of T-states required
STAX 7 T-states
SPHL 6 T-states
SIM 4 T-states
STA 10 T-states
Q.124
Ans(a)
The instruction XTHL is used to exchange the contents of top of stack with HL pair. It requires 5 machine
cycles and 16 T-states. Each T-state is precisely equal to the time period of clock signal. The frequency of
crystal is devided by two internally in 8085 microprocessor. So, if crystal of 6 MHz is used then the clock
frequency is 3 MHz.
Then time period of each clock pulse,
1 1
T = = µsec
f 3
1
The time required to execute instruction XTHL = 16T = 16 × = 5.33 µsec
3
Q.125 Ans(c)
Hardware and sorftware interrupts of 8085 and their respective memory locations:
Hardware Interrupts Software Interrupts

Instruction Location
RST0 0000H
Instruction Location
RST1 0008H
TRAP 0024H
RST2 0010H
RST5.5 002CH
RST3 0018H
RST.6.5 0034H
RST4 0020H
RST7.5 003CH
RST5 0028H
INTR -
RST6 0030H
RST7 0038H
Q.126 Ans(c)
Facts about 8085 microprocessor,
1. The DAD instruction adds the contents of the specified register pair to the contents of the HL register
pair.
2. The program counter is an stores the address of the next instruction to be executed. So, it is an instruction
pointer.
3. HL in 8085 is used as a memory pointer. Whenever an instruction uses the HL pair for memory pointer,
the addressing is called indirect addressing.
4. HL register pair is also called data pointer.
Q.127 Ans(a)
CALL instruction is used to call a subroutine stored at the address given in instruction. It requires five
machines. Out of the five machines cycles first machine cycle is opcode fetch or instruction fetch, two
machines cycles are memory read and remaining two are memory write machine cycles. Thus I/O machine
cycle is not required in CALL instruction.
Q.128 Ans(c)
1. PUSH PSW
This instruction is used to store the contents of accumulator and flag register on the top of stack. The
stack pointer is decremented by two after execution of this instruction.
2. CALL ADDR
This instruction is used to call a subroutine stored at the address included in the instruction. When
call instruction is executed the contents of program counter are saved on the top of the stack and stack
pointer is decremented by two before transferring the execution to the address of the subroutine.
3. XTHL
This instruction is used to exchange the contents of the HL pair with top of the stack. After executio of
this instructio the contents of stack pointer are same as before.
4. RST n
Start is a software interrupt which is used to call a subroutine stored at a fixed address. When this
instruction is executed the contents of program counter are saved on the top of the stack and stack
pointer is decremented by two before transferring the execution to the address of the subroutine.
Q.129 Ans(a)
Instruction Addressing Mode
CMA Implied addressing
JMP Immediate addressing
ADC Register or indirect addressing
SBB Register or indirect addressing
Q.130 Ans(d)
The instruction MOV require 7 T states.
One T state is precisely equal to one time period of clock signal.
1
So, Time of one T-state, T = µs
2.5
1
Time of 7 T-states = 7T = 7 × = 2.8 µs
2.5
Q.131 Ans(a)
The instruction XRI F0 H performs the Exclusive OR operation of data F0 H with the contents of Accumulator
and stores the results in accumulator only. This instruction can be used to complement the upper nibble of A.
Let the content of A is FF H. The contents of A after execution of instruction XRI F0 H are as under,
A; FFH : 11111111
F 0 H : 11110000
00001111 :0F H
Thus upper nibble of A is complemented by the instruction XRI F0 H.

Q.132 Ans(d)
DELAY: MVI H, 255 D : Move decimal number 255 in register H.
MVI L, 255 D : Move decimal number 255 in register L.
LOOP DCR L : Decrement L by ‘1’
JNZ LOOP : First time DCR L runs for 255 times and second time
onward DCR L is executed 256 times as because
second time onward contents of L also changes from
00H to FFH.
DCR H : Decrement H by ‘1’
JNZ LOOP : Jump to LOOP till contents of H becomes zero. It will
run the loop 255 times.
During first run DCR L is executed 255 times. From second run onward DCR L is executed 256 times.
So, total number times DCR L will be executed will be 255 + 254*256 = 65279
Q.133 Ans(a)
The instruction RLC rotates the contents of Accumulator to left without carry fllag.
Given, A = 70 H, Cy = 0, S = 0
Before rotation:
CY = 0

0 1 1 1 0 0 0 0
After rotation:
CY = 0

1 1 1 0 0 0 0 0
⇒ A = E0 Hand Cy = 0
The instruction RLC affects only carry flag. So, it does not affect the Sign (S) flag. As S is reset initially so
it remains reset after the execution of instruction RLC. So, after the execution of instruction RLC, Cy = 0
and S = 0.
Q.134 Ans(a)
I. RST n : This instruction is a software interrupt which calls a subroutine store at a
fixed address. This instruction uses direct addressing mode.
II. PCHL : The instruction PCHL moves the contents of HL pair to the program

counter. Thus the execution of program is transferred to new address
unconditionally. This instructtion uses register addressing mode.
Q.135 Ans(*)
Address Instruction Operation
0100 H LXI, SP, 00FF ; Loads the stack pointer with 16 bit data 00FF H.
0103 H LXI H, 0701 ; Loads the HL pair with 16 bit data 0701 H. So, H =
07 H and L = 01 H.
0106 H MVI A, 20 H ; Moves 20 H to A. So, A = 20 H.
0108 H SUB M ; Subtracts the contents of memory location, whose
address is stored in HL pair, from the contents of A
and stores the result in A only.
In the given set of instructions the contents of 0701 H which the address stored in
HL pair are not known. So, none of the options is correct. But if the instruction LXI H, 0701 is modified
to LXI 0107 H then the contents of HL pair become 0107 H and the data stored at 0107 H is 20 H which is
the data of instruction MVI A, 20H. Then the contents of A after the execution of program is 00H.
Q.136 Ans(c)
MVI A, F0 H ; Moves F0 H to A. So, A = F0 H.
ORI FF H ; Performs OR operation of FF H with the contents of A. The result is stored in
A. After the OR operation the contents of A become FF H.
A; F0H : 11110000
FF H : 11111111
11111111 :FF H
XRI F0 H ; Performs XOR operation of F0 H with the contents of A. The result is stored
in A. After XOR the contents of A become 0F H.
A; FFH : 11111111
F0 H : 11110000
00001111 :0F H
Q.137 Ans(d)
The correct program is
MVI A, 00H ; Moves 00H to A.
LOOP: ADD B ; Adds the contents of B to the contents of A.
DCR C ; Decrements the contents of C by one.
JNZ LOOP ; Jumps to LOOP until the zero flag is set which is set
only when the contents of C become zero.
Above program adds the contents of B to contents of itself for number of times equal to the number stored
in register C. The operation is equivalent to multiplication of contents of B and C.
Q.138 Ans(b)
The instruction ADD C adds the contents of register C to the contents of Accumulator and stores the result
in Accumulator. Here the contents of A are F0 H and contents of C are 0F H. After the addition operation
the contents of A become FF H.
Q.139 Ans (c)
1000 LXI SP, 27FFH ; Initialize the stack pointer with 27FFH
1003 CALL 1006H ; Save the contents of program counter (i.e. address of next instruction, 1006H)
on top of stack and call the subroutine stored at address 1006H . During the
saving the contents of program counter the stack pointer is decremented by
one and 10H is saved at 27FEH and stack pointer is again decremented by
one& 06H is saved at 27FDH
1006 POP H ; Retrieve the contents of top of stack in HL pair. During popping up of stack
the contents of 27FDH (i.e.06H ) are stored in L and stack pointer is incremented
by one to 27FEH . Then the contents of next memory location 27FEH (i.e. 10H)
are stored in H and stack pointer is again incremented by one to 27FFH
Therefore, the contents of the stack pointer (SP) and the HL, register pair on completion of execution of
these instructions are , SP = 27FFH, HL = 1006H
Q.140 Ans (c)
I. Branch instructions like jump in a micro-processor are used to change the sequence of program. This
statement is true.
II. All logical instructions are not branch instructions. For example, ANA, ORA, XRA etc. are not branch
instructions. So, statement II is not true.
Q.141 Ans (b)
1. IN is 2-byte instruction
2. OUT is 2-byte instruction
3. STA is 3-byte instruction
Q.142 Ans (c)
The instruction CMP M use indirect addressing mode.
Q.143 Ans (c)
i. XRI byte uses two machine cycles and 7 T states.
ii. STA address uses 4 machine cycles and 13 T states
iii. CALL address uses 5 machine cycles and 18 T states.
iv. JMP address uses 3 machine cycles and 10 T states.
Note : CALL instruction uses 18 T-states which are the maximum number of T-states used by any instruction of 8085.
Q.144 Ans (c)
STA instruction uses 4 machine cycles which are Opcode fetch, memory read, memory read and memory
write.
Q.145 Ans (a)
POP PC reads the contents of top of stack into the program counter and RET instruction also reads the
contents of stack into the program counter. So, POP PC and RET are close match of each other.
Note : However there is not instruction like POP PC in 8085.
Q.146 Ans (c)
i. Memory to accumulator data transfer is possible using instructions like, MOV A, M, LDA 2000 etc.
ii. Accumulator to memory data transfer is possible using instructions like MOV M, A, STA 2000 etc.
iii. I/O device to accumulator data transfer is possible using instruction IN 03
iv. There is no instruction for data transfer from one memory location to another memory location directly.
Q.147 Ans (c)
Let HL = 10FB = 0001000011111011
DAD H adds the contents of HL pair to HL pair only. After execution,
HL = 10FB H = 0001000011111011
+ HL = 10FB H = 0001000011111011
HL = 21F6 H = 0010000111110110
Thus, a ‘DAD H’ instruction is the same as shifting each bit by one position to the left with a zero inserted
in LSB position.
Q.148 Ans (b,c)
I. RAL affects only CY flag.
II. POP PSW affects all the flags.
III. XRA A affects all flags with CY and AC flag reset.
IV. DCR A affects all flags except CY flag.
Q.149 Ans (a)
Correct sequence of various fields in each instruction in an assembly language program is
1. Label field
2. Mnemonic field
3. Operand field
4. Comment field
Q.150 Ans (d)
LXI H, 2500H ; Load HL pair with 16 bit data 2500 H. So, contents of HL pair become 2500H
wich H = 25 H and L = 00H.
LXI D, 0200H ; Load DE pair with 16 bit data 0200 H. So, contents of DE pair become
0200H wich D = 02 H and E = 00H.
DAD D ; Add the contents of DE pair to contents of HL pair and store the result in HL
pair.
HL : 2500 H
+DE : 0200 H
HL : 2700 H
XCHG ; Exchange the contents of HE pair and DE pair. After exchange, HL = 0200H
and DE = 2700H.
Q.151 Ans (c)
XCHG instruction of 8085 exchanges the content of HL and DE register pairs.
Q.152 Ans(b)
The instruction JNC 16-bit refers to jump to 16-bit address if CY flag is reset.
Q.153
Ans(a)
The instruction CMP A compare contents of accumulator with contents of register A.
Q.154
Ans(c)
When RET instruction is executed by microprocessor, it takes three machines cycles. During first machine
cycle microprocessor fetches the Opcode and during second and third machines it reads the contents of top
of stack.
Q.155 Ans.(b)
I. Stack works on the principle of LIFO. The statement I is true.
II. Stack pointer contains address of the top of the stack. The statement II is also true but is not correct
explanation of statement I.
Q.156 Ans.(c)
I. I/O devices can be accessed using IN and
OUT instructions. The statement I is true.
II. IN and OUT instructions are data transfer instructions which transfer the data from I/O devices to
accumulator. These cannot be used for arithmetic and logic operations directly. So, arithmetic and logic
operations cannot be directly performed with I/O data.
Q.157 Ans.(c)
I. On executing the HLT instruction, the microprocessor enters into a half state and all the buses are tri-
stated. The statement I is true.
II. On executing the HLT instruction, the microprocessor enters in to wait state till the reset is pressed. So,
the statement II is false.
Q.158 Ans.(d)
I. Stack is organized as 8-bit storage outside the microprocessor. The statement I is false.
II. Stack is a set of memory locations in R/W memory reserved for storing information temporarily during
the execution of a program. The statement II is true.
Q.159 Ans.(b)
MVI A, 04H ; Moves the data 04 H to accumulator, A.
RRC ; Rotates the contents of accumulator to right without
carry flag.
Before rotation :
A : 0000 0100
After rotation :
A : 0000 0010
MOV B, A ; Moves the contents of accumulator to register B.
Contents of B becomes :
B : 0000 0010
RLC ; Rotates the contents of accumulator to left without
carry flag.
Before rotation :
A : 0000 0010
After rotation :
A : 0000 0100
RLC ; Rotates the contents of accumulator to left without
carry flag.
Before rotation :
A : 0000 0100
After rotation :
A : 0000 1000
ADD B ; Adds the contents of B to A.
A : 0000 1000
+ B : 0000 0010
A : 0000 1010
RRC ; Rotates the contents of accumulator to right without
carry flag.
Before rotation :
A : 0000 1010
After rotation :
A : 0000 0101 or 05 H
So, the contents of A after execution of given set iof instructions is 05 H.
Q.160 Ans.(b)
The instruction IN <8-bit port address> accepts the data from the input port- specified in the second byte
and loads into the accumulator.
Q.161 Ans.(b)
Data transfer instructions are used to copy from the source to the destination location.
Q.162 Ans.(d)
CMA and RET are implied addressing modes of 8085.
Q.163 Ans.(b)
Contents of A : 0010 1110
Contents of C : 0110 1100
The instruction ADD C addst the contents of register C to contents of A and stores the result in A.
So, the operation of addition is as under,
0010 1110
0110 1100
1001 1010
The parity flag P is set when number of ‘1s’ in result is even number and AC flag is set when a carry is
generated while adding D3 bits of lower nibbles of the numbers. In this case a carry is generated while
adding D3 bits of both numbers so AC flag is 1 and P is also set as number of 1s in result are 4 which is even
number.
Q.164 Ans.(c)
PUSH and POP operations are performed by stack pointer register.
Q.165 Ans (a)
In immediate addressing mode, the operand is specified within the instruction itself. So, the advantage is
that the processor decodes the operand easily.
Q.166 Ans (a)
The addressing mode in which the machine language instruction itself includes the data is called immediate
addressing mode.
Q.167 Ans (b)
A. Immediate addressing is used in LXI H, 2050H.
B. Implied or implicit addressing is used in RRC.
C. Register addressing is used in MOV A, B
D. Direct Addressing used in LDA 3000 H
Q.168 Ans.(b)
Characters used in assembly language and their meaning are as under,
A. Blank is used as separator for op field and operand
B. Colon is used as end of label field
C. Semicolon is used as beginning of comment field
D. Comma is used as a separator for operand
Q.169 Ans (a)
Data transfer instruction does not affect the flags of 8085.
Q.170 Ans (a)
ANI 5CH : 8 bit data 8CH is ANDed with contents of A and result is stored in A , so,
contents of accumulator get modified.
CMP C : This instruction compares the contents of register C with the contents of
accumulator but contents of A and C remains unchanged.
CPI 3AH : This instruction compares the 8bit data 3AH with the contents of accumulator
but contents of A and C remains unchanged.
ORA A : Contents of A are ORed with contents of A itself and result is stored in A ,
but result of operation is same as contents before execution of ORA A. So,
contents of accumulator remains unchanged.
Q.171 Ans (b)
DAA instruction is used in a microprocessor to perform BCD addition.
Note : DAA instruction changes the binary values of contents of accumulator to BCD. This instruction makes use
of status of CY and AC flags. It performs the operation as follows,
II. If value of higher order four bits (D7-D4) in the accumulator is greater than 9 or if CY flag is set , the
Q.172 Ans (c)
When the RET (return) instruction is executed at the end of the subroutine the memory address stored on
the stack is retrieved and the sequence of execution (assigned to PC) is resumed in the main program. So,
RET uses the stack
Q.173 Ans (b)
INX B does not affect any of the flags of 8085.
Q.174 Ans (b)
JMP does not use stack ,whereas CALL and RET use stack.
Q.175 Ans.(b)
The instruction DAD H shifts each bit one position to left with a 0 inserted in LSB position.
Example :
Let H–L pair has 0243H
DAD H : Add contents of H–L with H–L pair
Therefore,
0243H = 0000 0010 0100 0011
+0243H = 0000 0010 0100 0011
0000 0100 1000 0110
0 4 8 6
It can be observed from result that each bit is shifted to left position with a 0 inserted in LSB.
Q.176 Ans(b)
Let A = 96H = 1001 0110
ANI 0F H ; Contents of Accumulator are ANDed with 8 bit data, 0FH and result are stored
in A.
A : 96H = 1001 0110
0FH = 0000 1111
0000 0110
Lower nibble of A remains unchanged, so it is not complemented.
XRI 0F H ; Contents of Accumulator are ExORed with 8 bit data, 0FH and result are
stored in A.
A : 96H = 1001 0110
0FH = 0000 1111
1001 1001
Lower nibble of A is complemented from 0110 to 1001 and upper nibble
remains unchanged.
ORI 0F H ; Contents of Accumulator are ORed with 8 bit data, 0FH and result are stored
in A.
A : 96H = 1001 0110
0FH = 0000 1111
1001 1111
Lower nibble of A changes from 0110 to 1111 but is not complemented.
CMA ; Complements both upper and lower order nibble of accumulator.
Q.177 Ans. (a)
The instruction “STA addr” requires 13 T-states
One T-state is precisely equal to one time period of clock signal.
1
So, Time of one T-state, T = µs
3
1
Time of 13 T-states = 13T = 13 × = 4333 ns
3
Q.178 Ans. (d)
PUSH instruction used to store contents of register pairs on top of stack is as under,
PUSH RP i. Stores the contents of register pair Rp on two
Rp→BC, DE, HL & PSW top locations of stack.
iv. Three machine cycles (OP+MW+MW) & 12 T-states
It is clear from instruction that it cannot be used for storing the data of SP and PC on top of stack.
Q.179 Ans. (a)
MVI A, 92H ; Moves 92H to register A. So, A = 92 H
ORA A ; Contents of A are ORed with contents of A itself and result is stored in A , but
result of operation is same as contents before execution of ORA A. So,
contents of accumulator remains unchanged. But flags are affected
accordingly. Here,
A = 92 H = 10010010
As D7 bit of accumulator is ‘1’ so the Sign flag is set after execution of ORA A.
JP PORT1 ; Jumps the execution of programme to PORT1 if sign flag is reset. Since
since sign flag is set by ORA A so, the execution of program will not be
jumped to PORT1 rather normal execution continues.
XRA A ; Performs XOR operation the contents of A and store result in A.
A ⊕ A : 10010010
10010010
00000000
⇒ A = 00H. Since the contents of A are 00H after execution of XRA A

instruction so zero flag is set.
OUT F2 H ; Sends contents of A(i.e. 00H) to I/O device connected at port address F2 H.
Q.180 Ans. (c)
The instruction PUSH B has register indirect addressing.
Q.181 Ans. (b)
XRA A ; The instruction XRA A performs ExOR operation on contents of A with
contents of A only and store the result in A. The instruction clears the contents
of A. So, the zero flag is set by the instruction.
LXI B, 0007H ; Loads BC pair with 16 bit data 0007 H. So, contents of BC pair becomes
0007H.
LOOP : DCX B ; Decrements the contents of BC pair by one.
JNZ LOOP ; Jumps the execution of program to LOOP if zero flag is not set.
In the above program zero flag is set when XRA A is executed and status of zero flag remains unaffected by
DCX B instruction as it does not affect the flags. So, the execution comes out of LOOP during first instance
itself as Z flag is already set. So, loop runs only once.
Q.182 Ans. (b)
LXI B, 2070 H ; Loads BC pair with 2070H. with 20H→B; 70H→C
MVI A, 8FH ; Moves 8FH to A
MVI C, 6 8 H ; Moves 68 H to C
SUB C ; Subtracts contents of C from A and store result in A.
8FH
⇒ −68H
27H
ANI 0FH
; 0FH is ANDed with contents of A(i.e.27H) and result is stored in A.
A(27H) : 00100111
0 H : 00001111
00000111
⇒ A = 07H
STAX B ; Stores the contents of ‘A’ (i.e. 07H) at address stored in BC pair (i.e. 2070 H)
So, contents of memory location 2070H after execution of program are 07H.
Q.183 Ans. (b)

Jump instruction used in 8085 microprocessor are,
i. JC : Jump on carry
ii. JNC : Jump on no carry
iii. JZ : Jump on zero
iv. JNZ : Jump on no zero
v. JP : Jump on plus
vi. JM : Jump on minus
vii. JPE : Jump even parity
viii. JPO : Jump on odd parity
ix. JMP : Unconditional Jump
No. of jump instruction = 9
No. of bytes required for each jump instruction = 3
∴ total memory bytes required by all jump instruction = 9 × 3 = 27 bytes
Q.184 Ans. (a)
In the register indirect addressing mode of 8085 microprocessor, data is stored at the address contained in
the register pair.
Q.185 Ans. (a)
Sign flag is set when bit D7 of accumulator is ‘1’ and Parity flag is set when result of arithmetic operation
has even parity. Therefore , if contents of accumulator after arithmetic operation are 10110100, both sign
and parity flags are set.
Q.186 Ans. (a)
MVI M, 8F requires both memory read and memory write machine cycles . Microprocessor first reads the
data 8F from memory and then write the same at memory location whose address stored in HL pair.
Q.187 Ans. (b)
203A MVI A, 20H ; Moves data 20 H to register A.
So, contents of A = 20 H
203C LHLD 203A H ; Loads the HL pair directly with the contents of memory location 203AH
(i.e. 3E H) and contents of next memory location, 203BH (i.e. 20H). The
contents of 203A H are loaded in L and contents of 203BH are loaded in H.
So, new contents of H & L will be, L =3EH and H =20H
ADD M ; Adds the contents of memory location whose address is stored in HL pair to
contents of accumulator. The address stored in HL pair is 203E H. So, the
contents of memory location 203E H(i.e. 20H from program) are added to A.
A : 00100000
+ B : 00100000
0 01000000
So, A = 40H & CY =0

Q.188 Ans. (a)
Given,
Contents of A = a,
Contents of B = b,
Contents of C = c,
Contents of flag register = f
Let, initially contents of SP = x
Given program,
PUSH B ; This instruction first decrements the contents of stack pointer by one to
(x − 1) and then copies the contents of B (i.e. b) on the location shown by
stack pointer (i.e x − 1). Then stack pointer register is decremented again by
one to (x − 2) and then content of C(i.e.c) are copied at (x − 2).
PUSH PSW ; This instruction first decrements the contents of stack pointer by one to
(x − 3) and then copies the contents of accumulator(i.e. a) on the location
shown by stack pointer register (i.e. x − 3). Then stack pointer register is
decremented again by one to (x − 4) and the content of flag register (i.e.f )
are copied at (x − 4) . So, the contents of stack pointer becomes (x − 4) after
execution of PUSH PSW.
POP B ; When POP B instruction is executed, two data bytes at the top of the stack are
transferred to the BC pair. The contents(i.e. f ) of the memory location
indicated by the stack pointer (i.e. x − 4) are copied in to low-order register
(e.g. register C) and then the stack pointer register is incremented by 1 to
(x − 3)and then contents(i.e. a) of memory location x − 3 are copied into
high order register (e.g. register B) and stack pointer register is again
incremented by 1 to (x − 2). So, After the execution of POP B the register B
contains ‘a’ and register C contains ‘f’.
XRA A ; The instruction XRA A performs XOR operation on contents of A with
contents of A only and store the result in A. The instruction clears the
contents of A. So, after execution of XRA A the zero flag is set by the
instruction, sign flag is reset , parity flag is set, CY and AC flags are reset.
MOV B,A ; Copies the contents of A(i.e. 0) to register B. So B = 0.
PUSH B ; This instruction first decrements the contents of stack pointer by one to
(x − 3) and then copies the contents of B (i.e. 0) on the location shown by
stack pointer (i.e x − 3). Then stack pointer is decremented again by one to
(x − 4) and then content of C(i.e.f ) are copied at (x − 4).
POP PSW ; When POP PSW instruction is executed, two data bytes at the top of
the stack are transferred to the PSW(i.e A + F). The contents(i.e. f ) of the
memory location indicated by the stack pointer (i.e. x − 4) are copied in to
low-order register (e.g. register F) and then the stack pointer register is
incremented by 1 to (x − 3)and then contents(i.e. 0) of memory location
(x − 3) are copied into high order register (e.g. register A) and stack pointer
register is again incremented by 1 to (x − 2). So, after the execution of
POP PSW the accumulator contains ‘0’ and flag register contains ‘f’.
So, after execution of program contents of registers are, A = 0 , B = 0 , C = f, F = f.
Q.189 Ans (b)
Given, contents of A = AAH
CPI 99 H ; Compares the data 99 H with contents of A . The comparison is made by
subtracting 99 H from contents of A ( i.e. AA H). The contents of A remains
unaffected but status of result is reflected by flags.
A : 1010 1010
99 H : 1001 1001
0 0001 0001
After comparison both zero flag and carry flag are reset.


Instruction set of 8085 microprocessor

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Instruction set of 8085 microprocessor

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6 Instruction Set of 8085

 Statistical Analysis of Chapter 6

6.1 Classification of Instructions

6.4 Instruction Set

7. LDA 16 bit address i. Load accumulator directly with the contents of

9. LDAX RP i. Load accumulator with contents of memory

10. STAX RP i. Store the contents of accumulator at memory

Ex 6.4 Consider the execution of the following instructions by a 8085 microprocessor :

13. SPHL i. The contents of HL pair are copied in stack

14. PCHL i. The contents of HL Pair are copied in program

1. ADD R i. Add the contents of R to A and store the result

2. ADD M i. Add the contents of memory location, whose

4. ADC R i. Add the contents of R along with carry flag to

7. DAD RP i. Add the contents of register pair Rp to contents

8. DAA i. Decimal Adjust Accumulator. Binary contents

Ex6.6 The following instructions have been executed by an 8085 microprocessor,

9. SUB R i. Subtract contents of R from contents of A and

10. SUB M i. Subtract contents of M from A and store result

12. SBB R i. Subtract the contents of R along with carry flag

13. SBB M i. Subtract the contents of M along with carry

15. INR R i. Increment contents of R by 1

16. INR M i. Increment contents of M by 1

17. DCR R i. Decrement contents of R by 1

18. DCR M i. Decrement contents of M by 1

20. DCX RP i. Decrement contents of register pair RP by 1

Ex6.8 MVI B, 00H

6.4.3 Logical Instructions

7. XRA R i. Contents of R are Ex-ORed with contents of A

10. CMA i. Compliment the contents of Accumulator

12. STC i. Set the Carry flag

13. RLC i. Rotate the contents of Accumulator to left without

14. RAL i. Rotate the contents of Accumulator to left through

15. RRC i. Rotate the contents of Accumulator to right without

16. RAR i. Rotate the contents of Accumulator to right through

Ex.6.9 An 8085 assembly language program is given below.

4: ADD B ; Adds contents of B to contents of A and result is

Ex.6.19 An Intel 8085 processor is executing the program given below.

Ex.6.20 How many time will the following loop be executed?

Ex.6.23 A part of a program written for an 8085 microprocessor is shown below.

So, now contents of HL pair becomes 200EH

OBJECTIVE TYPE PRACTICE QUESTIONS

(a) 00H (b) 10H

Q.44 A sequence of instruction is executed as follows:

Q.165 The advantages of immediate addressing is

Q.1 Ans (d)

So, A = 76H and CY = 0

From above flag register,

HLT ; Halts the execution of the program.

So, A = FF H and CY = 0 (OR instruction resets the CY flag)

So, contents of A after execution of program are 67 H.

Hardware Interrupts Software Interrupts

Thus upper nibble of A is complemented by the instruction XRI F0 H.

⇒ A = 00H. Since the contents of A are 00H after execution of XRA A

Q.183 Ans. (b)

So, A = 40H & CY =0

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Statistical Analysis of Chapter 6