Chapter 5 Bus Timings & Communication With Peripherals

5 Bus Timings & Communication
with Peripherals
Statistical Analysis of Chapter 5

Year 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20
IES(obj) 2 2 2 1 1
IES(Con) 10 15
E&T 1 1
GATE 2 2
3
IES(obj) 1 2 1 2 2 2 4 2
IES(Con) 10 25 8
EE 1 2
GATE
2
IAS (mains) 12 26 20
IN GATE 2
* Number in box is no. of Questions for IES (obj) and marks for all other exams
Conclusion
This chapter is important for objective and conventional papers of
Engineering Services Examination of both Electronics and Electrical
Engineering.
5.1 Introduction
This chapter explains how a microprocessor communicates with the memory and I/O devices. The bus
timing with respect to changes in the signals has been explained in detail. Time required for various
operation has explained for various instruction.
5.2 T-State
It is the part of operation performed in one clock cycle. One T-state is precisely equal to one clock period.
5.3 Machine Cycle

It is time required by the microprocessor for performing one reading, writing or acknowledgment operation
with memory or external peripherals . One machine cycle indicates one operation of accessing the memory
or other peripherals. One machine cycle may consists of 3 to 6 T-states.
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Bus Timings & Communication with Peripherals [2]
5.3.1 Types of Machine Cycle in 8085
i. Op-code Fetch Cycle
It is operation of fetching of Op-code from the memory. Op-code fetch cycle may consist of 4 to 6
T-states. Very first cycle of a program and very first cycle of each instruction is Op-code fetch cycle.
ii. Memory Read Cycle
The memory read cycle is an operation of reading the data from the memory. It requires three T-states.
iii. Memory Write Cycle
It is the operation of writing the data on the memory. It requires three T-states.
iv. I/O Read Cycle
It is the reading of the data from the I/O device. It requires three T-states.
v. I/O Write Cycle
It is the operation of writing the data on the I/O device. It requires three T-states.
5.3.2 Difference between Op-code Fetch and Memory Read Cycles
Op-code Fetch Memory Read Cycles
1. It is the fetching of instruction code 1. It is the reading of the data from
from the memory memory
2. S0 = 1 , S1 = 1 2. S1 = 1, S0 = 0
3. It requires 4 to 6 T-states. 3. It requires 3T-states.
5.4 Instruction Cycle

It is the total time required to execute an instruction. The instruction cycle includes the operation of fetching,
decoding and execution of an instruction. An instruction cycle may consists of 1 to 5 machine cycles.
5.5 Interrupt Acknowledgment Cycle

It is the cycle of acknowledgment of interrupt request , INTR, of 8085. It is the cycle which requires 3
machine cycles and 12 T-states.
5.6 Communication With Memory

Communication of microprocessor involves reading from or writing the data into the memory. Every
operation of processor with memory is done in relation to the system clock. Data flow diagram of figure
4.1 shows how a data byte is transferred from memory to the MPU. The timing diagram has five different
signals in relation to the system clock. Ex.5.1 given below illustrate the steps and timing of data flow when
instruction code of MOV H,D stored at 2000 H is fetched from memory.
Ex.5.1 2000 H MOV H, D

Instruction : MOV H, D
Starting Address : 2000 H
Instruction Code : 62 H
Function Performed : Moves the contents of ‘D’ to register ‘H’.
Data Flow :
62 01100010
Data Bus
Memory
Internal Data Bus 1FFF
Instruction
Decoder
Flag 2000
B C
Accumulator Flip-
Flops D E 0 1 1 0 0 0 10
H L
Arithmetic/Logic Unit SP
PC
Control
Unit
2000
Address Bus
Control Signals
MEMR 62
8085
Microprocessor
Fig. 5.1 Memory Read Cycle

Sequence of Events:
Step-I At T1 the microprocessor identifies that it is an Op-code Fetch Cycle and make the status signals
IO /=
M 0,S = 1 1andS
= 0 1 . The microprocessor places the 16-bit memory address 2000 H from
program counter (PC) on the address bus with 20H on A15-A8, and 00H on AD7-AD0 and increments
the program counter to 2001H to point to the next machine code. The ALE signal goes low at end
of T1, which is used to latch the low-order address 00H from the bus AD7-AD0.
Step-II At T2 the 8085 makes control signal RD = 0, which enables the memory and the memory places
the byte 62H from location 2000H on the data bus.
Step-III Then the 8085 places the op-code in the instruction register and disables the RD signal. The fetch
cycle is completed in state T3.
M1 (Opcode Fetch)
T1 T2 T3 T4
CLK
A15-A8 High-Order
20H Memory Unspecified
Address
AD7-
00H 62H Opcode
AD0 Low-Order
Memory
Address
ALE
IO/M Status IO/M=0, S1=1, S0=1 Opcode
Fetch
S1,S0
RD
Fig. 5.2 Bus Timing of Op-code Fetch Cycle

Step-IV D
uring T4, the 8085 decodes the op-code and passes the information to control unit which
establishes the necessary connections for moving the data of register ‘D’ to ‘H’ which in turn
completes the operation of moving the contents of register ‘D’ to register ‘H’.
• Let Clock frequency f = 5 MHz
• T-state = clock period (1/f) = 0.2 µs
• Execution time for Op-code Fetch: (4 T) × 0.2 = 0.8 µs
• Execution time for Instruction : (4 T) × 0.2 = 0.8 µs
Ex. 5.2 5000 H ADI 6AH
Instruction : ADI 6AH
Starting Address : 5000H
Instruction code : C6 H
Function performed : Adds 8 bit data 6AH to contents of
accumulator ‘A’ and stores the result in ‘A’.
Sequence of Events:
IO /=
M 0,S = 1 1andS
the program counter to 5001H to point to the next machine code. The ALE signal goes low at the
end of T1, which is used to latch the low-order address 00H from the bus AD7-AD0.
M1 (Opcode Fetch) M2 (Memory Read)

T1 T2 T3 T4 T1 T2 T3
CLK
A15-A8 High-Order High-Order

50H Unspecified 50H Memory Address
Memory Address
AD7-
00H C6H Opcode 01H 6AH Data
AD0
Low-Order Low-Order
Memory Memory
Address Address
ALE
IO/M
Status IO/M=0, S1=1, S0=1 Opcode
Fetch
S1,S0
RD
Fig. 5.3 Bus Timing of Memory Read Cycle

Step-II At T2, the 8085 makes control signal RD = 0, which enables the memory and the memory places
the byte C6H from location 5000H on the data bus.
Step-III Then the 8085 places the op-code in the instruction register and disables the RD signal. The fetch
cycle is completed in state T3. After the T3 state, the contents of the bus A15-A8 are unknown, and
the data bus AD7-AD0 goes into high impedance.
Step-IV D
uring T4, the 8085 decodes the op-code and passes the information to control unit which
establishes the necessary connections for adding data of next memory location 5001H to contents
of A. During T4, while decoding the op-code the microprocessor finds out that a second byte needs
to be read from next memory location.
Step-V After completion of the Op-code Fetch Cycle, the 8085 places the address 5001 H on the address
bus and increments the program counter to the next address 5002H. The second machine cycle M2
is identified as the Memory Read Cycle ( IO / M = 0, S1 = 1, S0 = 0) and the ALE is made high.
Step-VI At T2, the RD signal becomes low and enables the memory chip. At the rising edge of T2, the 8085
activates the data bus as an input bus, memory places the data byte 6A H on the data bus, and the
8085 reads and adds the 6AH to contents of the accumulator during T3.
• Execution time for Opcode Fetch: (4 T) × 0.2 = 0.8 µs
• Execution time for Memory Read: (3T) × 0.2 = 0.6 µ s
• Execution time for Instruction : (7T) × 0.2 = 1.4 µ s
Note :- i. Decoding and internal connections are made during last T-state of Op-code fetch cycle.
ii. The memory read cycle requires 3T-states and similarly memory write cycle also requires 3T-states.
5.7 I/O Devices and Their Communication with Microprocessor

Input/output devices are the means through which the MPU accepts binary data as input from devices such
as keyboards and A/D converters and sends data to output devices such as LEDs or printers. There are 2
types of I/O devices used in 8085:
i. Memory mapped I/O devices
ii. Peripheral mapped or I/O mapped I/O devices
5.7.1 Memory mapped I/O devices
The memory mapped I/O devices are identified just like a memory location. Microprocessor uses same
control signals and instructions as those used for memory. The devices are identified with the 16 bit address
and, therefore, 216 (64K) different memory mapped I/O devices can be identified by 8085 µP.
Instructions used for data transfer between memory mapped I/O devices and microprocessor are same as
the instructions used for data transfer between memory and microprocessor.
e.g. LDA, STA, MOV M, ADD M etc.
5.7.2 Peripheral mapped or I/O mapped I/O devices
The peripheral mapped I/O devices are identified with 8 bit port address. Therefore, 28 (i.e.256) different
input or 28 (i.e.256) different output peripheral mapped I/O devices, with addresses ranging from 00H to
FFH , can be identified by 8085. During the reading and writing operation of I/O devices the same port
address is placed on higher order as well as lower order address lines, therefore, the device can be identified
or connected either at higher order address lines or at the lower order address lines but the data lines of the
device must be connected to the lower order address lines only.
The input and output devices are differentiated by the control signals; the MPU uses the I/O Read control
signal for input devices and the I/O Write control signal for output devices. The entire range of I/O addresses
from 00 to FF is known as an I/O map, and individual addresses are referred to as I/O device addresses or
I/O port numbers.
Note : i. Input port and an output port can have the same port address. They are differentiated by control signals.
The RD is used to enable the input port and the WR is used to enable the output port.
ii. Memory mapped and I/O or peripheral mapped devices are differentiated by control signals. If the
control signal is IOW (or IOR ), it mustbe a peripheral I/O, and if the control signal is MEMW (or
MEMR ), it must be a memory-mapped I/O .
iii. In memory-mapped I/O, the microprocessor cannot differentiate between an I/O and memory; it treats
an I/O as if it is memory. Therefore, an I/O and memory register cannot have the same address; the
entire memory map (64K) of the system has to be shared between memory and I/O.
5.7.3 Instructions Related to Peripheral mapped I/O devices

1. IN 8 bit port address : This instruction is used for reading data into accumulator from I/O mapped I/O
device connected at 8bit port address given in the instruction.
Ex. 5.3 3000 H IN 08H
Instruction : IN 08H
Starting Address : 3000H
Instruction code : DBH
Function performed : Moves the contents of IO mapped IO device
connected at 08H to accumulator.
Sequence of Events:
Step-I At T1 the microprocessor identifies that it is an Opcode Fetch cycle and make the status signals
IO /=
M 0,S = 1 1andS
the program counter to 3001H to point to the next machine code. The ALE signal goes low at end of
T1, which is used to latch the low-order address 00H from the bus AD7-AD0.
Step-II At T2, the 8085 makes control signal = 0, which enables the memory and the memory places
the byte DBH from location 3000H on the data bus.
Step-III Then the 8085 places the Op-code in the instruction register and disables the signal. The fetch
cycle is completed in state T3. After the T3 state, the contents of the bus A15-A8 are unknown, and
the data bus AD7-AD0 goes into high impedance.
Step-IV D
uring T4, the 8085 decodes the Op-code and passes the information to control unit which
establishes the necessary connections. During T4, while decoding the opcode the microprocessor
finds out that a second byte needs to be read from next memory location.
Step-V After completion of the Op-code Fetch cycle, the 8085 places the address 3001 H on the address
bus and increments the program counter to the next address 3002H. The second machine cycle M2
is identified as the Memory Read cycle ( = 0, S1 = 1, and S0 = 0) and the ALE is made high.
Step-VI At T2, the signal becomes low and enables the memory chip. At the rising edge of T2, the 8085
activates the data bus as an input bus, memory places the data byte 08H on the data bus.
Step-VII During T1 of machine cycle M3 , the microprocessor places the address 08H of input device on
low order as well as high order address buses. The third machine cycle M3 is identified as the I/O
Read cycle ( = 1, S1 = 1, and S0 = 0) and the ALE is made high.
M1 (Opcode Fetch) M2 (Memory Read) M3 (I/O read)

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
CLK
A15-A8 High-Order
30H Memory High-Order Port
Address
Unspecified 30H memory Address 08H Address
Low-Order Low-Order
Ad7- Memory Address Memory Address
Port Address Data from
00H DBH Opcode 01H 08H 08H input port
AD0
I.O port
Address
ALE
IO/M
S1
S0
RD
Step-VIII At T2, the signal is made low which enables the I/O device. At the rising edge of T2, the
8085 activates the data bus as an input bus, I/O device places the data byte on the data bus
• Execution time for Opcode Fetch: (4 T) × 0.2 = 0.8 µs
• Execution time for Memory Read: (3T) × 0.2 = 0.6 µ s
• Execution time for I/O Read: (3T) × 0.2 = 0.6 µ s
• Execution time for Instruction : (10T) × 0.2 = 2 µ s
2. OUT 8 bit port address : This instruction is used for writing data from accumulator on I/O mapped
I/O device connected at 8 bit port address given in the instruction.
Note: 1. In the above instructions the data is always communicated between accumulator and I/O devices.
2. IN instruction requires three machine cycles i.e. Opcode fetch + memory read + I/O read and 10
T-states.
3. OUT instruction requires three machine cycles i.e. Op-code fetch + Memory read + I/O write and 10
T-states.
Table 5.1 Comparison of Memory-Mapped I/O and Peripheral I/O devices
Characteristics
Memory-Mapped I/O Peripheral I/O

1. Device address 16-bit 8-bit
2. Control signals MEMR / MEMW IOR / IOW
for Input/Output
3. Instruction Memory-related IN and OUT available
instructions such as STA;
LDA; LDAX; STAX;
MOV M.R; ADD M;
SUB M; ANA M etc.
4. Data transfer Between any register Only between I/O and the
and I/O accumulator
5. Maximum The momory map (64K) The I/O map is independent
number of I/Os is shared between I/Os of the memory map; 256
possible devices and system memory input devices and 256 output
can be connected
6. Execution speed 13 T-states (STA,LDA) 10-T-states
7 T-states (MOV M,R)
7. Hardware More hardware is needed Less hardware is
requirements to decode 16-bit address needed to decode 8-bit address
8. Other features Arithmetic or logical Not available
operations can be
directly performed with
I/O data

OBJECTIVE TYPE PRACTICE QUESTIONS
GATE QUESTIONS
Q.1
A snapshot of the address, data and control buses of an 8085 microprocessor executing a program is given
below:
Address 2020H
Data 24H
IO / M Logic High
RD Logic High
WR Logic Low
The assembly language instruction being executed is
(a) IN 24H (b) IN 20H
(c) OUT 24H (d) OUT 20H
GATE(IN,07)
Q.2 In an 8085 microprocessor system with memory mapped I/O,
(a) I/O devices have 16-bit addresses
(b) I/O devices are accessed using IN and OUT instructions
(c) There can be a maximum of 256 input devices and 256 output devices
(d) Arithmetic and logic operations can be directly performed with the I/O data.
GATE(EC,92)
Q.3 An 8085 microprocessor executes “STA 1234H” with starting address location 1FFEH (STA copies the
contents of the Accumulator to the 16-bit address location). While the instruction is fetched and executed,
the sequence of values written at the address pins A8 – A15 is
(a) 1FH, 1FH, 20H, 12H (b) 1FH, FEH, 1FH, FEH, 12H
(c) 1 FH, 1FH, 12 H, 12 H (d) 1 FH, 1FH, 12 H, 20 H, 12 H
GATE(EC-IV/2014/2M)
Q.4 The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is
1.4 µs then the number of T-states needed for executing the instruction is s,.
(a) 1 (b) 6
(c) 7 (d) 8
GATE (EC-I/2017/1M)
IES QUESTIONS
Q.5 In 8085, if the clock frequency is 5 MHz, the time required to execute an instruction of 18 T-states is
(a) 3.0 µ s (b) 3.6 µ s
(c) 4.0 µ s (d) 6.0 µ s
IES (E&T,08)
Q.6 Consider the following read and Write cycles:
Clock Clock
Address Address
Valid address Valid address
Read Write
Data Valid Data Valid
1. data 2. data
Clock Clock
Address Address
Valid address Valid address
Read Write
Data Valid Data Valid
3. data 4. data
The combinations of read and write cycles of a typical microprocessor would include
(a) 1 and 2 (b) 1 and 4
(c) 2 and 3 (d) 3 and 4
IES(E&T,91)
Q.7 The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of the following ?
(a) Clock cycle (b) Memory cycle
(c) Machine cycle (d) Instruction cycle
IES(EE,07)
Q.8 In an Intel 8085A, which is always the first machine cycle of an instruction ?
(a) An op-code fetch cycle (b) A memory read cycle
(c) A memory write cycle (d) An I/O read cycle
IES(EE,08)
Q.9 After an operation code has been fetched, which one of the following is the next process that takes place?
(a) Reading the operands (b) Displaying the result
(c) Decoding the opcode (d) Clearing the accumulator
IES(EE,93)
Q.10 Consider the following figure showing clock period of Instruction Fetch machine cycle for INTEL 8085:
MC1 MC2
T1 T2 T3 T4
10/M
S0
S1
RD
ALE
An ERROR in the above diagram relates to the signal

(a) IO / M (b) SO
(c) S1 (d) R D
IES(EE,97)
Q.11 Consider the following features in an 8085 microprocessor system with memory mapped
I/O :
1. I/O devices have 16-bit addresses
2. I/O devices are accessed using IN and OUT instructions
3. There can be maximum of 256 input devices and 256 output devices
4. Arithmetic and logic operations can be directly performed with the I/O data
Select the correct answer using the codes given below:
Codes:
(a) 1,2 and 4 (b) 1,3 and 4
(c) 2 and 3 (d) 1 and 4
IES(E&T,03)
Q.12 Memory-mapped I/O scheme for the allocation of address to memories and I/O devices, is used for
(a) small systems (b) large systems
(c) both large and small systems (d) very large systems
IES(EE,02)
Q.13 What is the total number of memory locations and input-output devices that can be addressed with a
processor having 16-bits address bus, using memory mapped I/O?
(a) 64 K memory locations and 256 I/O devices
(b) 256 I/O devices and 65279 memory locations
(c) 64 K memory locations and no I/O devices
(d) 64 K memory locations or I/O devices
IES(EE,04)
Q.14 Consider the following statements :
1. Indirect addressing is not possible for I/O mapped I/O port addresses.
2. Pointers cannot be used to access memory mapped I/O addresses.
3. Fewer Machine instructions can be used with I/O mapped I/O addressing as compared to memory
mapped I/O addressing.
4. With an 8085 microprocessor, one can access at the most 512 devices with unique addressing using I/O
mapped I/O addressing.
Which of the statements given above are correct?
(a) 1, 2 and 3 (b) 2 and 4
(c) 3 and 4 (d) 1 and 3
IES(EE,06)
Q.15 The first machine cycle of an instruction is always:
(a) A memory read cycle (b) A fetch cycle
(c) An I/O read cycle (d) A memory write cycle
IES(EE,11)
Q.16 The correct sequence of steps in the instruction cycle of a basic computer is
(a) Fetch, Execute, Decode and Read effective address
(b) Read effective address, Decode, Fetch and Execute
(c) Fetch, Decode, Read effective address and Execute
(d) Fetch, Read effective address, Decode and Execute
IES(EE,12)
Q.17 The sub-system which ensures that only one I/O device is active at a time to avoid a bus conflict caused by
two I/O devices writing different data to the same bus is
(a) Control bus (b) Control instructions
(c) Address decoder (d) Priority encoder
IES(EE, 12)
Q.18 Number of address lines necessary to connect 8 k memory chip is
(a) 10 (b) 11
(c) 12 (d) 13
IES(EE,12)
Q.19 An 8085 microprocessor based system uses a 4K× 8-bit RAM whose starting address is AA00H. The
address of the last byte in this RAM is
(a) 0FFFH (b) 1000H
(c) B9FFH (d) BA00H
IES(EE, 12)
Q.20 A memory system has a total of 8 memory chips, each with 12 address lines and 4 data lines. The size of the
memory system is
(a) 16 k bytes (b) 32 k bytes
(c) 48 k bytes (d) 64 k bytes
IES(E&T,12)
Q.21 For Opcode fetch operation in 8085 microprocessor
(a) S1 = 0, S2 = 1, RD = 0, ALE high in T1

(b) S1 = 1, S2 = 1, RD = 0, ALE high in T1
(c) S1 = 1, S2 = 1, RD = 0, ALE high in T2

(d) S1 = 0, S2 = 1, RD = 0, ALE high in T2
IES(E&T,12)
Q.22 In a 8085 microprocessor system with memory mapped I/O, which of the following is true?
(a) Devices have 8-bit address line
(b) Devices are accessed using IN and OUT instructions
(c) There can be maximum of 256 input devices and 256 output devices
(d) Arithmetic and logic operations can be directly performed with the I/O data
IES(EE,13)
Q.23 I/O mapped system identify their input/output devices by giving them an :
(a) 8 bit port number (b) 16 bit port number
(c) 8 bit buffer number (d) 16 bit buffer number
IES(EE,13)
Q.24 In 8085 microprocessor with memory mapped I/O, which one of the following is correct?
(a) I/O devices have 16 bit addresses
(b) I/O devices are accessed during IN and OUT instructions
(c) There can be a maximum of 256 input and 256 output devices
(d) Logic operations cannot be performed
IES(EE,15)
Q.25 In a microprocessor system with memory mapped I/O
(a) Devices have 8-bit addresses
(b) Devices are accessed using IN and OUT instructions
(c) There can be a maximum of 256 input devices and 256 output devices
(d) Arithmetic and logic operations can be directly performed with the I/O data
IES(E&T,15)
Q.26 The relation among IC (Instruction Cycle), FC (Fetch Cycle) and EC (Execute Cycle) is
(a) IC = FC − EC (b) IC = FC + EC
(c) IC = FC + 2EC (d) EC = IC + FC
IES(EE,15)
Q.27 The correct instruction execution sequence is
(a) Execute, Decode and Fetch (b) Fetch, Execute and Decode
(c) Execute, Fetch and Decode (d) Fetch, Decode and Execute
IES(E&T,15)
Q.28 At the beginning of a fetch cycle, the contents of the program counter are
(a) Incremented by one (b) Transferred to address bus
(c) Transferred to memory address registers (d) Transferred to memory data register
IES(EE,15)
Q.29 During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)?
(a) T1 OP code Fetch (b) T2 OP code Fetch
(c) T3 OP code Fetch (d) T4 OP code Fetch
IES(EE,15)
Q.30 When a peripheral is connected to the microprocessor in input/output mode, the data transfer takes place between
(a) any register and I/O device (b) memory and I/O device
(c) accumulator and I/O device (d) HL register and I/O device
IES(EE,16)
Q.31 While execution of I/O instruction takes place, the 8-bit address of the port is placed on
(a) lower address bus (b) higher address bus
(c) data bus (d) lower as well as higher order address bus
IES(EE,16)
Q.32 An addressing mode in which the location of the data is contained within the mnemonic, is known as
(a) Immediate addressing mode (b) Implied addressing mode
(c) Register addressing mode (d) Direct addressing mode
IES(E&T,16)
Q.33 The maximum number of input or output devices that can be connected to 8085 microprocessor are
(a) 8 (b) 16
(c) 40 (d) 256
IES (EE, 2019)
MISCELLANEOUS QUESTIONS
Q.34 An 8085 µP uses a crystal of frequency 6.25 MHz. The time of one T state will be :
(a) 320 ns (b) 640 ns
(c) 960 ns (d) 1280 ns
UPPCS(2003)
Q.35 The duration of one T-state in the 8085 microprocessor that uses a crystal of 5.00 MHz is
(a) 0.2 µs (b) 0.4 µs
(c) 2.5 µs (d) 5.0 µs
BSNL-JTO(EE,09)
Q.36 A microprocessor using a 3 MHz clock has three ‘T’ states in each machine cycle. If an instruction cycle
needs 4 machine cycles, how much time will be taken to complete the execution of this instruction ?
(a) 333 ns (b) 1333 ns
(c) 1µ s (d) 4 µ s
IAS(2005)
Q.37 An instruction cycle is the time in which, a hard-wired controller completes four functions. What is the
correct sequence of these functions ?
(a) Fetch-update-decode-execute (b) Fetch-decode-update-execute
(c) Decode-execute-fetch-update (d) Execute-decode-fetch-update
IAS (2005)
Q.38 In 8085 microprocessor , the I/O devices can be used in :
(a) Memory mapped I/O only (b) I/O mapped I/O only
(c) Memory mapped I/O or I/O mapped I/O (d) None of these
UPPSC(2000)
Q.39 In a 8085 microprocessor based system, the maximum number of memory and I/O devices that can be
addressed to
(a) 28 (b) 216
(c) 28 +216 (d) infinite
(2002/EE/1A(f)/2)
Q.40 In connection with memory mapped I/O which one of the following statements is NOT true?
(a) The processor treats an interface register as a part of the memory system.
(b) It reduces the memory space available.
(c) The processor cannot manipulate I/O data residing in interface registers with the same instructions that
are used to manipulate memory location.
(d) Arithmetic or logical operation can be directly performed with I/O data.
BSNL-JTO(TC,09)
ANSWERS AND EXPLANATIONS

Q.1 Ans.(d)
IO / M : Signal IO / M is used to differentiate the microprocessor and I/O related operation. When signal
of this pin is high that indicates that operation is being performed with I/O device.
RD : Signal RD is used to perform reading operation with either memory or I/O device. This is active
low signal.
WR : Signal WR is used to perform writing operation with either memory or I/O device. This is active
low signal.
When processor performs reading or writing operation with I/O mapped I/O device , the device is identified
with 8 bit port address, placed simultaneously on lower and higher order buses.
Given,
Address 2020H
Data 24H
IO / M Logic High
RD Logic High
WR Logic Low
Above combination of control signals indicates that the processor writes 8 bit data 24 H stored in accumulator
on I/O device connected at 8 bit port address 20 H. The instruction used for the same purpose is OUT 20H.
Q.2 Ans (a, d)
In an 8085 microprocessor system with memory mapped I/O, I/O devices have 16-bit addresses and
arithmetic or logical operation can be directly performed with I/O data.
Q.3 Ans. (a)
The STA 1234 H stores the contents of accumulator(A) at memory addrress 2300H. Opcode of STA 1234H
is stored at address 1FFEH. Let XX is opcode of instruction. The location 1FFEH has XX , 1FFFH has 34H
and 2000H has 12H. The timing diagram and sequence of events are as follows,
M1 (Opcode Fetch) M2 (Memory Read) M3 (Memory read) M4 (Memory write)
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3
CLK
A15-A8 High-Order
1FH Memory Unspecified High-Order
1FH memory High-Order
20H memory High-Order
12H memory
Address Address Address Address
Low-Order Low-Order Low-Order Low-Order
AD7- Memory Address Memory Address Memory Address Memory Address
34H Data from
FEH XX Opcode FFH 34H 12H 23H A to 2300H
AD0
ALE
IO/M
S1
S0
RD
WR
Sequence of Events:
Step-I At T1 the microprocessor identifies that it is an Opcode Fetch cycle and make the status signals
IO /=
M 0,S = 1 1andS
= 0 1 . The microprocessor places the 16-bit memory address 1FFE H from
program counter (PC) on the address bus with 1FH on A15-A8, and FEH on AD7-AD0 and
increments the program counter to 1FFFH to point to the next machine code. The ALE signal
goes low at end of T1, which is used to latch the low-order address FEH from the bus AD7-AD0.
Step-II At T2, the 8085 makes control signal RD = 0, which enables the memory and the memory
places the byte XXH from location 1FFEH on the data bus.
Step-III Then the 8085 places the opcode in the instruction register and disables the RD signal. The
fetch cycle is completed in state T3. After the T3 state, the contents of the bus A15-A8 are unknown,
and the data bus AD7-AD0 goes into high impedance.
Step-IV During T4, the 8085 decodes the opcode and passes on the information to control unit which
establishes the necessary connections . During T4, while decoding the opcode the microprocessor
finds out that it has to read data from a memory location whose address is to be read from next
two memory locations.
Step-V uring machine cycle M2 microprocessor reads lower order byte of address (i.e. 34H) from next
D
memory location 1FFFH
Step-VI During machine cycle M3 microprocessor reads higher order byte of address (i.e. 12H) from next
memory location 2000H.
Step-VII During of machine cycle M4 , the microprocessor places the address 1234H on address lines and
then writes the data at 1234H. The four machine cycle M4 is identified as the memory write
cycle ( IO / M = 0, S1 = 0, and S0 = 1).
Thus, while the given instruction is fetched and executed, the sequence of values written at the address pins
A15 – A8 is 1F,1F,20H,12H
Q.4 Ans. (c)
Time period of one T-state,
1 1
T = = = 0.2µs
Clock frequency 5 MHz
The number of T-states required for execution of instruction requiring time of 1.4 µs will be given as,
total time
No. of T-states =
T
1.4
= = 7 T-states
0.2
Q.5 Ans(b)
One T state is precisely equal to one time period of clock signal.
1
So, time of one T-state, T = µs
5
1
Time of 18 T-states = 18T = 18 × =3.6 µ s
5
Q.6 Ans (b)

Case-I: Memory read cycle of microprocessor :
Clock
Address
Valid address
Read
Data Valid
data
Steps for reading data from memory:
Step-I : Place 16 bit valid address on address lines.

Step-II : Give the read command to read data from memory.

Step-III: Data is available on data lines.

Case-II: Memory write cycle of microprocessor:
Clock
Address
Valid address
Write
Data Valid
data
Steps for writing data on memory:
Step-I : Place 16 bit valid address on address lines.

Step-II : Send the data on data lines.

Step-III: Give the write command to write data on memory

Q.7 Ans(d)
The cycle required to fetch and execute an instruction in a 8085 microprocessor is Instruction cycle.
Q.8 Ans.(a)
The first machine cycle of an instruction is always an Opcode fetch cycle. The opcode fetch cycle is called
the M1 cycle and may have 4T to 6T states.
Q.9 Ans (c)
When an instruction is fetched from memory, it is loaded in the instruction register. Then instruction
decoder decodes the instruction and establishes the sequence of events to follow.
Q.10 Ans (c)
The first machine cycle is always opcode fetch cycle with S1 = 1 & S0=1. Given figure has S1 = 0 which is
an error.
Note : Status signals for various operations are as under,
IO / M S1 S 2 Machine Cycle
0 1 1 Opcode Fetch
0 1 0 Memory Read
0 0 1 Memory write
1 1 1 Interrupt Acknowledge
1 1 0 I/O Read
1 0 1 I/O Write
Q.11 Ans (d)

Facts about memory mapped I/O:
1. I/O devices are identified with 16-bit addresses just like a memory location.
2. I/O devices are accessed using same instructions which are used to access memory locations. IN and
OUT instructions are used to access I/O mapped I/O devices.
3. There can be maximum of 216 or 64 K memory mapped I/O devices which can be identified with 8085
microprocessor.
4. Arithmetic and logic operations can be directly performed with the I/O data in memory mapped I/O
devices. But in case of I/O mapped I/O devices data is first store in accumulator and only then arithmetic
or local operation can be performed.
So, statements 1 and 4 are true.
Q.12 Ans (a)
Memory mapped I/O is used for small systems.
Q.13 Ans (d)
A microprocessor having 16-bits address bus can identify 64 K memory locations or memory mapped I/O
devices.
Q.14 Ans.(d)
Facts about I/O devices,
1. Indirect addressing is not possible for I/O mapped I/O port addresses.
2. Pointers can be used to access memory mapped I/O addresses.
3. Fewer Machine instructions can be used with I/O
mapped I/O addressing as compared to memory mapped I/O addressing.
4. With an 8085 microprocessor, one can access at the most 2 (=256)devices with unique addressing
8
using I/O mapped I/O addressing.

Q.15 Ans (b)
The first machine cycle of an instruction is always an Opcode fetch cycle. The opcode fetch cycle is called
the M1 cycle and may have 4T to 6T states.
Q.16 Ans(c)
The correct sequence of steps in the instruction cycle of a basic computer is
Step-I: Fetch the code from memory
Step-II: Update the programme counter
Step-III: Decode the instruction code
Step-IV: Execute the instruction.
Q.17 Ans(c)
The sub-system which ensures that only one I/O device is active at a time to avoid a bus conflict caused by
two I/O devices writing different data to the same bus is Address decoder.
Q.18 Ans(d)
Size of memory is defined as 2n×m bits, where, ‘m’ is number of data lines and ‘n’ is number of address
lines.
Given , 8K memory means 8K bytes of memory. That is a memory with 8 data lines. And 1 K bytes of
memory means 1024 bytes of memory.
⇒ 8 K bytes = 8 × 1024 bytes =8192 bytes
= 213 × 8 bits = 2n×m bits
Thus 13 address lines will be required to address a 4K memory.
Q.19 Ans(c)
Size of 4K×8 memory is 4K bytes or 4096 bytes. In hexadecimal code 4096 bytes = 1000H
The last address in RAM with AA00H as starting address will be AA00 H + 0FFF H =
B9FF H
Q.20 Ans(a)
Size of memory is defined as 2n × m bits, where, ‘m’ is number of data lines and ‘n’ is number of address
lines.
Given , n = 12 and m = 4 , so size of each memory chip will be 212 × 4 bits = 2 kbytes. So, the total size of
8 chips will be 16 kbytes.
Note: 1 K bytes of memory means 1024 bytes of memory.
Q.21 Ans(b)
The status of signal during opcode fetch machine cycle of an instruction of 8085 is shown in the figure
below,
Step-I : At T1 the microprocessor identifies that it is an Op-code Fetch Cycle and make the signals
ALE = 1, IO /=
M 0,S= 1 1andS
= 0 1 . The microprocessor places the higer order byte of program
counter (PC) on the address lines A15-A8, and lower order data of PC on AD7-AD0 and increments
the program counter to next address. The ALE signal goes low at end of T 1, which is used to
latch the low-order address from the bus AD7-AD0.
Step-II : At T2 the 8085 makes control signal RD = 0, which enables the memory and the memory places
the opcode from current location on the data bus.
Step-III : Then the 8085 places the op-code in the instruction register and disables the RD signal. The
fetch cycle is completed in state T3.
Step-IV : During T4, the 8085 decodes the op-code and passes the information to control unit which
establishes the necessary connections for operation to be performed.
M1 (Opcode Fetch)
T1 T2 T3 T4
CLK
A15-A8 High-Order Unspecified

Memory Address
AD7-
Opcode
AD0 Low-Order
Memory
Address
ALE
IO/M Status IO/M=0, S1=1, S0=1 Opcode
Fetch
S1,S0
RD
Fig. Bus Timing of Op-code Fetch Cycle

Q.22 Ans (d)
Facts about memory mapped I/O and I/O mapped I/O devices of 8085 microprocessor system
i. Memory mapped devices have 16-bit address line just like a memory location. 8 bit address is used for
I/O mapped I/O device.
ii. Memory mapped devices are accessed using same set of instructions which are used for accessing a
memory location. The IN and OUT instructions are used for data transfer with I/O mapped I/O device.
iii. There can be maximum of 216 different input and output devices which can be identified with memory
mapped devices. Where as in I/O mapped I/O devices it is 256 input or output devices which can be
identified.
iv. Arithmetic and logic operations can be directly performed with the I/O data in case memory mapped
devices which is not possible in case I/O mapped I/O devices. But in case of I/O mapped I/O devices
data is first store in accumulator and only then arithmetic or local operation can be performed.
Q.23 Ans (a)
I/O mapped system identify their input/output devices by giving them an 8 bit port number.
Q.24 Ans (d)
microprocessor.
So, option (d) is correct.
Q.25 Ans (d)
microprocessor.
So, option (d) is correct.
Q.26 Ans (b)
The relation among IC (Instruction Cycle), FC (Fetch Cycle) and EC (Execute Cycle) is,
IC = FC + EC
Q.27 Ans (d)
The correct sequence of steps in the instruction cycle of a basic computer is
Step-I: Fetch the code from memory
Step-II: Update the program counter
Step-III: Decode the instruction code
Step-IV: Execute the instruction.
Q.28 Ans (b)
At the beginning of a fetch cycle, the contents of the program counter are transferred to address bus.
Steps of OP code fetch cycle are,
IO /=
M 0,S = 1 1andS
= 0 1 . The microprocessor places the 16-bit memory address from program
counter (PC) on the address bus. The ALE signal goes low at end of T1, which is used to latch
the low-order address.
the data from memory on the data bus.
Step-III Then the 8085 places the op-code in the instruction register and disables the RD signal. The
Step-IV During T4, the 8085 decodes the op-code and passes the information to control unit which
establishes the necessary connections for completion of of operation.
Q.29 Ans (c)
During which T-state, contents of OP code from memory are loaded into IR T3 OP code Fetch.
Steps of OP code fetch cycle are,
IO /=
M 0,S = 1 1andS
= 0 1 . The microprocessor places the 16-bit memory address from program
counter (PC) on the address bus. The ALE signal goes low at end of T1, which is used to latch
the low-order address.
the data from memory on the data bus.
Step-III Then the 8085 places the op-code in the instruction register and disables the RD signal. The
Step-IV During T4, the 8085 decodes the op-code and passes the information to control unit which
establishes the necessary connections for completion of operation.
Q.30 Ans(c)
When a peripheral is connected to the microprocessor in input/output mode, the data transfer takes place
between accumulator and I/O device.
Q.31 Ans(d)
While execution of I/O instruction takes place, the 8-bit address of the port is placed on lower as well as
higher order address bus.
Q.32 Ans(b)
An addressing mode in which the location of the data is contained within the mnemonic, is known as
implied addressing mode.
Q.33 Ans.(d)
The maximum number of input or output devices that can be connected to 8085 microprocessor are 28 or
256.
Q.34 Ans (a)
The frequency of crystal is divided by two internally. So the frequency of clock will be 3.125 MHz. One T
state is precisely equal to one time period of clock signal.
1
So, Time of one T-state, T = µ s = 320 nsec
3.125
Q.35 Ans (b)
The frequency of crystal is divided by two internally. So the frequency of clock will be 2.5 MHz. One T
state is precisely equal to one time period of clock signal.
So,duration of one T-state is,
1
T = µ s = 0.4 µ s
2.5
Q.36 Ans (d)
Given , No. of T-states in each m/c cycle = 3
No. of T-states required in 4 m/c cycles = 12
One T state is precisely equal to one time period of clock signal.
1
So, time of one T-state, T = µ s
3
1
Time of 12 T-states = 12T = 12 × = 4 µs
3
Q.37 Ans (a)
An instruction cycle is the time in which, a hard-wired controller completes four functions i.e.
Step-I : F etch the code from memory
Step-II : U
pdate the program counter
Step-III : Decode the instruction code
Step-IV : Execute the instruction.
Q.38 Ans (c)
In 8085 microprocessor , the I/O device can be used in memory mapped I/O or I/O mapped I/O.
Q.39 Ans (b)
A 8085 microprocessor has 16 address lines which can address maximum of 2 I/O devices and
16
memory.
Q.40 Ans (c)
Facts about memory mapped I/O :
i. The processor treats an interface register as a part of the memory system.
ii. It reduces the memory space available
iii. The processor manipulates registers with same instruction that are used to manipulate memory locations.
iv. Arithmetic or logical operations can be directly performed with I/O data.


Chapter 5 Bus Timings & Communication With Peripherals

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Chapter 5 Bus Timings & Communication With Peripherals

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5 Bus Timings & Communication

 Statistical Analysis of Chapter 5

5.3 Machine Cycle

5.4 Instruction Cycle

5.5 Interrupt Acknowledgment Cycle

5.6 Communication With Memory

Ex.5.1 2000 H MOV H, D

Fig. 5.1 Memory Read Cycle

Fig. 5.2 Bus Timing of Op-code Fetch Cycle

M1 (Opcode Fetch) M2 (Memory Read)

A15-A8 High-Order High-Order

Fig. 5.3 Bus Timing of Memory Read Cycle

5.7 I/O Devices and Their Communication with Microprocessor

5.7.3 Instructions Related to Peripheral mapped I/O devices

M1 (Opcode Fetch) M2 (Memory Read) M3 (I/O read)

Table 5.1 Comparison of Memory-Mapped I/O and Peripheral I/O devices

OBJECTIVE TYPE PRACTICE QUESTIONS

An ERROR in the above diagram relates to the signal

(c) S1 = 1, S2 = 1, RD = 0, ALE high in T2

ANSWERS AND EXPLANATIONS

Q.6 Ans (b)

Q.11 Ans (d)

using I/O mapped I/O addressing.

A15-A8 High-Order Unspecified

Fig. Bus Timing of Op-code Fetch Cycle

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Statistical Analysis of Chapter 5